July 2016 - U-Boot

[U-Boot] [PATCH 0/9] rockchip: cosmetics, a fix and first steps on the rk3188
by Heiko Stuebner 20 Jul '16

20 Jul '16

I've made some nice progress on using mainline uboot on the rk3188 and would like to dump some first results. Right now I can use uboot on the rk3188 with the Rockchip binary ddr init, similar to what barebox does and can even netboot a kernel image using a usb ethernet adapter [0] . While working on this I found quite some cosmetic stuff that shouldn't persist to make extending easier. So while I don't know what the policy is for my standalone pinctrl and clock drivers (without the actual board) at least the cosmetics + fix might get in at least. [0] https://github.com/mmind/u-boot-rockchip/commits/rk3188-netboot Heiko Stuebner (9): cosmetic: rockchip: rk3288: pinctrl: fix config symbol naming cosmetic: rockchip: rk3036: pinctrl: fix config symbol naming cosmetic: rockchip: sort socs according to numbers cosmetic: rockchip: rk3288: rename rkclk_configure_cpu rockchip: rk3288: fix FREF_MIN_HZ constant rockchip: rk3188: Add header files for PMU and GRF rockchip: rk3188: Add pinctrl driver rockchip: rk3188: Bring in rk3066/rk3188 clock bindings rockchip: rk3188: Add clock driver arch/arm/include/asm/arch-rockchip/clock.h | 2 +- arch/arm/include/asm/arch-rockchip/cru_rk3188.h | 186 +++++++ arch/arm/include/asm/arch-rockchip/grf_rk3188.h | 589 +++++++++++++++++++++++ arch/arm/include/asm/arch-rockchip/pmu_rk3188.h | 36 ++ arch/arm/mach-rockchip/Kconfig | 20 +- arch/arm/mach-rockchip/Makefile | 4 +- arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 2 +- configs/chromebook_jerry_defconfig | 2 +- configs/evb-rk3036_defconfig | 2 +- configs/firefly-rk3288_defconfig | 2 +- configs/kylin-rk3036_defconfig | 2 +- configs/rock2_defconfig | 2 +- configs/sandbox_defconfig | 4 +- configs/sandbox_noblk_defconfig | 4 +- drivers/clk/Makefile | 1 + drivers/clk/clk_rk3188.c | 464 ++++++++++++++++++ drivers/clk/clk_rk3288.c | 4 +- drivers/pinctrl/Kconfig | 23 +- drivers/pinctrl/rockchip/Makefile | 5 +- drivers/pinctrl/rockchip/pinctrl_rk3188.c | 614 ++++++++++++++++++++++++ include/dt-bindings/clock/rk3066a-cru.h | 40 ++ include/dt-bindings/clock/rk3188-cru-common.h | 256 ++++++++++ include/dt-bindings/clock/rk3188-cru.h | 56 +++ 23 files changed, 2286 insertions(+), 34 deletions(-) create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3188.h create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3188.h create mode 100644 arch/arm/include/asm/arch-rockchip/pmu_rk3188.h create mode 100644 drivers/clk/clk_rk3188.c create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3188.c create mode 100644 include/dt-bindings/clock/rk3066a-cru.h create mode 100644 include/dt-bindings/clock/rk3188-cru-common.h create mode 100644 include/dt-bindings/clock/rk3188-cru.h -- 2.8.0.rc3

4 35

[U-Boot] [PATCH] image: fix IH_ARCH_... values for uImage compatibility
by Masahiro Yamada 20 Jul '16

20 Jul '16

Commit 555f45d8f916 ("image: Convert the IH_... values to enums") accidentally changed some IH_ARCH_... values. Originally, there existed a gap between IH_ARCH_M68K and IH_ARCH_MICROBLAZE, like follows. #define IH_ARCH_SPARC64 11 /* Sparc 64 Bit */ #define IH_ARCH_M68K 12 /* M68K */ #define IH_ARCH_MICROBLAZE 14 /* MicroBlaze */ #define IH_ARCH_NIOS2 15 /* Nios-II */ The enum conversion broke the compatibility with existing uImage files. Reverting 555f45d8f916 will cause build error unfortunately, so here is another way to fix it more easily. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- include/image.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/image.h b/include/image.h index 2a5b560..b43b179 100644 --- a/include/image.h +++ b/include/image.h @@ -182,7 +182,7 @@ enum { IH_ARCH_SPARC, /* Sparc */ IH_ARCH_SPARC64, /* Sparc 64 Bit */ IH_ARCH_M68K, /* M68K */ - IH_ARCH_MICROBLAZE, /* MicroBlaze */ + IH_ARCH_MICROBLAZE = 14, /* MicroBlaze */ IH_ARCH_NIOS2, /* Nios-II */ IH_ARCH_BLACKFIN, /* Blackfin */ IH_ARCH_AVR32, /* AVR32 */ -- 1.9.1

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[U-Boot] Please pull u-boot-cfi-flash/master
by Stefan Roese 20 Jul '16

20 Jul '16

Hi Tom, please pull the following patch: The following changes since commit 66669fcf809c1e3ff644b12e04e625d3737ffd8e: Merge git://git.denx.de/u-boot-fsl-qoriq (2016-07-19 16:38:57 -0400) are available in the git repository at: git://www.denx.de/git/u-boot-cfi-flash.git for you to fetch changes up to 55edb9d4d521ff733d217ddf47ad7bf4650676be: mtd: cfi_flash: fix polling for bit XSR.7 on Intel chips (2016-07-20 11:13:26 +0200) ---------------------------------------------------------------- Daniel Schwierzeck (1): mtd: cfi_flash: fix polling for bit XSR.7 on Intel chips drivers/mtd/cfi_flash.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

2 1

[U-Boot] Booting armv8 Kernel on UBoot
by Rajkumar Ramasamy 20 Jul '16

20 Jul '16

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1 0

[U-Boot] UBIFS broken on Microblaze architecture and possibly on other architectrures as well
by Hoefle Marco 20 Jul '16

20 Jul '16

Hallo, for ubifs on a spi flash I needed to add dummy functions and at atomic.h to the microblaze port in order to get it compile and work. code base is v2016.07 Marco

2 1

[U-Boot] [PATCH v3] dm: atmel: Add driver model support for the ehci driver
by Wenyou Yang 20 Jul '16

20 Jul '16

Add driver model support while retaining the existing legacy code. This allows the driver to support boards that have converted to driver model as well as those that have not. Signed-off-by: Wenyou Yang <wenyou.yang(a)atmel.com> Acked-by: Simon Glass <sjg(a)chromium.org> --- Changes in v3: - Change clk_client.h -> clk.h to adapt to clk API conversion. Changes in v2: - Collect Acked-by tag. - Update the clk API based on [PATCH] clk: convert API to match reset/mailbox fstyle (http://patchwork.ozlabs.org/patch/625342/). drivers/usb/host/Kconfig | 7 +++ drivers/usb/host/ehci-atmel.c | 116 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 123 insertions(+) diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 89580cc..b8dd18e 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -60,6 +60,13 @@ config USB_EHCI if USB_EHCI_HCD +config USB_EHCI_ATMEL + bool "Support for Atmel on-chip EHCI USB controller" + depends on ARCH_AT91 + default y + ---help--- + Enables support for the on-chip EHCI controller on Atmel chips. + config USB_EHCI_MARVELL bool "Support for MVEBU (AXP / A38x) on-chip EHCI USB controller" depends on ARCH_MVEBU diff --git a/drivers/usb/host/ehci-atmel.c b/drivers/usb/host/ehci-atmel.c index 1d7d280..d65bbe9 100644 --- a/drivers/usb/host/ehci-atmel.c +++ b/drivers/usb/host/ehci-atmel.c @@ -7,12 +7,18 @@ */ #include <common.h> +#include <clk.h> +#include <dm.h> #include <usb.h> #include <asm/io.h> #include <asm/arch/clk.h> #include "ehci.h" +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_DM_USB + int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { @@ -41,3 +47,113 @@ int ehci_hcd_stop(int index) return 0; } + +#else + +struct ehci_atmel_priv { + struct ehci_ctrl ehci; +}; + +static int ehci_atmel_enable_clk(struct udevice *dev) +{ + struct udevice *dev_clk; + struct clk clk; + int periph; + int ret; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return ret; + + ret = clk_enable(&clk); + if (ret) + return ret; + + ret = clk_get_by_index(dev, 1, &clk); + if (ret) + return -EINVAL; + + periph = fdtdec_get_uint(gd->fdt_blob, clk.dev->of_offset, "reg", -1); + if (periph < 0) + return -EINVAL; + + dev_clk = dev_get_parent(clk.dev); + if (!dev_clk) + return -ENODEV; + + ret = clk_request(dev_clk, &clk); + if (ret) + return ret; + + clk.id = periph; + ret = clk_enable(&clk); + if (ret) + return ret; + + clk_free(&clk); + + return 0; +} + +static int ehci_atmel_probe(struct udevice *dev) +{ + struct ehci_hccr *hccr; + struct ehci_hcor *hcor; + fdt_addr_t hcd_base; + int ret; + + ret = ehci_atmel_enable_clk(dev); + if (ret) { + debug("Failed to enable USB Host clock\n"); + return ret; + } + + /* + * Get the base address for EHCI controller from the device node + */ + hcd_base = dev_get_addr(dev); + if (hcd_base == FDT_ADDR_T_NONE) { + debug("Can't get the EHCI register base address\n"); + return -ENXIO; + } + + hccr = (struct ehci_hccr *)hcd_base; + hcor = (struct ehci_hcor *) + ((u32)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + + debug("echi-atmel: init hccr %x and hcor %x hc_length %d\n", + (u32)hccr, (u32)hcor, + (u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + + return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST); +} + +static int ehci_atmel_remove(struct udevice *dev) +{ + int ret; + + ret = ehci_deregister(dev); + if (ret) + return ret; + + return 0; +} + +static const struct udevice_id ehci_usb_ids[] = { + { .compatible = "atmel,at91sam9g45-ehci", }, + { } +}; + +U_BOOT_DRIVER(ehci_atmel) = { + .name = "ehci_atmel", + .id = UCLASS_USB, + .of_match = ehci_usb_ids, + .probe = ehci_atmel_probe, + .remove = ehci_atmel_remove, + .ops = &ehci_usb_ops, + .platdata_auto_alloc_size = sizeof(struct usb_platdata), + .priv_auto_alloc_size = sizeof(struct ehci_atmel_priv), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; + +#endif -- 2.7.4

1 0

[U-Boot] [PATCH] mtd: cfi_flash: fix polling for bit XSR.7 on Intel chips
by Daniel Schwierzeck 20 Jul '16

20 Jul '16

flash_full_status_check() checks bit XSR.7 on Intel chips. This should be done by only checking bit 7 and not by comparing the whole status byte or word with 0x80. This fixes the non-working block erase in the pflash emulation of Qemu when used with the MIPS Malta board. MIPS Malta uses x32 mode to access the pflash device. In x32 mode Qemu mirrors the lower 16 bits of the status word into the upper 16 bits. Thus the CFI driver gets a status word of 0x8080 in x32 mode. If flash_full_status_check() uses flash_isequal(), then it polls for XSR.7 by comparing 0x8080 with 0x80 which never becomes true. Reported-by: Alon Bar-Lev <alon.barlev(a)gmail.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> --- drivers/mtd/cfi_flash.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 8ccaff0..33c4a93 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -608,7 +608,7 @@ static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, case CFI_CMDSET_INTEL_EXTENDED: case CFI_CMDSET_INTEL_STANDARD: if ((retcode == ERR_OK) - && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) { + && !flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { retcode = ERR_INVAL; printf ("Flash %s error at address %lx\n", prompt, info->start[sector]); -- 2.9.2

2 1

Re: [U-Boot] u-boot: x86: interrupt mapping
by Bin Meng 20 Jul '16

20 Jul '16

+Jian, Simon, ML, this info might be useful for other guys on the ML. Hi Christian, On Mon, Jul 18, 2016 at 11:02 PM, Christian Gmeiner <christian.gmeiner(a)gmail.com> wrote: > Hi Bin, > > > 2016-06-28 3:15 GMT+02:00 Bin Meng <bmeng.cn(a)gmail.com>: >> Hi Christian, >> >> On Mon, Jun 27, 2016 at 8:37 PM, Christian Gmeiner >> <christian.gmeiner(a)gmail.com> wrote: >>> Hi Bin >>> >>> >>> 2016-06-27 14:05 GMT+02:00 Bin Meng <bmeng.cn(a)gmail.com>: >>>> Hi Christian, >>>> >>>> On Mon, Jun 27, 2016 at 6:59 PM, Christian Gmeiner >>>> <christian.gmeiner(a)gmail.com> wrote: >>>>> Hi Bin, >>>>> >>>>> 2016-06-17 4:10 GMT+02:00 Bin Meng <bmeng.cn(a)gmail.com>: >>>>>> Hi Christian, >>>>>> >>>>>> On Fri, Jun 17, 2016 at 4:13 AM, Christian Gmeiner >>>>>> <christian.gmeiner(a)gmail.com> wrote: >>>>>>> Hi Bin, >>>>>>> >>>>>>> I am writing you off-list to look for some help. I am currently >>>>>>> porting u-boot-x86 onto a crownbay/tunnelcreek based device. >>>>>> >>>>>> What's the board? Is the board similar to Crown Bay? >>>>>> >>>>> >>>>> Yes the design is heavily based on Crown Bay. >>>>> >>>>>>> I got the basis up and running quite fast, but interrupts/mp tables >>>>>>> eats my nerves. Is there a good approach to get the interrupt >>>>>>> mapping done correctly without try-and-error all the time? I have >>>>>>> access to the schematics (which could help). >>>>>> >>>>>> If it is E6xx and Topcliff chipset based, you should just use the >>>>>> interrupt mapping in the crownbay.dts as majority of the interrupt >>>>>> mapping is the same within SoC. >>>>>> >>>>> >>>>> After some hours debugging this issue I finally found the root cause for >>>>> the non working interrupts. The old bootloader does ioapic init sutff. >>>>> >>>>> The old boot chain was: bios -> bootloader (vxworks 6.8 based) -> system >>>>> (vxworks 5.5 based). >>>> >>>> When you talk 'bios', do you mean U-Boot? >>> >>> Nope. bios == bldk based bios. >>> >>> My job is to port the old used booting system (bldk, vxworks 6.8 based boot app, >>> vxworks 5.5 runtime system) over to u-boot. >>> >>>> >>>>> >>>>> To get the following boot chain working I needed to hackup up the interrupt >>>>> line assignment for pci devices. >>>>> >>>>> u-boot -> sytem >>>>> >>>>> +++ b/arch/x86/cpu/pci.c >>>>> @@ -80,6 +80,10 @@ void pci_assign_irqs(int bus, int device, u8 irq[4]) >>>>> if (!line) >>>>> continue; >>>>> >>>>> +#ifdef HACK >>>>> + line = pin + 15; >>>>> +#endif >>>> >>>> I don't understand the hack here. >>> >>> I try my best to explain it. loaded system expects that the PCI >>> devices interrupt >>> lines are configured correctly. For instance without that hack the >>> system failed to >>> identify the sata device as interrupts were not working/wrong. >>> >>> The +15 comes from the fact that in the I/O APIC redirection table the entries >>> 16-23 correspond to PCI Lines A-H. >>> >> >> I think it should be +16? >> > > Yeah.. > >> >>> Normally mp table usage should happen in the os - in my case vxw 5.5 image, but >>> it does not support it and there too many devices in the field so a >>> change in the os >>> is not possible. >>> >> >> I still do not get the hack here. Are you saying that the VxW 5.5 >> image does not support MPTable? Then why does it bother to use IOAPIC? >> It can just use PIC and get the IRQ number from the interrupt line >> register configured by U-Boot. >> > > For the moment I have no answer to this question. I need to dive into > the vxworks code, which > is not what I like to do now (but needs to be done)- > Yes, please do track it down. The interrupt line register configured by U-Boot should be enough for VxWorks to function under PIC mode. > I have an other (wired) question you may could help out. > > http://www.mouser.com/pdfdocs/Intel_Platform_Controller_Hub_EG20T_datasheet… > (page 124) > > On my development board the uart_clk is connected to a oscillator and > everything works as expected. > But on the production devices the uart_clk is not connected and fsp > hangs with post code 0x2e. > I am not sure about the meaning of post code 0x2e. Jian has some working experience on Atom E6xx with U-Boot. Adding him. > Now I would like to change the initial mux settings to use usb_48mhz > but I am quite sure that I need > to have the pci bus and its devices initialised already in order to > change the CLKCFG register. Do you > think there is an other way of accessing this register like fixed > memory address etc? > Which register do you want to program for this uart_clk? If it's on the PCI configuration space, you can use PCI config APIs to program. > thanks > -- Regards, Bin

3 8

[U-Boot] [PATCH v3] driver: spi: fsl-qspi: disable AHB buffer prefetch
by Yunhui Cui 20 Jul '16

20 Jul '16

From: Yunhui Cui <yunhui.cui(a)nxp.com> Errata: A-009282: QuadSPI data pre-fetch can result in incorrect data We need this errata workaround when CONFIG_SYS_FSL_QSPI_AHB is enabled. Signed-off-by: Yunhui Cui <yunhui.cui(a)nxp.com> --- drivers/spi/fsl_qspi.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 75cbab2..0354e20 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -438,13 +438,23 @@ static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv) static void qspi_init_ahb_read(struct fsl_qspi_priv *priv) { struct fsl_qspi_regs *regs = priv->regs; + int rx_size = 0x80; /* AHB configuration for access buffer 0/1/2 .*/ qspi_write32(priv->flags, &regs->buf0cr, QSPI_BUFXCR_INVALID_MSTRID); qspi_write32(priv->flags, &regs->buf1cr, QSPI_BUFXCR_INVALID_MSTRID); qspi_write32(priv->flags, &regs->buf2cr, QSPI_BUFXCR_INVALID_MSTRID); + +#ifdef CONFIG_SYS_FSL_ERRATUM_A009282 + /*A-009282: QuadSPI data pre-fetch can result in incorrect data + *Workaround: Keep the read data size to 64 bits (8 Bytes), which + *disables the prefetch on the AHB buffer,and prevents this issue + *from occurring. + */ + rx_size = 0x1; +#endif qspi_write32(priv->flags, &regs->buf3cr, QSPI_BUF3CR_ALLMST_MASK | - (0x80 << QSPI_BUF3CR_ADATSZ_SHIFT)); + (rx_size << QSPI_BUF3CR_ADATSZ_SHIFT)); /* We only use the buffer3 */ qspi_write32(priv->flags, &regs->buf0ind, 0); -- 2.1.0.27.g96db324

4 6

[U-Boot] [PATCH] usb: Kconfig: Add Kconfigs entry USB_EHCI_ZYNQ
by Siva Durga Prasad Paladugu 20 Jul '16

20 Jul '16

Add Kconfig entry config option for USB_EHCI_ZYNQ and update the same to enable for all zynq boards which supports USB Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> --- - This series is based on latest mainline Changes for v2: - Moved CONFIG_USB_EHCI_ZYNQ to Kconfig and removed config ZYNQ_USB as per review comment --- configs/zynq_microzed_defconfig | 3 +++ configs/zynq_picozed_defconfig | 3 +++ configs/zynq_zc702_defconfig | 3 +++ configs/zynq_zc706_defconfig | 3 +++ configs/zynq_zed_defconfig | 3 +++ configs/zynq_zybo_defconfig | 3 +++ drivers/usb/host/Kconfig | 7 +++++++ include/configs/zynq-common.h | 4 +--- include/configs/zynq_microzed.h | 2 -- include/configs/zynq_picozed.h | 2 -- include/configs/zynq_zc70x.h | 1 - include/configs/zynq_zed.h | 2 -- include/configs/zynq_zybo.h | 1 - 13 files changed, 26 insertions(+), 11 deletions(-) diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index d88c61b..91d5c82 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -38,6 +38,9 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_ZYNQ_GEM=y CONFIG_ZYNQ_QSPI=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI=y +CONFIG_USB_EHCI_ZYNQ=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y CONFIG_USB_GADGET=y diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig index aeb1270..6d3aef5 100644 --- a/configs/zynq_picozed_defconfig +++ b/configs/zynq_picozed_defconfig @@ -28,6 +28,9 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ZYNQ_SDHCI=y CONFIG_ZYNQ_GEM=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI=y +CONFIG_USB_EHCI_ZYNQ=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y CONFIG_USB_GADGET=y diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig index d68ed0e..57019da 100644 --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@ -43,6 +43,9 @@ CONFIG_DEBUG_UART_BASE=0xe0001000 CONFIG_DEBUG_UART_CLOCK=50000000 CONFIG_ZYNQ_QSPI=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI=y +CONFIG_USB_EHCI_ZYNQ=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y CONFIG_USB_GADGET=y diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index 8bd9230..e19f34f 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -39,6 +39,9 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_ZYNQ_GEM=y CONFIG_ZYNQ_QSPI=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI=y +CONFIG_USB_EHCI_ZYNQ=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y CONFIG_USB_GADGET=y diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index c70b860..6cb8a80 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -38,6 +38,9 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_ZYNQ_GEM=y CONFIG_ZYNQ_QSPI=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI=y +CONFIG_USB_EHCI_ZYNQ=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y CONFIG_USB_GADGET=y diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index 624545e..cce29bc 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -41,6 +41,9 @@ CONFIG_DEBUG_UART_BASE=0xe0001000 CONFIG_DEBUG_UART_CLOCK=50000000 CONFIG_ZYNQ_QSPI=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI=y +CONFIG_USB_EHCI_ZYNQ=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y CONFIG_USB_GADGET=y diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 89580cc..202cb29 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -85,6 +85,13 @@ config USB_EHCI_MSM This driver supports combination of Chipidea USB controller and Synapsys USB PHY in host mode only. +config USB_EHCI_ZYNQ + bool "Support for Xilinx Zynq on-chip EHCI USB controller" + depends on ARCH_ZYNQ + default n + ---help--- + Enable support for Zynq on-chip EHCI USB controller + config USB_EHCI_GENERIC bool "Support for generic EHCI USB controller" depends on OF_CONTROL diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 8dbac87..08b7602 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -86,10 +86,8 @@ # define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000 #endif -#ifdef CONFIG_ZYNQ_USB -# define CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_ZYNQ # define CONFIG_USB_STORAGE -# define CONFIG_USB_EHCI_ZYNQ # define CONFIG_EHCI_IS_TDI # define CONFIG_USB_MAX_CONTROLLER_COUNT 2 diff --git a/include/configs/zynq_microzed.h b/include/configs/zynq_microzed.h index ec7bb1c..e66088d 100644 --- a/include/configs/zynq_microzed.h +++ b/include/configs/zynq_microzed.h @@ -12,8 +12,6 @@ #define CONFIG_SYS_NO_FLASH -#define CONFIG_ZYNQ_USB - #include <configs/zynq-common.h> #endif /* __CONFIG_ZYNQ_MICROZED_H */ diff --git a/include/configs/zynq_picozed.h b/include/configs/zynq_picozed.h index adc4d0f..f2598a2 100644 --- a/include/configs/zynq_picozed.h +++ b/include/configs/zynq_picozed.h @@ -12,8 +12,6 @@ #define CONFIG_SYS_NO_FLASH -#define CONFIG_ZYNQ_USB - #include <configs/zynq-common.h> #endif /* __CONFIG_ZYNQ_PICOZED_H */ diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h index 8a04590..a27b49c 100644 --- a/include/configs/zynq_zc70x.h +++ b/include/configs/zynq_zc70x.h @@ -12,7 +12,6 @@ #define CONFIG_SYS_NO_FLASH -#define CONFIG_ZYNQ_USB #define CONFIG_ZYNQ_I2C0 #define CONFIG_ZYNQ_EEPROM diff --git a/include/configs/zynq_zed.h b/include/configs/zynq_zed.h index 150cb4a..dbb4621 100644 --- a/include/configs/zynq_zed.h +++ b/include/configs/zynq_zed.h @@ -12,8 +12,6 @@ #define CONFIG_SYS_NO_FLASH -#define CONFIG_ZYNQ_USB - #include <configs/zynq-common.h> #endif /* __CONFIG_ZYNQ_ZED_H */ diff --git a/include/configs/zynq_zybo.h b/include/configs/zynq_zybo.h index 637b1c5..ca3ad9c 100644 --- a/include/configs/zynq_zybo.h +++ b/include/configs/zynq_zybo.h @@ -13,7 +13,6 @@ #define CONFIG_SYS_NO_FLASH -#define CONFIG_ZYNQ_USB #define CONFIG_ZYNQ_I2C0 #define CONFIG_ZYNQ_I2C1 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -- 2.7.4

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