June 2016 - U-Boot

[U-Boot] [PATCH v2 1/3] spi: spi_flash: Dont set quad enable for micron in all cases
by Siva Durga Prasad Paladugu 14 Jul '16

14 Jul '16

Dont set quad enable for micron devices in all cases Setting the quad enable bit in micron expects all other commands like register reads on quad lines which may not be supported by some controllers. Hence, dont set the quad enable if controller driver sets the no_all_quad. Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> --- Changes for v2: - Newly added in series. --- drivers/mtd/spi/spi_flash.c | 13 ++++++++++++- include/spi.h | 2 +- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 5451725..5b22ae2 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -926,6 +926,8 @@ static int micron_quad_enable(struct spi_flash *flash) static int set_quad_mode(struct spi_flash *flash, u8 idcode0) { + struct spi_slave *spi = flash->spi; + switch (idcode0) { #ifdef CONFIG_SPI_FLASH_MACRONIX case SPI_FLASH_CFI_MFR_MACRONIX: @@ -938,7 +940,16 @@ static int set_quad_mode(struct spi_flash *flash, u8 idcode0) #endif #ifdef CONFIG_SPI_FLASH_STMICRO case SPI_FLASH_CFI_MFR_STMICRO: - return micron_quad_enable(flash); + /* + * Set quad enable for micron only + * if controller supports sending of + * all commands on quad lines, otherwise + * dont enable it + */ + if (spi->no_all_quad) + return 0; + else + return micron_quad_enable(flash); #endif default: printf("SF: Need set QEB func for %02x flash\n", idcode0); diff --git a/include/spi.h b/include/spi.h index 4b88d39..17c6e4d 100644 --- a/include/spi.h +++ b/include/spi.h @@ -117,7 +117,7 @@ struct spi_slave { unsigned int max_write_size; void *memory_map; u8 option; - + u8 no_all_quad; u8 flags; #define SPI_XFER_BEGIN BIT(0) /* Assert CS before transfer */ #define SPI_XFER_END BIT(1) /* Deassert CS after transfer */ -- 1.7.1

3 8

[U-Boot] [PATCH 1/9] spi: zynq_qspi: Add quad support for zynq qspi
by Siva Durga Prasad Paladugu 14 Jul '16

14 Jul '16

Add quad commands supports for zynq qspi driver Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> --- - Tested on zc702 board --- drivers/spi/zynq_qspi.c | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index b98663c..e636244 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -11,7 +11,9 @@ #include <dm.h> #include <malloc.h> #include <spi.h> +#include <spi_flash.h> #include <asm/io.h> +#include "../mtd/spi/sf_internal.h" DECLARE_GLOBAL_DATA_PTR; @@ -156,6 +158,17 @@ static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv) writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr); } +static int zynq_qspi_child_pre_probe(struct udevice *bus) +{ + struct spi_slave *slave = dev_get_parent_priv(bus); + + slave->mode_rx = QUAD_OUTPUT_FAST; + slave->mode = SPI_TX_QUAD; + slave->no_all_quad = 1; + + return 0; +} + static int zynq_qspi_probe(struct udevice *bus) { struct zynq_qspi_platdata *plat = dev_get_platdata(bus); @@ -627,4 +640,5 @@ U_BOOT_DRIVER(zynq_qspi) = { .platdata_auto_alloc_size = sizeof(struct zynq_qspi_platdata), .priv_auto_alloc_size = sizeof(struct zynq_qspi_priv), .probe = zynq_qspi_probe, + .child_pre_probe = zynq_qspi_child_pre_probe, }; -- 1.7.1

2 12

[U-Boot] [PATCH] mx6: support i.MX6UL speed grading reading from OTP bits
by Hector Palacios 13 Jul '16

13 Jul '16

i.MX6UL defines speed grading in OCOTP register 0x440[17:16] as follows: 00 reserved 01 528MHz 10 700MHz 11 reserved This commit removes the constants (which had the speed hardcoded in their names) and uses values instead. Signed-off-by: Hector Palacios <hector.palacios(a)digi.com> --- arch/arm/cpu/armv7/mx6/soc.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index d4b22ad7f315..49b5773b1b77 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -103,10 +103,6 @@ u32 get_cpu_rev(void) * defines a 2-bit SPEED_GRADING */ #define OCOTP_CFG3_SPEED_SHIFT 16 -#define OCOTP_CFG3_SPEED_800MHZ 0 -#define OCOTP_CFG3_SPEED_850MHZ 1 -#define OCOTP_CFG3_SPEED_1GHZ 2 -#define OCOTP_CFG3_SPEED_1P2GHZ 3 u32 get_cpu_speed_grade_hz(void) { @@ -122,18 +118,23 @@ u32 get_cpu_speed_grade_hz(void) switch (val) { /* Valid for IMX6DQ */ - case OCOTP_CFG3_SPEED_1P2GHZ: + case 3: if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) return 1200000000; - /* Valid for IMX6SX/IMX6SDL/IMX6DQ */ - case OCOTP_CFG3_SPEED_1GHZ: - return 996000000; - /* Valid for IMX6DQ */ - case OCOTP_CFG3_SPEED_850MHZ: + /* Valid for IMX6SX/IMX6SDL/IMX6DQ/IMX6UL */ + case 2: + if (is_cpu_type(MXC_CPU_MX6UL)) + return 700000000; + else + return 996000000; + /* Valid for IMX6DQ/IMX6UL */ + case 1: if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) return 852000000; + else if (is_cpu_type(MXC_CPU_MX6UL)) + return 528000000; /* Valid for IMX6SX/IMX6SDL/IMX6DQ */ - case OCOTP_CFG3_SPEED_800MHZ: + case 0: return 792000000; } return 0;

2 1

[U-Boot] [PATCH v2] imx: mx6var_som: Add support for Variscite mx6 boards
by Eran Matityahu 13 Jul '16

13 Jul '16

Add support for Variscite VAR-SOM-MX6 / VAR-SOM-SOLO/DUAL / DART-MX6 boards with features: PMIC, NAND flash, SD/MMC, USB, Ethernet, I2C, LVDS, HDMI. Signed-off-by: Eran Matityahu <eran.m(a)variscite.com> Cc: Stefano Babic <sbabic(a)denx.de> --- Note: This patch depends on two other patches I've submitted that were not yet reviewed: https://patchwork.ozlabs.org/patch/614924/ or http://lists.denx.de/pipermail/u-boot/2016-April/252840.html https://patchwork.ozlabs.org/patch/627880/ or http://lists.denx.de/pipermail/u-boot/2016-May/256341.html Changes for v2: - Many changes, code reorganization & cleanups and minor bug fixes - On DART board mmc0 is now always SD and mmc1 is eMMC, regardless of the current boot device - Move all previous automatic env settings from the code to env scripts, and also add some new ones, with options to enable/disable each one individually from the env - Add audiocodec_reset to SPL to fix a bug in "L" SOM variants (Low power) - Change kernel device tree file names for Variscite's 4.1.15 kernel - Change mmcblk device numbers for Variscite's 4.1.15 kernel - Changed a lot of things following Stefano's comments: Some things were fixed and some were made more clear. Some explanations: - This single U-Boot supports 3 different carrier boards: VAR-MX6CustomBoard, VAR-SOLOCustomBoard and VAR-DT6CustomBoard, and 3 different SOM types: VAR-SOM-MX6, VAR-SOM-SOLO/DUAL and DART-MX6 (DART-MX6 goes with VAR-DT6CustomBoard, and the others can be mixed). Each SOM type can come in various configurations (can be with different CPU types and frequencies, can be with or without eMMC, can be with different types and capacities of NAND, RAM, etc.) - About the EEPROM code: Since each SOM can come with a different RAM type and capacity, we use an EPPROM to keep the configuration of the specific RAM on the SOM. This code is based on an old U-Boot Variscite was managing internally before my time in the company. I've changed and simplified a lot of the code, but I cannot change the data on the EEPROM completely, since these SOMs are already in the market for a few years now. arch/arm/cpu/armv7/mx6/Kconfig | 7 + board/variscite/mx6var_som/Kconfig | 12 + board/variscite/mx6var_som/MAINTAINERS | 7 + board/variscite/mx6var_som/Makefile | 9 + board/variscite/mx6var_som/addresses.inc | 38 + board/variscite/mx6var_som/mx6var_eeprom.h | 16 + board/variscite/mx6var_som/mx6var_eeprom_v1.c | 244 +++++ board/variscite/mx6var_som/mx6var_eeprom_v1.h | 66 ++ board/variscite/mx6var_som/mx6var_eeprom_v2.c | 238 ++++ board/variscite/mx6var_som/mx6var_eeprom_v2.h | 57 + board/variscite/mx6var_som/mx6var_som.c | 1444 +++++++++++++++++++++++++ board/variscite/mx6var_som/values.inc | 39 + configs/mx6var_som_nand_defconfig | 31 + configs/mx6var_som_sd_defconfig | 31 + include/configs/mx6var_som.h | 429 ++++++++ tools/logos/variscite.bmp | Bin 0 -> 15414 bytes 16 files changed, 2668 insertions(+) create mode 100644 board/variscite/mx6var_som/Kconfig create mode 100644 board/variscite/mx6var_som/MAINTAINERS create mode 100644 board/variscite/mx6var_som/Makefile create mode 100644 board/variscite/mx6var_som/addresses.inc create mode 100644 board/variscite/mx6var_som/mx6var_eeprom.h create mode 100644 board/variscite/mx6var_som/mx6var_eeprom_v1.c create mode 100644 board/variscite/mx6var_som/mx6var_eeprom_v1.h create mode 100644 board/variscite/mx6var_som/mx6var_eeprom_v2.c create mode 100644 board/variscite/mx6var_som/mx6var_eeprom_v2.h create mode 100644 board/variscite/mx6var_som/mx6var_som.c create mode 100644 board/variscite/mx6var_som/values.inc create mode 100644 configs/mx6var_som_nand_defconfig create mode 100644 configs/mx6var_som_sd_defconfig create mode 100644 include/configs/mx6var_som.h create mode 100644 tools/logos/variscite.bmp diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 663f970..738c2ea 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -129,6 +129,12 @@ config TARGET_MX6UL_14X14_EVK select DM_THERMAL select SUPPORT_SPL +config TARGET_MX6VAR_SOM + bool "mx6var_som" + select SUPPORT_SPL + select DM + select DM_THERMAL + config TARGET_NITROGEN6X bool "nitrogen6x" @@ -208,6 +214,7 @@ source "board/technexion/pico-imx6ul/Kconfig" source "board/tbs/tbs2910/Kconfig" source "board/tqc/tqma6/Kconfig" source "board/udoo/Kconfig" +source "board/variscite/mx6var_som/Kconfig" source "board/wandboard/Kconfig" source "board/warp/Kconfig" diff --git a/board/variscite/mx6var_som/Kconfig b/board/variscite/mx6var_som/Kconfig new file mode 100644 index 0000000..0b82df7 --- /dev/null +++ b/board/variscite/mx6var_som/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MX6VAR_SOM + +config SYS_BOARD + default "mx6var_som" + +config SYS_VENDOR + default "variscite" + +config SYS_CONFIG_NAME + default "mx6var_som" + +endif diff --git a/board/variscite/mx6var_som/MAINTAINERS b/board/variscite/mx6var_som/MAINTAINERS new file mode 100644 index 0000000..a9367f0 --- /dev/null +++ b/board/variscite/mx6var_som/MAINTAINERS @@ -0,0 +1,7 @@ +MX6VAR_SOM BOARD +M: Eran Matityahu <eran.m(a)variscite.com> +S: Maintained +F: board/variscite/mx6var_som/ +F: include/configs/mx6var_som.h +F: configs/mx6var_som_nand_defconfig +F: configs/mx6var_som_sd_defconfig diff --git a/board/variscite/mx6var_som/Makefile b/board/variscite/mx6var_som/Makefile new file mode 100644 index 0000000..818d6c6 --- /dev/null +++ b/board/variscite/mx6var_som/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski <lg(a)denx.de> +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6var_som.o mx6var_eeprom_v1.o mx6var_eeprom_v2.o diff --git a/board/variscite/mx6var_som/addresses.inc b/board/variscite/mx6var_som/addresses.inc new file mode 100644 index 0000000..3aaea54 --- /dev/null +++ b/board/variscite/mx6var_som/addresses.inc @@ -0,0 +1,38 @@ +0x00000000, 0x020C4068, 0x020C406C, 0x020C4070, +0x020C4074, 0x020C4078, 0x020C407C, 0x020C4080, +0x020C4084, 0x020E0464, 0x020E0470, 0x020E0474, +0x020E0478, 0x020E047C, 0x020E0480, 0x020E0484, +0x020E0488, 0x020E048C, 0x020E0490, 0x020E0494, +0x020E04A0, 0x020E04AC, 0x020E04B0, 0x020E04B4, +0x020E04B8, 0x020E04BC, 0x020E04C0, 0x020E04C4, +0x020E04C8, 0x020E04CC, 0x020E04D0, 0x020E04D4, +0x020E04D8, 0x020E050C, 0x020E0510, 0x020E0514, +0x020E0518, 0x020E051C, 0x020E0520, 0x020E0524, +0x020E0528, 0x020E056C, 0x020E0578, 0x020E057C, +0x020E0588, 0x020E058C, 0x020E0594, 0x020E059C, +0x020E05A0, 0x020E05A8, 0x020E05AC, 0x020E05B0, +0x020E05B4, 0x020E05B8, 0x020E05BC, 0x020E05C0, +0x020E05C4, 0x020E0748, 0x020E074C, 0x020E0750, +0x020E0754, 0x020E0758, 0x020E0760, 0x020E0764, +0x020E076C, 0x020E0770, 0x020E0774, 0x020E0778, +0x020E077C, 0x020E0780, 0x020E0784, 0x020E0788, +0x020E078C, 0x020E0794, 0x020E0798, 0x020E079C, +0x020E07A0, 0x020E07A4, 0x020E07A8, 0x021B0000, +0x021B0004, 0x021B0008, 0x021B000C, 0x021B0010, +0x021B0014, 0x021B0018, 0x021B001C, 0x021B0020, +0x021B002C, 0x021B0030, 0x021B0038, 0x021B0040, +0x021B0400, 0x021B0404, 0x021B0800, 0x021B080C, +0x021B0810, 0x021B0818, 0x021B081C, 0x021B0820, +0x021B0824, 0x021B0828, 0x021B082C, 0x021B0830, +0x021B0834, 0x021B0838, 0x021B083C, 0x021B0840, +0x021B0848, 0x021B0850, 0x021B085C, 0x021B0890, +0x021B08B8, 0x021B08C0, 0x021B4000, 0x021B4004, +0x021B4008, 0x021B400C, 0x021B4010, 0x021B4014, +0x021B4018, 0x021B401C, 0x021B4020, 0x021B402C, +0x021B4030, 0x021B4038, 0x021B4040, 0x021B4400, +0x021B4404, 0x021B4800, 0x021B480C, 0x021B4810, +0x021B4818, 0x021B481C, 0x021B4820, 0x021B4824, +0x021B4828, 0x021B482C, 0x021B4830, 0x021B4834, +0x021B4838, 0x021B483C, 0x021B4840, 0x021B4848, +0x021B4850, 0x021B485C, 0x021B4890, 0x021B48B8, +0x021B48BC, 0x021B48C0 diff --git a/board/variscite/mx6var_som/mx6var_eeprom.h b/board/variscite/mx6var_som/mx6var_eeprom.h new file mode 100644 index 0000000..ae67a78 --- /dev/null +++ b/board/variscite/mx6var_som/mx6var_eeprom.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2016 Variscite Ltd. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MX6VAR_EEPROM_H_ +#define _MX6VAR_EEPROM_H_ + +u32 var_eeprom_v1_get_ram_size(void); +int var_eeprom_v1_dram_init(void); + +u32 var_eeprom_v2_get_ram_size(void); +int var_eeprom_v2_dram_init(void); + +#endif /* _MX6VAR_EEPROM_H_ */ diff --git a/board/variscite/mx6var_som/mx6var_eeprom_v1.c b/board/variscite/mx6var_som/mx6var_eeprom_v1.c new file mode 100644 index 0000000..fcf97e7 --- /dev/null +++ b/board/variscite/mx6var_som/mx6var_eeprom_v1.c @@ -0,0 +1,244 @@ +/* + * Copyright (C) 2016 Variscite Ltd. All Rights Reserved. + * + * Setup DRAM parametes and calibration values + * for the specific DRAM on the board. + * The parameters were provided by + * i.MX6 DDR Stress Test Tool and saved on EEPROM. + * + * For non-DART boards + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include "mx6var_eeprom_v1.h" + +static inline bool var_eeprom_v1_is_valid(const struct var_eeprom_v1_cfg *p_var_eeprom_v1_cfg) +{ + return (VARISCITE_MAGIC == p_var_eeprom_v1_cfg->header.variscite_magic); +} + +static int var_eeprom_v1_read_struct(struct var_eeprom_v1_cfg *p_var_eeprom_v1_cfg) +{ + i2c_set_bus_num(VAR_EEPROM_I2C_BUS); + if (i2c_probe(VAR_EEPROM_I2C_ADDR)) { + printf("\nError: couldn't find EEPROM device\n"); + return -1; + } + + if (i2c_read(VAR_EEPROM_I2C_ADDR, 0, 1, + (u8 *)p_var_eeprom_v1_cfg, + sizeof(struct var_eeprom_v1_cfg))) { + printf("\nError reading data from EEPROM\n"); + return -1; + } + + if (!var_eeprom_v1_is_valid(p_var_eeprom_v1_cfg)) { + printf("\nError: Data on EEPROM is invalid\n"); + return -1; + } + + return 0; +} + +/* + * Returns DRAM size in MiB + */ +u32 var_eeprom_v1_get_ram_size(void) +{ + struct var_eeprom_v1_cfg var_eeprom_v1_cfg = {{0}}; + + if (var_eeprom_v1_read_struct(&var_eeprom_v1_cfg)) + return -1; + + return var_eeprom_v1_cfg.header.dram_size; +} + +#ifdef CONFIG_SPL_BUILD +#include <asm/arch/mx6-ddr.h> +#include <asm/arch/sys_proto.h> + +static void var_eeprom_v1_mx6sdl_dram_setup_iomux(const struct var_pinmux_group_regs *pinmux_group) +{ + const struct mx6sdl_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_sdclk_0 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_sdclk_1 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_cas = pinmux_group->pinmux_ctrlpad_all_value, + .dram_ras = pinmux_group->pinmux_ctrlpad_all_value, + .dram_reset = pinmux_group->dram_reset, + .dram_sdcke0 = pinmux_group->dram_sdcke0, + .dram_sdcke1 = pinmux_group->dram_sdcke1, + .dram_sdba2 = pinmux_group->IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2, + .dram_sdodt0 = pinmux_group->dram_sdodt0, + .dram_sdodt1 = pinmux_group->dram_sdodt1, + .dram_sdqs0 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_sdqs1 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_sdqs2 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_sdqs3 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_sdqs4 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_sdqs5 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_sdqs6 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_sdqs7 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_dqm0 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_dqm1 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_dqm2 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_dqm3 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_dqm4 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_dqm5 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_dqm6 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_dqm7 = pinmux_group->pinmux_ctrlpad_all_value, + }; + + const struct mx6sdl_iomux_grp_regs mx6_grp_ioregs = { + .grp_ddr_type = pinmux_group->IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE, + .grp_ddrpke = pinmux_group->IOMUXC_SW_PAD_CTL_GRP_DDRPKE, + .grp_addds = pinmux_group->pinmux_ctrlpad_all_value, + .grp_ctlds = pinmux_group->pinmux_ctrlpad_all_value, + .grp_ddrmode_ctl = pinmux_group->IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL, + .grp_ddrmode = pinmux_group->IOMUXC_SW_PAD_CTL_GRP_DDRMODE, + .grp_b0ds = pinmux_group->pinmux_ctrlpad_all_value, + .grp_b1ds = pinmux_group->pinmux_ctrlpad_all_value, + .grp_b2ds = pinmux_group->pinmux_ctrlpad_all_value, + .grp_b3ds = pinmux_group->pinmux_ctrlpad_all_value, + .grp_b4ds = pinmux_group->pinmux_ctrlpad_all_value, + .grp_b5ds = pinmux_group->pinmux_ctrlpad_all_value, + .grp_b6ds = pinmux_group->pinmux_ctrlpad_all_value, + .grp_b7ds = pinmux_group->pinmux_ctrlpad_all_value, + }; + + mx6sdl_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); +} + +static void var_eeprom_v1_mx6dq_dram_setup_iomux(const struct var_pinmux_group_regs *pinmux_group) +{ + const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_sdclk_0 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_sdclk_1 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_cas = pinmux_group->pinmux_ctrlpad_all_value, + .dram_ras = pinmux_group->pinmux_ctrlpad_all_value, + .dram_reset = pinmux_group->dram_reset, + .dram_sdcke0 = pinmux_group->dram_sdcke0, + .dram_sdcke1 = pinmux_group->dram_sdcke1, + .dram_sdba2 = pinmux_group->IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2, + .dram_sdodt0 = pinmux_group->dram_sdodt0, + .dram_sdodt1 = pinmux_group->dram_sdodt1, + .dram_sdqs0 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_sdqs1 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_sdqs2 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_sdqs3 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_sdqs4 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_sdqs5 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_sdqs6 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_sdqs7 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_dqm0 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_dqm1 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_dqm2 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_dqm3 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_dqm4 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_dqm5 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_dqm6 = pinmux_group->pinmux_ctrlpad_all_value, + .dram_dqm7 = pinmux_group->pinmux_ctrlpad_all_value, + }; + + const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { + .grp_ddr_type = pinmux_group->IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE, + .grp_ddrpke = pinmux_group->IOMUXC_SW_PAD_CTL_GRP_DDRPKE, + .grp_addds = pinmux_group->pinmux_ctrlpad_all_value, + .grp_ctlds = pinmux_group->pinmux_ctrlpad_all_value, + .grp_ddrmode_ctl = pinmux_group->IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL, + .grp_ddrmode = pinmux_group->IOMUXC_SW_PAD_CTL_GRP_DDRMODE, + .grp_b0ds = pinmux_group->pinmux_ctrlpad_all_value, + .grp_b1ds = pinmux_group->pinmux_ctrlpad_all_value, + .grp_b2ds = pinmux_group->pinmux_ctrlpad_all_value, + .grp_b3ds = pinmux_group->pinmux_ctrlpad_all_value, + .grp_b4ds = pinmux_group->pinmux_ctrlpad_all_value, + .grp_b5ds = pinmux_group->pinmux_ctrlpad_all_value, + .grp_b6ds = pinmux_group->pinmux_ctrlpad_all_value, + .grp_b7ds = pinmux_group->pinmux_ctrlpad_all_value, + }; + + mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); +} + +static void var_eeprom_v1_handle_write_opcodes(const struct reg_write_opcode write_opcodes[]) +{ + volatile struct mmdc_p_regs *mmdc_p0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; + u32 opcode, address, value, i = 0; + volatile u32 *reg_ptr; + + /* Go through all register initializations and apply to correct registers */ + while (i < VAR_EEPROM_MAX_NUM_OF_OPCODES) { + address = write_opcodes[i].address; + if (address == 0) + break; + reg_ptr = (u32 *)address; + value = write_opcodes[i].value; + + opcode = address & 0xF0000000; + switch (opcode) { + case VAR_DDR_INIT_OPCODE_WRITE_VAL_TO_ADDRESS: + /* ZQ calibration? ==> Need to wait? */ + if ((address == mmdc_p0->mpzqhwctrl) && (value & 0x3)) + while (mmdc_p0->mpzqhwctrl & 0x00010000); + else + /* write value to reg */ + *reg_ptr = value; + break; + case VAR_DDR_INIT_OPCODE_WAIT_MASK_RISING: + while ((value & (*reg_ptr)) != value); + break; + case VAR_DDR_INIT_OPCODE_WAIT_MASK_FALLING: + while ((value & ~(*reg_ptr)) != value); + break; + case VAR_DDR_INIT_OPCODE_DELAY_USEC: + udelay(value); + break; + default: + break; + } + + i++; + } + + udelay(500); +} + +/* + * Null terminate the info strings, in case the info was never written to EEPROM and it contains garbage + */ +static void var_eeprom_v1_null_term_strings(struct var_eeprom_v1_cfg *p_var_eeprom_v1_cfg) +{ + p_var_eeprom_v1_cfg->header.part_number[sizeof(p_var_eeprom_v1_cfg->header.part_number) - 1] = (u8)0; + p_var_eeprom_v1_cfg->header.Assembly[sizeof(p_var_eeprom_v1_cfg->header.Assembly) - 1] = (u8)0; + p_var_eeprom_v1_cfg->header.date[sizeof(p_var_eeprom_v1_cfg->header.date) - 1] = (u8)0; +} + +static void var_eeprom_v1_print_info(const struct var_eeprom_v1_cfg *p_var_eeprom_v1_cfg) +{ + printf("\nPart number: %s\n", (char *)p_var_eeprom_v1_cfg->header.part_number); + printf("Assembly: %s\n", (char *)p_var_eeprom_v1_cfg->header.Assembly); + printf("Date of production: %s\n", (char *)p_var_eeprom_v1_cfg->header.date); +} + +int var_eeprom_v1_dram_init(void) +{ + struct var_eeprom_v1_cfg var_eeprom_v1_cfg = {{0}}; + + if (var_eeprom_v1_read_struct(&var_eeprom_v1_cfg)) + return -1; + + if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO)) + var_eeprom_v1_mx6sdl_dram_setup_iomux(&(var_eeprom_v1_cfg.pinmux_group)); + else if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) + var_eeprom_v1_mx6dq_dram_setup_iomux(&(var_eeprom_v1_cfg.pinmux_group)); + + var_eeprom_v1_handle_write_opcodes(var_eeprom_v1_cfg.write_opcodes); + + var_eeprom_v1_null_term_strings(&var_eeprom_v1_cfg); + var_eeprom_v1_print_info(&var_eeprom_v1_cfg); + + return 0; +} +#endif /* CONFIG_SPL_BUILD */ diff --git a/board/variscite/mx6var_som/mx6var_eeprom_v1.h b/board/variscite/mx6var_som/mx6var_eeprom_v1.h new file mode 100644 index 0000000..9707d08 --- /dev/null +++ b/board/variscite/mx6var_som/mx6var_eeprom_v1.h @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2016 Variscite Ltd. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MX6VAR_EEPROM_V1_H_ +#define _MX6VAR_EEPROM_V1_H_ + +#define VARISCITE_MAGIC 0x49524157 /* == HEX("VARI")*/ + +#define VAR_EEPROM_I2C_BUS 1 +#define VAR_EEPROM_I2C_ADDR 0x56 +#define VAR_EEPROM_SIZE_BYTES 512 +#define VAR_EEPROM_MAX_NUM_OF_OPCODES ((VAR_EEPROM_SIZE_BYTES \ + - sizeof(struct var_eeprom_v1_cfg_header) \ + - sizeof(struct var_pinmux_group_regs)) \ + / sizeof(struct reg_write_opcode)) + +#define VAR_DDR_INIT_OPCODE_WRITE_VAL_TO_ADDRESS 0x00000000 +#define VAR_DDR_INIT_OPCODE_WAIT_MASK_RISING 0x10000000 +#define VAR_DDR_INIT_OPCODE_WAIT_MASK_FALLING 0x20000000 +#define VAR_DDR_INIT_OPCODE_DELAY_USEC 0x30000000 + +struct var_eeprom_v1_cfg_header +{ + u32 variscite_magic; /* == HEX("VARI")?*/ + u8 part_number[16]; + u8 Assembly[16]; + u8 date[16]; + u8 version; + u8 reserved[7]; + /* DRAM size in MiB */ + u32 dram_size; +}; + +struct var_pinmux_group_regs +{ + u32 IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE; + u32 IOMUXC_SW_PAD_CTL_GRP_DDRPKE; + u32 IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL; + u32 IOMUXC_SW_PAD_CTL_GRP_DDRMODE; + u32 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2; + u32 dram_reset; + u32 dram_sdcke0; + u32 dram_sdcke1; + u32 dram_sdodt0; + u32 dram_sdodt1; + u32 reserved; + u32 pinmux_ctrlpad_all_value; +}; + +struct reg_write_opcode +{ + u32 address; /* address encoded with opcode */ + u32 value; +}; + +struct var_eeprom_v1_cfg +{ + struct var_eeprom_v1_cfg_header header; + struct var_pinmux_group_regs pinmux_group; + struct reg_write_opcode write_opcodes[VAR_EEPROM_MAX_NUM_OF_OPCODES]; +}; + +#endif /* _MX6VAR_EEPROM_V1_H_ */ diff --git a/board/variscite/mx6var_som/mx6var_eeprom_v2.c b/board/variscite/mx6var_som/mx6var_eeprom_v2.c new file mode 100644 index 0000000..b148b20 --- /dev/null +++ b/board/variscite/mx6var_som/mx6var_eeprom_v2.c @@ -0,0 +1,238 @@ +/* + * Copyright (C) 2016 Variscite Ltd. All Rights Reserved. + * + * Setup DRAM parametes and calibration values + * for the specific DRAM on the board. + * The parameters were provided by + * i.MX6 DDR Stress Test Tool and saved on EEPROM. + * + * For DART board + * (Can hold more parameters than "VAR EEPROM V1") + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include "mx6var_eeprom_v2.h" + +static inline bool var_eeprom_v2_is_valid(const struct var_eeprom_v2_cfg *p_var_eeprom_v2_cfg) +{ + return (VARISCITE_MAGIC_V2 == p_var_eeprom_v2_cfg->variscite_magic); +} + +static int var_eeprom_v2_read_struct(struct var_eeprom_v2_cfg *var_eeprom_v2_cfg) +{ + i2c_set_bus_num(VAR_DART_EEPROM_I2C_BUS); + if (i2c_probe(VAR_DART_EEPROM_I2C_ADDR)) { + printf("\nError: Couldn't find EEPROM device\n"); + return -1; + } + + if (i2c_read(VAR_DART_EEPROM_I2C_ADDR, 0, 1, + (u8 *) var_eeprom_v2_cfg, + sizeof(struct var_eeprom_v2_cfg))) { + printf("\nError reading data from EEPROM\n"); + return -1; + } + + if (!var_eeprom_v2_is_valid(var_eeprom_v2_cfg)) { + printf("\nError: Data on EEPROM is invalid\n"); + return -1; + } + + return 0; +} + +/* + * Returns DRAM size in MiB + */ +u32 var_eeprom_v2_get_ram_size(void) +{ + struct var_eeprom_v2_cfg var_eeprom_v2_cfg = {0}; + + if (var_eeprom_v2_read_struct(&var_eeprom_v2_cfg)) + return -1; + + return var_eeprom_v2_cfg.dram_size * 128; +} + +#ifdef CONFIG_SPL_BUILD +/* + * Fills custom_addresses & custom_values, from custom_addresses_values + */ +static void load_custom_data(u32 *custom_addresses, u32 *custom_values, const u32 *custom_addresses_values) +{ + int i, j=0; + + for (i = 0; i < MAX_CUSTOM_ADDRESSES; i++) { + if (custom_addresses_values[i] == 0) + break; + custom_addresses[i] = custom_addresses_values[i]; + } + + i++; + if (i > MAX_CUSTOM_ADDRESSES) + return; + + j=0; + for (; i < MAX_CUSTOM_VALUES; i++) { + if (custom_addresses_values[i] == 0) + break; + custom_values[j] = custom_addresses_values[i]; + j++; + } +} + +static u32 get_address_by_index(u8 index, const u32 *common_addresses, const u32 *custom_addresses) +{ + if (index >= MAX_COMMON_ADDRS_INDEX) + return custom_addresses[index - MAX_COMMON_ADDRS_INDEX]; + + return common_addresses[index]; +} + +static u32 get_value_by_index(u8 index, const u32 *common_values, const u32 *custom_values) +{ + if (index >= MAX_COMMON_VALUES_INDEX) + return custom_values[index - MAX_COMMON_VALUES_INDEX]; + + return common_values[index]; +} + +static int handle_commands(const struct eeprom_command commands[], + const u32 *common_addresses, + const u32 *common_values, + const u32 *custom_addresses, + const u32 *custom_values) +{ + u32 address, value; + volatile u32 *reg_ptr; + u8 wait_idx = 0; + int i = 0; + + while (i < MAX_NUM_OF_COMMANDS) { + + eeprom_v2_debug("Executing command %03d: %03d, %03d\n", + i, + commands[i].address_index, + commands[i].value_index); + + if (commands[i].address_index == LAST_COMMAND_INDEX) + return 0; + + if (commands[i].address_index == DELAY_10USEC_INDEX) { + /* Delay for Value * 10 uSeconds */ + eeprom_v2_debug("Delaying for %d microseconds\n", commands[i].value_index * 10); + udelay((int)(commands[i].value_index * 10)); + ++i; + continue; + } + + /* + * Check for a wait index. + * A wait index means "next command is a wait command". + */ + switch (commands[i].address_index) { + case WHILE_NOT_EQUAL_INDEX: + case WHILE_EQUAL_INDEX: + case WHILE_AND_INDEX: + case WHILE_NOT_AND_INDEX: + /* Save wait index and go to next command */ + wait_idx = commands[i].address_index; + ++i; + break; + } + + /* Get address and value */ + address = get_address_by_index(commands[i].address_index, common_addresses, custom_addresses); + value = get_value_by_index(commands[i].value_index, common_values, custom_values); + reg_ptr = (u32 *)address; + + switch (wait_idx) { + case WHILE_NOT_EQUAL_INDEX: + eeprom_v2_debug("Waiting while data at address %08x is not equal %08x\n", address, value); + while(*reg_ptr != value); + break; + case WHILE_EQUAL_INDEX: + eeprom_v2_debug("Waiting while data at address %08x is equal %08x\n", address, value); + while(*reg_ptr == value); + break; + case WHILE_AND_INDEX: + eeprom_v2_debug("Waiting while data at address %08x and %08x is not zero\n", address, value); + while(*reg_ptr & value); + break; + case WHILE_NOT_AND_INDEX: + eeprom_v2_debug("Waiting while data at address %08x and %08x is zero\n", address, value); + while(!(*reg_ptr & value)); + break; + default: + /* This is a regular set command (non-wait) */ + eeprom_v2_debug("Setting data at address %08x to %08x\n", address, value); + *reg_ptr = value; + break; + } + + ++i; + } + + return 0; +} + +/* + * Null terminate the info strings, in case the info was never written to EEPROM and it contains garbage + */ +static void var_eeprom_v2_null_term_strings(struct var_eeprom_v2_cfg *p_var_eeprom_v2_cfg) +{ + p_var_eeprom_v2_cfg->part_number[sizeof(p_var_eeprom_v2_cfg->part_number)-1] = (u8)0; + p_var_eeprom_v2_cfg->Assembly[sizeof(p_var_eeprom_v2_cfg->Assembly)-1] = (u8)0; + p_var_eeprom_v2_cfg->date[sizeof(p_var_eeprom_v2_cfg->date)-1] = (u8)0; +} + +static void var_eeprom_v2_print_info(const struct var_eeprom_v2_cfg *p_var_eeprom_v2_cfg) +{ + printf("\nPart number: %s\n", (char *)p_var_eeprom_v2_cfg->part_number); + printf("Assembly: %s\n", (char *)p_var_eeprom_v2_cfg->Assembly); + printf("Date of production: %s\n", (char *)p_var_eeprom_v2_cfg->date); +} + +int var_eeprom_v2_dram_init(void) +{ + struct var_eeprom_v2_cfg var_eeprom_v2_cfg = {0}; + + /* + * The eeprom contains commands with + * 1 byte index to a common address in this array, and + * 1 byte index to a common value in the next array - to write to the address. + */ + const u32 common_addresses[]= + { + #include "addresses.inc" + }; + + const u32 common_values[] = + { + #include "values.inc" + }; + + /* + * Some commands in the eeprom contain higher indices, + * to custom addresses and values which are not present in the common arrays, + * and it also contains an array of the custom addresses and values themselves. + */ + u32 custom_addresses[MAX_CUSTOM_ADDRESSES]={0}; + u32 custom_values[MAX_CUSTOM_VALUES]={0}; + + if (var_eeprom_v2_read_struct(&var_eeprom_v2_cfg)) + return -1; + + load_custom_data(custom_addresses, custom_values, var_eeprom_v2_cfg.custom_addresses_values); + + handle_commands(var_eeprom_v2_cfg.commands, common_addresses, common_values, custom_addresses, custom_values); + + var_eeprom_v2_null_term_strings(&var_eeprom_v2_cfg); + var_eeprom_v2_print_info(&var_eeprom_v2_cfg); + + return 0; +} +#endif /* CONFIG_SPL_BUILD */ diff --git a/board/variscite/mx6var_som/mx6var_eeprom_v2.h b/board/variscite/mx6var_som/mx6var_eeprom_v2.h new file mode 100644 index 0000000..c0c159a --- /dev/null +++ b/board/variscite/mx6var_som/mx6var_eeprom_v2.h @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2016 Variscite Ltd. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MX6VAR_EEPROM_V2_H_ +#define _MX6VAR_EEPROM_V2_H_ + +#define VARISCITE_MAGIC_V2 0x32524156 /* == HEX("VAR2") */ + +#define VAR_DART_EEPROM_I2C_BUS 1 +#define VAR_DART_EEPROM_I2C_ADDR 0x52 + +#define WHILE_NOT_EQUAL_INDEX 241 +#define WHILE_EQUAL_INDEX 242 +#define WHILE_AND_INDEX 243 +#define WHILE_NOT_AND_INDEX 244 +#define DELAY_10USEC_INDEX 245 +#define LAST_COMMAND_INDEX 255 + +#define MAX_CUSTOM_ADDRESSES 32 +#define MAX_CUSTOM_VALUES 32 + +#define MAX_COMMON_ADDRS_INDEX 200 +#define MAX_COMMON_VALUES_INDEX 200 + +#define MAX_NUM_OF_COMMANDS 150 + +#ifdef EEPROM_V2_DEBUG +#define eeprom_v2_debug(M, ...) printf("EEPROM_V2 DEBUG: " M, ##__VA_ARGS__) +#else +#define eeprom_v2_debug(M, ...) +#endif + +struct __attribute__((packed)) eeprom_command +{ + u8 address_index; + u8 value_index; +}; + +struct __attribute__((packed)) var_eeprom_v2_cfg +{ + u32 variscite_magic; /* == HEX("VAR2")? */ + u8 part_number[16]; + u8 Assembly[16]; + u8 date[12]; + /* Contains addresses and values not present in .inc files */ + u32 custom_addresses_values[32]; + struct eeprom_command commands[MAX_NUM_OF_COMMANDS]; + u8 reserved[34]; + /* DRAM size in 8KiB unit */ + u8 dram_size; + u8 crc; +}; + +#endif /* _MX6VAR_EEPROM_V2_H_ */ diff --git a/board/variscite/mx6var_som/mx6var_som.c b/board/variscite/mx6var_som/mx6var_som.c new file mode 100644 index 0000000..4673525 --- /dev/null +++ b/board/variscite/mx6var_som/mx6var_som.c @@ -0,0 +1,1444 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Author: Fabio Estevam <fabio.estevam(a)freescale.com> + * + * Copyright (C) 2016 Variscite Ltd. All Rights Reserved. + * + * Author: Eran Matityahu <eran.m(a)variscite.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fsl_esdhc.h> +#include <i2c.h> +#include <malloc.h> +#include <micrel.h> +#include <miiphy.h> +#include <mmc.h> +#include <netdev.h> +#include <power/pmic.h> +#include <power/pfuze100_pmic.h> +#include <splash.h> +#include <usb.h> +#include <usb/ehci-ci.h> +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/mxc_hdmi.h> +#include <asm/arch/sys_proto.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <asm/imx-common/mxc_i2c.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/video.h> +#include <asm/io.h> +#include "mx6var_eeprom.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + +#define PER_VCC_EN_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + + +#define VAR_SOM_BACKLIGHT_EN IMX_GPIO_NR(4, 30) + +bool lvds_enabled=false; + +/* + * Returns true iff the SOM is VAR-SOM-SOLO + */ +static bool is_som_solo(void) +{ + bool ret; + int oldbus = i2c_get_bus_num(); + + i2c_set_bus_num(PMIC_I2C_BUS); + /* Probing for PMIC which is preset on all SOM types but SOM-SOLO */ + ret = (0 != i2c_probe(CONFIG_POWER_PFUZE100_I2C_ADDR)); + + i2c_set_bus_num(oldbus); + return ret; +} + +/* + * Returns true iff the carrier board is VAR-SOLOCustomBoard + */ +static bool is_solo_custom_board(void) +{ + bool ret; + int oldbus = i2c_get_bus_num(); + + i2c_set_bus_num(1); + /* Probing for extra EEPROM present only on SOLOCustomBoard */ + ret = (0 == i2c_probe(0x51)); + + i2c_set_bus_num(oldbus); + return ret; +} + +static bool is_cpu_pop_packaged(void) +{ + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + u32 soc_sbmr = readl(&src_regs->sbmr1); + u8 boot_cfg3 = (soc_sbmr >> 16) & 0xFF; + + /* DDR Memory Map config == 4KB Interleaving Enabled */ + return ((boot_cfg3 & 0x30) == 0x20); +} + +/* + * Returns true iff the carrier board is VAR-DT6CustomBoard + * (and the SOM is DART-MX6) + */ +static inline bool is_dart_board(void) +{ + return is_cpu_pop_packaged(); +} + +/* + * Returns true iff the carrier board is VAR-MX6CustomBoard + */ +static inline bool is_mx6_custom_board(void) +{ + return (!is_dart_board() && !is_solo_custom_board()); +} + +enum current_board { + DART_BOARD, + SOLO_CUSTOM_BOARD, + MX6_CUSTOM_BOARD, +}; + +static enum current_board get_board_indx(void) +{ + if (is_dart_board()) + return DART_BOARD; + if (is_solo_custom_board()) + return SOLO_CUSTOM_BOARD; + if (is_mx6_custom_board()) + return MX6_CUSTOM_BOARD; + + printf("Error identifing carrier board!\n"); + hang(); +} + +static int check_env(char *var, char *val) +{ + char *read_val; + if (var==NULL || val==NULL) + return 0; + + read_val = getenv(var); + + if ((read_val != NULL) && + (strcmp(read_val, val) == 0)) { + return 1; + } + + return 0; +} + +#ifdef CONFIG_SPLASH_SCREEN +static void set_splashsource_to_boot_rootfs(void) +{ + if (!check_env("splashsourceauto", "yes")) + return; + +#ifdef CONFIG_SYS_BOOT_NAND + setenv("splashsource", getenv("rootfs_device")); +#else + if (mmc_get_env_dev() == 0) + setenv("splashsource", "sd"); + else if (mmc_get_env_dev() == 1) + setenv("splashsource", "emmc"); +#endif +} + +int splash_screen_prepare(void) +{ + int ret; + + struct splash_location var_splash_locations[] = { + { + .name = "sd", + .storage = SPLASH_STORAGE_MMC, + .flags = SPLASH_STORAGE_FS, + .devpart = "0:2", + }, + { + .name = "emmc", + .storage = SPLASH_STORAGE_MMC, + .flags = SPLASH_STORAGE_FS, + .devpart = (is_dart_board() ? "1:2" : "1:1"), + }, + { + .name = "nand", + .storage = SPLASH_STORAGE_NAND, + .flags = SPLASH_STORAGE_FS, + .mtdpart = "rootfs", + .ubivol = "ubi0:rootfs", + }, + }; + + set_splashsource_to_boot_rootfs(); + + ret = splash_source_load(var_splash_locations, + ARRAY_SIZE(var_splash_locations)); + + /* Turn on backlight */ + if (lvds_enabled) + gpio_set_value(VAR_SOM_BACKLIGHT_EN, 1); + + return ret; +} +#endif + +static void print_emmc_size(void) +{ + struct mmc *mmc; + int err; + + mmc = find_mmc_device(1); + err = !mmc; + if (!err) { + /* Silence mmc_init since SOMs can be with or without eMMC */ + gd->flags |= GD_FLG_SILENT; + err = mmc_init(mmc); + gd->flags &= ~GD_FLG_SILENT; + } + + if (err) { + puts("No eMMC\n"); + return; + } + + puts("eMMC: "); + print_size(mmc->capacity, "\n"); +} + +/* + * Returns DRAM size in MiB + */ +static u32 read_ram_size_from_eeprom(void) +{ + u32 ram_size = is_dart_board() ? + var_eeprom_v2_get_ram_size() : + var_eeprom_v1_get_ram_size(); + + if (ram_size < 0) { + printf("Error reading RAM size from EEPROM\n"); + hang(); + } + + /* Just to be sure */ + if (ram_size > 3840) + ram_size = 3840; + + return ram_size; +} + +int dram_init(void) +{ + gd->ram_size = read_ram_size_from_eeprom() * 1024 * 1024; + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const enet_pads1[] = { + IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)), + /* pin 35 - 1 (PHY_AD2) on reset */ + IOMUX_PADS(PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)), + /* pin 32 - 1 - (MODE0) all */ + IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)), + /* pin 31 - 1 - (MODE1) all */ + IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)), + /* pin 28 - 1 - (MODE2) all */ + IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)), + /* pin 27 - 1 - (MODE3) all */ + IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), + /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ + IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)), + /* PHY Reset */ + IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const enet_pads2[] = { + IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), +}; + +static void setup_iomux_enet(void) +{ + gpio_direction_output(IMX_GPIO_NR(1, 25), 0); + gpio_direction_output(IMX_GPIO_NR(6, 30), 1); + gpio_direction_output(IMX_GPIO_NR(6, 25), 1); + gpio_direction_output(IMX_GPIO_NR(6, 27), 1); + gpio_direction_output(IMX_GPIO_NR(6, 28), 1); + gpio_direction_output(IMX_GPIO_NR(6, 29), 1); + + SETUP_IOMUX_PADS(enet_pads1); + + gpio_direction_output(IMX_GPIO_NR(6, 24), 1); + + mdelay(10); + /* Reset PHY */ + gpio_set_value(IMX_GPIO_NR(1, 25), 1); + + SETUP_IOMUX_PADS(enet_pads2); +} + +static iomux_v3_cfg_t const usdhc1_pads[] = { + IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), +}; + + +static iomux_v3_cfg_t const usdhc2_pads[] = { + IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const usdhc2_cd_pad[][1*2] = { + { + /* DART */ + IOMUX_PADS(PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)), + }, + { + /* Non-DART */ + IOMUX_PADS(PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)), + } +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), +}; + +#ifdef CONFIG_SYS_I2C_MXC +I2C_PADS(i2c_pad_info1, + PAD_CSI0_DAT9__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), + PAD_CSI0_DAT9__GPIO5_IO27 | MUX_PAD_CTRL(I2C_PAD_CTRL), + IMX_GPIO_NR(5, 27), + PAD_CSI0_DAT8__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), + PAD_CSI0_DAT8__GPIO5_IO26 | MUX_PAD_CTRL(I2C_PAD_CTRL), + IMX_GPIO_NR(5, 26)); + +I2C_PADS(i2c_pad_info2, + PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), + PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL), + IMX_GPIO_NR(4, 12), + PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), + PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL), + IMX_GPIO_NR(4, 13)); + +I2C_PADS(i2c_pad_info3, + PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), + PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(I2C_PAD_CTRL), + IMX_GPIO_NR(1, 5), + PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), + PAD_GPIO_16__GPIO7_IO11 | MUX_PAD_CTRL(I2C_PAD_CTRL), + IMX_GPIO_NR(7, 11)); +#endif + +void setup_local_i2c(void) { + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c_pad_info1)); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c_pad_info2)); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c_pad_info3)); +} + +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart1_pads); +} + +#ifdef CONFIG_FSL_ESDHC +static struct fsl_esdhc_cfg usdhc_cfg[2]; + +int board_mmc_get_env_dev(int devno) +{ + return devno - 1; +} + +#ifdef CONFIG_ENV_IS_IN_MMC +static int mmc_map_to_kernel_blk(int dev_no) +{ + return dev_no + 1; +} +#endif + +static int usdhc2_cd_gpio[] = { + /* DART */ + IMX_GPIO_NR(1, 6), + /* Non-DART */ + IMX_GPIO_NR(4, 14) +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int board = is_dart_board() ? 0 : 1; + + /* SD card */ + if (cfg->esdhc_base == USDHC2_BASE_ADDR) { + return !gpio_get_value(usdhc2_cd_gpio[board]); + } + + /* + * On DART SOMs eMMC is always present. + * + * On non DART SOMs eMMC can be present or not, + * but we can't know until we try to init it + * so return 1 here anyway + */ + return 1; +} + +#ifdef CONFIG_SPL_BUILD +enum mmc_boot_device { + USDHC1, + USDHC2, + USDHC3, + USDHC4, +}; + +static enum mmc_boot_device get_mmc_boot_device(void) +{ + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned reg = readl(&psrc->sbmr1) >> 11; + /* + * Upon reading BOOT_CFG register + * Bit 11 and 12 of BOOT_CFG register can determine the current + * mmc port + */ + + return (reg & 0x3); +} +#endif + +int board_mmc_init(bd_t *bis) +{ +#ifndef CONFIG_SPL_BUILD + int ret, i, board; + + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * On non DART boards: + * mmc0 SD2 (SD) + * mmc1 SD1 (eMMC) + * + * On DART board: + * mmc0 SD2 (SD) + * mmc1 SD3 (eMMC) + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc2_pads); + + board = is_dart_board() ? 0 : 1; + SETUP_IOMUX_PADS(usdhc2_cd_pad[board]); + gpio_direction_input(usdhc2_cd_gpio[board]); + + usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + usdhc_cfg[0].max_bus_width = 4; + break; + case 1: + if (is_dart_board()) { + SETUP_IOMUX_PADS(usdhc3_pads); + usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + } else { + SETUP_IOMUX_PADS(usdhc1_pads); + usdhc_cfg[1].esdhc_base = USDHC1_BASE_ADDR; + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + } + usdhc_cfg[1].max_bus_width = 4; + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) then supported by the board (%d)\n", + i + 1, CONFIG_SYS_FSL_USDHC_NUM); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + return 0; +#else + /* + * Possible MMC boot devices: + * SD2 (SD) + * SD3 (DART eMMC) + */ + puts("MMC Boot Device: "); + switch (get_mmc_boot_device()) { + case USDHC2: + puts("mmc0 (SD)\n"); + SETUP_IOMUX_PADS(usdhc2_pads); + usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + usdhc_cfg[0].max_bus_width = 4; + break; + case USDHC3: + puts("mmc1 (eMMC)\n"); + SETUP_IOMUX_PADS(usdhc3_pads); + usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + usdhc_cfg[0].max_bus_width = 4; + break; + default: + break; + } + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +#endif +} +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC +static void mmc_late_init(void) +{ + char cmd[32]; + char mmcblk[32]; + u32 dev_no = mmc_get_env_dev(); + + if (!check_env("mmcautodetect", "yes")) + return; + + setenv_ulong("mmcdev", dev_no); + + /* Set mmcroot env */ + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", + mmc_map_to_kernel_blk(dev_no)); + setenv("mmcroot", mmcblk); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} +#endif + +#ifdef CONFIG_SYS_USE_NAND +static iomux_v3_cfg_t const gpmi_pads[] = { + IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)), + IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1)), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + SETUP_IOMUX_PADS(gpmi_pads); + + /* gate ENFC_CLK_ROOT clock first,before clk source switch */ + clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); + + /* config gpmi and bch clock to 100 MHz */ + clrsetbits_le32(&mxc_ccm->cs2cdr, + MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, + MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); + + /* enable ENFC_CLK_ROOT clock */ + setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); + + /* enable gpmi and bch clock gating */ + setbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + + /* manually configure PHY as master during master-slave negotiation */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x9, 0x1c00); + + /* control data pad skew */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); + /* rx data pad skew */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); + /* tx data pad skew */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); + /* gtx and rx clock pad skew */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF); + + return 0; +} + +#if defined(CONFIG_VIDEO_IPUV3) +static void disable_lvds(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + int reg = readl(&iomux->gpr[2]); + + reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK | + IOMUXC_GPR2_LVDS_CH1_MODE_MASK); + + writel(reg, &iomux->gpr[2]); +} + +static void do_enable_hdmi(struct display_info_t const *dev) +{ + disable_lvds(dev); + /* + * imx_enable_hdmi_phy(); should be called here. + * It is ommitted to avoid a current known bug where + * the boot sometimes hangs if an HDMI cable is attached + * - at least on some SOMs. + */ +} + +static void lvds_enable_disable(struct display_info_t const *dev) +{ + if (getenv("splashimage") != NULL) + lvds_enabled=true; + else + disable_lvds(dev); +} + +static int detect_dart_vsc_display(struct display_info_t const *dev) +{ + return (!is_mx6_custom_board()); +} + +static int detect_mx6cb_cdisplay(struct display_info_t const *dev) +{ + if (!is_mx6_custom_board()) + return 0; + + i2c_set_bus_num(dev->bus); + return (0 == i2c_probe(dev->addr)); +} + +static int detect_mx6cb_rdisplay(struct display_info_t const *dev) +{ + if (!is_mx6_custom_board()) + return 0; + + /* i2c probe the *c*display */ + i2c_set_bus_num(MX6CB_CDISPLAY_I2C_BUS); + return (0 != i2c_probe(MX6CB_CDISPLAY_I2C_ADDR)); +} + +#define MHZ2PS(f) (1000000/(f)) + +struct display_info_t const displays[] = {{ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = do_enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, /* optional */ + .xres = 800, + .yres = 480, + .pixclock = 31777, + .left_margin = 48, + .right_margin = 16, + .upper_margin = 33, + .lower_margin = 10, + .hsync_len = 96, + .vsync_len = 2, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB666, + .detect = detect_dart_vsc_display, + .enable = lvds_enable_disable, + .mode = { + .name = "VAR-WVGA", + .refresh = 60, /* optional */ + .xres = 800, + .yres = 480, + .pixclock = MHZ2PS(50), + .left_margin = 40, + .right_margin = 40, + .upper_margin = 29, + .lower_margin = 13, + .hsync_len = 48, + .vsync_len = 3, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = MX6CB_CDISPLAY_I2C_BUS, + .addr = MX6CB_CDISPLAY_I2C_ADDR, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_mx6cb_cdisplay, + .enable = lvds_enable_disable, + .mode = { + .name = "VAR-WVGA MX6CB-C", + .refresh = 60, /* optional */ + .xres = 800, + .yres = 480, + .pixclock = MHZ2PS(50), + .left_margin = 39, + .right_margin = 39, + .upper_margin = 29, + .lower_margin = 13, + .hsync_len = 128, + .vsync_len = 2, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_mx6cb_rdisplay, + .enable = lvds_enable_disable, + .mode = { + .name = "VAR-WVGA MX6CB-R", + .refresh = 60, /* optional */ + .xres = 800, + .yres = 480, + .pixclock = MHZ2PS(50), + .left_margin = 0, + .right_margin = 40, + .upper_margin = 20, + .lower_margin = 13, + .hsync_len = 48, + .vsync_len = 3, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} } }; + +size_t display_count = ARRAY_SIZE(displays); + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + int reg; + + /* Setup backlight */ + SETUP_IOMUX_PAD(PAD_DISP0_DAT9__GPIO4_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)); + + /* Turn off backlight until display is ready */ + gpio_direction_output(VAR_SOM_BACKLIGHT_EN , 0); + + enable_ipu_clock(); + imx_setup_hdmi(); + + /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */ + reg = readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; + writel(reg, &mxc_ccm->CCGR3); + + /* set LDB0, LDB1 clk select to 011/011 */ + reg = readl(&mxc_ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK + | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + /* 1 -> ~50MHz , 2 -> ~56MHz, 3 -> ~75MHz, 4 -> ~68MHz */ + reg |= (1 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) + | (1 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->cs2cdr); + + reg = readl(&mxc_ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; + writel(reg, &mxc_ccm->cscmr2); + + reg = readl(&mxc_ccm->chsccdr); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->chsccdr); + + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES + | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW + | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW + | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG + | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT + | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT + | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 + | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[2]); + + reg = readl(&iomux->gpr[3]); + reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK | IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET); + writel(reg, &iomux->gpr[3]); +} +#endif /* CONFIG_VIDEO_IPUV3 */ + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +int board_eth_init(bd_t *bis) +{ + uint32_t base = IMX_FEC_BASE; + struct mii_dev *bus = NULL; + struct phy_device *phydev = NULL; + int ret; + + setup_iomux_enet(); + +#ifdef CONFIG_FEC_MXC + bus = fec_get_miibus(base, -1); + if (!bus) { + printf("FEC MXC bus: %s:failed\n", __func__); + return 0; + } + + phydev = phy_find_by_mask(bus, (0x1 << CONFIG_FEC_MXC_PHYADDR), PHY_INTERFACE_MODE_RGMII); + if (!phydev) { + printf("FEC MXC phy find: %s:failed\n", __func__); + free(bus); + return 0; + } + printf("using phy at %d\n", phydev->addr); + + ret = fec_probe(bis, -1, base, bus, phydev); + if (ret) { + printf("FEC MXC probe: %s:failed\n", __func__); + free(phydev); + free(bus); + } +#endif + +#if defined(CONFIG_CI_UDC) && defined(CONFIG_USB_ETHER) + /* USB Ethernet Gadget */ + usb_eth_initialize(bis); +#endif + + return 0; +} + +#ifdef CONFIG_USB_EHCI_MX6 +static int const usb_otg_pwr_en_gpio[] = { + /* DART */ + IMX_GPIO_NR(4, 15), + /* SOLOCustomBoard */ + IMX_GPIO_NR(3, 22), +}; + +static int const usb_h1_pwr_en_gpio[] = { + /* DART */ + IMX_GPIO_NR(1, 28), + /* SOLOCustomBoard */ + IMX_GPIO_NR(4, 15), +}; + +static iomux_v3_cfg_t const usb_pads[][3*2] = { + { + /* DART */ + IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)), + }, + { + /* SOLOCustomBoard */ + IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)), + } +}; + +static void setup_usb(void) +{ + int board = get_board_indx(); + if (board == MX6_CUSTOM_BOARD) + return; + + SETUP_IOMUX_PADS(usb_pads[board]); + gpio_direction_output(usb_otg_pwr_en_gpio[board], 0); + gpio_direction_output(usb_h1_pwr_en_gpio[board], 0); + + if (board == DART_BOARD) + imx_iomux_set_gpr_register(1, 13, 1, 0); + else if (board == SOLO_CUSTOM_BOARD) + imx_iomux_set_gpr_register(1, 13, 1, 1); +} + +int board_usb_phy_mode(int port) +{ + if (is_mx6_custom_board() && port == 0) { + if (check_env("usbmode", "host")) + return USB_INIT_HOST; + else + return USB_INIT_DEVICE; + } + return usb_phy_mode(port); +} + +int board_ehci_power(int port, int on) +{ + int board = get_board_indx(); + if (board == MX6_CUSTOM_BOARD) + return 0; /* no power enable needed */ + + if (port > 1) + return -EINVAL; + + if (port) + gpio_set_value(usb_h1_pwr_en_gpio[board], on); + else + gpio_set_value(usb_otg_pwr_en_gpio[board], on); + + return 0; +} +#endif /* CONFIG_USB_EHCI_MX6 */ + +int board_early_init_f(void) +{ + setup_iomux_uart(); +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif +#ifdef CONFIG_SYS_I2C_MXC + setup_local_i2c(); +#endif +#ifdef CONFIG_SYS_USE_NAND + setup_gpmi_nand(); +#endif + + return 0; +} + +int board_init(void) +{ + int ret = 0; + + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_arch_number = CONFIG_MACH_VAR_SOM_MX6; + +#ifdef CONFIG_USB_EHCI_MX6 + setup_usb(); +#endif + return ret; +} + +static struct pmic *pfuze; + +struct pmic_write_values { + u32 reg; + u32 mask; + u32 writeval; +}; + +static int pmic_write_val(struct pmic *p, struct pmic_write_values pmic_struct) +{ + unsigned int val = 0; + int retval = 0; + + if (!p) { + printf("No PMIC found!\n"); + return -1; + } + + retval += pmic_reg_read(p, pmic_struct.reg, &val); + val &= ~(pmic_struct.mask); + val |= pmic_struct.writeval; + retval += pmic_reg_write(p, pmic_struct.reg, val); + + if (retval) + printf("PMIC write voltages error!\n"); + + return retval; +} + +static int pmic_write_vals(struct pmic *p, struct pmic_write_values *arr, int arr_size) +{ + int i, retval; + + for (i = 0; i < arr_size; ++i) { + retval = pmic_write_val(p, arr[i]); + if (retval) + return retval; + } + + return 0; +} + +static void set_anatop_bypass(void) +{ + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + u32 reg = readl(&anatop->reg_core); + + /* bypass VDDARM/VDDSOC */ + reg |= (0x1F << 18) | 0x1F; + writel(reg, &anatop->reg_core); +} + +static void ldo_mode_set(void) +{ + if (!is_som_solo()) { + struct pmic *p = pfuze; + + struct pmic_write_values ldo_mode_arr[] = { + /* Set SW1AB to 1.325V */ + {PFUZE100_SW1ABVOL, SW1x_NORMAL_MASK, SW1x_1_325V}, + /* Set SW1C to 1.325V */ + {PFUZE100_SW1CVOL, SW1x_NORMAL_MASK, SW1x_1_325V} + }; + + if (pmic_write_vals(p, ldo_mode_arr, ARRAY_SIZE(ldo_mode_arr))) + return; + + set_anatop_bypass(); + printf("switch to ldo_bypass mode!\n"); + } +} + +int power_init_board(void) +{ + if (!is_som_solo()) { + unsigned int reg; + int retval; + + retval = power_pfuze100_init(PMIC_I2C_BUS); + if (retval) + return -ENODEV; + pfuze = pmic_get("PFUZE100"); + retval = pmic_probe(pfuze); + if (retval) + return -ENODEV; + pmic_reg_read(pfuze, PFUZE100_DEVICEID, &reg); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + + if (is_dart_board()) { + + struct pmic_write_values dart_pmic_arr[] = { + /* Set SW1AB standby volage to 0.9V */ + {PFUZE100_SW1ABSTBY, SW1x_STBY_MASK, SW1x_0_900V}, + + /* Set SW1AB off volage to 0.9V */ + {PFUZE100_SW1ABOFF, SW1x_OFF_MASK, SW1x_0_900V}, + + /* Set SW1C standby voltage to 0.9V */ + {PFUZE100_SW1CSTBY, SW1x_STBY_MASK, SW1x_0_900V}, + + /* Set SW1C off volage to 0.9V */ + {PFUZE100_SW1COFF, SW1x_OFF_MASK, SW1x_0_900V}, + + /* Set SW2 to 3.3V */ + {PFUZE100_SW2VOL, SWx_NORMAL_MASK, SWx_HR_3_300V}, + + /* Set SW2 standby voltage to 3.2V */ + {PFUZE100_SW2STBY, SWx_STBY_MASK, SWx_HR_3_200V}, + + /* Set SW2 off voltage to 3.2V */ + {PFUZE100_SW2OFF, SWx_OFF_MASK, SWx_HR_3_200V}, + + /* Set SW1AB/VDDARM step ramp up time 2us */ + {PFUZE100_SW1ABCONF, SW1xCONF_DVSSPEED_MASK, SW1xCONF_DVSSPEED_2US}, + + /* Set SW1AB, SW1C, SW2 normal mode to PWM, and standby mode to PFM */ + {PFUZE100_SW1ABMODE, SW_MODE_MASK, PWM_PFM}, + {PFUZE100_SW1CMODE, SW_MODE_MASK, PWM_PFM}, + {PFUZE100_SW2MODE, SW_MODE_MASK, PWM_PFM}, + + /* Set VGEN6 to 3.3V */ + {PFUZE100_VGEN6VOL, LDO_VOL_MASK, LDOB_3_30V} + }; + + retval = pmic_write_vals(pfuze, dart_pmic_arr, ARRAY_SIZE(dart_pmic_arr)); + + } else { + + struct pmic_write_values pmic_arr[] = { + /* Set SW1AB standby volage to 0.975V */ + {PFUZE100_SW1ABSTBY, SW1x_STBY_MASK, SW1x_0_975V}, + + /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + {PFUZE100_SW1ABCONF, SW1xCONF_DVSSPEED_MASK, SW1xCONF_DVSSPEED_4US}, + + /* Set SW1C standby voltage to 0.975V */ + {PFUZE100_SW1CSTBY, SW1x_STBY_MASK, SW1x_0_975V}, + + /* Set Gigbit Ethernet voltage */ + {PFUZE100_SW4VOL, SWx_NORMAL_MASK, SWx_LR_1_200V}, + + /* Increase VGEN5 from 2.8 to 3V */ + {PFUZE100_VGEN5VOL, LDO_VOL_MASK, LDOB_3_00V}, + + /* Set VGEN3 to 2.5V */ + {PFUZE100_VGEN3VOL, LDO_VOL_MASK, LDOB_2_50V}, +#ifdef LOW_POWER_MODE_ENABLE + /* Set low power mode voltages to disable */ + + /* Set SW2 to 3.2V */ + {PFUZE100_SW2VOL, SWx_NORMAL_MASK, SWx_HR_3_200V}, + + /* Set SW3A standby voltage to 1.275V */ + {PFUZE100_SW3ASTBY, SWx_STBY_MASK, SWx_LR_1_275V}, + + /* Set SW3A off voltage to 1.275V */ + {PFUZE100_SW3AOFF, SWx_OFF_MASK, SWx_LR_1_275V}, + + /* SW4MODE = OFF in standby */ + {PFUZE100_SW4MODE, SW_MODE_MASK, PWM_OFF}, + + /* Set VGEN3CTL = OFF in standby */ + {PFUZE100_VGEN3VOL, (LDO_MODE_MASK | LDO_EXT_MODE_MASK), \ + (LDO_EN | LDO_EXT_MODE_ON_OFF << LDO_EXT_MODE_SHIFT)} +#else + /* Set VGEN3CTL = low power in standby */ + {PFUZE100_VGEN3VOL, (LDO_MODE_MASK | LDO_EXT_MODE_MASK), \ + (LDO_EN | LDO_EXT_MODE_ON_LPM << LDO_EXT_MODE_SHIFT)} +#endif + }; + + retval = pmic_write_vals(pfuze, pmic_arr, ARRAY_SIZE(pmic_arr)); + } + + /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ + retval += pmic_write_val(pfuze, + (struct pmic_write_values) + {PFUZE100_SW1CCONF, SW1xCONF_DVSSPEED_MASK, SW1xCONF_DVSSPEED_4US}); + + if (retval) + return retval; + + ldo_mode_set(); + } + + return 0; +} + +static void imx6_pcie_assert_core_reset(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + if (is_mx6dqp()) + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST); + + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); + clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); +} + +static void imx6_pcie_init_phy(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE); + + clrsetbits_le32(&iomuxc_regs->gpr[12], + IOMUXC_GPR12_DEVICE_TYPE_MASK, + IOMUXC_GPR12_DEVICE_TYPE_RC); + clrsetbits_le32(&iomuxc_regs->gpr[12], + IOMUXC_GPR12_LOS_LEVEL_MASK, + IOMUXC_GPR12_LOS_LEVEL_9); + + writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) | + (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) | + (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) | + (127 << IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET) | + (127 << IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET), + &iomuxc_regs->gpr[8]); +} + +static void imx6_pcie_deassert_core_reset(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + if (is_mx6dqp()) + clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST); + + /* + * Wait for the clock to settle a bit, when the clock are sourced + * from the CPU, we need about 30 ms to settle. + */ + mdelay(50); + + /* Enable PCIe */ + clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); +} + +/* + * Init the PCIe phy in order to prevent a soft reboot hang + */ +static void imx_pcie_reset(void) +{ + imx6_pcie_assert_core_reset(); + imx6_pcie_init_phy(); + imx6_pcie_deassert_core_reset(); +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_IS_IN_MMC + mmc_late_init(); +#endif + print_emmc_size(); + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + if (is_dart_board()) + setenv("board_name", "DT6CUSTOM"); + else if (is_solo_custom_board()) + setenv("board_name", "SOLOCUSTOM"); + else + setenv("board_name", "MX6CUSTOM"); + + if (is_som_solo()) + setenv("board_som", "SOM-SOLO"); + else if (is_dart_board()) + setenv("board_som", "DART-MX6"); + else + setenv("board_som", "SOM-MX6"); + + if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) + setenv("board_rev", "MX6Q"); + else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO)) + setenv("board_rev", "MX6DL"); +#endif + + imx_pcie_reset(); + + return 0; +} + +int checkboard(void) +{ + puts("Board: Variscite VAR-SOM-MX6 "); + + switch (get_cpu_type()) { + case MXC_CPU_MX6Q: + puts("Quad"); + if (is_cpu_pop_packaged()) + puts("-PoP"); + break; + case MXC_CPU_MX6D: + puts("Dual"); + if (is_cpu_pop_packaged()) + puts("-PoP"); + break; + case MXC_CPU_MX6DL: + if (is_som_solo()) + puts("SOM-Dual"); + else + puts("Dual Lite"); + break; + case MXC_CPU_MX6SOLO: + if (is_som_solo()) + puts("SOM-Solo"); + else + puts("Solo"); + break; + default: + puts("????"); + break; + } + puts("\n"); + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +#include <spl.h> +#include <libfdt.h> +#include <asm/arch/mx6-ddr.h> + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0x00FFF300, &ccm->CCGR4); + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +static void gpr_init(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* enable AXI cache for VDOA/VPU/IPU */ + writel(0xF00000CF, &iomux->gpr[4]); + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ + writel(0x007F007F, &iomux->gpr[6]); + writel(0x007F007F, &iomux->gpr[7]); +} + +static void setup_iomux_var_per_vcc_en(void) +{ + SETUP_IOMUX_PAD(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(PER_VCC_EN_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(3, 31), 1); +} + +static void setup_iomux_audiocodec(void) +{ + SETUP_IOMUX_PAD(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(4, 5), 1); +} + +static void audiocodec_reset(int rst) +{ + gpio_set_value(IMX_GPIO_NR(4, 5), !rst); +} + +/* + * Bugfix: Fix Freescale wrong processor documentation. + */ +static void spl_mx6qd_dram_setup_iomux_check_reset(void) +{ + if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) { + volatile struct mx6dq_iomux_ddr_regs *mx6dq_ddr_iomux; + + mx6dq_ddr_iomux = (struct mx6dq_iomux_ddr_regs *) MX6DQ_IOM_DDR_BASE; + + if (mx6dq_ddr_iomux->dram_reset == (u32)0x000C0030) + mx6dq_ddr_iomux->dram_reset = (u32)0x00000030; + } +} + +static void spl_dram_init(void) +{ + int err = is_dart_board() ? + var_eeprom_v2_dram_init() : + var_eeprom_v1_dram_init(); + + if (err) { + printf("Error initializing RAM using EEPROM\n"); + hang(); + } + spl_mx6qd_dram_setup_iomux_check_reset(); +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + gpr_init(); + + setup_iomux_var_per_vcc_en(); + setup_iomux_audiocodec(); + audiocodec_reset(1); + + /* iomux and setup of i2c */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + mdelay(330); + + audiocodec_reset(0); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} +#endif diff --git a/board/variscite/mx6var_som/values.inc b/board/variscite/mx6var_som/values.inc new file mode 100644 index 0000000..aafc088 --- /dev/null +++ b/board/variscite/mx6var_som/values.inc @@ -0,0 +1,39 @@ +0x00000000,0x00000010,0x00000013,0x00000017, +0x00000027,0x00000028,0x00000030,0x00000038, +0x00000047,0x00000053,0x00000080,0x000000DD, +0x0000020E,0x00000800,0x00001740,0x0000174C, +0x00001800,0x000026D2,0x00003000,0x00003030, +0x00005800,0x00007800,0x00008000,0x00008033, +0x0000803B,0x00011006,0x00011117,0x00011740, +0x00020000,0x00020025,0x0002002D,0x00020036, +0x00022227,0x00025565,0x0002556D,0x00025576, +0x00048031,0x00048039,0x00080000,0x00081740, +0x000C0000,0x000C0030,0x00130029,0x00160E83, +0x0019002E,0x001C0019,0x001D002C,0x001F0019, +0x001F001F,0x001F002B,0x00220AAC,0x0024001F, +0x00260026,0x00333030,0x00333040,0x003F1023, +0x003F8030,0x003F8038,0x00400000,0x00431023, +0x00450000,0x005A1023,0x006B1023,0x008E1023, +0x008F1023,0x017B017A,0x01FF00DB,0x02008032, +0x0200803A,0x02038030,0x02088032,0x0208803A, +0x0214021C,0x021B08B8,0x02280228,0x02300238, +0x02580258,0x03038038,0x03200314,0x032C0278, +0x033C0350,0x04008032,0x0400803A,0x04008040, +0x04008048,0x04088032,0x0408803A,0x05208030, +0x05208038,0x052C0470,0x052C0520,0x06028030, +0x06028038,0x07208030,0x09408030,0x09444040, +0x0F9F26D2,0x11420000,0x15208030,0x15208038, +0x19408030,0x19408038,0x1B5F01FF,0x20000000, +0x24911492,0x24921492,0x2B35382B,0x3234342C, +0x33333333,0x38362E32,0x38363236,0x38383E3A, +0x3A363446,0x3A38443C,0x3A3F7975,0x3E363A40, +0x3E373A3C,0x3E463E40,0x3F435313,0x4036363A, +0x403C3246,0x40404040,0x421C0216,0x421C0228, +0x423D3843,0x42440244,0x43240334,0x432C0340, +0x4528053C,0x45300544,0x454A61A5,0x46344840, +0x48364A3E,0x484A4C4A,0x4B2B4842,0x4B4A4E4C, +0x555A7974,0x676B5313,0x821A0000,0x83110000, +0x831A0000,0x84190000,0x841A0000,0x8A8F7955, +0xA1390003,0xB66D8B63,0xB66E8B63,0xC2018030, +0xC2018038,0xC41A0000,0xDB538F64,0xF3333333, +0xFF0A8030,0xFF0A8038,0xFF328F64,0xFFFFFFFF diff --git a/configs/mx6var_som_nand_defconfig b/configs/mx6var_som_nand_defconfig new file mode 100644 index 0000000..1a38095 --- /dev/null +++ b/configs/mx6var_som_nand_defconfig @@ -0,0 +1,31 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6VAR_SOM=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6QDL,SYS_BOOT_NAND" +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Variscite" +CONFIG_G_DNL_VENDOR_NUM=0x0525 +CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 +CONFIG_OF_LIBFDT=y diff --git a/configs/mx6var_som_sd_defconfig b/configs/mx6var_som_sd_defconfig new file mode 100644 index 0000000..6ccac65 --- /dev/null +++ b/configs/mx6var_som_sd_defconfig @@ -0,0 +1,31 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6VAR_SOM=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6QDL" +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Variscite" +CONFIG_G_DNL_VENDOR_NUM=0x0525 +CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 +CONFIG_OF_LIBFDT=y diff --git a/include/configs/mx6var_som.h b/include/configs/mx6var_som.h new file mode 100644 index 0000000..1860502 --- /dev/null +++ b/include/configs/mx6var_som.h @@ -0,0 +1,429 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2016 Variscite Ltd. All Rights Reserved. + * + * Author: Eran Matityahu <eran.m(a)variscite.com> + * + * Configuration settings for Variscite VAR-SOM-MX6 board family. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX6VAR_SOM_CONFIG_H +#define __MX6VAR_SOM_CONFIG_H + +#ifdef CONFIG_SPL +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#ifdef CONFIG_SYS_BOOT_NAND +#define CONFIG_SPL_NAND_SUPPORT +#else +#define CONFIG_SPL_MMC_SUPPORT +#endif +#include "imx6_spl.h" +#endif +#include "mx6_common.h" + +/* Address of reserved 4Bytes in OCRAM for sending RAM size from SPL to U-Boot */ +#define RAM_SIZE_ADDR ((CONFIG_SPL_TEXT_BASE) + (CONFIG_SPL_MAX_SIZE)) + +#define CONFIG_MACH_VAR_SOM_MX6 4419 +#define CONFIG_MACH_TYPE CONFIG_MACH_VAR_SOM_MX6 + +#define CONFIG_MXC_UART_BASE UART1_BASE +#define CONFIG_CONSOLE_DEV "ttymxc0" +#define CONFIG_MMCROOT "/dev/mmcblk0p2" + +#define CONFIG_IMX_THERMAL + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_SILENT_CONSOLE + +#define CONFIG_MXC_UART + +#define LOW_POWER_MODE_ENABLE + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 0 +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* Ethernet Configs */ +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 7 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL + +#ifdef CONFIG_BOOTDELAY +#undef CONFIG_BOOTDELAY +#endif +#define CONFIG_BOOTDELAY 1 + +#ifdef CONFIG_SYS_BOOT_NAND +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:16m(boot),16m(kernel),16m(dtb),-(rootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif + +#ifdef CONFIG_SYS_BOOT_NAND +#define MMC_DEV_SET " " +#else +#define MMC_DEV_SET "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) +#endif + +#define MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + "enable_wait_mode=off "\ + MFG_NAND_PARTITION \ + "\0" \ + "initrd_addr=0x12C00000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;bootm ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define MMC_BOOT_ENV_SETTINGS \ + "uimage=uImage\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + MMC_DEV_SET \ + "\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot}; " \ + "run videoargs\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadfdt=run findfdt; " \ + "fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootm; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootm; " \ + "fi;\0" \ + + +#define NAND_BOOT_ENV_SETTINGS \ + "bootargs_nand=setenv bootargs console=${console},${baudrate} ubi.mtd=3 " \ + "root=ubi0:rootfs rootfstype=ubifs; " \ + "run videoargs\0" \ + "bootargs_emmc=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/mmcblk0p1 rootwait rw; " \ + "run videoargs\0" \ + "rootfs_device=nand\0" \ + "bootcmd=" \ + "if test ${rootfs_device} != emmc; then " \ + "run bootargs_nand; " \ + "else " \ + "run bootargs_emmc; " \ + "fi; " \ + "nand read ${loadaddr} 0x400000 0x600000;" \ + "nand read ${fdt_addr} 0x3e0000 0x20000;" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + + +#ifdef CONFIG_SYS_BOOT_NAND +#define BOOT_ENV_SETTINGS NAND_BOOT_ENV_SETTINGS +#else +#define BOOT_ENV_SETTINGS MMC_BOOT_ENV_SETTINGS +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else " \ + "run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" +#endif + + +#define CONFIG_EXTRA_ENV_SETTINGS \ + MFG_ENV_SETTINGS \ + BOOT_ENV_SETTINGS \ + "fdt_file=undefined\0" \ + "fdt_addr=0x18000000\0" \ + "fdt_high=0xffffffff\0" \ + "splashsourceauto=yes\0" \ + "splashfile=/boot/splash.bmp\0" \ + "splashimage=0x18100000\0" \ + "splashenable=setenv splashfile /boot/splash.bmp; " \ + "setenv splashimage 0x18100000\0" \ + "splashdisable=setenv splashfile; setenv splashimage\0" \ + "console=" CONFIG_CONSOLE_DEV "\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs rw " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp; " \ + "run videoargs\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${uimage}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "run findfdt; " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootm; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootm; " \ + "fi;\0" \ + "videoargs=" \ + "if hdmidet; then " \ + "setenv bootargs ${bootargs} " \ + "video=mxcfb0:dev=hdmi,1920x1080M@60,if=RGB24; " \ + "fi; " \ + "setenv bootargs ${bootargs} " \ + "video=mxcfb1:off;\0" \ + "findfdt="\ + "if test $fdt_file = undefined; then " \ + "if test $board_name = DT6CUSTOM && test $board_rev = MX6Q; then " \ + "setenv fdt_file imx6q-var-dart.dtb; " \ + "fi; " \ + "if test $board_name = SOLOCUSTOM && test $board_rev = MX6Q; then " \ + "setenv fdt_file imx6q-var-som-vsc.dtb; " \ + "fi; " \ + "if test $board_name = SOLOCUSTOM && test $board_rev = MX6DL && test $board_som = SOM-SOLO; then " \ + "setenv fdt_file imx6dl-var-som-solo-vsc.dtb; " \ + "fi; " \ + "if test $board_name = SOLOCUSTOM && test $board_rev = MX6DL && test $board_som = SOM-MX6; then " \ + "setenv fdt_file imx6dl-var-som-vsc.dtb; " \ + "fi; " \ + "if test $board_name = MX6CUSTOM && test $board_rev = MX6Q; then " \ + "i2c dev 2; " \ + "if i2c probe 0x38; then " \ + "setenv fdt_file imx6q-var-som-cap.dtb; " \ + "else " \ + "setenv fdt_file imx6q-var-som-res.dtb; " \ + "fi; " \ + "fi; " \ + "if test $board_name = MX6CUSTOM && test $board_rev = MX6DL && test $board_som = SOM-SOLO; then " \ + "i2c dev 2; " \ + "if i2c probe 0x38; then " \ + "setenv fdt_file imx6dl-var-som-solo-cap.dtb; " \ + "else " \ + "setenv fdt_file imx6dl-var-som-solo-res.dtb; " \ + "fi; " \ + "fi; " \ + "if test $board_name = MX6CUSTOM && test $board_rev = MX6DL && test $board_som = SOM-MX6; then " \ + "i2c dev 2; " \ + "if i2c probe 0x38; then " \ + "setenv fdt_file imx6dl-var-som-cap.dtb; " \ + "else " \ + "setenv fdt_file imx6dl-var-som-res.dtb; " \ + "fi; " \ + "fi; " \ + "if test $fdt_file = undefined; then " \ + "echo WARNING: Could not determine dtb to use; " \ + "fi; " \ + "fi;\0" + + +#define CONFIG_ARP_TIMEOUT 200UL + +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x10010000 +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 + +#define CONFIG_STACKSIZE (128 * 1024) + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_ENV_SIZE (8 * 1024) + +#ifdef CONFIG_SYS_BOOT_NAND +#define CONFIG_SYS_USE_NAND +#define CONFIG_ENV_IS_IN_NAND +/* NAND boot config */ +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#else +#define CONFIG_ENV_IS_IN_MMC +#endif + +#ifdef CONFIG_SYS_USE_NAND +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS + +/* UBI/UBIFS support */ +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_UBI_SILENCE_MSG +#define CONFIG_UBIFS_SILENCE_MSG +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_LZO + +#define MTDIDS_DEFAULT "nand0=nandflash-0" + +/* + * Partions' layout for NAND is: + * mtd0: 2M (spl) First boot loader + * mtd1: 2M (u-boot, dtb) + * mtd2: 6M (kernel) + * mtd4: left (rootfs) + */ +/* Default mtd partition table */ +#define MTDPARTS_DEFAULT "mtdparts=nandflash-0:"\ + "2m(spl),"\ + "2m(u-boot),"\ + "6m(kernel),"\ + "-(rootfs)" /* ubifs */ + +/* NAND stuff */ +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 +#endif + +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (0x3E0000) +#elif defined(CONFIG_ENV_IS_IN_NAND) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET (0x180000) +#define CONFIG_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif + +/* Framebuffer */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_SPLASH_SOURCE +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#ifdef CONFIG_MX6DL +#define CONFIG_IPUV3_CLK 198000000 +#else +#define CONFIG_IPUV3_CLK 264000000 +#endif +#define CONFIG_IMX_HDMI +#define CONFIG_CMD_HDMIDETECT +#define CONFIG_IMX_VIDEO_SKIP +#define CONFIG_CMD_BMP + +#define PMIC_I2C_BUS 1 +#define MX6CB_CDISPLAY_I2C_BUS 2 +#define MX6CB_CDISPLAY_I2C_ADDR 0x38 + +/* I2C Configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ +#endif + +#define CONFIG_USBD_HS + +/* Uncomment for USB Ethernet Gadget support */ +/* + * #define CONFIG_USB_ETHER + * #define CONFIG_USB_ETH_CDC + */ +#define CONFIG_NETCONSOLE + +#define CONFIG_USB_FUNCTION_MASS_STORAGE + +/* USB Device Firmware Update support */ +#define CONFIG_CMD_DFU +#define CONFIG_USB_FUNCTION_DFU +#define CONFIG_DFU_MMC +#define CONFIG_DFU_RAM +#ifdef CONFIG_SYS_USE_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_DFU_NAND +#endif + +#endif /* __MX6VAR_SOM_CONFIG_H */ diff --git a/tools/logos/variscite.bmp b/tools/logos/variscite.bmp new file mode 100644 index 0000000000000000000000000000000000000000..f3ca27ceb169cd5d174fa919248968877cb0e3d3 GIT binary patch literal 15414 zcmeHO34B!LwU2kgL_-?_NHAh*x%YW*oFT>rL2W@1H!9Ey5zD@apnzf#MH;{mV~o*= z6n&VdJdo9}8iv3iVKoq03NnF<0ok<4kPu*!FqZ;F&pYRQ_s(MTMEYxgCYA$t`Id9; z`G05m&Nuw%+OuP)2&Rsa5fO>_b{wxRcwG~5E#3ufjfse$3p>RX5dj^4l?)wIQsAyT z+QYB!>IlEN^DgLo_uX*cJ)NOzmwVy<d%M5`UAscJ2Oos)-5!SS4|ju}k30gse%BNF z^zIFP`#c5%`}KpNg9pQtLx;fdAw%KGVZ&h5$dNGm>8IeCQKMnp*s<{9`0?<k2@_yS zS{lsxLnO@ZE5V${uY>uiHkkLg1Pkz*pV|aIO0{D<65ElGkA3-%H-ULLcR}B4@EHjU z@ye%n<jp7kzSqKne%ImkGnn5m78dny4)X>#hlPXiIiM9R=pP632DXMpgIYoUpcb&C z|MjqVa2zZeasw<JoB&G(-vEn;;`p$eVezmVVZm@27C+GzmJgF*=|~xtjc5z`Puv1a zM%;q$x4??gDtt5|5ta;3gym1&3d=@2VdW?XEFY5sE1yY$g3))t%4hF@6@Tmit`|DN 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zu%<FYF#LhwVaYSy;`ipXiJ>2NBBPq6xvWkd&z|Y&s9t$S4E{1hR?riO(yYzM_c5}e zi`k>&vUH1$p5C1JXzY)SzA?v|Yj}utcp8bxPEViA_?prebmBnr6%LQVIw~@{O+W=P z5O!yLRS!`~swn-%(2H1$5ha@Kw`FdoYzX1>>pR?T^Sl$%O|O1D42AxT7dq_I-EMbj z07P)e>p^kf4W8hzI3ES_r#V2<Jg0-R>Um>)#sn_H<UDp?OehW!aCh!yj;$$VKP5G^ zbgoC#zq8A%&#wFvjL*OQmx+q3bfV4OFgE`Ze}us*9Lt$m)b>}UI`P*F<sEALNF*ZJ zsz0wl31Ppwr!_~Sqd%L^pX<=tX>`g^<RQ2N`u)bAR6H_v5ta89$o>~j6_vt2i?7aq zpaX7sd47x?qq>ixa{S4fe2=hbaSB=&M}Isr?RVu02>ThvbXmPifZ2Jw?9}j(@078a zo6Wx^R;D_&{{MgQU-?(Bn4{EA6!zo550hcxs~)Tls3DfxcPW{eq>L0lmQK{}quTmM zBrj5VJ$d(XDp~l9&wu;J%^NmsE?VDT>;}9gC=aaNRE)hJbk674yqvU#Hy*%eY<Z}i znv|s7Do((b1vM;elC;hrG(63Jm_|W-#<t#6XR4xjG4VO^bSpc$%%feqQBnv#qwFcf z$F(%0<3mKEoFqRMTDUYal%e>HQwtxJ#bJS>kD$t`+WrkXaWz&7#fRIU_rJR<?FgG7 zS-W%Gfv|sXYHT<|@v-hz%SQb^g?__V)ui7H``_b@4bXS={RezFUcKj&`S1OC_VSX7 zMw(PYFxH2!(I(3fT-Iy-_^i>!|GbK?aog~!{jS=tA+Nwy|7^(Cxx8*y?RWV#YREHw Ls{bo4fb0JN2LML% literal 0 HcmV?d00001 -- 1.9.1

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[U-Boot] [PATCH 1/2] imx: kconfig: introduce IMX_FIXED_IVT_OFFSET
by Peng Fan 13 Jul '16

13 Jul '16

Introduce IMX_FIXED_IVT_OFFSET, which means different boot medias use the same IVT offset. To i.MX7, different boot medias' IVT offset is fixed at 0x400. So select IMX_FIXED_IVT_OFFSET for i.MX7D. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/cpu/armv7/mx7/Kconfig | 1 + arch/arm/imx-common/Kconfig | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm/cpu/armv7/mx7/Kconfig b/arch/arm/cpu/armv7/mx7/Kconfig index ecfa4a2..6e70394 100644 --- a/arch/arm/cpu/armv7/mx7/Kconfig +++ b/arch/arm/cpu/armv7/mx7/Kconfig @@ -7,6 +7,7 @@ config MX7 config MX7D select ROM_UNIFIED_SECTIONS + select IMX_FIXED_IVT_OFFSET bool choice diff --git a/arch/arm/imx-common/Kconfig b/arch/arm/imx-common/Kconfig index 1b7da5a..b248ef3 100644 --- a/arch/arm/imx-common/Kconfig +++ b/arch/arm/imx-common/Kconfig @@ -4,6 +4,13 @@ config IMX_CONFIG config ROM_UNIFIED_SECTIONS bool +config IMX_FIXED_IVT_OFFSET + bool "The IVT offset for different medias fixed or not" + help + The IVT offset for different boot medias are fixed or not. + To i.MX7, the IVT offset for different boot medias are + fixed. + config IMX_RDC bool "i.MX Resource domain controller driver" depends on ARCH_MX6 || ARCH_MX7 -- 2.6.2

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[U-Boot] [PATCH] net: designware: Make driver independent from DM_GPIO again
by Alexey Brodkin 12 Jul '16

12 Jul '16

Commit 90b7fc924adf "net: designware: support phy reset device-tree bindings" made DW GMAC driver dependent on DM_GPIO by unconditional usage of purely DM_GPIO stuff like: * dm_gpio_XXX() * gpio_request_by_name() But since that driver as of today might be easily used without DM_GPIO (that's the case for Synopsys AXS10x boards) we're shielding all DM_GPIO things by ifdefs. Signed-off-by: Alexey Brodkin <abrodkin(a)synopsys.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Beniamino Galvani <b.galvani(a)gmail.com> Cc: Joe Hershberger <joe.hershberger(a)ni.com> Cc: Sjoerd Simons <sjoerd.simons(a)collabora.co.uk> Cc: Sonic Zhang <sonic.zhang(a)analog.com> Cc: Bin Meng <bmeng.cn(a)gmail.com> Cc: Marek Vasut <marex(a)denx.de> --- drivers/net/designware.c | 10 ++++++++-- drivers/net/designware.h | 7 ++++++- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 8858f07..8ba72e3 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -80,7 +80,7 @@ static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, return ret; } -#if CONFIG_DM_ETH +#if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO) static int dw_mdio_reset(struct mii_dev *bus) { struct udevice *dev = bus->priv; @@ -126,7 +126,7 @@ static int dw_mdio_init(const char *name, void *priv) bus->read = dw_mdio_read; bus->write = dw_mdio_write; snprintf(bus->name, sizeof(bus->name), "%s", name); -#ifdef CONFIG_DM_ETH +#if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO) bus->reset = dw_mdio_reset; #endif @@ -690,11 +690,15 @@ static const struct eth_ops designware_eth_ops = { static int designware_eth_ofdata_to_platdata(struct udevice *dev) { struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev); +#ifdef CONFIG_DM_GPIO struct dw_eth_dev *priv = dev_get_priv(dev); +#endif struct eth_pdata *pdata = &dw_pdata->eth_pdata; const char *phy_mode; const fdt32_t *cell; +#ifdef CONFIG_DM_GPIO int reset_flags = GPIOD_IS_OUT; +#endif int ret = 0; pdata->iobase = dev_get_addr(dev); @@ -712,6 +716,7 @@ static int designware_eth_ofdata_to_platdata(struct udevice *dev) if (cell) pdata->max_speed = fdt32_to_cpu(*cell); +#ifdef CONFIG_DM_GPIO if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "snps,reset-active-low")) reset_flags |= GPIOD_ACTIVE_LOW; @@ -724,6 +729,7 @@ static int designware_eth_ofdata_to_platdata(struct udevice *dev) } else if (ret == -ENOENT) { ret = 0; } +#endif return ret; } diff --git a/drivers/net/designware.h b/drivers/net/designware.h index 51ba769..d345c5b 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -8,7 +8,9 @@ #ifndef _DW_ETH_H #define _DW_ETH_H -#include <asm/gpio.h> +#ifdef CONFIG_DM_GPIO +#include <asm-generic/gpio.h> +#endif #define CONFIG_TX_DESCR_NUM 16 #define CONFIG_RX_DESCR_NUM 16 @@ -234,7 +236,10 @@ struct dw_eth_dev { #ifndef CONFIG_DM_ETH struct eth_device *dev; #endif +#ifdef CONFIG_DM_GPIO struct gpio_desc reset_gpio; +#endif + struct phy_device *phydev; struct mii_dev *bus; }; -- 2.5.5

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[U-Boot] Avoiding overwriting FDT from FIT image
by Chris Packham 12 Jul '16

12 Jul '16

Hi, We have several boards making use of FIT images for the kernel/initrd/fdt. With v2015.04 we can successfully boot our application image. With v2016.05 we run into a problem where the FDT is overwritten when the ramdisk is relocated. Here's a snippet of boot output that illustrates the problem v2015.04 ------------- Booting image 01000000#x930-52GPX ... WARNING: adjusting available memory to 30000000 ## Loading kernel from FIT Image at 01000000 ... ## Loading ramdisk from FIT Image at 01000000 ... ## Loading fdt from FIT Image at 01000000 ... Booting using the fdt blob at 0x34ab4d4 Uncompressing Kernel Image ... OK Loading Ramdisk to 2df6b000, end 30000000 ... OK Loading Device Tree to 03fe6000, end 03fff862 ... OK v2016.04 ------------- Booting image 01000000#x930-52GPX ... WARNING: adjusting available memory to 30000000 ## Loading kernel from FIT Image at 01000000 ... ## Loading ramdisk from FIT Image at 01000000 ... ## Loading fdt from FIT Image at 01000000 ... Booting using the fdt blob at 0x34ab4d4 Uncompressing Kernel Image ... OK Loading Ramdisk to 01f6a000, end 03fff000 ... OK ERROR: image is not a fdt - must RESET the board to recover. Error: -9 Reverting commit 20e072f37402 ("image: check "bootm_low" and "bootm_size" if "initrd_high" is missing") avoids the problem as does setting initrd_high to 0xfffffffff. But I'm wondering if a better fix would be to tell boot_ramdisk_high() to avoid overwriting anything in the range $loadaddr -- +$filesize. Any suggestion as to how to go about this?

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[U-Boot] Support for GPIO in U-boot for Intel Edison
by SANRIO ALVARES 12 Jul '16

12 Jul '16

Hi, Is there any support for GPIO in U-boot for Intel Edison Boards? Thanks salvares

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[U-Boot] [PATCH] mmc: exynos_dw_mmc: support the Driver mode for Exynos
by Jaehoon Chung 12 Jul '16

12 Jul '16

This patch support the driver mode for exynos dwmmc controller. To support the legacy model, maintained the existing code. Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> --- drivers/mmc/exynos_dw_mmc.c | 72 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index ab0df46..283befc 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -23,8 +23,21 @@ #define DWMMC_MMC0_SDR_TIMING_VAL 0x03030001 #define DWMMC_MMC2_SDR_TIMING_VAL 0x03020001 +#ifdef CONFIG_DM_MMC +#include <dm.h> +DECLARE_GLOBAL_DATA_PTR; + +struct exynos_mmc_plat { + struct mmc_config cfg; + struct mmc mmc; +}; +#endif + /* Exynos implmentation specific drver private data */ struct dwmci_exynos_priv_data { +#ifdef CONFIG_DM_MMC + struct dwmci_host host; +#endif u32 sdr_timing; }; @@ -105,11 +118,15 @@ static int exynos_dwmci_core_init(struct dwmci_host *host) host->caps = MMC_MODE_DDR_52MHz; host->clksel = exynos_dwmci_clksel; host->get_mmc_clk = exynos_dwmci_get_clk; + +#ifndef CONFIG_DM_MMC /* Add the mmc channel to be registered with mmc core */ if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) { printf("DWMMC%d registration failed\n", host->dev_index); return -1; } +#endif + return 0; } @@ -237,3 +254,58 @@ int exynos_dwmmc_init(const void *blob) return err; } + +#ifdef CONFIG_DM_MMC +static int exynos_dwmmc_probe(struct udevice *dev) +{ + struct exynos_mmc_plat *plat = dev_get_platdata(dev); + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct dwmci_exynos_priv_data *priv = dev_get_priv(dev); + struct dwmci_host *host = &priv->host; + int err; + + err = exynos_dwmci_get_config(gd->fdt_blob, dev->of_offset, host); + if (err) + return err; + err = do_dwmci_init(host); + if (err) + return err; + + dwmci_setup_cfg(&plat->cfg, host->name, host->buswidth, host->caps, + DWMMC_MAX_FREQ, DWMMC_MIN_FREQ); + host->mmc = &plat->mmc; + host->mmc->priv = &priv->host; + host->priv = dev; + upriv->mmc = host->mmc; + + return dwmci_probe(dev); +} + +static int exynos_dwmmc_bind(struct udevice *dev) +{ + struct exynos_mmc_plat *plat = dev_get_platdata(dev); + int ret; + + ret = dwmci_bind(dev, &plat->mmc, &plat->cfg); + if (ret) + return ret; + + return 0; +} + +static const struct udevice_id exynos_dwmmc_ids[] = { + { .compatible = "samsung,exynos4412-dw-mshc" }, + { } +}; + +U_BOOT_DRIVER(exynos_dwmmc_drv) = { + .name = "exynos_dwmmc", + .id = UCLASS_MMC, + .of_match = exynos_dwmmc_ids, + .bind = exynos_dwmmc_bind, + .ops = &dm_dwmci_ops, + .probe = exynos_dwmmc_probe, + .priv_auto_alloc_size = sizeof(struct dwmci_exynos_priv_data), + .platdata_auto_alloc_size = sizeof(struct exynos_mmc_plat), +}; +#endif -- 1.9.1

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[U-Boot] [PATCH 0/5] mmc: exynos_dw_mmc: clean the unnecessary codes
by Jaehoon Chung 12 Jul '16

12 Jul '16

This patch-set is for maintaining more easier than now. Now, exynos_dw_mmc codes are too huge. Some codes can be reused and removed. Basic goal is the using DM. Before applied DM, it needs to clean more. In future, exynos_dw_mmc controller should support DM. Jaehoon Chung (5): mmc: exynos_dw_mmc: remove the unused function mmc: exynos_dw_mmc: remove #ifdef for OF_CONTROL mmc: exynos_dw_mmc: add the error control for checking index mmc: exynos_dw_mmc: clean the unused and unnecessary codes mmc: exynos_dw_mmc: use the 4bit bus-width by default arch/arm/mach-exynos/include/mach/dwmmc.h | 1 - drivers/mmc/exynos_dw_mmc.c | 78 ++++++------------------------- 2 files changed, 14 insertions(+), 65 deletions(-) -- 1.9.1

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