May 2016 - U-Boot

[U-Boot] OMAP 3530 - BeagleBoard Rev. C4
by Derald D. Woods 05 May '16

05 May '16

Hi Tom, Is anyone still attempting to boot the OMAP 3530 BeagleBoard with U-Boot master? In order to boot my BeagleBoard Rev. C4, I need to basically undefine CONFIG_SPL_EXT_SUPPORT and CONFIG_SYS_THUMB_BUILD. There is some background in this old thread from last year: - http://lists.denx.de/pipermail/u-boot/2015-July/220332.html The thread ended without an apparent solution. What does work is this patch from EEWiki: - https://github.com/eewiki/u-boot-patches/blob/master/v2016.03/0001-omap3_be… If there is some additional useful information, I would be happy to take a look. I use the board for testing generic code intended for other OMAP3 systems. Derald

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[U-Boot] mkimage needs fitImage
by shr ch 05 May '16

05 May '16

Hi, For adding public keys to uboot dtb the mkimage step is mkimage -D "-I dts -O dtb -p 2000" -F -k keys -K u-boot.dtb -r fitImage It resigns fitImage and adds public key to uboot dtb but why do we need fitImage for adding public keys to uboot dtb ? can't this be two different steps ? there is already a step to just build fitImage. This creates unnecessary dependency of building fitImage before building uboot.

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[U-Boot] pedantic cleanup -- sure is a lot of "#if 0" out there :-)
by Robert P. J. Day 05 May '16

05 May '16

another observation -- noticed "#if 0" in a header file i'm working with, so did a quick grep from the top: $ grep -r "^#if 0" * | wc -l 223 $ and, what the heck: $ grep -r "^#if 1" * | wc -l 37 $ so after next release, i might rummage around in that and submit patches, particularly when i see stuff like: #if 0 /* already in asm/8xx_immap.h */ #define TBSCR_REFA 0x0080 /* Reference Interrupt Status A */ #define TBSCR_REFB 0x0040 /* Reference Interrupt Status B */ #define TBSCR_REFAE 0x0008 /* Second Interrupt Enable A */ #define TBSCR_REFBE 0x0004 /* Second Interrupt Enable B */ #define TBSCR_TBF 0x0002 /* Time Base Freeze */ #define TBSCR_TBE 0x0001 /* Time Base Enable */ #endif /*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control Register 11-31 */ #undef PISCR_PIRQ /* TBD */ #define PISCR_PITF 0x0002 /* Periodic Interrupt Timer Freeze */ #if 0 /* already in asm/8xx_immap.h */ #define PISCR_PS 0x0080 /* Periodic interrupt Status */ #define PISCR_PIE 0x0004 /* Periodic Interrupt Enable */ #define PISCR_PTE 0x0001 /* Periodic Timer Enable */ #endif after all, if you have a comment that helpfully states that that content is #if 0'ed out because it's already elsewhere, then (after confirming that it is), that seems like a good candidate for deletion. all in good time ... rday -- ======================================================================== Robert P. J. Day Ottawa, Ontario, CANADA http://crashcourse.ca Twitter: http://twitter.com/rpjday LinkedIn: http://ca.linkedin.com/in/rpjday ========================================================================

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[U-Boot] [PATCH] ARM: zynq: load u-boot.img whether CONFIG_OF_SEPARATE is defined or not
by Masahiro Yamada 05 May '16

05 May '16

Since commit ad1ecd2063da ("fdt: Build a U-Boot binary without device tree"), u-boot-dtb.img is identical to u-boot.img, so SPL can always load u-boot.img whether CONFIG_OF_SEPARATE is defined or not. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- include/configs/zynq-common.h | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 49d9fd0..3b5cd5b 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -339,11 +339,7 @@ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_FAT_SUPPORT -#ifdef CONFIG_OF_SEPARATE -# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" -#else -# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #endif /* Disable dcache for SPL just for sure */ -- 1.9.1

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[U-Boot] Pull request, u-boot-tegra/master
by Tom Warren 05 May '16

05 May '16

Tom, Please pull u-boot-tegra/master into U-Boot/master. Thanks! All tegra builds are OK (32-bit and 64-bit), and Stephen reports that tests of u-boot-tegra/master all pass. The following changes since commit b38eaec53570821043c94ad44eabcb23747d9969: include/configs: Numerous typo fixes: "controler" -> "controller". (2016-05-03 21:36:13 -0400) are available in the git repository at: git://git.denx.de/u-boot-tegra.git master for you to fetch changes up to bbca7108db79076d3a9a9c112792d7c4608a665c: ARM: tegra: import latest Jetson TK1 spreadsheet (2016-05-04 13:31:04 -0700) ---------------------------------------------------------------- Stephen Warren (3): ARM: tegra: enable GPU node by compatible value pci: tegra: fix DM conversion issues on Tegra20 ARM: tegra: import latest Jetson TK1 spreadsheet arch/arm/include/asm/arch-tegra/gpu.h | 2 +- arch/arm/mach-tegra/board2.c | 20 +++++++++++++------- arch/arm/mach-tegra/gpu.c | 15 ++++++++------- board/nvidia/jetson-tk1/jetson-tk1.c | 3 +++ board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h | 12 +++++++++++- drivers/pci/pci_tegra.c | 21 ++++++++++----------- 6 files changed, 46 insertions(+), 27 deletions(-)

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[U-Boot] [PATCH] ARM: tegra: import latest Jetson TK1 spreadsheet
by Stephen Warren 04 May '16

04 May '16

From: Stephen Warren <swarren(a)nvidia.com> This imports v11 of "Jetson TK1 Development Platform Pin Mux" from https://developer.nvidia.com/embedded/downloads. The new version defines the mux option for the MIPI pad ctrl selection. The OWR pin no longer has an entry in the configuration table because the only mux option it support is OWR, that feature isn't supported, and hence can't conflict with any other pin. This pin can only usefully be used as a GPIO. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- Note that the cleanup series I sent on Tuesday accidentally depends on this being applied first. I'd expect this to have higher priority than the cleanup series and be applied earlier anyway. board/nvidia/jetson-tk1/jetson-tk1.c | 3 +++ board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h | 12 +++++++++++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c b/board/nvidia/jetson-tk1/jetson-tk1.c index 14f0ce54554e..a66b710cddab 100644 --- a/board/nvidia/jetson-tk1/jetson-tk1.c +++ b/board/nvidia/jetson-tk1/jetson-tk1.c @@ -31,6 +31,9 @@ void pinmux_init(void) pinmux_config_drvgrp_table(jetson_tk1_drvgrps, ARRAY_SIZE(jetson_tk1_drvgrps)); + + pinmux_config_mipipadctrlgrp_table(jetson_tk1_mipipadctrlgrps, + ARRAY_SIZE(jetson_tk1_mipipadctrlgrps)); } #ifdef CONFIG_PCI_TEGRA diff --git a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h index b2b2057e3bd3..00e0cdc4b8c0 100644 --- a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h +++ b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h @@ -276,7 +276,6 @@ static const struct pmux_pingrp_config jetson_tk1_pingrps[] = { PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(PWR_INT_N, PMI, UP, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(OWR, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, NORMAL), PINCFG(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(JTAG_RTCK, RTCK, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT), }; @@ -296,4 +295,15 @@ static const struct pmux_pingrp_config jetson_tk1_pingrps[] = { static const struct pmux_drvgrp_config jetson_tk1_drvgrps[] = { }; +#define MIPIPADCTRLCFG(_grp, _mux) \ + { \ + .grp = PMUX_MIPIPADCTRLGRP_##_grp, \ + .func = PMUX_FUNC_##_mux, \ + } + +static const struct pmux_mipipadctrlgrp_config jetson_tk1_mipipadctrlgrps[] = { + /* grp, mux */ + MIPIPADCTRLCFG(DSI_B, DSI_B), +}; + #endif /* PINMUX_CONFIG_JETSON_TK1_H */ -- 2.8.1

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[U-Boot] [PATCH] pci: tegra: fix DM conversion issues on Tegra20
by Stephen Warren 04 May '16

04 May '16

From: Stephen Warren <swarren(a)nvidia.com> Tegra20's PCIe controller has a couple of quirks. There are workarounds in the driver for these, but they don't work after the DM conversion: 1) The PCI_CLASS value is wrong in HW. This is worked around in pci_tegra_read_config() by patching up the value read from that register. Pre-DM, the PCIe core always read this via a 16-bit access to the 16-bit offset 0xa. With DM, 32-bit accesses are used, so we need to check for offset 0x8 instead. Mask the offset value back to 32-bit alignment to make this work in all cases. 2) Accessing devices other than dev 1 causes a data abort. Pre-DM, this was worked around in pci_skip_dev(), which the PCIe core code called during enumeration while iterating over a bus. The DM PCIe core doesn't use this function. Instead, enhance tegra_pcie_conf_address() to validate the bdf being accessed, and refuse to access invalid devices. Since pci_skip_dev() isn't used, delete it. I've also validated that both these WARs are only needed for Tegra20, by testing on Tegra30/Cardhu and Tegra124/Jetson TKx. So, compile them in conditionally. Fixes: e81ca88451cf ("dm: tegra: pci: Convert tegra boards to driver model for PCI") Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- drivers/pci/pci_tegra.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c index 5dadf6fa62a7..c5b04daffa65 100644 --- a/drivers/pci/pci_tegra.c +++ b/drivers/pci/pci_tegra.c @@ -275,12 +275,17 @@ static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf, return 0; } } + return -EFAULT; } else { +#ifdef CONFIG_TEGRA20 + unsigned int dev = PCI_DEV(bdf); + if (dev != 0) + return -EFAULT; +#endif + *address = pcie->cs.start + tegra_pcie_conf_offset(bdf, where); return 0; } - - return -EFAULT; } static int pci_tegra_read_config(struct udevice *bus, pci_dev_t bdf, @@ -299,13 +304,15 @@ static int pci_tegra_read_config(struct udevice *bus, pci_dev_t bdf, value = readl(address); +#ifdef CONFIG_TEGRA20 /* fixup root port class */ if (PCI_BUS(bdf) == 0) { - if (offset == PCI_CLASS_REVISION) { + if ((offset & ~3) == PCI_CLASS_REVISION) { value &= ~0x00ff0000; value |= PCI_CLASS_BRIDGE_PCI << 16; } } +#endif done: *valuep = pci_conv_32_to_size(value, offset, size); @@ -1041,11 +1048,3 @@ U_BOOT_DRIVER(pci_tegra) = { .probe = pci_tegra_probe, .priv_auto_alloc_size = sizeof(struct tegra_pcie), }; - -int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) -{ - if (PCI_BUS(dev) != 0 && PCI_DEV(dev) > 0) - return 1; - - return 0; -} -- 2.8.1

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[U-Boot] [PATCH V2 1/2] mtd: cqspi: Simplify indirect write code
by Marek Vasut 04 May '16

04 May '16

The indirect write code is buggy pile of nastiness which fails horribly when the system runs fast enough to saturate the controller. The failure results in some pages (256B) not being written to the flash. This can be observed on systems which run with Dcache enabled and L2 cache enabled, like the Altera SoCFPGA. This patch replaces the whole unmaintainable indirect write implementation with the one from upcoming Linux CQSPI driver, which went through multiple rounds of thorough review and testing. While this makes the patch look terrifying and violates all best-practices of software development, all the patch does is it plucks out duplicate ad-hoc code distributed across the driver and replaces it with more compact code doing exactly the same thing. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Anatolij Gustschin <agust(a)denx.de> Cc: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Jagan Teki <jteki(a)openedev.com> Cc: Pavel Machek <pavel(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> Cc: Vignesh R <vigneshr(a)ti.com> --- V2: Handle non-4-byte aligned transfers --- drivers/spi/cadence_qspi_apb.c | 126 ++++++++++------------------------------- 1 file changed, 30 insertions(+), 96 deletions(-) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 7786dd6..5e84144 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -28,6 +28,7 @@ #include <common.h> #include <asm/io.h> #include <asm/errno.h> +#include <wait_bit.h> #include "cadence_qspi.h" #define CQSPI_REG_POLL_US (1) /* 1us */ @@ -214,32 +215,6 @@ static void cadence_qspi_apb_read_fifo_data(void *dest, return; } -static void cadence_qspi_apb_write_fifo_data(const void *dest_ahb_addr, - const void *src, unsigned int bytes) -{ - unsigned int temp = 0; - int i; - int remaining = bytes; - unsigned int *dest_ptr = (unsigned int *)dest_ahb_addr; - unsigned int *src_ptr = (unsigned int *)src; - - while (remaining >= CQSPI_FIFO_WIDTH) { - for (i = CQSPI_FIFO_WIDTH/sizeof(src_ptr) - 1; i >= 0; i--) - writel(*(src_ptr+i), dest_ptr+i); - src_ptr += CQSPI_FIFO_WIDTH/sizeof(src_ptr); - remaining -= CQSPI_FIFO_WIDTH; - } - if (remaining) { - /* dangling bytes */ - i = remaining/sizeof(dest_ptr); - memcpy(&temp, src_ptr+i, remaining % sizeof(dest_ptr)); - writel(temp, dest_ptr+i); - for (--i; i >= 0; i--) - writel(*(src_ptr+i), dest_ptr+i); - } - return; -} - /* Read from SRAM FIFO with polling SRAM fill level. */ static int qspi_read_sram_fifo_poll(const void *reg_base, void *dest_addr, const void *src_addr, unsigned int num_bytes) @@ -276,44 +251,6 @@ static int qspi_read_sram_fifo_poll(const void *reg_base, void *dest_addr, return 0; } -/* Write to SRAM FIFO with polling SRAM fill level. */ -static int qpsi_write_sram_fifo_push(struct cadence_spi_platdata *plat, - const void *src_addr, unsigned int num_bytes) -{ - const void *reg_base = plat->regbase; - void *dest_addr = plat->ahbbase; - unsigned int retry = CQSPI_REG_RETRY; - unsigned int sram_level; - unsigned int wr_bytes; - unsigned char *src = (unsigned char *)src_addr; - int remaining = num_bytes; - unsigned int page_size = plat->page_size; - unsigned int sram_threshold_words = CQSPI_REG_SRAM_THRESHOLD_WORDS; - - while (remaining > 0) { - retry = CQSPI_REG_RETRY; - while (retry--) { - sram_level = CQSPI_GET_WR_SRAM_LEVEL(reg_base); - if (sram_level <= sram_threshold_words) - break; - } - if (!retry) { - printf("QSPI: SRAM fill level (0x%08x) not hit lower expected level (0x%08x)", - sram_level, sram_threshold_words); - return -1; - } - /* Write a page or remaining bytes. */ - wr_bytes = (remaining > page_size) ? - page_size : remaining; - - cadence_qspi_apb_write_fifo_data(dest_addr, src, wr_bytes); - src += wr_bytes; - remaining -= wr_bytes; - } - - return 0; -} - void cadence_qspi_apb_controller_enable(void *reg_base) { unsigned int reg; @@ -810,48 +747,45 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat, } int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, - unsigned int txlen, const u8 *txbuf) + unsigned int n_tx, const u8 *txbuf) { - unsigned int reg = 0; - unsigned int retry; + unsigned int page_size = plat->page_size; + unsigned int remaining = n_tx; + unsigned int write_bytes; + int ret; /* Configure the indirect read transfer bytes */ - writel(txlen, plat->regbase + CQSPI_REG_INDIRECTWRBYTES); + writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES); /* Start the indirect write transfer */ writel(CQSPI_REG_INDIRECTWR_START_MASK, plat->regbase + CQSPI_REG_INDIRECTWR); - if (qpsi_write_sram_fifo_push(plat, (const void *)txbuf, txlen)) - goto failwr; - - /* Wait until last write is completed (FIFO empty) */ - retry = CQSPI_REG_RETRY; - while (retry--) { - reg = CQSPI_GET_WR_SRAM_LEVEL(plat->regbase); - if (reg == 0) - break; - - udelay(1); - } - - if (reg != 0) { - printf("QSPI: timeout for indirect write\n"); - goto failwr; - } + while (remaining > 0) { + write_bytes = remaining > page_size ? page_size : remaining; + /* Handle non-4-byte aligned access to avoid data abort. */ + if (((uintptr_t)txbuf % 4) || (write_bytes % 4)) + writesb(plat->ahbbase, txbuf, write_bytes); + else + writesl(plat->ahbbase, txbuf, write_bytes >> 2); + + ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL, + CQSPI_REG_SDRAMLEVEL_WR_MASK << + CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0); + if (ret) { + printf("Indirect write timed out (%i)\n", ret); + goto failwr; + } - /* Check flash indirect controller status */ - retry = CQSPI_REG_RETRY; - while (retry--) { - reg = readl(plat->regbase + CQSPI_REG_INDIRECTWR); - if (reg & CQSPI_REG_INDIRECTWR_DONE_MASK) - break; - udelay(1); + txbuf += write_bytes; + remaining -= write_bytes; } - if (!(reg & CQSPI_REG_INDIRECTWR_DONE_MASK)) { - printf("QSPI: indirect completion status error with reg 0x%08x\n", - reg); + /* Check indirect done status */ + ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTWR, + CQSPI_REG_INDIRECTWR_DONE_MASK, 1, 10, 0); + if (ret) { + printf("Indirect write completion error (%i)\n", ret); goto failwr; } @@ -864,7 +798,7 @@ failwr: /* Cancel the indirect write */ writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, plat->regbase + CQSPI_REG_INDIRECTWR); - return -1; + return ret; } void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy) -- 2.7.0

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[U-Boot] how to feed kernel, initrd and rootfs into uboot
by JPT 04 May '16

04 May '16

Hi, I am having difficulties installing openwrt on an old router box. The guide stops after u-boot is up and running. https://wiki.openwrt.org/toh/arcadyan/arv752dpw#brnboot I know how to load kernel image etc into RAM, but it does not boot the kernel. What am I doing wrong? I already posted in openwrt forums, but it seems nobody is going to help. :( https://forum.openwrt.org/viewtopic.php?id=64615 U-Boot 2013.10-openwrt4 (May 03 2016 - 16:56:57) ARV752DPW Board: Arcadyan ARV752DPW SoC: Lantiq Danube-S v1.5 CPU: 333.333 MHz IO: 166.667 MHz BUS: 83.333 MHz BOOT: NOR DRAM: 64 MiB Flash: 8 MiB Using default environment In: serial Out: serial Err: serial Net: Board Net Initialization Failed ltq-eth Hit any key to stop autoboot: 0 ARV752DPW # printenv ... addconsole=setenv bootargs $bootargs console=$consoledev,$baudrate ... baudrate=115200 bootcmd=bootm ${kernel_addr} consoledev=ttyLTQ1 kernel_addr=0xB0040000 loadaddr=0x81000000 stderr=serial stdin=serial stdout=serial bootargs is not defined :( now I use "loadx" to load the kernel into ram. after that I "bootm". Nothing happens. Then I tried setenv bootargs console=ttyLTQ1,115200 Did not change anything. Why does it load to 0x8100 0000? The device has got 64MB RAM, which is 0x0400 0000 ~/src/openwrt/bin/lantiq$ 4,3M openwrt-lantiq-xway-ARV752DPW-squashfs.image 1,4M openwrt-lantiq-xway-ARV752DPW-uImage 4,0M openwrt-lantiq-xway-ARV752DPW-uImage-initramfs 178K uboot-lantiq-arv752dpw_brn/openwrt-lantiq-arv752dpw_brn-u-boot.img packages/ which file should I load to what address? then bootm <kernel-address> <initramfs-address> but what to do with the squashfs? what bootargs do I need? Please CC to my email, I did not subscribe to the list. thank you very much JPT

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[U-Boot] [PATCH] fdt: fix setting MAC addresses for multiple interfaces
by Lev Iserovich 04 May '16

04 May '16

For multiple ethernet interfaces the FDT offset of '/aliases' will change as we are adding MAC addresses to the FDT. Therefore only the first interface ('ethernet0') will get properly updated in the FDT, with the rest getting FDT errors when we try to set their MAC address. Switch to using fdt_get_alias() which is the proper way to get the FDT path. Signed-off-by: Lev Iserovich <iserovil(a)deshawresearch.com> --- common/fdt_support.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/common/fdt_support.c b/common/fdt_support.c index 66464db..20e0e1c 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -481,16 +481,12 @@ int fdt_fixup_memory(void *blob, u64 start, u64 size) void fdt_fixup_ethernet(void *fdt) { - int node, i, j; + int i, j; char enet[16], *tmp, *end; char mac[16]; const char *path; unsigned char mac_addr[6]; - node = fdt_path_offset(fdt, "/aliases"); - if (node < 0) - return; - if (!getenv("ethaddr")) { if (getenv("usbethaddr")) { strcpy(mac, "usbethaddr"); @@ -505,7 +501,7 @@ void fdt_fixup_ethernet(void *fdt) i = 0; while ((tmp = getenv(mac)) != NULL) { sprintf(enet, "ethernet%d", i); - path = fdt_getprop(fdt, node, enet, NULL); + path = fdt_get_alias(fdt, enet); if (!path) { debug("No alias for %s\n", enet); sprintf(mac, "eth%daddr", ++i); -- 2.1.0

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