May 2016 - U-Boot

[U-Boot] [PATCH 0/4] efi_loader: PXE boot support
by Alexander Graf 06 May '16

06 May '16

One of the most common boot cases with EFI on arm64 is to boot from the network using PXE boot. While TianoCore implements that just fine, we were lacking support for it in U-Boot so far. But no longer! Here is a patch set, enabling PXE booting of EFI payloads. With this patch set, I was successfully able to automatically boot our normal (usually used with TianoCore based systems) environment to boot and run grub2 and a kernel from there with U-Boot. Alexander Graf (4): efi_loader: Add network access support bootp: Move vendor class identifier set to function net: Move the VCI and client arch values to Kconfig distro: Add efi pxe boot code cmd/bootefi.c | 7 + configs/ls2080a_emu_defconfig | 1 + configs/ls2080a_simu_defconfig | 1 + configs/thunderx_88xx_defconfig | 1 + configs/vexpress_aemv8a_dram_defconfig | 1 + configs/vexpress_aemv8a_juno_defconfig | 1 + configs/vexpress_aemv8a_semi_defconfig | 1 + configs/vexpress_ca15_tc2_defconfig | 1 + configs/vexpress_ca5x2_defconfig | 1 + configs/vexpress_ca9x4_defconfig | 1 + include/config_distro_bootcmd.h | 37 ++++- include/config_distro_defaults.h | 21 --- include/configs/ls2080a_emu.h | 1 - include/configs/ls2080a_simu.h | 1 - include/configs/thunderx_88xx.h | 2 - include/configs/vexpress_aemv8a.h | 2 - include/configs/vexpress_ca15_tc2.h | 1 - include/configs/vexpress_ca5x2.h | 1 - include/configs/vexpress_ca9x4.h | 1 - include/efi_api.h | 119 ++++++++++++++ include/efi_loader.h | 7 + include/net.h | 2 +- lib/efi_loader/Makefile | 1 + lib/efi_loader/efi_net.c | 291 +++++++++++++++++++++++++++++++++ net/Kconfig | 12 ++ net/bootp.c | 37 +++-- net/net.c | 4 +- net/tftp.c | 2 + 28 files changed, 511 insertions(+), 47 deletions(-) create mode 100644 lib/efi_loader/efi_net.c -- 1.8.5.6

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[U-Boot] [PATCH] test/py: dfu: wait for USB device to go away at boot
by Stephen Warren 06 May '16

06 May '16

From: Stephen Warren <swarren(a)nvidia.com> It can take a while for a host machine to notice that a USB device has disconnected, and process the change. At the end of the DFU test, we wait up to 10 seconds for this to happen. This change makes the test wait the same (up to) 10 seconds at the start of the test for any previously active USB device-mode session to be cleaned up. Such as session might have been used to download U-Boot into memory for example; this is certainly true on my Tegra test systems. This changes should solve the DFU test intermittency issues I've been seeing on some Tegra devices. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- test/py/tests/test_dfu.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/test/py/tests/test_dfu.py b/test/py/tests/test_dfu.py index 8649d8731b73..585e6b29d7f8 100644 --- a/test/py/tests/test_dfu.py +++ b/test/py/tests/test_dfu.py @@ -136,6 +136,8 @@ def test_dfu(u_boot_console, env__usb_dev_port, env__dfu_config): Nothing. """ + u_boot_utils.wait_until_file_open_fails( + env__usb_dev_port['host_usb_dev_node'], True) fh = u_boot_utils.attempt_to_open_file( env__usb_dev_port['host_usb_dev_node']) if fh: -- 2.8.2

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[U-Boot] [PATCH] ARM: am33xx: Fix DDR initialization delays
by Russ Dill 06 May '16

06 May '16

The current delays in the DDR initialization routines for am33xx architectures are sometimes not running long enough leading to DDR init errors. On am437x, this shows up as an L3 NOC error after the kernel boots. This is due to the timer not being initialized properly, but instead still containing the timer init values from the boot ROM which cause timers to expire in 1/4th the time required. timer_init is typically not called until board_init_r, however on am33xx/am43xx udelay is required in sdram_init which is called from board_init_f, so a call to timer_init is required earlier. Note that this issue introduced in v2015.01 by: b352dde "am33xx: Drop timer_init call from s_init". Although this could instead fixed by reverting said commit, it would cause timer_init to be called twice in both SPL and non-SPL cases. This gives a little more fine grained control and also matches what is being done on omap-command and fsl-layerscape. Signed-off-by: Russ Dill <russ.dill(a)ti.com> --- arch/arm/cpu/armv7/am33xx/clock.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c index 595c951..9b9b78e 100644 --- a/arch/arm/cpu/armv7/am33xx/clock.c +++ b/arch/arm/cpu/armv7/am33xx/clock.c @@ -237,4 +237,5 @@ void prcm_init() enable_basic_clocks(); scale_vcores(); setup_dplls(); + timer_init(); } -- 2.8.1

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[U-Boot] [PATCH] ARM: fix ifdefs in ARMv8 lowlevel_init()
by Stephen Warren 06 May '16

06 May '16

From: Stephen Warren <swarren(a)nvidia.com> Commit 724219a65f55 "ARM: always perform per-CPU GIC init" removed some ifdefs to unify the MULTIENTRY-vs-non-MULTIENTRY paths. However, the wrong endif was removed. This patch adds back that missing endif, and adds a new ifdef to match the endif the now-correctly-terminated block used to match against. Use "git show -U25 724219a65f55" to see enough context to make the original issue clear. In practical terms, this makes no difference to runtime behaviour. The code that was incorrectly compiled into the binary when ifndef MULTIENTRY is a no-op for other cases, since branch_if_master evaluates to a hard- coded jump. The only issues were: - A few extra instructions were added to the binary. - The comment on the endif at the very end of the function, indicating which ifdef it matched, were wrong. An alternative might be to simply fix the comment on that trailing ifdef, but that only addresses the second point above, not the first. Fixes: 724219a65f55 ("ARM: always perform per-CPU GIC init") Cc: Masahiro Yamada <yamada.masahiro(a)socionext.com> Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- arch/arm/cpu/armv8/start.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index deb44a895fda..c3cc8199caf9 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -214,7 +214,9 @@ WEAK(lowlevel_init) ldr x1, =GICC_BASE bl gic_init_secure_percpu #endif +#endif +#ifndef CONFIG_ARMV8_MULTIENTRY branch_if_master x0, x1, 2f /* -- 2.8.1

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[U-Boot] [PATCH] Fix various typos, scattered over the code.
by Robert P. J. Day 06 May '16

06 May '16

Spelling corrections for (among other things): * environment * override * variable * ftd (should be "fdt", for flattened device tree) * embedded * FTDI * emulation * controller --- the fixes for "controller" here are independent of the previous patch. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index d580a43..a9b12a4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -180,7 +180,7 @@ ulong get_ddr_freq(ulong ctrl_num) /* * DDR controller 0 & 1 are on memory complex 0 - * DDR controler 2 is on memory complext 1 + * DDR controller 2 is on memory complext 1 */ #ifdef CONFIG_SYS_FSL_HAS_DP_DDR if (ctrl_num >= 2) diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode.c b/arch/arm/mach-uniphier/boot-mode/boot-mode.c index b08cd6c..614f85f 100644 --- a/arch/arm/mach-uniphier/boot-mode/boot-mode.c +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode.c @@ -110,7 +110,7 @@ static int do_mmcsetn(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD( mmcsetn, 1, 1, do_mmcsetn, - "Set the first MMC (not SD) dev number to \"mmc_first_dev\" enviroment", + "Set the first MMC (not SD) dev number to \"mmc_first_dev\" environment", "" ); #endif diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index f852a1f..fe37d1f 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -145,7 +145,7 @@ config MIPS_BOOT_ENV_LEGACY Enable this option if you want U-Boot to hand over the Yamon-style environment to the kernel. Information like memory size, initrd address and size will be prepared as zero-terminated key/value list. - The address of the enviroment is stored in register $a2. + The address of the environment is stored in register $a2. config MIPS_BOOT_FDT bool "Hand over a flattened device tree to Linux kernel" diff --git a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c index 916451a..455136c 100644 --- a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c +++ b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c @@ -1151,7 +1151,7 @@ phys_size_t initdram(int board_type) dram_size *= ranks; debug("dram_size = %lu\n", dram_size); - /* Start the SDRAM controler */ + /* Start the SDRAM controller */ mtsdram(DDR0_02, DDR0_02_START_ENCODE(1)); denali_wait_for_dlllock(); diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 64e4e30..8c171b1 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -812,9 +812,9 @@ static int calculate_cmp_img_sig(struct fsl_secboot_img_priv *img) } /* haddr - Address of the header of image to be validated. * arg_hash_str - Option hash string. If provided, this - * overides the key hash in the SFP fuses. + * overrides the key hash in the SFP fuses. * img_addr_ptr - Optional pointer to address of image to be validated. - * If non zero addr, this overides the addr of image in header, + * If non zero addr, this overrides the addr of image in header, * otherwise updated to image addr in header. * Acts as both input and output of function. * This pointer shouldn't be NULL. diff --git a/board/freescale/mx28evk/README b/board/freescale/mx28evk/README index a248fb2..b8bee89 100644 --- a/board/freescale/mx28evk/README +++ b/board/freescale/mx28evk/README @@ -45,7 +45,7 @@ or or -"make mx28evk_spi_config" - store enviroment variables into SPI NOR flash +"make mx28evk_spi_config" - store environment variables into SPI NOR flash Choose the target accordingly. diff --git a/cmd/fdt.c b/cmd/fdt.c index 4c18962..898217f 100644 --- a/cmd/fdt.c +++ b/cmd/fdt.c @@ -1055,7 +1055,7 @@ static char fdt_help_text[] = " <start> - addr of key blob\n" " default gd->fdt_blob\n" #endif - "NOTE: Dereference aliases by omiting the leading '/', " + "NOTE: Dereference aliases by omitting the leading '/', " "e.g. fdt print ethernet0."; #endif diff --git a/cmd/mtdparts.c b/cmd/mtdparts.c index 86a4689..44b2c3a 100644 --- a/cmd/mtdparts.c +++ b/cmd/mtdparts.c @@ -1742,7 +1742,7 @@ int mtdparts_init(void) debug("last_partition : %s\n", last_partition); debug("env_partition : %s\n", current_partition); - /* if mtdids varible is empty try to use defaults */ + /* if mtdids variable is empty try to use defaults */ if (!ids) { if (mtdids_default) { debug("mtdids variable not defined, using default\n"); diff --git a/doc/README.commands.spl b/doc/README.commands.spl index ac33273..cb3e0c8 100644 --- a/doc/README.commands.spl +++ b/doc/README.commands.spl @@ -10,7 +10,7 @@ export has two subcommands: fdt: exports the FDT Call is: -spl export <ftd|atags> [kernel_addr] [initrd_addr] [fdt_addr if fdt] +spl export <fdt|atags> [kernel_addr] [initrd_addr] [fdt_addr if fdt] TYPICAL CALL diff --git a/doc/README.marubun-pcmcia b/doc/README.marubun-pcmcia index d3563a3..0a363b2 100644 --- a/doc/README.marubun-pcmcia +++ b/doc/README.marubun-pcmcia @@ -34,7 +34,7 @@ U-Boot MARUBUN MR-SHPC-01 PCMCIA controller driver ex. #define CONFIG_PCMCIA_SLOT_A 1 * CONFIG_SYS_MARUBUN_MRSHPC - This is MR-SHPC-01 PCMCIA controler base address. + This is MR-SHPC-01 PCMCIA controller base address. You should do the setting matched to your environment. ex. #define CONFIG_SYS_MARUBUN_MRSHPC 0xb03fffe0 ( for MS7722SE01 environment ) diff --git a/doc/README.mxs b/doc/README.mxs index 6ea73b9..4edf19f 100644 --- a/doc/README.mxs +++ b/doc/README.mxs @@ -219,7 +219,7 @@ There are two possibilities when preparing an image writable to NAND flash. This script expects a working TFTP server containing the file "u-boot.nand" in it's root directory. This can be changed by - adjusting the "update_nand_full_filename" varible. + adjusting the "update_nand_full_filename" variable. To update the system, run the following in U-Boot prompt: @@ -242,7 +242,7 @@ There are two possibilities when preparing an image writable to NAND flash. This script expects a working TFTP server containing the file "u-boot.sb" in it's root directory. This can be changed by - adjusting the "update_nand_firmware_filename" varible. + adjusting the "update_nand_firmware_filename" variable. To update the system, run the following in U-Boot prompt: diff --git a/doc/SPI/README.sandbox-spi b/doc/SPI/README.sandbox-spi index bb73eaf..dfa845c 100644 --- a/doc/SPI/README.sandbox-spi +++ b/doc/SPI/README.sandbox-spi @@ -1,7 +1,7 @@ Sandbox SPI/SPI Flash Implementation ==================================== -U-Boot supports SPI and SPI flash emuation in sandbox. This must be enabled +U-Boot supports SPI and SPI flash emulation in sandbox. This must be enabled using the --spi_sf paramter when starting U-Boot. For example: diff --git a/doc/SPI/README.ti_qspi_flash b/doc/SPI/README.ti_qspi_flash index 9064739..5cc1fd0 100644 --- a/doc/SPI/README.ti_qspi_flash +++ b/doc/SPI/README.ti_qspi_flash @@ -31,7 +31,7 @@ Can be used in: Memory mapped read mode ----------------------- In this, SPI controller is configured using configuration port and then -controler is switched to memory mapped port for data read. +controller is switched to memory mapped port for data read. Driver ------ diff --git a/drivers/bios_emulator/x86emu/decode.c b/drivers/bios_emulator/x86emu/decode.c index da44c3d..a9a01b5 100644 --- a/drivers/bios_emulator/x86emu/decode.c +++ b/drivers/bios_emulator/x86emu/decode.c @@ -241,7 +241,7 @@ no segment override. Address modes such as -3[BP] or 10[BP+SI] all refer to addresses relative to SS (ie: on the stack). So, at the minimum, all decodings of addressing modes would have to set/clear a bit describing whether the access is relative to DS or SS. That is the function of the -cpu-state-varible M.x86.mode. There are several potential states: +cpu-state-variable M.x86.mode. There are several potential states: repe prefix seen (handled elsewhere) repne prefix seen (ditto) diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig index 4fe2219..6b92064 100644 --- a/drivers/dfu/Kconfig +++ b/drivers/dfu/Kconfig @@ -3,8 +3,8 @@ menu "DFU support" config DFU_TFTP bool "DFU via TFTP" help - This option allows performing update of DFU managed medium with data - send via TFTP boot. - Detailed description of this feature can be found at ./doc/README.dfutftp + This option allows performing update of DFU-managed medium with data + sent via TFTP boot. + Detailed description of this feature can be found at ./doc/README.dfutftp endmenu diff --git a/drivers/net/macb.c b/drivers/net/macb.c index be0659a..4bf8fa4 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -120,7 +120,7 @@ static int macb_is_gem(struct macb_device *macb) static int gem_is_gigabit_capable(struct macb_device *macb) { /* - * The GEM controllers embeded in SAMA5D2 and SAMA5D4 are + * The GEM controllers embedded in SAMA5D2 and SAMA5D4 are * configured to support only 10/100. */ return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4(); diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 443a4da..2fa2016 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -1,5 +1,5 @@ /* - * sh_eth.c - Driver for Renesas ethernet controler. + * sh_eth.c - Driver for Renesas ethernet controller. * * Copyright (C) 2008, 2011 Renesas Solutions Corp. * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index 5cb520c..3645f0e 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -1,5 +1,5 @@ /* - * sh_eth.h - Driver for Renesas SuperH ethernet controler. + * sh_eth.h - Driver for Renesas SuperH ethernet controller. * * Copyright (C) 2008 - 2012 Renesas Solutions Corp. * Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 3c6b36d..8e22ea7 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -1,7 +1,7 @@ config DM_THERMAL bool "Driver support for thermal devices" help - Enable support for temporary-sensing devices. Some SoCs have on-chip + Enable support for temperature-sensing devices. Some SoCs have on-chip temperature sensors to permit warnings, speed throttling or even automatic power-off when the temperature gets too high or low. Other devices may be discrete but connected on a suitable bus. diff --git a/include/configs/hikey.h b/include/configs/hikey.h index 0851626..29eb498 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -125,7 +125,7 @@ BOOTENV -/* Preserve enviroment on sd card */ +/* Preserve environment on sd card */ #define CONFIG_COMMAND_HISTORY #define CONFIG_ENV_SIZE 0x1000 diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 304e1ce..df22fec 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -152,7 +152,7 @@ #define CONFIG_PREBOOT \ "echo ======================NOTICE============================;"\ "echo \"The u-boot environment is not set.\";" \ - "echo \"If using a display a valid display varible for your panel\";" \ + "echo \"If using a display a valid display variable for your panel\";" \ "echo \"needs to be set.\";" \ "echo \"Valid display options are:\";" \ "echo \" 2 == LQ121S1DG31 TFT SVGA (12.1) Sharp\";" \ diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h index 1a670cb..c1adc04 100644 --- a/include/configs/pengwyn.h +++ b/include/configs/pengwyn.h @@ -102,7 +102,7 @@ "run mmcboot;" \ "run nandboot;" -/* NS16550 Configuration: primary UART via FDTI */ +/* NS16550 Configuration: primary UART via FTDI */ #define CONFIG_SYS_NS16550_COM1 0x44e09000 #define CONFIG_BAUDRATE 115200 diff --git a/include/fdtdec.h b/include/fdtdec.h index fb88273..37d482a 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -570,7 +570,7 @@ int fdtdec_check_fdt(void); * @param id Compatible ID to look for * @param node_list Place to put list of found nodes * @param maxcount Maximum number of nodes to find - * @return number of nodes found on success, FTD_ERR_... on error + * @return number of nodes found on success, FDT_ERR_... on error */ int fdtdec_find_aliases_for_id(const void *blob, const char *name, enum fdt_compat_id id, int *node_list, int maxcount); diff --git a/tools/moveconfig.py b/tools/moveconfig.py index 6f71b55..68631b7 100755 --- a/tools/moveconfig.py +++ b/tools/moveconfig.py @@ -273,12 +273,12 @@ def log_msg(color_enabled, color, defconfig, msg): color_text(color_enabled, color, msg) + '\n' def update_cross_compile(): - """Update per-arch CROSS_COMPILE via enviroment variables + """Update per-arch CROSS_COMPILE via environment variables The default CROSS_COMPILE values are available in the CROSS_COMPILE list above. - You can override them via enviroment variables + You can override them via environment variables CROSS_COMPILE_{ARCH}. For example, if you want to override toolchain prefixes rday -- ======================================================================== Robert P. J. Day Ottawa, Ontario, CANADA http://crashcourse.ca Twitter: http://twitter.com/rpjday LinkedIn: http://ca.linkedin.com/in/rpjday ========================================================================

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[U-Boot] [PATCH] mmc: Fix error in RPMB code
by Marek Vasut 06 May '16

06 May '16

Since we do not build any board with CONFIG_SUPPORT_EMMC_RPMB , this piece of code evaded conversion. Fix the following compiler error: cmd/mmc.c: In function 'do_mmcrpmb': cmd/mmc.c:316:32: error: 'struct blk_desc' has no member named 'part_num' original_part = mmc->block_dev.part_num; ^ Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Pantelis Antoniou <panto(a)antoniou-consulting.com> Cc: Tom Rini <trini(a)konsulko.com> --- cmd/mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmd/mmc.c b/cmd/mmc.c index 39ef072..c5454bf 100644 --- a/cmd/mmc.c +++ b/cmd/mmc.c @@ -313,7 +313,7 @@ static int do_mmcrpmb(cmd_tbl_t *cmdtp, int flag, return CMD_RET_FAILURE; } /* Switch to the RPMB partition */ - original_part = mmc->block_dev.part_num; + original_part = mmc->block_dev.hwpart; if (mmc_select_hwpart(curr_device, MMC_PART_RPMB) != 0) return CMD_RET_FAILURE; ret = cp->cmd(cmdtp, flag, argc, argv); -- 2.7.0

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[U-Boot] [PATCH 0/2] Re-enabled DuoVero platform
by Ash Charles 06 May '16

06 May '16

The Gumstix DuoVero board isn't compiling currently. These patches get it compiling and booting again. Ash Charles (2): omap4: load files for legacy boot omap4: duovero: Disable EFI booting include/configs/duovero.h | 1 + include/configs/ti_omap4_common.h | 5 ++++- 2 files changed, 5 insertions(+), 1 deletion(-) -- 2.1.4

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[U-Boot] [PATCH] usb: ehci-mx6: allow board_ehci_hcd_init to fail
by Stefan Agner 06 May '16

06 May '16

There could be runtime determined board specific reason why a EHCI initialization fails (e.g. ENODEV if a Port is not available). In this case, properly return the error code. While at it, that function (board_ehci_hcd_init) has actually two documentation blocks... Use the correct function name for the documentation block of board_usb_phy_mode. Signed-off-by: Stefan Agner <stefan(a)agner.ch> --- drivers/usb/host/ehci-mx6.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index a981b50..bb48d0d 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -254,7 +254,7 @@ static void usb_oc_config(int index) } /** - * board_ehci_hcd_init - override usb phy mode + * board_usb_phy_mode - override usb phy mode * @port: usb host/otg port * * Target board specific, override usb_phy_mode. @@ -310,6 +310,7 @@ int ehci_hcd_init(int index, enum usb_init_type init, #endif struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR + (controller_spacing * index)); + int ret; if (index > 3) return -EINVAL; @@ -317,7 +318,9 @@ int ehci_hcd_init(int index, enum usb_init_type init, mdelay(1); /* Do board specific initialization */ - board_ehci_hcd_init(index); + ret = board_ehci_hcd_init(index); + if (ret) + return ret; usb_power_config(index); usb_oc_config(index); -- 2.8.2

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[U-Boot] [PATCH 1/8] mips: ath79: Fix ar71xx_regs.h indent
by Marek Vasut 06 May '16

06 May '16

The indent in this file triggers my OCD, so fix it. Replace multiple spaces with tabs and align the values in one column. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> Cc: Wills Wang <wills.wang(a)live.com> --- arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 2103 ++++++++++++----------- 1 file changed, 1069 insertions(+), 1034 deletions(-) diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h index 893dedc..bff9d05 100644 --- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h +++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h @@ -16,709 +16,744 @@ #include <linux/bitops.h> #else #ifndef BIT -#define BIT(nr) (1 << (nr)) +#define BIT(nr) (1 << (nr)) #endif #endif -#define AR71XX_APB_BASE 0x18000000 -#define AR71XX_GE0_BASE 0x19000000 -#define AR71XX_GE0_SIZE 0x10000 -#define AR71XX_GE1_BASE 0x1a000000 -#define AR71XX_GE1_SIZE 0x10000 -#define AR71XX_EHCI_BASE 0x1b000000 -#define AR71XX_EHCI_SIZE 0x1000 -#define AR71XX_OHCI_BASE 0x1c000000 -#define AR71XX_OHCI_SIZE 0x1000 -#define AR71XX_SPI_BASE 0x1f000000 -#define AR71XX_SPI_SIZE 0x01000000 - -#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) -#define AR71XX_DDR_CTRL_SIZE 0x100 -#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) -#define AR71XX_UART_SIZE 0x100 -#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) -#define AR71XX_USB_CTRL_SIZE 0x100 -#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) -#define AR71XX_GPIO_SIZE 0x100 -#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) -#define AR71XX_PLL_SIZE 0x100 -#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) -#define AR71XX_RESET_SIZE 0x100 -#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000) -#define AR71XX_MII_SIZE 0x100 - -#define AR71XX_PCI_MEM_BASE 0x10000000 -#define AR71XX_PCI_MEM_SIZE 0x07000000 - -#define AR71XX_PCI_WIN0_OFFS 0x10000000 -#define AR71XX_PCI_WIN1_OFFS 0x11000000 -#define AR71XX_PCI_WIN2_OFFS 0x12000000 -#define AR71XX_PCI_WIN3_OFFS 0x13000000 -#define AR71XX_PCI_WIN4_OFFS 0x14000000 -#define AR71XX_PCI_WIN5_OFFS 0x15000000 -#define AR71XX_PCI_WIN6_OFFS 0x16000000 -#define AR71XX_PCI_WIN7_OFFS 0x07000000 +#define AR71XX_APB_BASE 0x18000000 +#define AR71XX_GE0_BASE 0x19000000 +#define AR71XX_GE0_SIZE 0x10000 +#define AR71XX_GE1_BASE 0x1a000000 +#define AR71XX_GE1_SIZE 0x10000 +#define AR71XX_EHCI_BASE 0x1b000000 +#define AR71XX_EHCI_SIZE 0x1000 +#define AR71XX_OHCI_BASE 0x1c000000 +#define AR71XX_OHCI_SIZE 0x1000 +#define AR71XX_SPI_BASE 0x1f000000 +#define AR71XX_SPI_SIZE 0x01000000 + +#define AR71XX_DDR_CTRL_BASE \ + (AR71XX_APB_BASE + 0x00000000) +#define AR71XX_DDR_CTRL_SIZE 0x100 +#define AR71XX_UART_BASE \ + (AR71XX_APB_BASE + 0x00020000) +#define AR71XX_UART_SIZE 0x100 +#define AR71XX_USB_CTRL_BASE \ + (AR71XX_APB_BASE + 0x00030000) +#define AR71XX_USB_CTRL_SIZE 0x100 +#define AR71XX_GPIO_BASE \ + (AR71XX_APB_BASE + 0x00040000) +#define AR71XX_GPIO_SIZE 0x100 +#define AR71XX_PLL_BASE \ + (AR71XX_APB_BASE + 0x00050000) +#define AR71XX_PLL_SIZE 0x100 +#define AR71XX_RESET_BASE \ + (AR71XX_APB_BASE + 0x00060000) +#define AR71XX_RESET_SIZE 0x100 +#define AR71XX_MII_BASE \ + (AR71XX_APB_BASE + 0x00070000) +#define AR71XX_MII_SIZE 0x100 + +#define AR71XX_PCI_MEM_BASE 0x10000000 +#define AR71XX_PCI_MEM_SIZE 0x07000000 + +#define AR71XX_PCI_WIN0_OFFS 0x10000000 +#define AR71XX_PCI_WIN1_OFFS 0x11000000 +#define AR71XX_PCI_WIN2_OFFS 0x12000000 +#define AR71XX_PCI_WIN3_OFFS 0x13000000 +#define AR71XX_PCI_WIN4_OFFS 0x14000000 +#define AR71XX_PCI_WIN5_OFFS 0x15000000 +#define AR71XX_PCI_WIN6_OFFS 0x16000000 +#define AR71XX_PCI_WIN7_OFFS 0x07000000 #define AR71XX_PCI_CFG_BASE \ (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000) -#define AR71XX_PCI_CFG_SIZE 0x100 - -#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) -#define AR7240_USB_CTRL_SIZE 0x100 -#define AR7240_OHCI_BASE 0x1b000000 -#define AR7240_OHCI_SIZE 0x1000 - -#define AR724X_PCI_MEM_BASE 0x10000000 -#define AR724X_PCI_MEM_SIZE 0x04000000 - -#define AR724X_PCI_CFG_BASE 0x14000000 -#define AR724X_PCI_CFG_SIZE 0x1000 -#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000) -#define AR724X_PCI_CRP_SIZE 0x1000 -#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000) -#define AR724X_PCI_CTRL_SIZE 0x100 - -#define AR724X_EHCI_BASE 0x1b000000 -#define AR724X_EHCI_SIZE 0x1000 - -#define AR913X_EHCI_BASE 0x1b000000 -#define AR913X_EHCI_SIZE 0x1000 -#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) -#define AR913X_WMAC_SIZE 0x30000 - -#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) -#define AR933X_UART_SIZE 0x14 -#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) -#define AR933X_GMAC_SIZE 0x04 -#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) -#define AR933X_WMAC_SIZE 0x20000 -#define AR933X_RTC_BASE (AR71XX_APB_BASE + 0x00107000) -#define AR933X_RTC_SIZE 0x1000 -#define AR933X_EHCI_BASE 0x1b000000 -#define AR933X_EHCI_SIZE 0x1000 -#define AR933X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) -#define AR933X_SRIF_SIZE 0x1000 - -#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) -#define AR934X_GMAC_SIZE 0x14 -#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) -#define AR934X_WMAC_SIZE 0x20000 -#define AR934X_EHCI_BASE 0x1b000000 -#define AR934X_EHCI_SIZE 0x200 -#define AR934X_NFC_BASE 0x1b000200 -#define AR934X_NFC_SIZE 0xb8 -#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) -#define AR934X_SRIF_SIZE 0x1000 - -#define QCA953X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) -#define QCA953X_GMAC_SIZE 0x14 -#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) -#define QCA953X_WMAC_SIZE 0x20000 -#define QCA953X_RTC_BASE (AR71XX_APB_BASE + 0x00107000) -#define QCA953X_RTC_SIZE 0x1000 -#define QCA953X_EHCI_BASE 0x1b000000 -#define QCA953X_EHCI_SIZE 0x200 -#define QCA953X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) -#define QCA953X_SRIF_SIZE 0x1000 - -#define QCA953X_PCI_CFG_BASE0 0x14000000 -#define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) -#define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) -#define QCA953X_PCI_MEM_BASE0 0x10000000 -#define QCA953X_PCI_MEM_SIZE 0x02000000 - -#define QCA955X_PCI_MEM_BASE0 0x10000000 -#define QCA955X_PCI_MEM_BASE1 0x12000000 -#define QCA955X_PCI_MEM_SIZE 0x02000000 -#define QCA955X_PCI_CFG_BASE0 0x14000000 -#define QCA955X_PCI_CFG_BASE1 0x16000000 -#define QCA955X_PCI_CFG_SIZE 0x1000 -#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) -#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) -#define QCA955X_PCI_CRP_SIZE 0x1000 -#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) -#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) -#define QCA955X_PCI_CTRL_SIZE 0x100 - -#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) -#define QCA955X_GMAC_SIZE 0x40 -#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) -#define QCA955X_WMAC_SIZE 0x20000 -#define QCA955X_EHCI0_BASE 0x1b000000 -#define QCA955X_EHCI1_BASE 0x1b400000 -#define QCA955X_EHCI_SIZE 0x1000 -#define QCA955X_NFC_BASE 0x1b800200 -#define QCA955X_NFC_SIZE 0xb8 - -#define QCA956X_PCI_MEM_BASE1 0x12000000 -#define QCA956X_PCI_MEM_SIZE 0x02000000 -#define QCA956X_PCI_CFG_BASE1 0x16000000 -#define QCA956X_PCI_CFG_SIZE 0x1000 -#define QCA956X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) -#define QCA956X_PCI_CRP_SIZE 0x1000 -#define QCA956X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) -#define QCA956X_PCI_CTRL_SIZE 0x100 - -#define QCA956X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) -#define QCA956X_WMAC_SIZE 0x20000 -#define QCA956X_EHCI0_BASE 0x1b000000 -#define QCA956X_EHCI1_BASE 0x1b400000 -#define QCA956X_EHCI_SIZE 0x200 -#define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) -#define QCA956X_GMAC_SIZE 0x64 +#define AR71XX_PCI_CFG_SIZE 0x100 + +#define AR7240_USB_CTRL_BASE \ + (AR71XX_APB_BASE + 0x00030000) +#define AR7240_USB_CTRL_SIZE 0x100 +#define AR7240_OHCI_BASE 0x1b000000 +#define AR7240_OHCI_SIZE 0x1000 + +#define AR724X_PCI_MEM_BASE 0x10000000 +#define AR724X_PCI_MEM_SIZE 0x04000000 + +#define AR724X_PCI_CFG_BASE 0x14000000 +#define AR724X_PCI_CFG_SIZE 0x1000 +#define AR724X_PCI_CRP_BASE \ + (AR71XX_APB_BASE + 0x000c0000) +#define AR724X_PCI_CRP_SIZE 0x1000 +#define AR724X_PCI_CTRL_BASE \ + (AR71XX_APB_BASE + 0x000f0000) +#define AR724X_PCI_CTRL_SIZE 0x100 + +#define AR724X_EHCI_BASE 0x1b000000 +#define AR724X_EHCI_SIZE 0x1000 + +#define AR913X_EHCI_BASE 0x1b000000 +#define AR913X_EHCI_SIZE 0x1000 +#define AR913X_WMAC_BASE \ + (AR71XX_APB_BASE + 0x000C0000) +#define AR913X_WMAC_SIZE 0x30000 + +#define AR933X_UART_BASE \ + (AR71XX_APB_BASE + 0x00020000) +#define AR933X_UART_SIZE 0x14 +#define AR933X_GMAC_BASE \ + (AR71XX_APB_BASE + 0x00070000) +#define AR933X_GMAC_SIZE 0x04 +#define AR933X_WMAC_BASE \ + (AR71XX_APB_BASE + 0x00100000) +#define AR933X_WMAC_SIZE 0x20000 +#define AR933X_RTC_BASE \ + (AR71XX_APB_BASE + 0x00107000) +#define AR933X_RTC_SIZE 0x1000 +#define AR933X_EHCI_BASE 0x1b000000 +#define AR933X_EHCI_SIZE 0x1000 +#define AR933X_SRIF_BASE \ + (AR71XX_APB_BASE + 0x00116000) +#define AR933X_SRIF_SIZE 0x1000 + +#define AR934X_GMAC_BASE \ + (AR71XX_APB_BASE + 0x00070000) +#define AR934X_GMAC_SIZE 0x14 +#define AR934X_WMAC_BASE \ + (AR71XX_APB_BASE + 0x00100000) +#define AR934X_WMAC_SIZE 0x20000 +#define AR934X_EHCI_BASE 0x1b000000 +#define AR934X_EHCI_SIZE 0x200 +#define AR934X_NFC_BASE 0x1b000200 +#define AR934X_NFC_SIZE 0xb8 +#define AR934X_SRIF_BASE \ + (AR71XX_APB_BASE + 0x00116000) +#define AR934X_SRIF_SIZE 0x1000 + +#define QCA953X_GMAC_BASE \ + (AR71XX_APB_BASE + 0x00070000) +#define QCA953X_GMAC_SIZE 0x14 +#define QCA953X_WMAC_BASE \ + (AR71XX_APB_BASE + 0x00100000) +#define QCA953X_WMAC_SIZE 0x20000 +#define QCA953X_RTC_BASE \ + (AR71XX_APB_BASE + 0x00107000) +#define QCA953X_RTC_SIZE 0x1000 +#define QCA953X_EHCI_BASE 0x1b000000 +#define QCA953X_EHCI_SIZE 0x200 +#define QCA953X_SRIF_BASE \ + (AR71XX_APB_BASE + 0x00116000) +#define QCA953X_SRIF_SIZE 0x1000 + +#define QCA953X_PCI_CFG_BASE0 0x14000000 +#define QCA953X_PCI_CTRL_BASE0 \ + (AR71XX_APB_BASE + 0x000f0000) +#define QCA953X_PCI_CRP_BASE0 \ + (AR71XX_APB_BASE + 0x000c0000) +#define QCA953X_PCI_MEM_BASE0 0x10000000 +#define QCA953X_PCI_MEM_SIZE 0x02000000 + +#define QCA955X_PCI_MEM_BASE0 0x10000000 +#define QCA955X_PCI_MEM_BASE1 0x12000000 +#define QCA955X_PCI_MEM_SIZE 0x02000000 +#define QCA955X_PCI_CFG_BASE0 0x14000000 +#define QCA955X_PCI_CFG_BASE1 0x16000000 +#define QCA955X_PCI_CFG_SIZE 0x1000 +#define QCA955X_PCI_CRP_BASE0 \ + (AR71XX_APB_BASE + 0x000c0000) +#define QCA955X_PCI_CRP_BASE1 \ + (AR71XX_APB_BASE + 0x00250000) +#define QCA955X_PCI_CRP_SIZE 0x1000 +#define QCA955X_PCI_CTRL_BASE0 \ + (AR71XX_APB_BASE + 0x000f0000) +#define QCA955X_PCI_CTRL_BASE1 \ + (AR71XX_APB_BASE + 0x00280000) +#define QCA955X_PCI_CTRL_SIZE 0x100 + +#define QCA955X_GMAC_BASE \ + (AR71XX_APB_BASE + 0x00070000) +#define QCA955X_GMAC_SIZE 0x40 +#define QCA955X_WMAC_BASE \ + (AR71XX_APB_BASE + 0x00100000) +#define QCA955X_WMAC_SIZE 0x20000 +#define QCA955X_EHCI0_BASE 0x1b000000 +#define QCA955X_EHCI1_BASE 0x1b400000 +#define QCA955X_EHCI_SIZE 0x1000 +#define QCA955X_NFC_BASE 0x1b800200 +#define QCA955X_NFC_SIZE 0xb8 + +#define QCA956X_PCI_MEM_BASE1 0x12000000 +#define QCA956X_PCI_MEM_SIZE 0x02000000 +#define QCA956X_PCI_CFG_BASE1 0x16000000 +#define QCA956X_PCI_CFG_SIZE 0x1000 +#define QCA956X_PCI_CRP_BASE1 \ + (AR71XX_APB_BASE + 0x00250000) +#define QCA956X_PCI_CRP_SIZE 0x1000 +#define QCA956X_PCI_CTRL_BASE1 \ + (AR71XX_APB_BASE + 0x00280000) +#define QCA956X_PCI_CTRL_SIZE 0x100 + +#define QCA956X_WMAC_BASE \ + (AR71XX_APB_BASE + 0x00100000) +#define QCA956X_WMAC_SIZE 0x20000 +#define QCA956X_EHCI0_BASE 0x1b000000 +#define QCA956X_EHCI1_BASE 0x1b400000 +#define QCA956X_EHCI_SIZE 0x200 +#define QCA956X_GMAC_BASE \ + (AR71XX_APB_BASE + 0x00070000) +#define QCA956X_GMAC_SIZE 0x64 /* * DDR_CTRL block */ -#define AR71XX_DDR_REG_CONFIG 0x00 -#define AR71XX_DDR_REG_CONFIG2 0x04 -#define AR71XX_DDR_REG_MODE 0x08 -#define AR71XX_DDR_REG_EMR 0x0c -#define AR71XX_DDR_REG_CONTROL 0x10 -#define AR71XX_DDR_REG_REFRESH 0x14 -#define AR71XX_DDR_REG_RD_CYCLE 0x18 -#define AR71XX_DDR_REG_TAP_CTRL0 0x1c -#define AR71XX_DDR_REG_TAP_CTRL1 0x20 - -#define AR71XX_DDR_REG_PCI_WIN0 0x7c -#define AR71XX_DDR_REG_PCI_WIN1 0x80 -#define AR71XX_DDR_REG_PCI_WIN2 0x84 -#define AR71XX_DDR_REG_PCI_WIN3 0x88 -#define AR71XX_DDR_REG_PCI_WIN4 0x8c -#define AR71XX_DDR_REG_PCI_WIN5 0x90 -#define AR71XX_DDR_REG_PCI_WIN6 0x94 -#define AR71XX_DDR_REG_PCI_WIN7 0x98 -#define AR71XX_DDR_REG_FLUSH_GE0 0x9c -#define AR71XX_DDR_REG_FLUSH_GE1 0xa0 -#define AR71XX_DDR_REG_FLUSH_USB 0xa4 -#define AR71XX_DDR_REG_FLUSH_PCI 0xa8 - -#define AR724X_DDR_REG_FLUSH_GE0 0x7c -#define AR724X_DDR_REG_FLUSH_GE1 0x80 -#define AR724X_DDR_REG_FLUSH_USB 0x84 -#define AR724X_DDR_REG_FLUSH_PCIE 0x88 - -#define AR913X_DDR_REG_FLUSH_GE0 0x7c -#define AR913X_DDR_REG_FLUSH_GE1 0x80 -#define AR913X_DDR_REG_FLUSH_USB 0x84 -#define AR913X_DDR_REG_FLUSH_WMAC 0x88 - -#define AR933X_DDR_REG_FLUSH_GE0 0x7c -#define AR933X_DDR_REG_FLUSH_GE1 0x80 -#define AR933X_DDR_REG_FLUSH_USB 0x84 -#define AR933X_DDR_REG_FLUSH_WMAC 0x88 -#define AR933X_DDR_REG_DDR2_CONFIG 0x8c -#define AR933X_DDR_REG_EMR2 0x90 -#define AR933X_DDR_REG_EMR3 0x94 -#define AR933X_DDR_REG_BURST 0x98 -#define AR933X_DDR_REG_TIMEOUT_MAX 0x9c -#define AR933X_DDR_REG_TIMEOUT_CNT 0x9c -#define AR933X_DDR_REG_TIMEOUT_ADDR 0x9c - -#define AR934X_DDR_REG_FLUSH_GE0 0x9c -#define AR934X_DDR_REG_FLUSH_GE1 0xa0 -#define AR934X_DDR_REG_FLUSH_USB 0xa4 -#define AR934X_DDR_REG_FLUSH_PCIE 0xa8 -#define AR934X_DDR_REG_FLUSH_WMAC 0xac - -#define QCA953X_DDR_REG_FLUSH_GE0 0x9c -#define QCA953X_DDR_REG_FLUSH_GE1 0xa0 -#define QCA953X_DDR_REG_FLUSH_USB 0xa4 -#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8 -#define QCA953X_DDR_REG_FLUSH_WMAC 0xac -#define QCA953X_DDR_REG_DDR2_CONFIG 0xb8 -#define QCA953X_DDR_REG_BURST 0xc4 -#define QCA953X_DDR_REG_BURST2 0xc8 -#define QCA953X_DDR_REG_TIMEOUT_MAX 0xcc -#define QCA953X_DDR_REG_CTL_CONF 0x108 -#define QCA953X_DDR_REG_CONFIG3 0x15c +#define AR71XX_DDR_REG_CONFIG 0x00 +#define AR71XX_DDR_REG_CONFIG2 0x04 +#define AR71XX_DDR_REG_MODE 0x08 +#define AR71XX_DDR_REG_EMR 0x0c +#define AR71XX_DDR_REG_CONTROL 0x10 +#define AR71XX_DDR_REG_REFRESH 0x14 +#define AR71XX_DDR_REG_RD_CYCLE 0x18 +#define AR71XX_DDR_REG_TAP_CTRL0 0x1c +#define AR71XX_DDR_REG_TAP_CTRL1 0x20 + +#define AR71XX_DDR_REG_PCI_WIN0 0x7c +#define AR71XX_DDR_REG_PCI_WIN1 0x80 +#define AR71XX_DDR_REG_PCI_WIN2 0x84 +#define AR71XX_DDR_REG_PCI_WIN3 0x88 +#define AR71XX_DDR_REG_PCI_WIN4 0x8c +#define AR71XX_DDR_REG_PCI_WIN5 0x90 +#define AR71XX_DDR_REG_PCI_WIN6 0x94 +#define AR71XX_DDR_REG_PCI_WIN7 0x98 +#define AR71XX_DDR_REG_FLUSH_GE0 0x9c +#define AR71XX_DDR_REG_FLUSH_GE1 0xa0 +#define AR71XX_DDR_REG_FLUSH_USB 0xa4 +#define AR71XX_DDR_REG_FLUSH_PCI 0xa8 + +#define AR724X_DDR_REG_FLUSH_GE0 0x7c +#define AR724X_DDR_REG_FLUSH_GE1 0x80 +#define AR724X_DDR_REG_FLUSH_USB 0x84 +#define AR724X_DDR_REG_FLUSH_PCIE 0x88 + +#define AR913X_DDR_REG_FLUSH_GE0 0x7c +#define AR913X_DDR_REG_FLUSH_GE1 0x80 +#define AR913X_DDR_REG_FLUSH_USB 0x84 +#define AR913X_DDR_REG_FLUSH_WMAC 0x88 + +#define AR933X_DDR_REG_FLUSH_GE0 0x7c +#define AR933X_DDR_REG_FLUSH_GE1 0x80 +#define AR933X_DDR_REG_FLUSH_USB 0x84 +#define AR933X_DDR_REG_FLUSH_WMAC 0x88 +#define AR933X_DDR_REG_DDR2_CONFIG 0x8c +#define AR933X_DDR_REG_EMR2 0x90 +#define AR933X_DDR_REG_EMR3 0x94 +#define AR933X_DDR_REG_BURST 0x98 +#define AR933X_DDR_REG_TIMEOUT_MAX 0x9c +#define AR933X_DDR_REG_TIMEOUT_CNT 0x9c +#define AR933X_DDR_REG_TIMEOUT_ADDR 0x9c + +#define AR934X_DDR_REG_FLUSH_GE0 0x9c +#define AR934X_DDR_REG_FLUSH_GE1 0xa0 +#define AR934X_DDR_REG_FLUSH_USB 0xa4 +#define AR934X_DDR_REG_FLUSH_PCIE 0xa8 +#define AR934X_DDR_REG_FLUSH_WMAC 0xac + +#define QCA953X_DDR_REG_FLUSH_GE0 0x9c +#define QCA953X_DDR_REG_FLUSH_GE1 0xa0 +#define QCA953X_DDR_REG_FLUSH_USB 0xa4 +#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8 +#define QCA953X_DDR_REG_FLUSH_WMAC 0xac +#define QCA953X_DDR_REG_DDR2_CONFIG 0xb8 +#define QCA953X_DDR_REG_BURST 0xc4 +#define QCA953X_DDR_REG_BURST2 0xc8 +#define QCA953X_DDR_REG_TIMEOUT_MAX 0xcc +#define QCA953X_DDR_REG_CTL_CONF 0x108 +#define QCA953X_DDR_REG_CONFIG3 0x15c /* * PLL block */ -#define AR71XX_PLL_REG_CPU_CONFIG 0x00 -#define AR71XX_PLL_REG_SEC_CONFIG 0x04 -#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 -#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 - -#define AR71XX_PLL_DIV_SHIFT 3 -#define AR71XX_PLL_DIV_MASK 0x1f -#define AR71XX_CPU_DIV_SHIFT 16 -#define AR71XX_CPU_DIV_MASK 0x3 -#define AR71XX_DDR_DIV_SHIFT 18 -#define AR71XX_DDR_DIV_MASK 0x3 -#define AR71XX_AHB_DIV_SHIFT 20 -#define AR71XX_AHB_DIV_MASK 0x7 - -#define AR71XX_ETH0_PLL_SHIFT 17 -#define AR71XX_ETH1_PLL_SHIFT 19 - -#define AR724X_PLL_REG_CPU_CONFIG 0x00 -#define AR724X_PLL_REG_PCIE_CONFIG 0x18 - -#define AR724X_PLL_DIV_SHIFT 0 -#define AR724X_PLL_DIV_MASK 0x3ff -#define AR724X_PLL_REF_DIV_SHIFT 10 -#define AR724X_PLL_REF_DIV_MASK 0xf -#define AR724X_AHB_DIV_SHIFT 19 -#define AR724X_AHB_DIV_MASK 0x1 -#define AR724X_DDR_DIV_SHIFT 22 -#define AR724X_DDR_DIV_MASK 0x3 - -#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c - -#define AR913X_PLL_REG_CPU_CONFIG 0x00 -#define AR913X_PLL_REG_ETH_CONFIG 0x04 -#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 -#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18 - -#define AR913X_PLL_DIV_SHIFT 0 -#define AR913X_PLL_DIV_MASK 0x3ff -#define AR913X_DDR_DIV_SHIFT 22 -#define AR913X_DDR_DIV_MASK 0x3 -#define AR913X_AHB_DIV_SHIFT 19 -#define AR913X_AHB_DIV_MASK 0x1 - -#define AR913X_ETH0_PLL_SHIFT 20 -#define AR913X_ETH1_PLL_SHIFT 22 - -#define AR933X_PLL_CPU_CONFIG_REG 0x00 -#define AR933X_PLL_CLK_CTRL_REG 0x08 -#define AR933X_PLL_DITHER_FRAC_REG 0x10 - -#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 -#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f -#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 -#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f -#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 -#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 - -#define AR933X_PLL_CLK_CTRL_BYPASS BIT(2) -#define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 -#define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x3 -#define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 -#define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x3 -#define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 -#define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x7 - -#define AR934X_PLL_CPU_CONFIG_REG 0x00 -#define AR934X_PLL_DDR_CONFIG_REG 0x04 -#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 -#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 -#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c - -#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 -#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f -#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6 -#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f -#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 -#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f -#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 -#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 - -#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 -#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff -#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10 -#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f -#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 -#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f -#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 -#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 - -#define AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) -#define AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) -#define AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) -#define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 -#define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f -#define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 -#define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f -#define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 -#define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f -#define AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) -#define AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) -#define AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) - -#define AR934X_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL BIT(6) - -#define QCA953X_PLL_CPU_CONFIG_REG 0x00 -#define QCA953X_PLL_DDR_CONFIG_REG 0x04 -#define QCA953X_PLL_CLK_CTRL_REG 0x08 -#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 -#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c -#define QCA953X_PLL_DDR_DIT_FRAC_REG 0x44 -#define QCA953X_PLL_CPU_DIT_FRAC_REG 0x48 - -#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 -#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f -#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6 -#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f -#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 -#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f -#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 -#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 - -#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 -#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff -#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10 -#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f -#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 -#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f -#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 -#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 - -#define QCA953X_PLL_CONFIG_PWD BIT(30) - -#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) -#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) -#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) -#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 -#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f -#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 -#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f -#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 -#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f -#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) -#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) -#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) - -#define QCA953X_PLL_CPU_DIT_FRAC_MAX_SHIFT 0 -#define QCA953X_PLL_CPU_DIT_FRAC_MAX_MASK 0x3f -#define QCA953X_PLL_CPU_DIT_FRAC_MIN_SHIFT 6 -#define QCA953X_PLL_CPU_DIT_FRAC_MIN_MASK 0x3f -#define QCA953X_PLL_CPU_DIT_FRAC_STEP_SHIFT 12 -#define QCA953X_PLL_CPU_DIT_FRAC_STEP_MASK 0x3f -#define QCA953X_PLL_CPU_DIT_UPD_CNT_SHIFT 18 -#define QCA953X_PLL_CPU_DIT_UPD_CNT_MASK 0x3f - -#define QCA953X_PLL_DDR_DIT_FRAC_MAX_SHIFT 0 -#define QCA953X_PLL_DDR_DIT_FRAC_MAX_MASK 0x3ff -#define QCA953X_PLL_DDR_DIT_FRAC_MIN_SHIFT 9 -#define QCA953X_PLL_DDR_DIT_FRAC_MIN_MASK 0x3ff -#define QCA953X_PLL_DDR_DIT_FRAC_STEP_SHIFT 20 -#define QCA953X_PLL_DDR_DIT_FRAC_STEP_MASK 0x3f -#define QCA953X_PLL_DDR_DIT_UPD_CNT_SHIFT 27 -#define QCA953X_PLL_DDR_DIT_UPD_CNT_MASK 0x3f - -#define QCA953X_PLL_DIT_FRAC_EN BIT(31) - -#define QCA955X_PLL_CPU_CONFIG_REG 0x00 -#define QCA955X_PLL_DDR_CONFIG_REG 0x04 -#define QCA955X_PLL_CLK_CTRL_REG 0x08 -#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28 -#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48 - -#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 -#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f -#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6 -#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f -#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 -#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f -#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 -#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 - -#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 -#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff -#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10 -#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f -#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 -#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f -#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 -#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 - -#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) -#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) -#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) -#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 -#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f -#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 -#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f -#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 -#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f -#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) -#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) -#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) - -#define QCA956X_PLL_CPU_CONFIG_REG 0x00 -#define QCA956X_PLL_CPU_CONFIG1_REG 0x04 -#define QCA956X_PLL_DDR_CONFIG_REG 0x08 -#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c -#define QCA956X_PLL_CLK_CTRL_REG 0x10 - -#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 -#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f -#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 -#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 - -#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0 -#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f -#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5 -#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x3fff -#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18 -#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff - -#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 -#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f -#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 -#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 - -#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0 -#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f -#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5 -#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x3fff -#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18 -#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff - -#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) -#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) -#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) -#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 -#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f -#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 -#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f -#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 -#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f -#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20) -#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21) -#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) +#define AR71XX_PLL_REG_CPU_CONFIG 0x00 +#define AR71XX_PLL_REG_SEC_CONFIG 0x04 +#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 +#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 + +#define AR71XX_PLL_DIV_SHIFT 3 +#define AR71XX_PLL_DIV_MASK 0x1f +#define AR71XX_CPU_DIV_SHIFT 16 +#define AR71XX_CPU_DIV_MASK 0x3 +#define AR71XX_DDR_DIV_SHIFT 18 +#define AR71XX_DDR_DIV_MASK 0x3 +#define AR71XX_AHB_DIV_SHIFT 20 +#define AR71XX_AHB_DIV_MASK 0x7 + +#define AR71XX_ETH0_PLL_SHIFT 17 +#define AR71XX_ETH1_PLL_SHIFT 19 + +#define AR724X_PLL_REG_CPU_CONFIG 0x00 +#define AR724X_PLL_REG_PCIE_CONFIG 0x18 + +#define AR724X_PLL_DIV_SHIFT 0 +#define AR724X_PLL_DIV_MASK 0x3ff +#define AR724X_PLL_REF_DIV_SHIFT 10 +#define AR724X_PLL_REF_DIV_MASK 0xf +#define AR724X_AHB_DIV_SHIFT 19 +#define AR724X_AHB_DIV_MASK 0x1 +#define AR724X_DDR_DIV_SHIFT 22 +#define AR724X_DDR_DIV_MASK 0x3 + +#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c + +#define AR913X_PLL_REG_CPU_CONFIG 0x00 +#define AR913X_PLL_REG_ETH_CONFIG 0x04 +#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 +#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18 + +#define AR913X_PLL_DIV_SHIFT 0 +#define AR913X_PLL_DIV_MASK 0x3ff +#define AR913X_DDR_DIV_SHIFT 22 +#define AR913X_DDR_DIV_MASK 0x3 +#define AR913X_AHB_DIV_SHIFT 19 +#define AR913X_AHB_DIV_MASK 0x1 + +#define AR913X_ETH0_PLL_SHIFT 20 +#define AR913X_ETH1_PLL_SHIFT 22 + +#define AR933X_PLL_CPU_CONFIG_REG 0x00 +#define AR933X_PLL_CLK_CTRL_REG 0x08 +#define AR933X_PLL_DITHER_FRAC_REG 0x10 + +#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 +#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 +#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 +#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define AR933X_PLL_CLK_CTRL_BYPASS BIT(2) +#define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x3 +#define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x3 +#define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x7 + +#define AR934X_PLL_CPU_CONFIG_REG 0x00 +#define AR934X_PLL_DDR_CONFIG_REG 0x04 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 +#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c + +#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 + +#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +#define AR934X_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL BIT(6) + +#define QCA953X_PLL_CPU_CONFIG_REG 0x00 +#define QCA953X_PLL_DDR_CONFIG_REG 0x04 +#define QCA953X_PLL_CLK_CTRL_REG 0x08 +#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 +#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c +#define QCA953X_PLL_DDR_DIT_FRAC_REG 0x44 +#define QCA953X_PLL_CPU_DIT_FRAC_REG 0x48 + +#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define QCA953X_PLL_CONFIG_PWD BIT(30) + +#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +#define QCA953X_PLL_CPU_DIT_FRAC_MAX_SHIFT 0 +#define QCA953X_PLL_CPU_DIT_FRAC_MAX_MASK 0x3f +#define QCA953X_PLL_CPU_DIT_FRAC_MIN_SHIFT 6 +#define QCA953X_PLL_CPU_DIT_FRAC_MIN_MASK 0x3f +#define QCA953X_PLL_CPU_DIT_FRAC_STEP_SHIFT 12 +#define QCA953X_PLL_CPU_DIT_FRAC_STEP_MASK 0x3f +#define QCA953X_PLL_CPU_DIT_UPD_CNT_SHIFT 18 +#define QCA953X_PLL_CPU_DIT_UPD_CNT_MASK 0x3f + +#define QCA953X_PLL_DDR_DIT_FRAC_MAX_SHIFT 0 +#define QCA953X_PLL_DDR_DIT_FRAC_MAX_MASK 0x3ff +#define QCA953X_PLL_DDR_DIT_FRAC_MIN_SHIFT 9 +#define QCA953X_PLL_DDR_DIT_FRAC_MIN_MASK 0x3ff +#define QCA953X_PLL_DDR_DIT_FRAC_STEP_SHIFT 20 +#define QCA953X_PLL_DDR_DIT_FRAC_STEP_MASK 0x3f +#define QCA953X_PLL_DDR_DIT_UPD_CNT_SHIFT 27 +#define QCA953X_PLL_DDR_DIT_UPD_CNT_MASK 0x3f + +#define QCA953X_PLL_DIT_FRAC_EN BIT(31) + +#define QCA955X_PLL_CPU_CONFIG_REG 0x00 +#define QCA955X_PLL_DDR_CONFIG_REG 0x04 +#define QCA955X_PLL_CLK_CTRL_REG 0x08 +#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28 +#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48 + +#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 + +#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +#define QCA956X_PLL_CPU_CONFIG_REG 0x00 +#define QCA956X_PLL_CPU_CONFIG1_REG 0x04 +#define QCA956X_PLL_DDR_CONFIG_REG 0x08 +#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c +#define QCA956X_PLL_CLK_CTRL_REG 0x10 + +#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x3fff +#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18 +#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff + +#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x3fff +#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18 +#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff + +#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20) +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21) +#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) /* * USB_CONFIG block */ -#define AR71XX_USB_CTRL_REG_FLADJ 0x00 -#define AR71XX_USB_CTRL_REG_CONFIG 0x04 +#define AR71XX_USB_CTRL_REG_FLADJ 0x00 +#define AR71XX_USB_CTRL_REG_CONFIG 0x04 /* * RESET block */ -#define AR71XX_RESET_REG_TIMER 0x00 -#define AR71XX_RESET_REG_TIMER_RELOAD 0x04 -#define AR71XX_RESET_REG_WDOG_CTRL 0x08 -#define AR71XX_RESET_REG_WDOG 0x0c -#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 -#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 -#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 -#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c -#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 -#define AR71XX_RESET_REG_RESET_MODULE 0x24 -#define AR71XX_RESET_REG_PERFC_CTRL 0x2c -#define AR71XX_RESET_REG_PERFC0 0x30 -#define AR71XX_RESET_REG_PERFC1 0x34 -#define AR71XX_RESET_REG_REV_ID 0x90 - -#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18 -#define AR913X_RESET_REG_RESET_MODULE 0x1c -#define AR913X_RESET_REG_PERF_CTRL 0x20 -#define AR913X_RESET_REG_PERFC0 0x24 -#define AR913X_RESET_REG_PERFC1 0x28 - -#define AR724X_RESET_REG_RESET_MODULE 0x1c - -#define AR933X_RESET_REG_RESET_MODULE 0x1c -#define AR933X_RESET_REG_BOOTSTRAP 0xac - -#define AR934X_RESET_REG_RESET_MODULE 0x1c -#define AR934X_RESET_REG_BOOTSTRAP 0xb0 -#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac - -#define QCA953X_RESET_REG_RESET_MODULE 0x1c -#define QCA953X_RESET_REG_BOOTSTRAP 0xb0 -#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac - -#define QCA955X_RESET_REG_RESET_MODULE 0x1c -#define QCA955X_RESET_REG_BOOTSTRAP 0xb0 -#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac - -#define QCA956X_RESET_REG_RESET_MODULE 0x1c -#define QCA956X_RESET_REG_BOOTSTRAP 0xb0 -#define QCA956X_RESET_REG_EXT_INT_STATUS 0xac - -#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28) -#define MISC_INT_ETHSW BIT(12) -#define MISC_INT_TIMER4 BIT(10) -#define MISC_INT_TIMER3 BIT(9) -#define MISC_INT_TIMER2 BIT(8) -#define MISC_INT_DMA BIT(7) -#define MISC_INT_OHCI BIT(6) -#define MISC_INT_PERFC BIT(5) -#define MISC_INT_WDOG BIT(4) -#define MISC_INT_UART BIT(3) -#define MISC_INT_GPIO BIT(2) -#define MISC_INT_ERROR BIT(1) -#define MISC_INT_TIMER BIT(0) - -#define AR71XX_RESET_EXTERNAL BIT(28) -#define AR71XX_RESET_FULL_CHIP BIT(24) -#define AR71XX_RESET_CPU_NMI BIT(21) -#define AR71XX_RESET_CPU_COLD BIT(20) -#define AR71XX_RESET_DMA BIT(19) -#define AR71XX_RESET_SLIC BIT(18) -#define AR71XX_RESET_STEREO BIT(17) -#define AR71XX_RESET_DDR BIT(16) -#define AR71XX_RESET_GE1_MAC BIT(13) -#define AR71XX_RESET_GE1_PHY BIT(12) -#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10) -#define AR71XX_RESET_GE0_MAC BIT(9) -#define AR71XX_RESET_GE0_PHY BIT(8) -#define AR71XX_RESET_USB_OHCI_DLL BIT(6) -#define AR71XX_RESET_USB_HOST BIT(5) -#define AR71XX_RESET_USB_PHY BIT(4) -#define AR71XX_RESET_PCI_BUS BIT(1) -#define AR71XX_RESET_PCI_CORE BIT(0) - -#define AR7240_RESET_USB_HOST BIT(5) -#define AR7240_RESET_OHCI_DLL BIT(3) - -#define AR724X_RESET_GE1_MDIO BIT(23) -#define AR724X_RESET_GE0_MDIO BIT(22) -#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) -#define AR724X_RESET_PCIE_PHY BIT(7) -#define AR724X_RESET_PCIE BIT(6) -#define AR724X_RESET_USB_HOST BIT(5) -#define AR724X_RESET_USB_PHY BIT(4) -#define AR724X_RESET_USBSUS_OVERRIDE BIT(3) - -#define AR913X_RESET_AMBA2WMAC BIT(22) -#define AR913X_RESET_USBSUS_OVERRIDE BIT(10) -#define AR913X_RESET_USB_HOST BIT(5) -#define AR913X_RESET_USB_PHY BIT(4) - -#define AR933X_RESET_GE1_MDIO BIT(23) -#define AR933X_RESET_GE0_MDIO BIT(22) -#define AR933X_RESET_GE1_MAC BIT(13) -#define AR933X_RESET_WMAC BIT(11) -#define AR933X_RESET_GE0_MAC BIT(9) -#define AR933X_RESET_USB_HOST BIT(5) -#define AR933X_RESET_USB_PHY BIT(4) -#define AR933X_RESET_USBSUS_OVERRIDE BIT(3) - -#define AR934X_RESET_HOST BIT(31) -#define AR934X_RESET_SLIC BIT(30) -#define AR934X_RESET_HDMA BIT(29) -#define AR934X_RESET_EXTERNAL BIT(28) -#define AR934X_RESET_RTC BIT(27) -#define AR934X_RESET_PCIE_EP_INT BIT(26) -#define AR934X_RESET_CHKSUM_ACC BIT(25) -#define AR934X_RESET_FULL_CHIP BIT(24) -#define AR934X_RESET_GE1_MDIO BIT(23) -#define AR934X_RESET_GE0_MDIO BIT(22) -#define AR934X_RESET_CPU_NMI BIT(21) -#define AR934X_RESET_CPU_COLD BIT(20) -#define AR934X_RESET_HOST_RESET_INT BIT(19) -#define AR934X_RESET_PCIE_EP BIT(18) -#define AR934X_RESET_UART1 BIT(17) -#define AR934X_RESET_DDR BIT(16) -#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) -#define AR934X_RESET_NANDF BIT(14) -#define AR934X_RESET_GE1_MAC BIT(13) -#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12) -#define AR934X_RESET_USB_PHY_ANALOG BIT(11) -#define AR934X_RESET_HOST_DMA_INT BIT(10) -#define AR934X_RESET_GE0_MAC BIT(9) -#define AR934X_RESET_ETH_SWITCH BIT(8) -#define AR934X_RESET_PCIE_PHY BIT(7) -#define AR934X_RESET_PCIE BIT(6) -#define AR934X_RESET_USB_HOST BIT(5) -#define AR934X_RESET_USB_PHY BIT(4) -#define AR934X_RESET_USBSUS_OVERRIDE BIT(3) -#define AR934X_RESET_LUT BIT(2) -#define AR934X_RESET_MBOX BIT(1) -#define AR934X_RESET_I2S BIT(0) - -#define QCA953X_RESET_USB_EXT_PWR BIT(29) -#define QCA953X_RESET_EXTERNAL BIT(28) -#define QCA953X_RESET_RTC BIT(27) -#define QCA953X_RESET_FULL_CHIP BIT(24) -#define QCA953X_RESET_GE1_MDIO BIT(23) -#define QCA953X_RESET_GE0_MDIO BIT(22) -#define QCA953X_RESET_CPU_NMI BIT(21) -#define QCA953X_RESET_CPU_COLD BIT(20) -#define QCA953X_RESET_DDR BIT(16) -#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) -#define QCA953X_RESET_GE1_MAC BIT(13) -#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12) -#define QCA953X_RESET_USB_PHY_ANALOG BIT(11) -#define QCA953X_RESET_GE0_MAC BIT(9) -#define QCA953X_RESET_ETH_SWITCH BIT(8) -#define QCA953X_RESET_PCIE_PHY BIT(7) -#define QCA953X_RESET_PCIE BIT(6) -#define QCA953X_RESET_USB_HOST BIT(5) -#define QCA953X_RESET_USB_PHY BIT(4) -#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3) - -#define QCA955X_RESET_HOST BIT(31) -#define QCA955X_RESET_SLIC BIT(30) -#define QCA955X_RESET_HDMA BIT(29) -#define QCA955X_RESET_EXTERNAL BIT(28) -#define QCA955X_RESET_RTC BIT(27) -#define QCA955X_RESET_PCIE_EP_INT BIT(26) -#define QCA955X_RESET_CHKSUM_ACC BIT(25) -#define QCA955X_RESET_FULL_CHIP BIT(24) -#define QCA955X_RESET_GE1_MDIO BIT(23) -#define QCA955X_RESET_GE0_MDIO BIT(22) -#define QCA955X_RESET_CPU_NMI BIT(21) -#define QCA955X_RESET_CPU_COLD BIT(20) -#define QCA955X_RESET_HOST_RESET_INT BIT(19) -#define QCA955X_RESET_PCIE_EP BIT(18) -#define QCA955X_RESET_UART1 BIT(17) -#define QCA955X_RESET_DDR BIT(16) -#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) -#define QCA955X_RESET_NANDF BIT(14) -#define QCA955X_RESET_GE1_MAC BIT(13) -#define QCA955X_RESET_SGMII_ANALOG BIT(12) -#define QCA955X_RESET_USB_PHY_ANALOG BIT(11) -#define QCA955X_RESET_HOST_DMA_INT BIT(10) -#define QCA955X_RESET_GE0_MAC BIT(9) -#define QCA955X_RESET_SGMII BIT(8) -#define QCA955X_RESET_PCIE_PHY BIT(7) -#define QCA955X_RESET_PCIE BIT(6) -#define QCA955X_RESET_USB_HOST BIT(5) -#define QCA955X_RESET_USB_PHY BIT(4) -#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3) -#define QCA955X_RESET_LUT BIT(2) -#define QCA955X_RESET_MBOX BIT(1) -#define QCA955X_RESET_I2S BIT(0) - -#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) -#define AR933X_BOOTSTRAP_DDR2 BIT(13) -#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) -#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) - -#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) -#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22) -#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21) -#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20) -#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19) -#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18) -#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17) -#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16) -#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7) -#define AR934X_BOOTSTRAP_PCIE_RC BIT(6) -#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5) -#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4) -#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2) -#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) -#define AR934X_BOOTSTRAP_DDR1 BIT(0) - -#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12) -#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11) -#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5) -#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4) -#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1) -#define QCA953X_BOOTSTRAP_DDR1 BIT(0) - -#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) - -#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2) - -#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) -#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) -#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) -#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) -#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4) -#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) -#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) -#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) -#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) +#define AR71XX_RESET_REG_TIMER 0x00 +#define AR71XX_RESET_REG_TIMER_RELOAD 0x04 +#define AR71XX_RESET_REG_WDOG_CTRL 0x08 +#define AR71XX_RESET_REG_WDOG 0x0c +#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 +#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 +#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 +#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c +#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 +#define AR71XX_RESET_REG_RESET_MODULE 0x24 +#define AR71XX_RESET_REG_PERFC_CTRL 0x2c +#define AR71XX_RESET_REG_PERFC0 0x30 +#define AR71XX_RESET_REG_PERFC1 0x34 +#define AR71XX_RESET_REG_REV_ID 0x90 + +#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18 +#define AR913X_RESET_REG_RESET_MODULE 0x1c +#define AR913X_RESET_REG_PERF_CTRL 0x20 +#define AR913X_RESET_REG_PERFC0 0x24 +#define AR913X_RESET_REG_PERFC1 0x28 + +#define AR724X_RESET_REG_RESET_MODULE 0x1c + +#define AR933X_RESET_REG_RESET_MODULE 0x1c +#define AR933X_RESET_REG_BOOTSTRAP 0xac + +#define AR934X_RESET_REG_RESET_MODULE 0x1c +#define AR934X_RESET_REG_BOOTSTRAP 0xb0 +#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + +#define QCA953X_RESET_REG_RESET_MODULE 0x1c +#define QCA953X_RESET_REG_BOOTSTRAP 0xb0 +#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + +#define QCA955X_RESET_REG_RESET_MODULE 0x1c +#define QCA955X_RESET_REG_BOOTSTRAP 0xb0 +#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac + +#define QCA956X_RESET_REG_RESET_MODULE 0x1c +#define QCA956X_RESET_REG_BOOTSTRAP 0xb0 +#define QCA956X_RESET_REG_EXT_INT_STATUS 0xac + +#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28) +#define MISC_INT_ETHSW BIT(12) +#define MISC_INT_TIMER4 BIT(10) +#define MISC_INT_TIMER3 BIT(9) +#define MISC_INT_TIMER2 BIT(8) +#define MISC_INT_DMA BIT(7) +#define MISC_INT_OHCI BIT(6) +#define MISC_INT_PERFC BIT(5) +#define MISC_INT_WDOG BIT(4) +#define MISC_INT_UART BIT(3) +#define MISC_INT_GPIO BIT(2) +#define MISC_INT_ERROR BIT(1) +#define MISC_INT_TIMER BIT(0) + +#define AR71XX_RESET_EXTERNAL BIT(28) +#define AR71XX_RESET_FULL_CHIP BIT(24) +#define AR71XX_RESET_CPU_NMI BIT(21) +#define AR71XX_RESET_CPU_COLD BIT(20) +#define AR71XX_RESET_DMA BIT(19) +#define AR71XX_RESET_SLIC BIT(18) +#define AR71XX_RESET_STEREO BIT(17) +#define AR71XX_RESET_DDR BIT(16) +#define AR71XX_RESET_GE1_MAC BIT(13) +#define AR71XX_RESET_GE1_PHY BIT(12) +#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10) +#define AR71XX_RESET_GE0_MAC BIT(9) +#define AR71XX_RESET_GE0_PHY BIT(8) +#define AR71XX_RESET_USB_OHCI_DLL BIT(6) +#define AR71XX_RESET_USB_HOST BIT(5) +#define AR71XX_RESET_USB_PHY BIT(4) +#define AR71XX_RESET_PCI_BUS BIT(1) +#define AR71XX_RESET_PCI_CORE BIT(0) + +#define AR7240_RESET_USB_HOST BIT(5) +#define AR7240_RESET_OHCI_DLL BIT(3) + +#define AR724X_RESET_GE1_MDIO BIT(23) +#define AR724X_RESET_GE0_MDIO BIT(22) +#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) +#define AR724X_RESET_PCIE_PHY BIT(7) +#define AR724X_RESET_PCIE BIT(6) +#define AR724X_RESET_USB_HOST BIT(5) +#define AR724X_RESET_USB_PHY BIT(4) +#define AR724X_RESET_USBSUS_OVERRIDE BIT(3) + +#define AR913X_RESET_AMBA2WMAC BIT(22) +#define AR913X_RESET_USBSUS_OVERRIDE BIT(10) +#define AR913X_RESET_USB_HOST BIT(5) +#define AR913X_RESET_USB_PHY BIT(4) + +#define AR933X_RESET_GE1_MDIO BIT(23) +#define AR933X_RESET_GE0_MDIO BIT(22) +#define AR933X_RESET_GE1_MAC BIT(13) +#define AR933X_RESET_WMAC BIT(11) +#define AR933X_RESET_GE0_MAC BIT(9) +#define AR933X_RESET_USB_HOST BIT(5) +#define AR933X_RESET_USB_PHY BIT(4) +#define AR933X_RESET_USBSUS_OVERRIDE BIT(3) + +#define AR934X_RESET_HOST BIT(31) +#define AR934X_RESET_SLIC BIT(30) +#define AR934X_RESET_HDMA BIT(29) +#define AR934X_RESET_EXTERNAL BIT(28) +#define AR934X_RESET_RTC BIT(27) +#define AR934X_RESET_PCIE_EP_INT BIT(26) +#define AR934X_RESET_CHKSUM_ACC BIT(25) +#define AR934X_RESET_FULL_CHIP BIT(24) +#define AR934X_RESET_GE1_MDIO BIT(23) +#define AR934X_RESET_GE0_MDIO BIT(22) +#define AR934X_RESET_CPU_NMI BIT(21) +#define AR934X_RESET_CPU_COLD BIT(20) +#define AR934X_RESET_HOST_RESET_INT BIT(19) +#define AR934X_RESET_PCIE_EP BIT(18) +#define AR934X_RESET_UART1 BIT(17) +#define AR934X_RESET_DDR BIT(16) +#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) +#define AR934X_RESET_NANDF BIT(14) +#define AR934X_RESET_GE1_MAC BIT(13) +#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12) +#define AR934X_RESET_USB_PHY_ANALOG BIT(11) +#define AR934X_RESET_HOST_DMA_INT BIT(10) +#define AR934X_RESET_GE0_MAC BIT(9) +#define AR934X_RESET_ETH_SWITCH BIT(8) +#define AR934X_RESET_PCIE_PHY BIT(7) +#define AR934X_RESET_PCIE BIT(6) +#define AR934X_RESET_USB_HOST BIT(5) +#define AR934X_RESET_USB_PHY BIT(4) +#define AR934X_RESET_USBSUS_OVERRIDE BIT(3) +#define AR934X_RESET_LUT BIT(2) +#define AR934X_RESET_MBOX BIT(1) +#define AR934X_RESET_I2S BIT(0) + +#define QCA953X_RESET_USB_EXT_PWR BIT(29) +#define QCA953X_RESET_EXTERNAL BIT(28) +#define QCA953X_RESET_RTC BIT(27) +#define QCA953X_RESET_FULL_CHIP BIT(24) +#define QCA953X_RESET_GE1_MDIO BIT(23) +#define QCA953X_RESET_GE0_MDIO BIT(22) +#define QCA953X_RESET_CPU_NMI BIT(21) +#define QCA953X_RESET_CPU_COLD BIT(20) +#define QCA953X_RESET_DDR BIT(16) +#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) +#define QCA953X_RESET_GE1_MAC BIT(13) +#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12) +#define QCA953X_RESET_USB_PHY_ANALOG BIT(11) +#define QCA953X_RESET_GE0_MAC BIT(9) +#define QCA953X_RESET_ETH_SWITCH BIT(8) +#define QCA953X_RESET_PCIE_PHY BIT(7) +#define QCA953X_RESET_PCIE BIT(6) +#define QCA953X_RESET_USB_HOST BIT(5) +#define QCA953X_RESET_USB_PHY BIT(4) +#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3) + +#define QCA955X_RESET_HOST BIT(31) +#define QCA955X_RESET_SLIC BIT(30) +#define QCA955X_RESET_HDMA BIT(29) +#define QCA955X_RESET_EXTERNAL BIT(28) +#define QCA955X_RESET_RTC BIT(27) +#define QCA955X_RESET_PCIE_EP_INT BIT(26) +#define QCA955X_RESET_CHKSUM_ACC BIT(25) +#define QCA955X_RESET_FULL_CHIP BIT(24) +#define QCA955X_RESET_GE1_MDIO BIT(23) +#define QCA955X_RESET_GE0_MDIO BIT(22) +#define QCA955X_RESET_CPU_NMI BIT(21) +#define QCA955X_RESET_CPU_COLD BIT(20) +#define QCA955X_RESET_HOST_RESET_INT BIT(19) +#define QCA955X_RESET_PCIE_EP BIT(18) +#define QCA955X_RESET_UART1 BIT(17) +#define QCA955X_RESET_DDR BIT(16) +#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) +#define QCA955X_RESET_NANDF BIT(14) +#define QCA955X_RESET_GE1_MAC BIT(13) +#define QCA955X_RESET_SGMII_ANALOG BIT(12) +#define QCA955X_RESET_USB_PHY_ANALOG BIT(11) +#define QCA955X_RESET_HOST_DMA_INT BIT(10) +#define QCA955X_RESET_GE0_MAC BIT(9) +#define QCA955X_RESET_SGMII BIT(8) +#define QCA955X_RESET_PCIE_PHY BIT(7) +#define QCA955X_RESET_PCIE BIT(6) +#define QCA955X_RESET_USB_HOST BIT(5) +#define QCA955X_RESET_USB_PHY BIT(4) +#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3) +#define QCA955X_RESET_LUT BIT(2) +#define QCA955X_RESET_MBOX BIT(1) +#define QCA955X_RESET_I2S BIT(0) + +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) +#define AR933X_BOOTSTRAP_DDR2 BIT(13) +#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) +#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) + +#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) +#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22) +#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21) +#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20) +#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19) +#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18) +#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17) +#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16) +#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7) +#define AR934X_BOOTSTRAP_PCIE_RC BIT(6) +#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5) +#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4) +#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2) +#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) +#define AR934X_BOOTSTRAP_DDR1 BIT(0) + +#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12) +#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11) +#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5) +#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4) +#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1) +#define QCA953X_BOOTSTRAP_DDR1 BIT(0) + +#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) + +#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2) + +#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) +#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) +#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) +#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) +#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4) +#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) +#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) +#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) +#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) #define AR934X_PCIE_WMAC_INT_WMAC_ALL \ (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \ AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP) @@ -728,15 +763,15 @@ AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ AR934X_PCIE_WMAC_INT_PCIE_RC3) -#define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0) -#define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1) -#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) -#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) -#define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4) -#define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) -#define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) -#define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) -#define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) +#define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0) +#define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1) +#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) +#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) #define QCA953X_PCIE_WMAC_INT_WMAC_ALL \ (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \ QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP) @@ -746,22 +781,22 @@ QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \ QCA953X_PCIE_WMAC_INT_PCIE_RC3) -#define QCA955X_EXT_INT_WMAC_MISC BIT(0) -#define QCA955X_EXT_INT_WMAC_TX BIT(1) -#define QCA955X_EXT_INT_WMAC_RXLP BIT(2) -#define QCA955X_EXT_INT_WMAC_RXHP BIT(3) -#define QCA955X_EXT_INT_PCIE_RC1 BIT(4) -#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5) -#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6) -#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7) -#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8) -#define QCA955X_EXT_INT_PCIE_RC2 BIT(12) -#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13) -#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14) -#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15) -#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16) -#define QCA955X_EXT_INT_USB1 BIT(24) -#define QCA955X_EXT_INT_USB2 BIT(28) +#define QCA955X_EXT_INT_WMAC_MISC BIT(0) +#define QCA955X_EXT_INT_WMAC_TX BIT(1) +#define QCA955X_EXT_INT_WMAC_RXLP BIT(2) +#define QCA955X_EXT_INT_WMAC_RXHP BIT(3) +#define QCA955X_EXT_INT_PCIE_RC1 BIT(4) +#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5) +#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6) +#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7) +#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8) +#define QCA955X_EXT_INT_PCIE_RC2 BIT(12) +#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13) +#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14) +#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15) +#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16) +#define QCA955X_EXT_INT_USB1 BIT(24) +#define QCA955X_EXT_INT_USB2 BIT(28) #define QCA955X_EXT_INT_WMAC_ALL \ (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \ @@ -777,22 +812,22 @@ QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ QCA955X_EXT_INT_PCIE_RC2_INT3) -#define QCA956X_EXT_INT_WMAC_MISC BIT(0) -#define QCA956X_EXT_INT_WMAC_TX BIT(1) -#define QCA956X_EXT_INT_WMAC_RXLP BIT(2) -#define QCA956X_EXT_INT_WMAC_RXHP BIT(3) -#define QCA956X_EXT_INT_PCIE_RC1 BIT(4) -#define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5) -#define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6) -#define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7) -#define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8) -#define QCA956X_EXT_INT_PCIE_RC2 BIT(12) -#define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13) -#define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14) -#define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15) -#define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16) -#define QCA956X_EXT_INT_USB1 BIT(24) -#define QCA956X_EXT_INT_USB2 BIT(28) +#define QCA956X_EXT_INT_WMAC_MISC BIT(0) +#define QCA956X_EXT_INT_WMAC_TX BIT(1) +#define QCA956X_EXT_INT_WMAC_RXLP BIT(2) +#define QCA956X_EXT_INT_WMAC_RXHP BIT(3) +#define QCA956X_EXT_INT_PCIE_RC1 BIT(4) +#define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5) +#define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6) +#define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7) +#define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8) +#define QCA956X_EXT_INT_PCIE_RC2 BIT(12) +#define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13) +#define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14) +#define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15) +#define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16) +#define QCA956X_EXT_INT_USB1 BIT(24) +#define QCA956X_EXT_INT_USB2 BIT(28) #define QCA956X_EXT_INT_WMAC_ALL \ (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \ @@ -808,377 +843,377 @@ QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \ QCA956X_EXT_INT_PCIE_RC2_INT3) -#define REV_ID_MAJOR_MASK 0xfff0 -#define REV_ID_MAJOR_AR71XX 0x00a0 -#define REV_ID_MAJOR_AR913X 0x00b0 -#define REV_ID_MAJOR_AR7240 0x00c0 -#define REV_ID_MAJOR_AR7241 0x0100 -#define REV_ID_MAJOR_AR7242 0x1100 -#define REV_ID_MAJOR_AR9330 0x0110 -#define REV_ID_MAJOR_AR9331 0x1110 -#define REV_ID_MAJOR_AR9341 0x0120 -#define REV_ID_MAJOR_AR9342 0x1120 -#define REV_ID_MAJOR_AR9344 0x2120 -#define REV_ID_MAJOR_QCA9533 0x0140 -#define REV_ID_MAJOR_QCA9533_V2 0x0160 -#define REV_ID_MAJOR_QCA9556 0x0130 -#define REV_ID_MAJOR_QCA9558 0x1130 -#define REV_ID_MAJOR_TP9343 0x0150 -#define REV_ID_MAJOR_QCA9561 0x1150 - -#define AR71XX_REV_ID_MINOR_MASK 0x3 -#define AR71XX_REV_ID_MINOR_AR7130 0x0 -#define AR71XX_REV_ID_MINOR_AR7141 0x1 -#define AR71XX_REV_ID_MINOR_AR7161 0x2 -#define AR913X_REV_ID_MINOR_AR9130 0x0 -#define AR913X_REV_ID_MINOR_AR9132 0x1 - -#define AR71XX_REV_ID_REVISION_MASK 0x3 -#define AR71XX_REV_ID_REVISION_SHIFT 2 -#define AR71XX_REV_ID_REVISION2_MASK 0xf +#define REV_ID_MAJOR_MASK 0xfff0 +#define REV_ID_MAJOR_AR71XX 0x00a0 +#define REV_ID_MAJOR_AR913X 0x00b0 +#define REV_ID_MAJOR_AR7240 0x00c0 +#define REV_ID_MAJOR_AR7241 0x0100 +#define REV_ID_MAJOR_AR7242 0x1100 +#define REV_ID_MAJOR_AR9330 0x0110 +#define REV_ID_MAJOR_AR9331 0x1110 +#define REV_ID_MAJOR_AR9341 0x0120 +#define REV_ID_MAJOR_AR9342 0x1120 +#define REV_ID_MAJOR_AR9344 0x2120 +#define REV_ID_MAJOR_QCA9533 0x0140 +#define REV_ID_MAJOR_QCA9533_V2 0x0160 +#define REV_ID_MAJOR_QCA9556 0x0130 +#define REV_ID_MAJOR_QCA9558 0x1130 +#define REV_ID_MAJOR_TP9343 0x0150 +#define REV_ID_MAJOR_QCA9561 0x1150 + +#define AR71XX_REV_ID_MINOR_MASK 0x3 +#define AR71XX_REV_ID_MINOR_AR7130 0x0 +#define AR71XX_REV_ID_MINOR_AR7141 0x1 +#define AR71XX_REV_ID_MINOR_AR7161 0x2 +#define AR913X_REV_ID_MINOR_AR9130 0x0 +#define AR913X_REV_ID_MINOR_AR9132 0x1 + +#define AR71XX_REV_ID_REVISION_MASK 0x3 +#define AR71XX_REV_ID_REVISION_SHIFT 2 +#define AR71XX_REV_ID_REVISION2_MASK 0xf /* * RTC block */ -#define AR933X_RTC_REG_RESET 0x40 -#define AR933X_RTC_REG_STATUS 0x44 -#define AR933X_RTC_REG_DERIVED 0x48 -#define AR933X_RTC_REG_FORCE_WAKE 0x4c -#define AR933X_RTC_REG_INT_CAUSE 0x50 -#define AR933X_RTC_REG_CAUSE_CLR 0x50 -#define AR933X_RTC_REG_INT_ENABLE 0x54 -#define AR933X_RTC_REG_INT_MASKE 0x58 - -#define QCA953X_RTC_REG_SYNC_RESET 0x40 -#define QCA953X_RTC_REG_SYNC_STATUS 0x44 +#define AR933X_RTC_REG_RESET 0x40 +#define AR933X_RTC_REG_STATUS 0x44 +#define AR933X_RTC_REG_DERIVED 0x48 +#define AR933X_RTC_REG_FORCE_WAKE 0x4c +#define AR933X_RTC_REG_INT_CAUSE 0x50 +#define AR933X_RTC_REG_CAUSE_CLR 0x50 +#define AR933X_RTC_REG_INT_ENABLE 0x54 +#define AR933X_RTC_REG_INT_MASKE 0x58 + +#define QCA953X_RTC_REG_SYNC_RESET 0x40 +#define QCA953X_RTC_REG_SYNC_STATUS 0x44 /* * SPI block */ -#define AR71XX_SPI_REG_FS 0x00 -#define AR71XX_SPI_REG_CTRL 0x04 -#define AR71XX_SPI_REG_IOC 0x08 -#define AR71XX_SPI_REG_RDS 0x0c - -#define AR71XX_SPI_FS_GPIO BIT(0) - -#define AR71XX_SPI_CTRL_RD BIT(6) -#define AR71XX_SPI_CTRL_DIV_MASK 0x3f - -#define AR71XX_SPI_IOC_DO BIT(0) -#define AR71XX_SPI_IOC_CLK BIT(8) -#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) -#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0) -#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1) -#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2) +#define AR71XX_SPI_REG_FS 0x00 +#define AR71XX_SPI_REG_CTRL 0x04 +#define AR71XX_SPI_REG_IOC 0x08 +#define AR71XX_SPI_REG_RDS 0x0c + +#define AR71XX_SPI_FS_GPIO BIT(0) + +#define AR71XX_SPI_CTRL_RD BIT(6) +#define AR71XX_SPI_CTRL_DIV_MASK 0x3f + +#define AR71XX_SPI_IOC_DO BIT(0) +#define AR71XX_SPI_IOC_CLK BIT(8) +#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) +#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0) +#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1) +#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2) #define AR71XX_SPI_IOC_CS_ALL \ (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | AR71XX_SPI_IOC_CS2) /* * GPIO block */ -#define AR71XX_GPIO_REG_OE 0x00 -#define AR71XX_GPIO_REG_IN 0x04 -#define AR71XX_GPIO_REG_OUT 0x08 -#define AR71XX_GPIO_REG_SET 0x0c -#define AR71XX_GPIO_REG_CLEAR 0x10 -#define AR71XX_GPIO_REG_INT_MODE 0x14 -#define AR71XX_GPIO_REG_INT_TYPE 0x18 -#define AR71XX_GPIO_REG_INT_POLARITY 0x1c -#define AR71XX_GPIO_REG_INT_PENDING 0x20 -#define AR71XX_GPIO_REG_INT_ENABLE 0x24 -#define AR71XX_GPIO_REG_FUNC 0x28 -#define AR933X_GPIO_REG_FUNC 0x30 - -#define AR934X_GPIO_REG_OUT_FUNC0 0x2c -#define AR934X_GPIO_REG_OUT_FUNC1 0x30 -#define AR934X_GPIO_REG_OUT_FUNC2 0x34 -#define AR934X_GPIO_REG_OUT_FUNC3 0x38 -#define AR934X_GPIO_REG_OUT_FUNC4 0x3c -#define AR934X_GPIO_REG_OUT_FUNC5 0x40 -#define AR934X_GPIO_REG_FUNC 0x6c - -#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c -#define QCA953X_GPIO_REG_OUT_FUNC1 0x30 -#define QCA953X_GPIO_REG_OUT_FUNC2 0x34 -#define QCA953X_GPIO_REG_OUT_FUNC3 0x38 -#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c -#define QCA953X_GPIO_REG_IN_ENABLE0 0x44 -#define QCA953X_GPIO_REG_FUNC 0x6c - -#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c -#define QCA955X_GPIO_REG_OUT_FUNC1 0x30 -#define QCA955X_GPIO_REG_OUT_FUNC2 0x34 -#define QCA955X_GPIO_REG_OUT_FUNC3 0x38 -#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c -#define QCA955X_GPIO_REG_OUT_FUNC5 0x40 -#define QCA955X_GPIO_REG_FUNC 0x6c - -#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c -#define QCA956X_GPIO_REG_OUT_FUNC1 0x30 -#define QCA956X_GPIO_REG_OUT_FUNC2 0x34 -#define QCA956X_GPIO_REG_OUT_FUNC3 0x38 -#define QCA956X_GPIO_REG_OUT_FUNC4 0x3c -#define QCA956X_GPIO_REG_OUT_FUNC5 0x40 -#define QCA956X_GPIO_REG_IN_ENABLE0 0x44 -#define QCA956X_GPIO_REG_IN_ENABLE3 0x50 -#define QCA956X_GPIO_REG_FUNC 0x6c - -#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) -#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) -#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) -#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) -#define AR71XX_GPIO_FUNC_UART_EN BIT(8) -#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) -#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) - -#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) -#define AR724X_GPIO_FUNC_SPI_EN BIT(18) -#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) -#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) -#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) -#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) -#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) -#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) -#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) -#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) -#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) -#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) -#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) -#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) -#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) -#define AR724X_GPIO_FUNC_UART_EN BIT(1) -#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) - -#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22) -#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) -#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20) -#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19) -#define AR913X_GPIO_FUNC_I2S1_EN BIT(18) -#define AR913X_GPIO_FUNC_I2S0_EN BIT(17) -#define AR913X_GPIO_FUNC_SLIC_EN BIT(16) -#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9) -#define AR913X_GPIO_FUNC_UART_EN BIT(8) -#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4) - -#define AR933X_GPIO(x) BIT(x) -#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31) -#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30) -#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29) -#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27) -#define AR933X_GPIO_FUNC_I2SO_EN BIT(26) -#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25) -#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24) -#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23) -#define AR933X_GPIO_FUNC_SPI_EN BIT(18) -#define AR933X_GPIO_FUNC_RES_TRUE BIT(15) -#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14) -#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13) -#define AR933X_GPIO_FUNC_XLNA_EN BIT(12) -#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) -#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) -#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) -#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) -#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) -#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) -#define AR933X_GPIO_FUNC_UART_EN BIT(1) -#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0) - -#define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9) -#define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8) -#define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7) -#define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6) -#define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5) -#define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4) -#define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3) -#define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2) -#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1) - -#define AR934X_GPIO_OUT_GPIO 0 -#define AR934X_GPIO_OUT_SPI_CS1 7 -#define AR934X_GPIO_OUT_LED_LINK0 41 -#define AR934X_GPIO_OUT_LED_LINK1 42 -#define AR934X_GPIO_OUT_LED_LINK2 43 -#define AR934X_GPIO_OUT_LED_LINK3 44 -#define AR934X_GPIO_OUT_LED_LINK4 45 -#define AR934X_GPIO_OUT_EXT_LNA0 46 -#define AR934X_GPIO_OUT_EXT_LNA1 47 - -#define QCA953X_GPIO(x) BIT(x) -#define QCA953X_GPIO_MUX_MASK(x) (0xff << (x)) -#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10 -#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11 -#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9 -#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8 -#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12 -#define QCA953X_GPIO_OUT_MUX_UART0_SOUT 22 -#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41 -#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42 -#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43 -#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44 -#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45 - -#define QCA953X_GPIO_IN_MUX_UART0_SIN 9 -#define QCA953X_GPIO_IN_MUX_SPI_DATA_IN 8 - -#define QCA956X_GPIO_OUT_MUX_GE0_MDO 32 -#define QCA956X_GPIO_OUT_MUX_GE0_MDC 33 - -#define AR71XX_GPIO_COUNT 16 -#define AR7240_GPIO_COUNT 18 -#define AR7241_GPIO_COUNT 20 -#define AR913X_GPIO_COUNT 22 -#define AR933X_GPIO_COUNT 30 -#define AR934X_GPIO_COUNT 23 -#define QCA953X_GPIO_COUNT 18 -#define QCA955X_GPIO_COUNT 24 -#define QCA956X_GPIO_COUNT 23 +#define AR71XX_GPIO_REG_OE 0x00 +#define AR71XX_GPIO_REG_IN 0x04 +#define AR71XX_GPIO_REG_OUT 0x08 +#define AR71XX_GPIO_REG_SET 0x0c +#define AR71XX_GPIO_REG_CLEAR 0x10 +#define AR71XX_GPIO_REG_INT_MODE 0x14 +#define AR71XX_GPIO_REG_INT_TYPE 0x18 +#define AR71XX_GPIO_REG_INT_POLARITY 0x1c +#define AR71XX_GPIO_REG_INT_PENDING 0x20 +#define AR71XX_GPIO_REG_INT_ENABLE 0x24 +#define AR71XX_GPIO_REG_FUNC 0x28 +#define AR933X_GPIO_REG_FUNC 0x30 + +#define AR934X_GPIO_REG_OUT_FUNC0 0x2c +#define AR934X_GPIO_REG_OUT_FUNC1 0x30 +#define AR934X_GPIO_REG_OUT_FUNC2 0x34 +#define AR934X_GPIO_REG_OUT_FUNC3 0x38 +#define AR934X_GPIO_REG_OUT_FUNC4 0x3c +#define AR934X_GPIO_REG_OUT_FUNC5 0x40 +#define AR934X_GPIO_REG_FUNC 0x6c + +#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c +#define QCA953X_GPIO_REG_OUT_FUNC1 0x30 +#define QCA953X_GPIO_REG_OUT_FUNC2 0x34 +#define QCA953X_GPIO_REG_OUT_FUNC3 0x38 +#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c +#define QCA953X_GPIO_REG_IN_ENABLE0 0x44 +#define QCA953X_GPIO_REG_FUNC 0x6c + +#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c +#define QCA955X_GPIO_REG_OUT_FUNC1 0x30 +#define QCA955X_GPIO_REG_OUT_FUNC2 0x34 +#define QCA955X_GPIO_REG_OUT_FUNC3 0x38 +#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c +#define QCA955X_GPIO_REG_OUT_FUNC5 0x40 +#define QCA955X_GPIO_REG_FUNC 0x6c + +#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c +#define QCA956X_GPIO_REG_OUT_FUNC1 0x30 +#define QCA956X_GPIO_REG_OUT_FUNC2 0x34 +#define QCA956X_GPIO_REG_OUT_FUNC3 0x38 +#define QCA956X_GPIO_REG_OUT_FUNC4 0x3c +#define QCA956X_GPIO_REG_OUT_FUNC5 0x40 +#define QCA956X_GPIO_REG_IN_ENABLE0 0x44 +#define QCA956X_GPIO_REG_IN_ENABLE3 0x50 +#define QCA956X_GPIO_REG_FUNC 0x6c + +#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) +#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) +#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) +#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) +#define AR71XX_GPIO_FUNC_UART_EN BIT(8) +#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) +#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) + +#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) +#define AR724X_GPIO_FUNC_SPI_EN BIT(18) +#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) +#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) +#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) +#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) +#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) +#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) +#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) +#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) +#define AR724X_GPIO_FUNC_UART_EN BIT(1) +#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) + +#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22) +#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) +#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20) +#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19) +#define AR913X_GPIO_FUNC_I2S1_EN BIT(18) +#define AR913X_GPIO_FUNC_I2S0_EN BIT(17) +#define AR913X_GPIO_FUNC_SLIC_EN BIT(16) +#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9) +#define AR913X_GPIO_FUNC_UART_EN BIT(8) +#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4) + +#define AR933X_GPIO(x) BIT(x) +#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31) +#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30) +#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29) +#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27) +#define AR933X_GPIO_FUNC_I2SO_EN BIT(26) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23) +#define AR933X_GPIO_FUNC_SPI_EN BIT(18) +#define AR933X_GPIO_FUNC_RES_TRUE BIT(15) +#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14) +#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13) +#define AR933X_GPIO_FUNC_XLNA_EN BIT(12) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) +#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) +#define AR933X_GPIO_FUNC_UART_EN BIT(1) +#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0) + +#define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9) +#define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8) +#define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7) +#define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6) +#define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5) +#define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4) +#define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3) +#define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2) +#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1) + +#define AR934X_GPIO_OUT_GPIO 0 +#define AR934X_GPIO_OUT_SPI_CS1 7 +#define AR934X_GPIO_OUT_LED_LINK0 41 +#define AR934X_GPIO_OUT_LED_LINK1 42 +#define AR934X_GPIO_OUT_LED_LINK2 43 +#define AR934X_GPIO_OUT_LED_LINK3 44 +#define AR934X_GPIO_OUT_LED_LINK4 45 +#define AR934X_GPIO_OUT_EXT_LNA0 46 +#define AR934X_GPIO_OUT_EXT_LNA1 47 + +#define QCA953X_GPIO(x) BIT(x) +#define QCA953X_GPIO_MUX_MASK(x) (0xff << (x)) +#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10 +#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11 +#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9 +#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8 +#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12 +#define QCA953X_GPIO_OUT_MUX_UART0_SOUT 22 +#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41 +#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42 +#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43 +#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44 +#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45 + +#define QCA953X_GPIO_IN_MUX_UART0_SIN 9 +#define QCA953X_GPIO_IN_MUX_SPI_DATA_IN 8 + +#define QCA956X_GPIO_OUT_MUX_GE0_MDO 32 +#define QCA956X_GPIO_OUT_MUX_GE0_MDC 33 + +#define AR71XX_GPIO_COUNT 16 +#define AR7240_GPIO_COUNT 18 +#define AR7241_GPIO_COUNT 20 +#define AR913X_GPIO_COUNT 22 +#define AR933X_GPIO_COUNT 30 +#define AR934X_GPIO_COUNT 23 +#define QCA953X_GPIO_COUNT 18 +#define QCA955X_GPIO_COUNT 24 +#define QCA956X_GPIO_COUNT 23 /* * SRIF block */ -#define AR933X_SRIF_DDR_DPLL1_REG 0x240 -#define AR933X_SRIF_DDR_DPLL2_REG 0x244 -#define AR933X_SRIF_DDR_DPLL3_REG 0x248 -#define AR933X_SRIF_DDR_DPLL4_REG 0x24c +#define AR933X_SRIF_DDR_DPLL1_REG 0x240 +#define AR933X_SRIF_DDR_DPLL2_REG 0x244 +#define AR933X_SRIF_DDR_DPLL3_REG 0x248 +#define AR933X_SRIF_DDR_DPLL4_REG 0x24c -#define AR934X_SRIF_CPU_DPLL1_REG 0x1c0 -#define AR934X_SRIF_CPU_DPLL2_REG 0x1c4 -#define AR934X_SRIF_CPU_DPLL3_REG 0x1c8 +#define AR934X_SRIF_CPU_DPLL1_REG 0x1c0 +#define AR934X_SRIF_CPU_DPLL2_REG 0x1c4 +#define AR934X_SRIF_CPU_DPLL3_REG 0x1c8 -#define AR934X_SRIF_DDR_DPLL1_REG 0x240 -#define AR934X_SRIF_DDR_DPLL2_REG 0x244 -#define AR934X_SRIF_DDR_DPLL3_REG 0x248 +#define AR934X_SRIF_DDR_DPLL1_REG 0x240 +#define AR934X_SRIF_DDR_DPLL2_REG 0x244 +#define AR934X_SRIF_DDR_DPLL3_REG 0x248 -#define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27 -#define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f -#define AR934X_SRIF_DPLL1_NINT_SHIFT 18 -#define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff -#define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff +#define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27 +#define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f +#define AR934X_SRIF_DPLL1_NINT_SHIFT 18 +#define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff +#define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff -#define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30) -#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 -#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 +#define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30) +#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 +#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 -#define QCA953X_SRIF_BB_DPLL1_REG 0x180 -#define QCA953X_SRIF_BB_DPLL2_REG 0x184 -#define QCA953X_SRIF_BB_DPLL3_REG 0x188 +#define QCA953X_SRIF_BB_DPLL1_REG 0x180 +#define QCA953X_SRIF_BB_DPLL2_REG 0x184 +#define QCA953X_SRIF_BB_DPLL3_REG 0x188 -#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0 -#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4 -#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8 +#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0 +#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4 +#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8 -#define QCA953X_SRIF_DDR_DPLL1_REG 0x240 -#define QCA953X_SRIF_DDR_DPLL2_REG 0x244 -#define QCA953X_SRIF_DDR_DPLL3_REG 0x248 +#define QCA953X_SRIF_DDR_DPLL1_REG 0x240 +#define QCA953X_SRIF_DDR_DPLL2_REG 0x244 +#define QCA953X_SRIF_DDR_DPLL3_REG 0x248 -#define QCA953X_SRIF_PCIE_DPLL1_REG 0xc00 -#define QCA953X_SRIF_PCIE_DPLL2_REG 0xc04 -#define QCA953X_SRIF_PCIE_DPLL3_REG 0xc08 +#define QCA953X_SRIF_PCIE_DPLL1_REG 0xc00 +#define QCA953X_SRIF_PCIE_DPLL2_REG 0xc04 +#define QCA953X_SRIF_PCIE_DPLL3_REG 0xc08 -#define QCA953X_SRIF_PMU1_REG 0xc40 -#define QCA953X_SRIF_PMU2_REG 0xc44 +#define QCA953X_SRIF_PMU1_REG 0xc40 +#define QCA953X_SRIF_PMU2_REG 0xc44 -#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27 -#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f +#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27 +#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f -#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18 -#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff -#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff +#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18 +#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff +#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff -#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30) +#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30) -#define QCA953X_SRIF_DPLL2_KI_SHIFT 29 -#define QCA953X_SRIF_DPLL2_KI_MASK 0x3 +#define QCA953X_SRIF_DPLL2_KI_SHIFT 29 +#define QCA953X_SRIF_DPLL2_KI_MASK 0x3 -#define QCA953X_SRIF_DPLL2_KD_SHIFT 25 -#define QCA953X_SRIF_DPLL2_KD_MASK 0xf +#define QCA953X_SRIF_DPLL2_KD_SHIFT 25 +#define QCA953X_SRIF_DPLL2_KD_MASK 0xf -#define QCA953X_SRIF_DPLL2_PWD BIT(22) +#define QCA953X_SRIF_DPLL2_PWD BIT(22) -#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13 -#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7 +#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13 +#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7 /* * MII_CTRL block */ -#define AR71XX_MII_REG_MII0_CTRL 0x00 -#define AR71XX_MII_REG_MII1_CTRL 0x04 +#define AR71XX_MII_REG_MII0_CTRL 0x00 +#define AR71XX_MII_REG_MII1_CTRL 0x04 -#define AR71XX_MII_CTRL_IF_MASK 3 -#define AR71XX_MII_CTRL_SPEED_SHIFT 4 -#define AR71XX_MII_CTRL_SPEED_MASK 3 -#define AR71XX_MII_CTRL_SPEED_10 0 -#define AR71XX_MII_CTRL_SPEED_100 1 -#define AR71XX_MII_CTRL_SPEED_1000 2 +#define AR71XX_MII_CTRL_IF_MASK 3 +#define AR71XX_MII_CTRL_SPEED_SHIFT 4 +#define AR71XX_MII_CTRL_SPEED_MASK 3 +#define AR71XX_MII_CTRL_SPEED_10 0 +#define AR71XX_MII_CTRL_SPEED_100 1 +#define AR71XX_MII_CTRL_SPEED_1000 2 -#define AR71XX_MII0_CTRL_IF_GMII 0 -#define AR71XX_MII0_CTRL_IF_MII 1 -#define AR71XX_MII0_CTRL_IF_RGMII 2 -#define AR71XX_MII0_CTRL_IF_RMII 3 +#define AR71XX_MII0_CTRL_IF_GMII 0 +#define AR71XX_MII0_CTRL_IF_MII 1 +#define AR71XX_MII0_CTRL_IF_RGMII 2 +#define AR71XX_MII0_CTRL_IF_RMII 3 -#define AR71XX_MII1_CTRL_IF_RGMII 0 -#define AR71XX_MII1_CTRL_IF_RMII 1 +#define AR71XX_MII1_CTRL_IF_RGMII 0 +#define AR71XX_MII1_CTRL_IF_RMII 1 /* * AR933X GMAC interface */ -#define AR933X_GMAC_REG_ETH_CFG 0x00 - -#define AR933X_ETH_CFG_RGMII_GE0 BIT(0) -#define AR933X_ETH_CFG_MII_GE0 BIT(1) -#define AR933X_ETH_CFG_GMII_GE0 BIT(2) -#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3) -#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4) -#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5) -#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7) -#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) -#define AR933X_ETH_CFG_RMII_GE0 BIT(9) -#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0 -#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10) +#define AR933X_GMAC_REG_ETH_CFG 0x00 + +#define AR933X_ETH_CFG_RGMII_GE0 BIT(0) +#define AR933X_ETH_CFG_MII_GE0 BIT(1) +#define AR933X_ETH_CFG_GMII_GE0 BIT(2) +#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3) +#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4) +#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5) +#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) +#define AR933X_ETH_CFG_RMII_GE0 BIT(9) +#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0 +#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10) /* * AR934X GMAC Interface */ -#define AR934X_GMAC_REG_ETH_CFG 0x00 - -#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0) -#define AR934X_ETH_CFG_MII_GMAC0 BIT(1) -#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2) -#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3) -#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4) -#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5) -#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6) -#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7) -#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9) -#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10) -#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11) -#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12) -#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) -#define AR934X_ETH_CFG_RXD_DELAY BIT(14) -#define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3 -#define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14 -#define AR934X_ETH_CFG_RDV_DELAY BIT(16) -#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3 -#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16 +#define AR934X_GMAC_REG_ETH_CFG 0x00 + +#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0) +#define AR934X_ETH_CFG_MII_GMAC0 BIT(1) +#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2) +#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3) +#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4) +#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5) +#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6) +#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9) +#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10) +#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11) +#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12) +#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) +#define AR934X_ETH_CFG_RXD_DELAY BIT(14) +#define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3 +#define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14 +#define AR934X_ETH_CFG_RDV_DELAY BIT(16) +#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3 +#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16 /* * QCA953X GMAC Interface */ -#define QCA953X_GMAC_REG_ETH_CFG 0x00 +#define QCA953X_GMAC_REG_ETH_CFG 0x00 -#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6) -#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7) -#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9) -#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) +#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6) +#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9) +#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) /* * QCA955X GMAC Interface */ -#define QCA955X_GMAC_REG_ETH_CFG 0x00 +#define QCA955X_GMAC_REG_ETH_CFG 0x00 -#define QCA955X_ETH_CFG_RGMII_EN BIT(0) -#define QCA955X_ETH_CFG_GE0_SGMII BIT(6) +#define QCA955X_ETH_CFG_RGMII_EN BIT(0) +#define QCA955X_ETH_CFG_GE0_SGMII BIT(6) #endif /* __ASM_AR71XX_H */ -- 2.7.0

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[U-Boot] [GIT] Pull request: u-boot-dfu
by Lukasz Majewski 06 May '16

06 May '16

Hi Marek, Please find following pull request: The following changes since commit e96e064f51139c4af39f14499564ef76e40bbc29: usb: dwc2: Init desc_before_addr (2016-05-03 19:21:18 +0200) are available in the git repository at: u-boot-dfu/master for you to fetch changes up to c3fdefb26d713eb34e506761be72395dec1cc4ab: usb: gadget: dfu: discard dead code (2016-05-06 09:58:56 +0200) ---------------------------------------------------------------- Peng Fan (2): dfu: avoid memory leak usb: gadget: dfu: discard dead code drivers/dfu/dfu.c | 4 +++- drivers/usb/gadget/f_dfu.c | 10 +--------- 2 files changed, 4 insertions(+), 10 deletions(-) Tested at Odroid U3 -> ./test/py {dfu|ums} -- Best regards, Lukasz Majewski Samsung R&D Institute Poland (SRPOL) | Linux Platform Group

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