May 2016 - U-Boot

[U-Boot] [PATCH v2] dm: at91: Add driver model support for the spi driver
by Wenyou Yang 26 May '16

26 May '16

Add driver model support while retaining the existing legacy code. This allows the driver to support boards that have converted to driver model as well as those that have not. Signed-off-by: Wenyou Yang <wenyou.yang(a)atmel.com> --- Changes in v2: - Add clock support. drivers/spi/Kconfig | 9 ++ drivers/spi/atmel_spi.c | 311 +++++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 319 insertions(+), 1 deletion(-) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index b7fd8e5..2ac145c 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -32,6 +32,15 @@ config ATH79_SPI uses driver model and requires a device tree binding to operate. please refer to doc/device-tree-bindings/spi/spi-ath79.txt. +config ATMEL_SPI + bool "Atmel SPI driver" + depends on ARCH_AT91 + select SPI_FLASH + select SPI_FLASH_ATMEL + help + Enable the Atmel SPI driver. This driver can be used to access + the SPI Flash, such as AT25DF321. + config CADENCE_QSPI bool "Cadence QSPI driver" help diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c index ed6278b..66b8580 100644 --- a/drivers/spi/atmel_spi.c +++ b/drivers/spi/atmel_spi.c @@ -4,16 +4,24 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <clk.h> +#include <dm.h> +#include <fdtdec.h> #include <spi.h> #include <malloc.h> #include <asm/io.h> -#include <asm/arch/clk.h> #include <asm/arch/hardware.h> +#include <asm/arch/at91_spi.h> +#include <asm/gpio.h> #include "atmel_spi.h" +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_DM_SPI + static int spi_has_wdrbt(struct atmel_spi_slave *slave) { unsigned int ver; @@ -209,3 +217,304 @@ out: return 0; } + +#else + +#define MAX_CS_COUNT 4 + +struct atmel_spi_platdata { + struct at91_spi *regs; +}; + +struct atmel_spi_priv { + unsigned int freq; /* Default frequency */ + unsigned int mode; + ulong bus_clk_rate; + struct gpio_desc cs_gpios[MAX_CS_COUNT]; +}; + +static int atmel_spi_claim_bus(struct udevice *dev) +{ + struct udevice *bus = dev_get_parent(dev); + struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus); + struct atmel_spi_priv *priv = dev_get_priv(bus); + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + struct at91_spi *reg_base = bus_plat->regs; + u32 cs = slave_plat->cs; + u32 freq = priv->freq; + u32 scbr, csrx, mode; + + scbr = (priv->bus_clk_rate + freq - 1) / freq; + if (scbr > ATMEL_SPI_CSRx_SCBR_MAX) + return -EINVAL; + + if (scbr < 1) + scbr = 1; + + csrx = ATMEL_SPI_CSRx_SCBR(scbr); + csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8); + + if (!(priv->mode & SPI_CPHA)) + csrx |= ATMEL_SPI_CSRx_NCPHA; + if (priv->mode & SPI_CPOL) + csrx |= ATMEL_SPI_CSRx_CPOL; + + writel(csrx, &reg_base->csr[cs]); + + mode = ATMEL_SPI_MR_MSTR | + ATMEL_SPI_MR_MODFDIS | + ATMEL_SPI_MR_WDRBT | + ATMEL_SPI_MR_PCS(~(1 << cs)); + + writel(mode, &reg_base->mr); + + writel(ATMEL_SPI_CR_SPIEN, &reg_base->cr); + + return 0; +} + +static int atmel_spi_release_bus(struct udevice *dev) +{ + struct udevice *bus = dev_get_parent(dev); + struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus); + + writel(ATMEL_SPI_CR_SPIDIS, &bus_plat->regs->cr); + + return 0; +} + +static void atmel_spi_cs_activate(struct udevice *dev) +{ + struct udevice *bus = dev_get_parent(dev); + struct atmel_spi_priv *priv = dev_get_priv(bus); + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + u32 cs = slave_plat->cs; + + dm_gpio_set_value(&priv->cs_gpios[cs], 0); +} + +static void atmel_spi_cs_deactivate(struct udevice *dev) +{ + struct udevice *bus = dev_get_parent(dev); + struct atmel_spi_priv *priv = dev_get_priv(bus); + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + u32 cs = slave_plat->cs; + + dm_gpio_set_value(&priv->cs_gpios[cs], 1); +} + +static int atmel_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev_get_parent(dev); + struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus); + struct at91_spi *reg_base = bus_plat->regs; + + u32 len_tx, len_rx, len; + u32 status; + const u8 *txp = dout; + u8 *rxp = din; + u8 value; + + if (bitlen == 0) + goto out; + + /* + * The controller can do non-multiple-of-8 bit + * transfers, but this driver currently doesn't support it. + * + * It's also not clear how such transfers are supposed to be + * represented as a stream of bytes...this is a limitation of + * the current SPI interface. + */ + if (bitlen % 8) { + /* Errors always terminate an ongoing transfer */ + flags |= SPI_XFER_END; + goto out; + } + + len = bitlen / 8; + + /* + * The controller can do automatic CS control, but it is + * somewhat quirky, and it doesn't really buy us much anyway + * in the context of U-Boot. + */ + if (flags & SPI_XFER_BEGIN) { + atmel_spi_cs_activate(dev); + + /* + * sometimes the RDR is not empty when we get here, + * in theory that should not happen, but it DOES happen. + * Read it here to be on the safe side. + * That also clears the OVRES flag. Required if the + * following loop exits due to OVRES! + */ + readl(&reg_base->rdr); + } + + for (len_tx = 0, len_rx = 0; len_rx < len; ) { + status = readl(&reg_base->sr); + + if (status & ATMEL_SPI_SR_OVRES) + return -1; + + if ((len_tx < len) && (status & ATMEL_SPI_SR_TDRE)) { + if (txp) + value = *txp++; + else + value = 0; + writel(value, &reg_base->tdr); + len_tx++; + } + + if (status & ATMEL_SPI_SR_RDRF) { + value = readl(&reg_base->rdr); + if (rxp) + *rxp++ = value; + len_rx++; + } + } + +out: + if (flags & SPI_XFER_END) { + /* + * Wait until the transfer is completely done before + * we deactivate CS. + */ + do { + status = readl(&reg_base->sr); + } while (!(status & ATMEL_SPI_SR_TXEMPTY)); + + atmel_spi_cs_deactivate(dev); + } + + return 0; +} + +static int atmel_spi_set_speed(struct udevice *bus, uint speed) +{ + struct atmel_spi_priv *priv = dev_get_priv(bus); + + priv->freq = speed; + + return 0; +} + +static int atmel_spi_set_mode(struct udevice *bus, uint mode) +{ + struct atmel_spi_priv *priv = dev_get_priv(bus); + + priv->mode = mode; + + return 0; +} + +static const struct dm_spi_ops atmel_spi_ops = { + .claim_bus = atmel_spi_claim_bus, + .release_bus = atmel_spi_release_bus, + .xfer = atmel_spi_xfer, + .set_speed = atmel_spi_set_speed, + .set_mode = atmel_spi_set_mode, + /* + * cs_info is not needed, since we require all chip selects to be + * in the device tree explicitly + */ +}; + +static int atmel_spi_ofdata_to_platdata(struct udevice *bus) +{ + struct atmel_spi_priv *priv = dev_get_priv(bus); + int ret; + + ret = gpio_request_list_by_name(bus, "cs-gpios", priv->cs_gpios, + ARRAY_SIZE(priv->cs_gpios), 0); + if (ret < 0) { + error("Can't get %s gpios! Error: %d", bus->name, ret); + return ret; + } + + return 0; +} + +static int atmel_spi_enable_clk(struct udevice *bus) +{ + struct atmel_spi_priv *priv = dev_get_priv(bus); + struct udevice *clkdev; + ulong clk_rate; + int periph; + int ret; + + ret = clk_get_by_index(bus, 0, &clkdev); + if (ret) { + dev_err(bus, "Failed to find peripheral clock node\n"); + return -EINVAL; + } + + periph = fdtdec_get_uint(gd->fdt_blob, clkdev->of_offset, "reg", -1); + if (periph < 0) { + dev_err(bus, "Failed to find peripheral id\n"); + return -EINVAL; + } + + clkdev = dev_get_parent(clkdev); + if (!clkdev) { + dev_err(bus, "Failed to find parent node\n"); + return -ENODEV; + } + + ret = clk_enable(clkdev, periph); + if (ret) { + dev_err(bus, "Failed to enable peripheral clock\n"); + return ret; + } + + ret = clk_get_by_index(clkdev, 0, &clkdev); + if (ret) { + dev_err(bus, "Failed to find bus clock node\n"); + return ret; + } + + clk_rate = clk_get_rate(clkdev); + if (!clk_rate) { + dev_err(bus, "Failed to get bus clock rate\n"); + return -ENODEV; + } + + priv->bus_clk_rate = clk_rate; + + return 0; +} + +static int atmel_spi_probe(struct udevice *bus) +{ + struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus); + int ret; + + ret = atmel_spi_enable_clk(bus); + if (ret) + return ret; + + bus_plat->regs = (struct at91_spi *)dev_get_addr(bus); + + writel(ATMEL_SPI_CR_SWRST, &bus_plat->regs->cr); + + return 0; +} + +static const struct udevice_id atmel_spi_ids[] = { + { .compatible = "atmel,at91rm9200-spi" }, + { } +}; + +U_BOOT_DRIVER(atmel_spi) = { + .name = "atmel_spi", + .id = UCLASS_SPI, + .of_match = atmel_spi_ids, + .ops = &atmel_spi_ops, + .ofdata_to_platdata = atmel_spi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct atmel_spi_platdata), + .priv_auto_alloc_size = sizeof(struct atmel_spi_priv), + .probe = atmel_spi_probe, +}; +#endif -- 2.7.4

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[U-Boot] [PATCH v3 0/5] ARM: AT91: Add AT91 PIO4 pinctrl driver and gpio driver with DM
by Wenyou Yang 26 May '16

26 May '16

AT91 PIO4 controller is a combined gpio-controller, pin-mux and pin-config module. This patch is to add the pinctrl driver, and rework the atmel-pio4 gpio driver to support driver model and device tree. Changes in v3: - Add bind callback to support the pinctl device regarding as a child of atmel_pio4 device. - Add clock support. - Rework due to the pinctrl device is regarded as atmel_pio4 device's child. Changes in v2: - remove meaningless comment. - add else path for argument of pinconf. - add inline attribute for atmel_pio4_bank_base(). - add handle if the pinmux entries is greater maximum value. - add detailed example to show how to configure pinctrl for device. - remove interrupt and gpio property description. - add reviewed-by tag. - integrate the gpio rework patch into this patch series. - add the new patch to move the PIO4 definitions to head file and rephrase them. - add the new patch to add #ifndef before CONFIG_ATMEL_PIO4 in configs/sama5d2_xplained.h Wenyou Yang (5): gpio: atmel_pio4: Move PIO4 definitions to head file gpio: atmel_pio4: Rework to support DM & DT pinctrl: at91-pio4: Add pinctrl driver atmel: Bring in at91 pio4 device tree file and bindings configs: sama5d2_xplained: Add #ifndef before CONFIG_ATMEL_PIO4 arch/arm/dts/sama5d2-pinfunc.h | 880 +++++++++++++++++++++ arch/arm/mach-at91/include/mach/atmel_pio4.h | 35 + .../pinctrl/atmel,at91-pio4-pinctrl.txt | 66 ++ drivers/gpio/Kconfig | 2 +- drivers/gpio/atmel_pio4.c | 204 +++-- drivers/pinctrl/Kconfig | 7 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-at91-pio4.c | 187 +++++ include/configs/sama5d2_xplained.h | 2 + 9 files changed, 1314 insertions(+), 70 deletions(-) create mode 100644 arch/arm/dts/sama5d2-pinfunc.h create mode 100644 doc/device-tree-bindings/pinctrl/atmel,at91-pio4-pinctrl.txt create mode 100644 drivers/pinctrl/pinctrl-at91-pio4.c -- 2.7.4

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[U-Boot] [PATCH 0/2] clk: at91: Add new clock driver
by Wenyou Yang 26 May '16

26 May '16

For CLK uclass add post binding support to recursively bind its children as clk devices. Add the clock driver for AT91's SoCs. Wenyou Yang (2): clk: clk-uclass: Add post binding for CLK uclass clk: at91: Add new clock driver arch/arm/mach-at91/include/mach/at91_pmc.h | 11 ++- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/at91/Kconfig | 14 +++ drivers/clk/at91/Makefile | 11 +++ drivers/clk/at91/clk-generated.c | 146 +++++++++++++++++++++++++++++ drivers/clk/at91/clk-h32mx.c | 56 +++++++++++ drivers/clk/at91/clk-main.c | 55 +++++++++++ drivers/clk/at91/clk-master.c | 33 +++++++ drivers/clk/at91/clk-peripheral.c | 68 ++++++++++++++ drivers/clk/at91/clk-plla.c | 55 +++++++++++ drivers/clk/at91/clk-slow.c | 37 ++++++++ drivers/clk/at91/clk-system.c | 65 +++++++++++++ drivers/clk/at91/clk-utmi.c | 67 +++++++++++++ drivers/clk/at91/pmc.c | 53 +++++++++++ drivers/clk/at91/pmc.h | 17 ++++ drivers/clk/at91/sckc.c | 30 ++++++ drivers/clk/clk-uclass.c | 51 ++++++++++ 18 files changed, 768 insertions(+), 3 deletions(-) create mode 100644 drivers/clk/at91/Kconfig create mode 100644 drivers/clk/at91/Makefile create mode 100644 drivers/clk/at91/clk-generated.c create mode 100644 drivers/clk/at91/clk-h32mx.c create mode 100644 drivers/clk/at91/clk-main.c create mode 100644 drivers/clk/at91/clk-master.c create mode 100644 drivers/clk/at91/clk-peripheral.c create mode 100644 drivers/clk/at91/clk-plla.c create mode 100644 drivers/clk/at91/clk-slow.c create mode 100644 drivers/clk/at91/clk-system.c create mode 100644 drivers/clk/at91/clk-utmi.c create mode 100644 drivers/clk/at91/pmc.c create mode 100644 drivers/clk/at91/pmc.h create mode 100644 drivers/clk/at91/sckc.c -- 2.7.4

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[U-Boot] [PATCH v2 00/25] exynos: video: Convert exynos LCD driver to use driver model
by Simon Glass 26 May '16

26 May '16

This series converts the exynos LCD driver to work with driver model. Only the eDP display is converted - the MIPI display is left mostly alone as I do not have a device to test with. The conversion involves some refactoring to simplify the code, reduce the amount of global/static data and allow boards to be built without LCD support. The series is tested with snow, spring, pit and pi. It disables LCD on other exynos boards so that they will still build with these changes. Further work will be needed (by someone with a board) to convert the others. I am not sure when this series can be applied. The series also brings in device tree features from Linux v4.4. It would be useful to do a full sync with the kernel on these files, but this is really a job for the Samsung maintainer :-) The series is available at u-boot-dm/rkg-working. Changes in v2: - Rebase to master - Rebase to master Simon Glass (25): exynos: video: Move driver files into their own directory exynos: video: Drop dead code exynos: video: Remove use of vidinfo_t typedef exynos: video: Drop the static lcd_base_addr variable exynos: video: Drop static variables in exynos_fimd.c exynos: video: Drop static variables in exynos_fb.c exynos: video: Drop static variables in exynos_dp_lowlevel.c exynos: video: Move dsim_config_dt into a function exynos: video: Move struct exynos_platform_mipi_dsim into vidinfo exynos: video: Move mipi_lcd_device_dt into a function exynos: video: Combine LCD driver into one file exynos: pwm: Add a driver for the exynos5 PWM video: Add an enum for active low/high exynos: dts: Add pwm device tree node exynos: Allow tizen to be built without an LCD exynos: Allow CONFIG_MISC_COMMON to be build without an LCD exynos: Disable LCD display for boards we can't convert dts: Add clock and regulator binding files for max77802 exynos: Allow PWM0 pinmux to be set up exynos: Simplify calling of exynos_dp_phy_ctrl() exynos: dts: Add display-related device tree fragments exynos: video: Rename edp_device_info to exynos_dp_priv exynos: video: Rename variables for driver model exynos: video: Convert several boards to driver model for video exynos: video: Drop old unused code arch/arm/cpu/armv7/s5p-common/timer.c | 3 + arch/arm/dts/exynos5.dtsi | 3 +- arch/arm/dts/exynos5250-snow.dts | 44 ++ arch/arm/dts/exynos5250-spring.dts | 53 ++ arch/arm/dts/exynos5250.dtsi | 7 + arch/arm/dts/exynos5420-peach-pit.dts | 55 ++ arch/arm/dts/exynos54xx.dtsi | 11 +- arch/arm/dts/exynos5800-peach-pi.dts | 40 ++ arch/arm/mach-exynos/include/mach/cpu.h | 2 - arch/arm/mach-exynos/include/mach/dp_info.h | 5 +- arch/arm/mach-exynos/include/mach/mipi_dsim.h | 10 +- arch/arm/mach-exynos/include/mach/power.h | 2 +- arch/arm/mach-exynos/pinmux.c | 6 + arch/arm/mach-exynos/power.c | 2 +- board/samsung/common/board.c | 15 - board/samsung/common/exynos5-dt.c | 158 ----- board/samsung/common/misc.c | 10 + board/samsung/trats/trats.c | 2 + board/samsung/universal_c210/universal.c | 2 + configs/peach-pi_defconfig | 4 + configs/peach-pit_defconfig | 4 + configs/snow_defconfig | 4 + configs/spring_defconfig | 4 + drivers/pwm/Kconfig | 9 + drivers/pwm/Makefile | 1 + drivers/pwm/exynos_pwm.c | 120 ++++ drivers/video/Makefile | 6 +- drivers/video/exynos/Makefile | 12 + drivers/video/{ => exynos}/exynos_dp.c | 599 ++++++++++------- drivers/video/{ => exynos}/exynos_dp_lowlevel.c | 268 ++++---- drivers/video/exynos/exynos_dp_lowlevel.h | 89 +++ drivers/video/exynos/exynos_fb.c | 720 +++++++++++++++++++++ drivers/video/{ => exynos}/exynos_mipi_dsi.c | 71 +- .../video/{ => exynos}/exynos_mipi_dsi_common.c | 6 +- .../video/{ => exynos}/exynos_mipi_dsi_common.h | 0 .../video/{ => exynos}/exynos_mipi_dsi_lowlevel.c | 0 .../video/{ => exynos}/exynos_mipi_dsi_lowlevel.h | 0 drivers/video/{ => exynos}/exynos_pwm_bl.c | 0 drivers/video/exynos_dp_lowlevel.h | 68 -- drivers/video/exynos_fb.c | 330 ---------- drivers/video/exynos_fb.h | 41 -- drivers/video/exynos_fimd.c | 409 ------------ drivers/video/s6e8ax0.c | 4 +- drivers/video/simple_panel.c | 2 + include/configs/exynos5-common.h | 1 - include/configs/exynos5-dt-common.h | 5 +- include/configs/s5pc210_universal.h | 3 - include/configs/smdk5250.h | 3 + include/configs/smdk5420.h | 4 + include/configs/trats.h | 4 - include/configs/trats2.h | 4 - include/dt-bindings/clock/maxim,max77802.h | 22 + include/dt-bindings/regulator/maxim,max77802.h | 18 + include/exynos_lcd.h | 4 +- include/libtizen.h | 2 + include/video.h | 5 + lib/tizen/tizen.c | 2 + 57 files changed, 1804 insertions(+), 1474 deletions(-) create mode 100644 drivers/pwm/exynos_pwm.c create mode 100644 drivers/video/exynos/Makefile rename drivers/video/{ => exynos}/exynos_dp.c (50%) rename drivers/video/{ => exynos}/exynos_dp_lowlevel.c (77%) create mode 100644 drivers/video/exynos/exynos_dp_lowlevel.h create mode 100644 drivers/video/exynos/exynos_fb.c rename drivers/video/{ => exynos}/exynos_mipi_dsi.c (80%) rename drivers/video/{ => exynos}/exynos_mipi_dsi_common.c (99%) rename drivers/video/{ => exynos}/exynos_mipi_dsi_common.h (100%) rename drivers/video/{ => exynos}/exynos_mipi_dsi_lowlevel.c (100%) rename drivers/video/{ => exynos}/exynos_mipi_dsi_lowlevel.h (100%) rename drivers/video/{ => exynos}/exynos_pwm_bl.c (100%) delete mode 100644 drivers/video/exynos_dp_lowlevel.h delete mode 100644 drivers/video/exynos_fb.c delete mode 100644 drivers/video/exynos_fb.h delete mode 100644 drivers/video/exynos_fimd.c create mode 100644 include/dt-bindings/clock/maxim,max77802.h create mode 100644 include/dt-bindings/regulator/maxim,max77802.h -- 2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v3 0/8] Add support for Espresso7420 board
by Thomas Abraham 26 May '16

26 May '16

Changes since v2: - changes based on comments from Simon Glass and Minkyu Kang. This patch series add support for Espresso7420 board. This board is the development/evaluation platform for Exynos7420 SoC. The SoC is composed of quad Cortex-A57 block, a quad Cortex-A53 block and various other peripherals. The board includes multiple components such as the EMMC/Codec and support multiple interconnect interfaces including HDMI and USB. The first two patches add Exynos7420 pinctrl driver support which was initially posted seperatly but now included in this series. Thanks to Simon Glass and Minkyu Kang for their review. The rest of the patches add Exynos7420 clock driver support, minor changes in the S5P serial driver, Exynos7420 SoC support and Espresso7420 board support. Thomas Abraham (8): pinctrl: add the DM_UC_FLAG_SEQ_ALIAS flag for numbering the devices pinctrl: Add pinctrl driver support for Exynos7420 SoC clk: exynos: add clock driver for Exynos7420 Soc serial: s5p: get the port id number from the alias of the device node serial: s5p: use clock api to get clock rate arm: exynos: realign the code to allow support for newer 64-bit platforms arm: exynos: add support for Exynos7420 SoC board: samsung: add initial Espresso7420 board support arch/arm/Kconfig | 1 - arch/arm/dts/Makefile | 1 + arch/arm/dts/exynos7420-espresso7420.dts | 24 +++ arch/arm/dts/exynos7420.dtsi | 83 ++++++++++ arch/arm/mach-exynos/Kconfig | 61 +++++++- arch/arm/mach-exynos/Makefile | 6 +- arch/arm/mach-exynos/include/mach/cpu.h | 2 +- arch/arm/mach-exynos/include/mach/gpio.h | 2 +- arch/arm/mach-exynos/mmu-arm64.c | 35 ++++ arch/arm/mach-exynos/soc.c | 10 + board/samsung/common/board.c | 10 +- board/samsung/espresso7420/Kconfig | 16 ++ board/samsung/espresso7420/MAINTAINERS | 5 + board/samsung/espresso7420/Makefile | 10 + board/samsung/espresso7420/espresso7420.c | 16 ++ configs/arndale_defconfig | 1 + configs/espresso7420_defconfig | 9 + configs/odroid-xu3_defconfig | 1 + configs/odroid_defconfig | 1 + configs/origen_defconfig | 1 + configs/peach-pi_defconfig | 1 + configs/peach-pit_defconfig | 1 + configs/s5pc210_universal_defconfig | 1 + configs/smdk5250_defconfig | 1 + configs/smdk5420_defconfig | 1 + configs/smdkv310_defconfig | 1 + configs/snow_defconfig | 1 + configs/spring_defconfig | 1 + configs/trats2_defconfig | 1 + configs/trats_defconfig | 1 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/exynos/Kconfig | 18 ++ drivers/clk/exynos/Makefile | 9 + drivers/clk/exynos/clk-exynos7420.c | 236 +++++++++++++++++++++++++++ drivers/clk/exynos/clk-pll.c | 33 ++++ drivers/clk/exynos/clk-pll.h | 9 + drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/exynos/Kconfig | 10 + drivers/pinctrl/exynos/Makefile | 9 + drivers/pinctrl/exynos/pinctrl-exynos.c | 141 ++++++++++++++++ drivers/pinctrl/exynos/pinctrl-exynos.h | 77 +++++++++ drivers/pinctrl/exynos/pinctrl-exynos7420.c | 120 ++++++++++++++ drivers/pinctrl/pinctrl-uclass.c | 1 + drivers/serial/serial_s5p.c | 19 ++- include/configs/espresso7420.h | 34 ++++ include/configs/exynos7420-common.h | 113 +++++++++++++ include/dt-bindings/clock/exynos7420-clk.h | 207 +++++++++++++++++++++++ 49 files changed, 1334 insertions(+), 11 deletions(-) create mode 100644 arch/arm/dts/exynos7420-espresso7420.dts create mode 100644 arch/arm/dts/exynos7420.dtsi create mode 100644 arch/arm/mach-exynos/mmu-arm64.c create mode 100644 board/samsung/espresso7420/Kconfig create mode 100644 board/samsung/espresso7420/MAINTAINERS create mode 100644 board/samsung/espresso7420/Makefile create mode 100644 board/samsung/espresso7420/espresso7420.c create mode 100644 configs/espresso7420_defconfig create mode 100644 drivers/clk/exynos/Kconfig create mode 100644 drivers/clk/exynos/Makefile create mode 100644 drivers/clk/exynos/clk-exynos7420.c create mode 100644 drivers/clk/exynos/clk-pll.c create mode 100644 drivers/clk/exynos/clk-pll.h create mode 100644 drivers/pinctrl/exynos/Kconfig create mode 100644 drivers/pinctrl/exynos/Makefile create mode 100644 drivers/pinctrl/exynos/pinctrl-exynos.c create mode 100644 drivers/pinctrl/exynos/pinctrl-exynos.h create mode 100644 drivers/pinctrl/exynos/pinctrl-exynos7420.c create mode 100644 include/configs/espresso7420.h create mode 100644 include/configs/exynos7420-common.h create mode 100644 include/dt-bindings/clock/exynos7420-clk.h

5 14

[U-Boot] [PATCH 0/8] x86: quark: Add ACPI support
by Bin Meng 26 May '16

26 May '16

This series adds basic ACPI support to Intel Quark platform, enables the support on the Intel Galileo board. Testing was performed by booting Linux kernel from an SD card. All interrupts are routed to I/O APIC based on information provided in the ACPI tables, and typing 'reboot' from shell can successfully reboot to U-Boot. This series is available at u-boot-x86/quark-acpi. Bin Meng (8): x86: acpi: Create a common irqlinks ASL file x86: acpi: Make irqroute.asl common acpi: Pass -D__ACPI__ when compiling ASL files x86: quark: Prepare device.h for inclusion by ASL x86: quark: Add platform ASL files x86: quark: Generate ACPI FADT/MADT tables x86: galileo: Enable ACPI table generation x86: baytrail: acpi: Fix I/O APIC ID in the MADT table arch/x86/cpu/baytrail/acpi.c | 2 +- arch/x86/cpu/quark/Makefile | 1 + arch/x86/cpu/quark/acpi.c | 163 ++++++++++++++++++ .../asm/{arch-baytrail => }/acpi/irq_helper.h | 2 +- .../asm/{arch-baytrail => }/acpi/irqlinks.asl | 33 ++-- .../asm/{arch-baytrail => }/acpi/irqroute.asl | 0 arch/x86/include/asm/arch-baytrail/acpi/lpc.asl | 23 ++- .../asm/arch-baytrail/acpi/southcluster.asl | 2 +- arch/x86/include/asm/arch-quark/acpi/irqroute.h | 15 ++ arch/x86/include/asm/arch-quark/acpi/lpc.asl | 125 ++++++++++++++ arch/x86/include/asm/arch-quark/acpi/platform.asl | 33 ++++ .../include/asm/arch-quark/acpi/sleepstates.asl | 10 ++ .../include/asm/arch-quark/acpi/southcluster.asl | 184 +++++++++++++++++++++ arch/x86/include/asm/arch-quark/device.h | 21 ++- arch/x86/include/asm/arch-quark/iomap.h | 47 ++++++ arch/x86/include/asm/arch-quark/irq.h | 19 +++ board/intel/galileo/.gitignore | 3 + board/intel/galileo/Makefile | 1 + board/intel/galileo/acpi/mainboard.asl | 11 ++ board/intel/galileo/dsdt.asl | 14 ++ configs/galileo_defconfig | 1 + doc/README.x86 | 5 +- scripts/Makefile.lib | 2 +- 23 files changed, 685 insertions(+), 32 deletions(-) create mode 100644 arch/x86/cpu/quark/acpi.c rename arch/x86/include/asm/{arch-baytrail => }/acpi/irq_helper.h (98%) rename arch/x86/include/asm/{arch-baytrail => }/acpi/irqlinks.asl (92%) rename arch/x86/include/asm/{arch-baytrail => }/acpi/irqroute.asl (100%) create mode 100644 arch/x86/include/asm/arch-quark/acpi/irqroute.h create mode 100644 arch/x86/include/asm/arch-quark/acpi/lpc.asl create mode 100644 arch/x86/include/asm/arch-quark/acpi/platform.asl create mode 100644 arch/x86/include/asm/arch-quark/acpi/sleepstates.asl create mode 100644 arch/x86/include/asm/arch-quark/acpi/southcluster.asl create mode 100644 arch/x86/include/asm/arch-quark/iomap.h create mode 100644 arch/x86/include/asm/arch-quark/irq.h create mode 100644 board/intel/galileo/.gitignore create mode 100644 board/intel/galileo/acpi/mainboard.asl create mode 100644 board/intel/galileo/dsdt.asl -- 1.8.2.1

2 18

[U-Boot] [PATCH] mtd: nand: Remove jz4740 driver
by Marek Vasut 26 May '16

26 May '16

This driver is not used by anyone, remove it. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> Cc: Paul Burton <paul.burton(a)imgtec.com> Cc: Scott Wood <oss(a)buserror.net> --- drivers/mtd/nand/Makefile | 1 - drivers/mtd/nand/jz4740_nand.c | 258 ----------------------------------------- 2 files changed, 259 deletions(-) delete mode 100644 drivers/mtd/nand/jz4740_nand.c diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 6fb3718..aea6a93 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -50,7 +50,6 @@ obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o obj-$(CONFIG_NAND_FSMC) += fsmc_nand.o -obj-$(CONFIG_NAND_JZ4740) += jz4740_nand.o obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c deleted file mode 100644 index abcedc2..0000000 --- a/drivers/mtd/nand/jz4740_nand.c +++ /dev/null @@ -1,258 +0,0 @@ -/* - * Platform independend driver for JZ4740. - * - * Copyright (c) 2007 Ingenic Semiconductor Inc. - * Author: <jlwei(a)ingenic.cn> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> - -#include <nand.h> -#include <asm/io.h> -#include <asm/jz4740.h> - -#define JZ_NAND_DATA_ADDR ((void __iomem *)0xB8000000) -#define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000) -#define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000) - -#define JZ_NAND_ECC_CTRL_ENCODING BIT(3) -#define JZ_NAND_ECC_CTRL_RS BIT(2) -#define JZ_NAND_ECC_CTRL_RESET BIT(1) -#define JZ_NAND_ECC_CTRL_ENABLE BIT(0) - -#define EMC_SMCR1_OPT_NAND 0x094c4400 -/* Optimize the timing of nand */ - -static struct jz4740_emc * emc = (struct jz4740_emc *)JZ4740_EMC_BASE; - -static struct nand_ecclayout qi_lb60_ecclayout_2gb = { - .eccbytes = 72, - .eccpos = { - 12, 13, 14, 15, 16, 17, 18, 19, - 20, 21, 22, 23, 24, 25, 26, 27, - 28, 29, 30, 31, 32, 33, 34, 35, - 36, 37, 38, 39, 40, 41, 42, 43, - 44, 45, 46, 47, 48, 49, 50, 51, - 52, 53, 54, 55, 56, 57, 58, 59, - 60, 61, 62, 63, 64, 65, 66, 67, - 68, 69, 70, 71, 72, 73, 74, 75, - 76, 77, 78, 79, 80, 81, 82, 83 }, - .oobfree = { - {.offset = 2, - .length = 10 }, - {.offset = 84, - .length = 44 } } -}; - -static int is_reading; - -static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - uint32_t reg; - - if (ctrl & NAND_CTRL_CHANGE) { - if (ctrl & NAND_ALE) - this->IO_ADDR_W = JZ_NAND_ADDR_ADDR; - else if (ctrl & NAND_CLE) - this->IO_ADDR_W = JZ_NAND_CMD_ADDR; - else - this->IO_ADDR_W = JZ_NAND_DATA_ADDR; - - reg = readl(&emc->nfcsr); - if (ctrl & NAND_NCE) - reg |= EMC_NFCSR_NFCE1; - else - reg &= ~EMC_NFCSR_NFCE1; - writel(reg, &emc->nfcsr); - } - - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - -static int jz_nand_device_ready(struct mtd_info *mtd) -{ - return (readl(GPIO_PXPIN(2)) & 0x40000000) ? 1 : 0; -} - -void board_nand_select_device(struct nand_chip *nand, int chip) -{ - /* - * Don't use "chip" to address the NAND device, - * generate the cs from the address where it is encoded. - */ -} - -static int jz_nand_rs_calculate_ecc(struct mtd_info *mtd, const u_char *dat, - u_char *ecc_code) -{ - uint32_t status; - int i; - - if (is_reading) - return 0; - - do { - status = readl(&emc->nfints); - } while (!(status & EMC_NFINTS_ENCF)); - - /* disable ecc */ - writel(readl(&emc->nfecr) & ~EMC_NFECR_ECCE, &emc->nfecr); - - for (i = 0; i < 9; i++) - ecc_code[i] = readb(&emc->nfpar[i]); - - return 0; -} - -static void jz_nand_hwctl(struct mtd_info *mtd, int mode) -{ - uint32_t reg; - - writel(0, &emc->nfints); - reg = readl(&emc->nfecr); - reg |= JZ_NAND_ECC_CTRL_RESET; - reg |= JZ_NAND_ECC_CTRL_ENABLE; - reg |= JZ_NAND_ECC_CTRL_RS; - - switch (mode) { - case NAND_ECC_READ: - reg &= ~JZ_NAND_ECC_CTRL_ENCODING; - is_reading = 1; - break; - case NAND_ECC_WRITE: - reg |= JZ_NAND_ECC_CTRL_ENCODING; - is_reading = 0; - break; - default: - break; - } - - writel(reg, &emc->nfecr); -} - -/* Correct 1~9-bit errors in 512-bytes data */ -static void jz_rs_correct(unsigned char *dat, int idx, int mask) -{ - int i; - - idx--; - - i = idx + (idx >> 3); - if (i >= 512) - return; - - mask <<= (idx & 0x7); - - dat[i] ^= mask & 0xff; - if (i < 511) - dat[i + 1] ^= (mask >> 8) & 0xff; -} - -static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat, - u_char *read_ecc, u_char *calc_ecc) -{ - int k; - uint32_t errcnt, index, mask, status; - - /* Set PAR values */ - const uint8_t all_ff_ecc[] = { - 0xcd, 0x9d, 0x90, 0x58, 0xf4, 0x8b, 0xff, 0xb7, 0x6f }; - - if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && - read_ecc[2] == 0xff && read_ecc[3] == 0xff && - read_ecc[4] == 0xff && read_ecc[5] == 0xff && - read_ecc[6] == 0xff && read_ecc[7] == 0xff && - read_ecc[8] == 0xff) { - for (k = 0; k < 9; k++) - writeb(all_ff_ecc[k], &emc->nfpar[k]); - } else { - for (k = 0; k < 9; k++) - writeb(read_ecc[k], &emc->nfpar[k]); - } - /* Set PRDY */ - writel(readl(&emc->nfecr) | EMC_NFECR_PRDY, &emc->nfecr); - - /* Wait for completion */ - do { - status = readl(&emc->nfints); - } while (!(status & EMC_NFINTS_DECF)); - - /* disable ecc */ - writel(readl(&emc->nfecr) & ~EMC_NFECR_ECCE, &emc->nfecr); - - /* Check decoding */ - if (!(status & EMC_NFINTS_ERR)) - return 0; - - if (status & EMC_NFINTS_UNCOR) { - printf("uncorrectable ecc\n"); - return -1; - } - - errcnt = (status & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT; - - switch (errcnt) { - case 4: - index = (readl(&emc->nferr[3]) & EMC_NFERR_INDEX_MASK) >> - EMC_NFERR_INDEX_BIT; - mask = (readl(&emc->nferr[3]) & EMC_NFERR_MASK_MASK) >> - EMC_NFERR_MASK_BIT; - jz_rs_correct(dat, index, mask); - case 3: - index = (readl(&emc->nferr[2]) & EMC_NFERR_INDEX_MASK) >> - EMC_NFERR_INDEX_BIT; - mask = (readl(&emc->nferr[2]) & EMC_NFERR_MASK_MASK) >> - EMC_NFERR_MASK_BIT; - jz_rs_correct(dat, index, mask); - case 2: - index = (readl(&emc->nferr[1]) & EMC_NFERR_INDEX_MASK) >> - EMC_NFERR_INDEX_BIT; - mask = (readl(&emc->nferr[1]) & EMC_NFERR_MASK_MASK) >> - EMC_NFERR_MASK_BIT; - jz_rs_correct(dat, index, mask); - case 1: - index = (readl(&emc->nferr[0]) & EMC_NFERR_INDEX_MASK) >> - EMC_NFERR_INDEX_BIT; - mask = (readl(&emc->nferr[0]) & EMC_NFERR_MASK_MASK) >> - EMC_NFERR_MASK_BIT; - jz_rs_correct(dat, index, mask); - default: - break; - } - - return errcnt; -} - -/* - * Main initialization routine - */ -int board_nand_init(struct nand_chip *nand) -{ - uint32_t reg; - - reg = readl(&emc->nfcsr); - reg |= EMC_NFCSR_NFE1; /* EMC setup, Set NFE bit */ - writel(reg, &emc->nfcsr); - - writel(EMC_SMCR1_OPT_NAND, &emc->smcr[1]); - - nand->IO_ADDR_R = JZ_NAND_DATA_ADDR; - nand->IO_ADDR_W = JZ_NAND_DATA_ADDR; - nand->cmd_ctrl = jz_nand_cmd_ctrl; - nand->dev_ready = jz_nand_device_ready; - nand->ecc.hwctl = jz_nand_hwctl; - nand->ecc.correct = jz_nand_rs_correct_data; - nand->ecc.calculate = jz_nand_rs_calculate_ecc; - nand->ecc.mode = NAND_ECC_HW_OOB_FIRST; - nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE; - nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; - nand->ecc.strength = 4; - nand->ecc.layout = &qi_lb60_ecclayout_2gb; - nand->chip_delay = 50; - nand->bbt_options |= NAND_BBT_USE_FLASH; - - return 0; -} -- 2.7.0

2 1

[U-Boot] [PATCH V2 1/7] mips: ath79: ar933x: Avoid warning with gcc5
by Wills Wang 26 May '16

26 May '16

GCC 5.3 report a warning: 'upper' and 'lower' may be used uninitialized in this function [-Wmaybe-uninitialized]. Compiler might need explicit initializer. Signed-off-by: Wills Wang <wills.wang(a)live.com> --- arch/mips/mach-ath79/ar933x/ddr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/mach-ath79/ar933x/ddr.c b/arch/mips/mach-ath79/ar933x/ddr.c index 91452bc..7f20d34 100644 --- a/arch/mips/mach-ath79/ar933x/ddr.c +++ b/arch/mips/mach-ath79/ar933x/ddr.c @@ -268,6 +268,8 @@ void ddr_tap_tuning(void) dir = 1; tap = readl(regs + AR71XX_DDR_REG_TAP_CTRL0); val = tap; + upper = tap; + lower = tap; while (!done) { err = 0; -- 1.9.1

3 3

[U-Boot] [PATCH V2 2/7] mips: ath79: ar933x: Fix ethernet PHY mismatch
by Wills Wang 26 May '16

26 May '16

We need reset the Ethernet Switch analog part before operation, or the build-in Ethernet PHY don't work. Signed-off-by: Wills Wang <wills.wang(a)live.com> --- arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 1 + arch/mips/mach-ath79/reset.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h index a8e51cb..dabcad0 100644 --- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h +++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h @@ -660,6 +660,7 @@ #define AR933X_RESET_GE1_MDIO BIT(23) #define AR933X_RESET_GE0_MDIO BIT(22) +#define AR933X_RESET_ETH_SWITCH_ANALOG BIT(14) #define AR933X_RESET_GE1_MAC BIT(13) #define AR933X_RESET_WMAC BIT(11) #define AR933X_RESET_GE0_MAC BIT(9) diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c index 188eccb..a88bcbc 100644 --- a/arch/mips/mach-ath79/reset.c +++ b/arch/mips/mach-ath79/reset.c @@ -81,7 +81,8 @@ static int eth_init_ar933x(void) MAP_NOCACHE); const u32 mask = AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO | AR933X_RESET_GE1_MAC | AR933X_RESET_GE1_MDIO | - AR933X_RESET_ETH_SWITCH; + AR933X_RESET_ETH_SWITCH | + AR933X_RESET_ETH_SWITCH_ANALOG; /* Clear MDIO slave EN bit. */ clrbits_be32(rregs + AR933X_RESET_REG_BOOTSTRAP, BIT(17)); -- 1.9.1

3 3

[U-Boot] [PATCH] mips: Drop JZ4740 remnants
by Marek Vasut 26 May '16

26 May '16

Remove the remnants of JZ4740 support. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> Cc: Paul Burton <paul.burton(a)imgtec.com> --- arch/mips/include/asm/global_data.h | 8 - arch/mips/include/asm/jz4740.h | 1150 ----------------------------------- 2 files changed, 1158 deletions(-) delete mode 100644 arch/mips/include/asm/jz4740.h diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h index 3f230b0..37f8ed5 100644 --- a/arch/mips/include/asm/global_data.h +++ b/arch/mips/include/asm/global_data.h @@ -15,14 +15,6 @@ struct arch_global_data { #ifdef CONFIG_DYNAMIC_IO_PORT_BASE unsigned long io_port_base; #endif -#ifdef CONFIG_JZSOC - /* There are other clocks in the jz4740 */ - unsigned long per_clk; /* Peripheral bus clock */ - unsigned long dev_clk; /* Device clock */ - unsigned long sys_clk; - unsigned long tbl; - unsigned long lastinc; -#endif #ifdef CONFIG_ARCH_ATH79 unsigned long id; unsigned long soc; diff --git a/arch/mips/include/asm/jz4740.h b/arch/mips/include/asm/jz4740.h deleted file mode 100644 index 7a7cfff..0000000 --- a/arch/mips/include/asm/jz4740.h +++ /dev/null @@ -1,1150 +0,0 @@ -/* - * head file for Ingenic Semiconductor's JZ4740 CPU. - */ -#ifndef __JZ4740_H__ -#define __JZ4740_H__ - -#include <asm/addrspace.h> -#include <asm/cacheops.h> - -/* Boot ROM Specification */ -/* NOR Boot config */ -#define JZ4740_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */ -#define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */ -#define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */ -/* NAND Boot config */ -#define JZ4740_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */ -#define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */ -#define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */ -#define JZ4740_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */ - -/* 1st-level interrupts */ -#define JZ4740_IRQ_I2C 1 -#define JZ4740_IRQ_UHC 3 -#define JZ4740_IRQ_UART0 9 -#define JZ4740_IRQ_SADC 12 -#define JZ4740_IRQ_MSC 14 -#define JZ4740_IRQ_RTC 15 -#define JZ4740_IRQ_SSI 16 -#define JZ4740_IRQ_CIM 17 -#define JZ4740_IRQ_AIC 18 -#define JZ4740_IRQ_ETH 19 -#define JZ4740_IRQ_DMAC 20 -#define JZ4740_IRQ_TCU2 21 -#define JZ4740_IRQ_TCU1 22 -#define JZ4740_IRQ_TCU0 23 -#define JZ4740_IRQ_UDC 24 -#define JZ4740_IRQ_GPIO3 25 -#define JZ4740_IRQ_GPIO2 26 -#define JZ4740_IRQ_GPIO1 27 -#define JZ4740_IRQ_GPIO0 28 -#define JZ4740_IRQ_IPU 29 -#define JZ4740_IRQ_LCD 30 -/* 2nd-level interrupts */ -#define JZ4740_IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */ -#define JZ4740_IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */ - -/* Register Definitions */ -#define JZ4740_CPM_BASE 0x10000000 -#define JZ4740_INTC_BASE 0x10001000 -#define JZ4740_TCU_BASE 0x10002000 -#define JZ4740_WDT_BASE 0x10002000 -#define JZ4740_RTC_BASE 0x10003000 -#define JZ4740_GPIO_BASE 0x10010000 -#define JZ4740_AIC_BASE 0x10020000 -#define JZ4740_ICDC_BASE 0x10020000 -#define JZ4740_MSC_BASE 0x10021000 -#define JZ4740_UART0_BASE 0x10030000 -#define JZ4740_I2C_BASE 0x10042000 -#define JZ4740_SSI_BASE 0x10043000 -#define JZ4740_SADC_BASE 0x10070000 -#define JZ4740_EMC_BASE 0x13010000 -#define JZ4740_DMAC_BASE 0x13020000 -#define JZ4740_UHC_BASE 0x13030000 -#define JZ4740_UDC_BASE 0x13040000 -#define JZ4740_LCD_BASE 0x13050000 -#define JZ4740_SLCD_BASE 0x13050000 -#define JZ4740_CIM_BASE 0x13060000 -#define JZ4740_ETH_BASE 0x13100000 - -/* 8bit Mode Register of SDRAM bank 0 */ -#define JZ4740_EMC_SDMR0 (JZ4740_EMC_BASE + 0xa000) - -/* GPIO (General-Purpose I/O Ports) */ -/* = 0,1,2,3 */ -#define GPIO_PXPIN(n) \ - (JZ4740_GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */ -#define GPIO_PXDAT(n) \ - (JZ4740_GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */ -#define GPIO_PXDATS(n) \ - (JZ4740_GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */ -#define GPIO_PXDATC(n) \ - (JZ4740_GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */ -#define GPIO_PXIM(n) \ - (JZ4740_GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */ -#define GPIO_PXIMS(n) \ - (JZ4740_GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */ -#define GPIO_PXIMC(n) \ - (JZ4740_GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */ -#define GPIO_PXPE(n) \ - (JZ4740_GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */ -#define GPIO_PXPES(n) \ - (JZ4740_GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */ -#define GPIO_PXPEC(n) \ - (JZ4740_GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */ -#define GPIO_PXFUN(n) \ - (JZ4740_GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */ -#define GPIO_PXFUNS(n) \ - (JZ4740_GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */ -#define GPIO_PXFUNC(n) \ - (JZ4740_GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */ -#define GPIO_PXSEL(n) \ - (JZ4740_GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */ -#define GPIO_PXSELS(n) \ - (JZ4740_GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */ -#define GPIO_PXSELC(n) \ - (JZ4740_GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */ -#define GPIO_PXDIR(n) \ - (JZ4740_GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */ -#define GPIO_PXDIRS(n) \ - (JZ4740_GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */ -#define GPIO_PXDIRC(n) \ - (JZ4740_GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */ -#define GPIO_PXTRG(n) \ - (JZ4740_GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */ -#define GPIO_PXTRGS(n) \ - (JZ4740_GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */ -#define GPIO_PXTRGC(n) \ - (JZ4740_GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */ - -/* Static Memory Control Register */ -#define EMC_SMCR_STRV_BIT 24 -#define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT) -#define EMC_SMCR_TAW_BIT 20 -#define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT) -#define EMC_SMCR_TBP_BIT 16 -#define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT) -#define EMC_SMCR_TAH_BIT 12 -#define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT) -#define EMC_SMCR_TAS_BIT 8 -#define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT) -#define EMC_SMCR_BW_BIT 6 -#define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT) - #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT) - #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT) - #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT) -#define EMC_SMCR_BCM (1 << 3) -#define EMC_SMCR_BL_BIT 1 -#define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT) -#define EMC_SMCR_SMT (1 << 0) - -/* Static Memory Bank Addr Config Reg */ -#define EMC_SACR_BASE_BIT 8 -#define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT) -#define EMC_SACR_MASK_BIT 0 -#define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT) - -/* NAND Flash Control/Status Register */ -#define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */ -#define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */ -#define EMC_NFCSR_NFCE3 (1 << 5) -#define EMC_NFCSR_NFE3 (1 << 4) -#define EMC_NFCSR_NFCE2 (1 << 3) -#define EMC_NFCSR_NFE2 (1 << 2) -#define EMC_NFCSR_NFCE1 (1 << 1) -#define EMC_NFCSR_NFE1 (1 << 0) - -/* NAND Flash ECC Control Register */ -#define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */ -#define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */ -#define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */ -#define EMC_NFECR_HAMMING (0 << 2) /* Use HAMMING Correction Algorithm */ -#define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */ -#define EMC_NFECR_ERST (1 << 1) /* ECC Reset */ -#define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */ - -/* NAND Flash ECC Data Register */ -#define EMC_NFECC_ECC2_BIT 16 -#define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT) -#define EMC_NFECC_ECC1_BIT 8 -#define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT) -#define EMC_NFECC_ECC0_BIT 0 -#define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT) - -/* NAND Flash Interrupt Status Register */ -#define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */ -#define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT) -#define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */ -#define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */ -#define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */ -#define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */ -#define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */ - -/* NAND Flash Interrupt Enable Register */ -#define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt */ -#define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt */ -#define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt */ -#define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr */ -#define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */ - -/* NAND Flash RS Error Report Register */ -#define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */ -#define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT) -#define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */ -#define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT) - -/* DRAM Control Register */ -#define EMC_DMCR_BW_BIT 31 -#define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT) -#define EMC_DMCR_CA_BIT 26 -#define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT) -#define EMC_DMCR_RMODE (1 << 25) -#define EMC_DMCR_RFSH (1 << 24) -#define EMC_DMCR_MRSET (1 << 23) -#define EMC_DMCR_RA_BIT 20 -#define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT) - #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT) - #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT) - #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT) -#define EMC_DMCR_BA_BIT 19 -#define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT) -#define EMC_DMCR_PDM (1 << 18) -#define EMC_DMCR_EPIN (1 << 17) -#define EMC_DMCR_TRAS_BIT 13 -#define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT) -#define EMC_DMCR_RCD_BIT 11 -#define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT) -#define EMC_DMCR_TPC_BIT 8 -#define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT) -#define EMC_DMCR_TRWL_BIT 5 -#define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT) -#define EMC_DMCR_TRC_BIT 2 -#define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT) -#define EMC_DMCR_TCL_BIT 0 -#define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT) - -/* Refresh Time Control/Status Register */ -#define EMC_RTCSR_CMF (1 << 7) -#define EMC_RTCSR_CKS_BIT 0 -#define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT) - -/* SDRAM Bank Address Configuration Register */ -#define EMC_DMAR_BASE_BIT 8 -#define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT) -#define EMC_DMAR_MASK_BIT 0 -#define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT) - -/* Mode Register of SDRAM bank 0 */ -#define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */ -#define EMC_SDMR_OM_BIT 7 /* Operating Mode */ -#define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT) - #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT) -#define EMC_SDMR_CAS_BIT 4 /* CAS Latency */ -#define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT) - #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT) - #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT) - #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT) -#define EMC_SDMR_BT_BIT 3 /* Burst Type */ -#define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT) - #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */ - #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */ -#define EMC_SDMR_BL_BIT 0 /* Burst Length */ -#define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT) - #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT) - #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT) - #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT) - #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT) - -#define EMC_SDMR_CAS2_16BIT \ - (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) -#define EMC_SDMR_CAS2_32BIT \ - (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) -#define EMC_SDMR_CAS3_16BIT \ - (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) -#define EMC_SDMR_CAS3_32BIT \ - (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) - -/* RTC Control Register */ -#define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */ -#define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */ -#define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */ -#define RTC_RCR_AF (1 << 4) /* Alarm Flag */ -#define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */ -#define RTC_RCR_AE (1 << 2) /* Alarm Enable */ -#define RTC_RCR_RTCE (1 << 0) /* RTC Enable */ - -/* RTC Regulator Register */ -#define RTC_RGR_LOCK (1 << 31) /* Lock Bit */ -#define RTC_RGR_ADJC_BIT 16 -#define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT) -#define RTC_RGR_NC1HZ_BIT 0 -#define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT) - -/* Hibernate Control Register */ -#define RTC_HCR_PD (1 << 0) /* Power Down */ - -/* Hibernate Wakeup Filter Counter Register */ -#define RTC_HWFCR_BIT 5 -#define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT) - -/* Hibernate Reset Counter Register */ -#define RTC_HRCR_BIT 5 -#define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT) - -/* Hibernate Wakeup Control Register */ -#define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */ - -/* Hibernate Wakeup Status Register */ -#define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */ -#define RTC_HWRSR_PPR (1 << 4) /* PPR reset */ -#define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */ -#define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */ - -/* Clock Control Register */ -#define CPM_CPCCR_I2CS (1 << 31) -#define CPM_CPCCR_CLKOEN (1 << 30) -#define CPM_CPCCR_UCS (1 << 29) -#define CPM_CPCCR_UDIV_BIT 23 -#define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT) -#define CPM_CPCCR_CE (1 << 22) -#define CPM_CPCCR_PCS (1 << 21) -#define CPM_CPCCR_LDIV_BIT 16 -#define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT) -#define CPM_CPCCR_MDIV_BIT 12 -#define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT) -#define CPM_CPCCR_PDIV_BIT 8 -#define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT) -#define CPM_CPCCR_HDIV_BIT 4 -#define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT) -#define CPM_CPCCR_CDIV_BIT 0 -#define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT) - -/* I2S Clock Divider Register */ -#define CPM_I2SCDR_I2SDIV_BIT 0 -#define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT) - -/* LCD Pixel Clock Divider Register */ -#define CPM_LPCDR_PIXDIV_BIT 0 -#define CPM_LPCDR_PIXDIV_MASK (0x1ff << CPM_LPCDR_PIXDIV_BIT) - -/* MSC Clock Divider Register */ -#define CPM_MSCCDR_MSCDIV_BIT 0 -#define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT) - -/* PLL Control Register */ -#define CPM_CPPCR_PLLM_BIT 23 -#define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT) -#define CPM_CPPCR_PLLN_BIT 18 -#define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT) -#define CPM_CPPCR_PLLOD_BIT 16 -#define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT) -#define CPM_CPPCR_PLLS (1 << 10) -#define CPM_CPPCR_PLLBP (1 << 9) -#define CPM_CPPCR_PLLEN (1 << 8) -#define CPM_CPPCR_PLLST_BIT 0 -#define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT) - -/* Low Power Control Register */ -#define CPM_LCR_DOZE_DUTY_BIT 3 -#define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT) -#define CPM_LCR_DOZE_ON (1 << 2) -#define CPM_LCR_LPM_BIT 0 -#define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT) - #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT) - #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT) - -/* Clock Gate Register */ -#define CPM_CLKGR_UART1 (1 << 15) -#define CPM_CLKGR_UHC (1 << 14) -#define CPM_CLKGR_IPU (1 << 13) -#define CPM_CLKGR_DMAC (1 << 12) -#define CPM_CLKGR_UDC (1 << 11) -#define CPM_CLKGR_LCD (1 << 10) -#define CPM_CLKGR_CIM (1 << 9) -#define CPM_CLKGR_SADC (1 << 8) -#define CPM_CLKGR_MSC (1 << 7) -#define CPM_CLKGR_AIC1 (1 << 6) -#define CPM_CLKGR_AIC2 (1 << 5) -#define CPM_CLKGR_SSI (1 << 4) -#define CPM_CLKGR_I2C (1 << 3) -#define CPM_CLKGR_RTC (1 << 2) -#define CPM_CLKGR_TCU (1 << 1) -#define CPM_CLKGR_UART0 (1 << 0) - -/* Sleep Control Register */ -#define CPM_SCR_O1ST_BIT 8 -#define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT) -#define CPM_SCR_UDCPHY_ENABLE (1 << 6) -#define CPM_SCR_USBPHY_DISABLE (1 << 7) -#define CPM_SCR_OSC_ENABLE (1 << 4) - -/* Hibernate Control Register */ -#define CPM_HCR_PD (1 << 0) - -/* Wakeup Filter Counter Register in Hibernate Mode */ -#define CPM_HWFCR_TIME_BIT 0 -#define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT) - -/* Reset Counter Register in Hibernate Mode */ -#define CPM_HRCR_TIME_BIT 0 -#define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT) - -/* Wakeup Control Register in Hibernate Mode */ -#define CPM_HWCR_WLE_LOW (0 << 2) -#define CPM_HWCR_WLE_HIGH (1 << 2) -#define CPM_HWCR_PIN_WAKEUP (1 << 1) -#define CPM_HWCR_RTC_WAKEUP (1 << 0) - -/* Wakeup Status Register in Hibernate Mode */ -#define CPM_HWSR_WSR_PIN (1 << 1) -#define CPM_HWSR_WSR_RTC (1 << 0) - -/* Reset Status Register */ -#define CPM_RSR_HR (1 << 2) -#define CPM_RSR_WR (1 << 1) -#define CPM_RSR_PR (1 << 0) - -/* Register definitions */ -#define TCU_TCSR_PWM_SD (1 << 9) -#define TCU_TCSR_PWM_INITL_HIGH (1 << 8) -#define TCU_TCSR_PWM_EN (1 << 7) -#define TCU_TCSR_PRESCALE_BIT 3 -#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT) -#define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT) -#define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT) -#define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT) -#define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT) -#define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT) -#define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT) -#define TCU_TCSR_EXT_EN (1 << 2) -#define TCU_TCSR_RTC_EN (1 << 1) -#define TCU_TCSR_PCK_EN (1 << 0) - -#define TCU_TER_TCEN5 (1 << 5) -#define TCU_TER_TCEN4 (1 << 4) -#define TCU_TER_TCEN3 (1 << 3) -#define TCU_TER_TCEN2 (1 << 2) -#define TCU_TER_TCEN1 (1 << 1) -#define TCU_TER_TCEN0 (1 << 0) - -#define TCU_TESR_TCST5 (1 << 5) -#define TCU_TESR_TCST4 (1 << 4) -#define TCU_TESR_TCST3 (1 << 3) -#define TCU_TESR_TCST2 (1 << 2) -#define TCU_TESR_TCST1 (1 << 1) -#define TCU_TESR_TCST0 (1 << 0) - -#define TCU_TECR_TCCL5 (1 << 5) -#define TCU_TECR_TCCL4 (1 << 4) -#define TCU_TECR_TCCL3 (1 << 3) -#define TCU_TECR_TCCL2 (1 << 2) -#define TCU_TECR_TCCL1 (1 << 1) -#define TCU_TECR_TCCL0 (1 << 0) - -#define TCU_TFR_HFLAG5 (1 << 21) -#define TCU_TFR_HFLAG4 (1 << 20) -#define TCU_TFR_HFLAG3 (1 << 19) -#define TCU_TFR_HFLAG2 (1 << 18) -#define TCU_TFR_HFLAG1 (1 << 17) -#define TCU_TFR_HFLAG0 (1 << 16) -#define TCU_TFR_FFLAG5 (1 << 5) -#define TCU_TFR_FFLAG4 (1 << 4) -#define TCU_TFR_FFLAG3 (1 << 3) -#define TCU_TFR_FFLAG2 (1 << 2) -#define TCU_TFR_FFLAG1 (1 << 1) -#define TCU_TFR_FFLAG0 (1 << 0) - -#define TCU_TFSR_HFLAG5 (1 << 21) -#define TCU_TFSR_HFLAG4 (1 << 20) -#define TCU_TFSR_HFLAG3 (1 << 19) -#define TCU_TFSR_HFLAG2 (1 << 18) -#define TCU_TFSR_HFLAG1 (1 << 17) -#define TCU_TFSR_HFLAG0 (1 << 16) -#define TCU_TFSR_FFLAG5 (1 << 5) -#define TCU_TFSR_FFLAG4 (1 << 4) -#define TCU_TFSR_FFLAG3 (1 << 3) -#define TCU_TFSR_FFLAG2 (1 << 2) -#define TCU_TFSR_FFLAG1 (1 << 1) -#define TCU_TFSR_FFLAG0 (1 << 0) - -#define TCU_TFCR_HFLAG5 (1 << 21) -#define TCU_TFCR_HFLAG4 (1 << 20) -#define TCU_TFCR_HFLAG3 (1 << 19) -#define TCU_TFCR_HFLAG2 (1 << 18) -#define TCU_TFCR_HFLAG1 (1 << 17) -#define TCU_TFCR_HFLAG0 (1 << 16) -#define TCU_TFCR_FFLAG5 (1 << 5) -#define TCU_TFCR_FFLAG4 (1 << 4) -#define TCU_TFCR_FFLAG3 (1 << 3) -#define TCU_TFCR_FFLAG2 (1 << 2) -#define TCU_TFCR_FFLAG1 (1 << 1) -#define TCU_TFCR_FFLAG0 (1 << 0) - -#define TCU_TMR_HMASK5 (1 << 21) -#define TCU_TMR_HMASK4 (1 << 20) -#define TCU_TMR_HMASK3 (1 << 19) -#define TCU_TMR_HMASK2 (1 << 18) -#define TCU_TMR_HMASK1 (1 << 17) -#define TCU_TMR_HMASK0 (1 << 16) -#define TCU_TMR_FMASK5 (1 << 5) -#define TCU_TMR_FMASK4 (1 << 4) -#define TCU_TMR_FMASK3 (1 << 3) -#define TCU_TMR_FMASK2 (1 << 2) -#define TCU_TMR_FMASK1 (1 << 1) -#define TCU_TMR_FMASK0 (1 << 0) - -#define TCU_TMSR_HMST5 (1 << 21) -#define TCU_TMSR_HMST4 (1 << 20) -#define TCU_TMSR_HMST3 (1 << 19) -#define TCU_TMSR_HMST2 (1 << 18) -#define TCU_TMSR_HMST1 (1 << 17) -#define TCU_TMSR_HMST0 (1 << 16) -#define TCU_TMSR_FMST5 (1 << 5) -#define TCU_TMSR_FMST4 (1 << 4) -#define TCU_TMSR_FMST3 (1 << 3) -#define TCU_TMSR_FMST2 (1 << 2) -#define TCU_TMSR_FMST1 (1 << 1) -#define TCU_TMSR_FMST0 (1 << 0) - -#define TCU_TMCR_HMCL5 (1 << 21) -#define TCU_TMCR_HMCL4 (1 << 20) -#define TCU_TMCR_HMCL3 (1 << 19) -#define TCU_TMCR_HMCL2 (1 << 18) -#define TCU_TMCR_HMCL1 (1 << 17) -#define TCU_TMCR_HMCL0 (1 << 16) -#define TCU_TMCR_FMCL5 (1 << 5) -#define TCU_TMCR_FMCL4 (1 << 4) -#define TCU_TMCR_FMCL3 (1 << 3) -#define TCU_TMCR_FMCL2 (1 << 2) -#define TCU_TMCR_FMCL1 (1 << 1) -#define TCU_TMCR_FMCL0 (1 << 0) - -#define TCU_TSR_WDTS (1 << 16) -#define TCU_TSR_STOP5 (1 << 5) -#define TCU_TSR_STOP4 (1 << 4) -#define TCU_TSR_STOP3 (1 << 3) -#define TCU_TSR_STOP2 (1 << 2) -#define TCU_TSR_STOP1 (1 << 1) -#define TCU_TSR_STOP0 (1 << 0) - -#define TCU_TSSR_WDTSS (1 << 16) -#define TCU_TSSR_STPS5 (1 << 5) -#define TCU_TSSR_STPS4 (1 << 4) -#define TCU_TSSR_STPS3 (1 << 3) -#define TCU_TSSR_STPS2 (1 << 2) -#define TCU_TSSR_STPS1 (1 << 1) -#define TCU_TSSR_STPS0 (1 << 0) - -#define TCU_TSSR_WDTSC (1 << 16) -#define TCU_TSSR_STPC5 (1 << 5) -#define TCU_TSSR_STPC4 (1 << 4) -#define TCU_TSSR_STPC3 (1 << 3) -#define TCU_TSSR_STPC2 (1 << 2) -#define TCU_TSSR_STPC1 (1 << 1) -#define TCU_TSSR_STPC0 (1 << 0) - -/* Register definition */ -#define WDT_TCSR_PRESCALE_BIT 3 -#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT) -#define WDT_TCSR_EXT_EN (1 << 2) -#define WDT_TCSR_RTC_EN (1 << 1) -#define WDT_TCSR_PCK_EN (1 << 0) -#define WDT_TCER_TCEN (1 << 0) - -/* - * Define macros for UART_IER - * UART Interrupt Enable Register - */ -#define UART_IER_RIE (1 << 0) /* 0: receive fifo full interrupt disable */ -#define UART_IER_TIE (1 << 1) /* 0: transmit fifo empty interrupt disable */ -#define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */ -#define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */ -#define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */ - -/* - * Define macros for UART_ISR - * UART Interrupt Status Register - */ -#define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */ -#define UART_ISR_IID (7 << 1) /* Source of Interrupt */ -#define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */ -#define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */ -#define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */ -#define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */ -/* FIFO mode select, set when UART_FCR.FE is set to 1 */ -#define UART_ISR_FFMS (3 << 6) -#define UART_ISR_FFMS_NO_FIFO (0 << 6) -#define UART_ISR_FFMS_FIFO_MODE (3 << 6) - -/* - * Define macros for UART_FCR - * UART FIFO Control Register - */ -#define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */ -#define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */ -#define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */ -#define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */ -#define UART_FCR_UUE (1 << 4) /* 0: disable UART */ -#define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */ -#define UART_FCR_RTRG_1 (0 << 6) -#define UART_FCR_RTRG_4 (1 << 6) -#define UART_FCR_RTRG_8 (2 << 6) -#define UART_FCR_RTRG_15 (3 << 6) - -/* - * Define macros for UART_LCR - * UART Line Control Register - */ -#define UART_LCR_WLEN (3 << 0) /* word length */ -#define UART_LCR_WLEN_5 (0 << 0) -#define UART_LCR_WLEN_6 (1 << 0) -#define UART_LCR_WLEN_7 (2 << 0) -#define UART_LCR_WLEN_8 (3 << 0) -#define UART_LCR_STOP (1 << 2) - /* 0: 1 stop bit when word length is 5,6,7,8 - 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ -#define UART_LCR_STOP_1 (0 << 2) - /* 0: 1 stop bit when word length is 5,6,7,8 - 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ -#define UART_LCR_STOP_2 (1 << 2) - /* 0: 1 stop bit when word length is 5,6,7,8 - 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ - -#define UART_LCR_PE (1 << 3) /* 0: parity disable */ -#define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */ -#define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */ -#define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */ -/* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */ -#define UART_LCR_DLAB (1 << 7) - -/* - * Define macros for UART_LSR - * UART Line Status Register - */ -/* 0: receive FIFO is empty 1: receive data is ready */ -#define UART_LSR_DR (1 << 0) -/* 0: no overrun error */ -#define UART_LSR_ORER (1 << 1) -/* 0: no parity error */ -#define UART_LSR_PER (1 << 2) -/* 0; no framing error */ -#define UART_LSR_FER (1 << 3) -/* 0: no break detected 1: receive a break signal */ -#define UART_LSR_BRK (1 << 4) -/* 1: transmit FIFO half "empty" */ -#define UART_LSR_TDRQ (1 << 5) -/* 1: transmit FIFO and shift registers empty */ -#define UART_LSR_TEMT (1 << 6) -/* 0: no receive error 1: receive error in FIFO mode */ -#define UART_LSR_RFER (1 << 7) - -/* - * Define macros for UART_MCR - * UART Modem Control Register - */ -#define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */ -#define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */ -/* 0: UART_MSR.RI is set to 0 and RI_ input high */ -#define UART_MCR_OUT1 (1 << 2) -/* 0: UART_MSR.DCD is set to 0 and DCD_ input high */ -#define UART_MCR_OUT2 (1 << 3) -#define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */ -#define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */ - -/* - * Define macros for UART_MSR - * UART Modem Status Register - */ -#define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ since last read */ -#define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ since last read */ -#define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ since last read */ -#define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ since last read */ -#define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */ -#define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */ -#define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */ -#define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */ - -/* - * Define macros for SIRCR - * Slow IrDA Control Register - */ -#define SIRCR_TSIRE (1 << 0) /* 0: TX is in UART mode 1: IrDA mode */ -#define SIRCR_RSIRE (1 << 1) /* 0: RX is in UART mode 1: IrDA mode */ -#define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length - 1: 0 pulse width is 1.6us for 115.2Kbps */ -#define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */ -#define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */ - -/* MSC Clock and Control Register (MSC_STRPCL) */ -#define MSC_STRPCL_EXIT_MULTIPLE (1 << 7) -#define MSC_STRPCL_EXIT_TRANSFER (1 << 6) -#define MSC_STRPCL_START_READWAIT (1 << 5) -#define MSC_STRPCL_STOP_READWAIT (1 << 4) -#define MSC_STRPCL_RESET (1 << 3) -#define MSC_STRPCL_START_OP (1 << 2) -#define MSC_STRPCL_CLOCK_CONTROL_BIT 0 -#define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT) -#define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) -#define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) - -/* MSC Status Register (MSC_STAT) */ -#define MSC_STAT_IS_RESETTING (1 << 15) -#define MSC_STAT_SDIO_INT_ACTIVE (1 << 14) -#define MSC_STAT_PRG_DONE (1 << 13) -#define MSC_STAT_DATA_TRAN_DONE (1 << 12) -#define MSC_STAT_END_CMD_RES (1 << 11) -#define MSC_STAT_DATA_FIFO_AFULL (1 << 10) -#define MSC_STAT_IS_READWAIT (1 << 9) -#define MSC_STAT_CLK_EN (1 << 8) -#define MSC_STAT_DATA_FIFO_FULL (1 << 7) -#define MSC_STAT_DATA_FIFO_EMPTY (1 << 6) -#define MSC_STAT_CRC_RES_ERR (1 << 5) -#define MSC_STAT_CRC_READ_ERROR (1 << 4) -#define MSC_STAT_CRC_WRITE_ERROR_BIT 2 -#define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT) -/* No error on transmission of data */ - #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) -/* Card observed erroneous transmission of data */ - #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) -/* No CRC status is sent back */ - #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) -#define MSC_STAT_TIME_OUT_RES (1 << 1) -#define MSC_STAT_TIME_OUT_READ (1 << 0) - -/* MSC Bus Clock Control Register (MSC_CLKRT) */ -#define MSC_CLKRT_CLK_RATE_BIT 0 -#define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT) - #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) - #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) - #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) - #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) - #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) - #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) - #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) - #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) - -/* MSC Command Sequence Control Register (MSC_CMDAT) */ -#define MSC_CMDAT_IO_ABORT (1 << 11) -#define MSC_CMDAT_BUS_WIDTH_BIT 9 -#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT) -#define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) -#define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) -#define MSC_CMDAT_DMA_EN (1 << 8) -#define MSC_CMDAT_INIT (1 << 7) -#define MSC_CMDAT_BUSY (1 << 6) -#define MSC_CMDAT_STREAM_BLOCK (1 << 5) -#define MSC_CMDAT_WRITE (1 << 4) -#define MSC_CMDAT_READ (0 << 4) -#define MSC_CMDAT_DATA_EN (1 << 3) -#define MSC_CMDAT_RESPONSE_BIT 0 -#define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT) -#define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) -#define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) -#define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) -#define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) -#define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) -#define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) -#define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) - -/* MSC Interrupts Mask Register (MSC_IMASK) */ -#define MSC_IMASK_SDIO (1 << 7) -#define MSC_IMASK_TXFIFO_WR_REQ (1 << 6) -#define MSC_IMASK_RXFIFO_RD_REQ (1 << 5) -#define MSC_IMASK_END_CMD_RES (1 << 2) -#define MSC_IMASK_PRG_DONE (1 << 1) -#define MSC_IMASK_DATA_TRAN_DONE (1 << 0) - -#ifndef __ASSEMBLY__ -/* INTC (Interrupt Controller) */ -struct jz4740_intc { - uint32_t isr; /* interrupt source register */ - uint32_t imr; /* interrupt mask register */ - uint32_t imsr; /* interrupt mask set register */ - uint32_t imcr; /* interrupt mask clear register */ - uint32_t ipr; /* interrupt pending register */ -}; - -/* RTC */ -struct jz4740_rtc { - uint32_t rcr; /* rtc control register */ - uint32_t rsr; /* rtc second register */ - uint32_t rsar; /* rtc second alarm register */ - uint32_t rgr; /* rtc regulator register */ - uint32_t hcr; /* hibernate control register */ - uint32_t hwfcr; /* hibernate wakeup filter counter reg */ - uint32_t hrcr; /* hibernate reset counter reg */ - uint32_t hwcr; /* hibernate wakeup control register */ - uint32_t hwrsr; /* hibernate wakeup status reg */ - uint32_t hspr; /* scratch pattern register */ -}; - -/* CPM (Clock reset and Power control Management) */ -struct jz4740_cpm { - uint32_t cpccr; /* 0x00 clock control reg */ - uint32_t lcr; /* 0x04 low power control reg */ - uint32_t rsr; /* 0x08 reset status reg */ - uint32_t pad00; - uint32_t cppcr; /* 0x10 pll control reg */ - uint32_t pad01[3]; - uint32_t clkgr; /* 0x20 clock gate reg */ - uint32_t scr; /* 0x24 sleep control reg */ - uint32_t pad02[14]; - uint32_t i2scd; /* 0x60 I2S device clock divider reg */ - uint32_t lpcdr; /* 0x64 LCD pix clock divider reg */ - uint32_t msccdr; /* 0x68 MSC device clock divider reg */ - uint32_t uhccdr; /* 0x6C UHC 48M clock divider reg */ - uint32_t uhcts; /* 0x70 UHC PHY test point reg */ - uint32_t ssicd; /* 0x74 SSI clock divider reg */ -}; - -/* TCU (Timer Counter Unit) */ -struct jz4740_tcu { - uint32_t pad00[4]; - uint32_t ter; /* 0x10 Timer Counter Enable Register */ - uint32_t tesr; /* 0x14 Timer Counter Enable Set Register */ - uint32_t tecr; /* 0x18 Timer Counter Enable Clear Register */ - uint32_t tsr; /* 0x1C Timer Stop Register */ - uint32_t tfr; /* 0x20 Timer Flag Register */ - uint32_t tfsr; /* 0x24 Timer Flag Set Register */ - uint32_t tfcr; /* 0x28 Timer Flag Clear Register */ - uint32_t tssr; /* 0x2C Timer Stop Set Register */ - uint32_t tmr; /* 0x30 Timer Mask Register */ - uint32_t tmsr; /* 0x34 Timer Mask Set Register */ - uint32_t tmcr; /* 0x38 Timer Mask Clear Register */ - uint32_t tscr; /* 0x3C Timer Stop Clear Register */ - uint32_t tdfr0; /* 0x40 Timer Data Full Register */ - uint32_t tdhr0; /* 0x44 Timer Data Half Register */ - uint32_t tcnt0; /* 0x48 Timer Counter Register */ - uint32_t tcsr0; /* 0x4C Timer Control Register */ - uint32_t tdfr1; /* 0x50 */ - uint32_t tdhr1; /* 0x54 */ - uint32_t tcnt1; /* 0x58 */ - uint32_t tcsr1; /* 0x5C */ - uint32_t tdfr2; /* 0x60 */ - uint32_t tdhr2; /* 0x64 */ - uint32_t tcnt2; /* 0x68 */ - uint32_t tcsr2; /* 0x6C */ - uint32_t tdfr3; /* 0x70 */ - uint32_t tdhr3; /* 0x74 */ - uint32_t tcnt3; /* 0x78 */ - uint32_t tcsr3; /* 0x7C */ - uint32_t tdfr4; /* 0x80 */ - uint32_t tdhr4; /* 0x84 */ - uint32_t tcnt4; /* 0x88 */ - uint32_t tcsr4; /* 0x8C */ - uint32_t tdfr5; /* 0x90 */ - uint32_t tdhr5; /* 0x94 */ - uint32_t tcnt5; /* 0x98 */ - uint32_t tcsr5; /* 0x9C */ -}; - -/* WDT (WatchDog Timer) */ -struct jz4740_wdt { - uint16_t tdr; /* 0x00 watchdog timer data reg*/ - uint16_t pad00; - uint8_t tcer; /* 0x04 watchdog counter enable reg*/ - uint8_t pad01[3]; - uint16_t tcnt; /* 0x08 watchdog timer counter*/ - uint16_t pad02; - uint16_t tcsr; /* 0x0C watchdog timer control reg*/ - uint16_t pad03; -}; - -struct jz4740_uart { - uint8_t rbr_thr_dllr; - /* 0x00 R 8b receive buffer reg */ - /* 0x00 W 8b transmit hold reg */ - /* 0x00 RW 8b divisor latch low reg */ - uint8_t pad00[3]; - uint8_t dlhr_ier; - /* 0x04 RW 8b divisor latch high reg */ - /* 0x04 RW 8b interrupt enable reg */ - uint8_t pad01[3]; - uint8_t iir_fcr; - /* 0x08 R 8b interrupt identification reg */ - /* 0x08 W 8b FIFO control reg */ - uint8_t pad02[3]; - uint8_t lcr; /* 0x0C RW 8b Line control reg */ - uint8_t pad03[3]; - uint8_t mcr; /* 0x10 RW 8b modem control reg */ - uint8_t pad04[3]; - uint8_t lsr; /* 0x14 R 8b line status reg */ - uint8_t pad05[3]; - uint8_t msr; /* 0x18 R 8b modem status reg */ - uint8_t pad06[3]; - uint8_t spr; /* 0x1C RW 8b scratch pad reg */ - uint8_t pad07[3]; - uint8_t isr; /* 0x20 RW 8b infrared selection reg */ - uint8_t pad08[3]; - uint8_t umr; /* 0x24 RW 8b */ -}; - -/* MSC */ -struct jz4740_msc { - uint16_t strpcl;/* 0x00 */ - uint32_t stat; /* 0x04 */ - uint16_t clkrt; /* 0x08 */ - uint32_t cmdat; /* 0x0C */ - uint16_t resto; /* 0x10 */ - uint16_t rdto; /* 0x14 */ - uint16_t blklen;/* 0x18 */ - uint16_t nob; /* 0x1C */ - uint16_t snob; /* 0x20 */ - uint16_t imask; /* 0x24 */ - uint16_t ireg; /* 0x28 */ - uint8_t cmd; /* 0x2C */ - uint32_t arg; /* 0x30 */ - uint16_t res; /* 0x34 */ - uint32_t rxfifo;/* 0x38 */ - uint32_t txfifo;/* 0x3C */ -}; - -/* External Memory Controller */ -struct jz4740_emc { - uint32_t bcr; /* 0x00 BCR */ - uint32_t pad00[3]; - uint32_t smcr[5]; - /* x10 Static Memory Control Register 0 */ - /* x14 Static Memory Control Register 1 */ - /* x18 Static Memory Control Register 2 */ - /* x1c Static Memory Control Register 3 */ - /* x20 Static Memory Control Register 4 */ - uint32_t pad01[3]; - uint32_t sacr[5]; - /* x30 Static Memory Bank 0 Addr Config Reg */ - /* x34 Static Memory Bank 1 Addr Config Reg */ - /* x38 Static Memory Bank 2 Addr Config Reg */ - /* x3c Static Memory Bank 3 Addr Config Reg */ - /* x40 Static Memory Bank 4 Addr Config Reg */ - uint32_t pad02[3]; - uint32_t nfcsr; /* x050 NAND Flash Control/Status Register */ - - uint32_t pad03[11]; - uint32_t dmcr; /* x80 DRAM Control Register */ - uint16_t rtcsr; /* x84 Refresh Time Control/Status Register */ - uint16_t pad04; - uint16_t rtcnt; /* x88 Refresh Timer Counter */ - uint16_t pad05; - uint16_t rtcor; /* x8c Refresh Time Constant Register */ - uint16_t pad06; - uint32_t dmar0; /* x90 SDRAM Bank 0 Addr Config Register */ - uint32_t pad07[27]; - uint32_t nfecr; /* x100 NAND Flash ECC Control Register */ - uint32_t nfecc; /* x104 NAND Flash ECC Data Register */ - uint8_t nfpar[12]; - /* x108 NAND Flash RS Parity 0 Register */ - /* x10c NAND Flash RS Parity 1 Register */ - /* x110 NAND Flash RS Parity 2 Register */ - uint32_t nfints; /* x114 NAND Flash Interrupt Status Register */ - uint32_t nfinte; /* x118 NAND Flash Interrupt Enable Register */ - uint32_t nferr[4]; - /* x11c NAND Flash RS Error Report 0 Register */ - /* x120 NAND Flash RS Error Report 1 Register */ - /* x124 NAND Flash RS Error Report 2 Register */ - /* x128 NAND Flash RS Error Report 3 Register */ -}; - -#define __gpio_as_nand() \ -do { \ - writel(0x02018000, GPIO_PXFUNS(1)); \ - writel(0x02018000, GPIO_PXSELC(1)); \ - writel(0x02018000, GPIO_PXPES(1)); \ - writel(0x30000000, GPIO_PXFUNS(2)); \ - writel(0x30000000, GPIO_PXSELC(2)); \ - writel(0x30000000, GPIO_PXPES(2)); \ - writel(0x40000000, GPIO_PXFUNC(2)); \ - writel(0x40000000, GPIO_PXSELC(2)); \ - writel(0x40000000, GPIO_PXDIRC(2)); \ - writel(0x40000000, GPIO_PXPES(2)); \ - writel(0x00400000, GPIO_PXFUNS(1)); \ - writel(0x00400000, GPIO_PXSELC(1)); \ -} while (0) - -#define __gpio_as_sdram_16bit_4720() \ -do { \ - writel(0x5442bfaa, GPIO_PXFUNS(0)); \ - writel(0x5442bfaa, GPIO_PXSELC(0)); \ - writel(0x5442bfaa, GPIO_PXPES(0)); \ - writel(0x81f9ffff, GPIO_PXFUNS(1)); \ - writel(0x81f9ffff, GPIO_PXSELC(1)); \ - writel(0x81f9ffff, GPIO_PXPES(1)); \ - writel(0x01000000, GPIO_PXFUNS(2)); \ - writel(0x01000000, GPIO_PXSELC(2)); \ - writel(0x01000000, GPIO_PXPES(2)); \ -} while (0) - -#define __gpio_as_lcd_18bit() \ -do { \ - writel(0x003fffff, GPIO_PXFUNS(2)); \ - writel(0x003fffff, GPIO_PXSELC(2)); \ - writel(0x003fffff, GPIO_PXPES(2)); \ -} while (0) - -/* MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3 */ -#define __gpio_as_msc() \ -do { \ - writel(0x00003f00, GPIO_PXFUNS(3)); \ - writel(0x00003f00, GPIO_PXSELC(3)); \ - writel(0x00003f00, GPIO_PXPES(3)); \ -} while (0) - -#define __gpio_get_port(p) (readl(GPIO_PXPIN(p))) - -#define __gpio_disable_pull(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - writel((1 << o), GPIO_PXPES(p)); \ -} while (0) - -#define __gpio_enable_pull(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - writel(1 << (o), GPIO_PXPEC(p)); \ -} while (0) - -#define __gpio_port_as_output(p, o) \ -do { \ - writel(1 << (o), GPIO_PXFUNC(p)); \ - writel(1 << (o), GPIO_PXSELC(p)); \ - writel(1 << (o), GPIO_PXDIRS(p)); \ -} while (0) - -#define __gpio_port_as_input(p, o) \ -do { \ - writel(1 << (o), GPIO_PXFUNC(p)); \ - writel(1 << (o), GPIO_PXSELC(p)); \ - writel(1 << (o), GPIO_PXDIRC(p)); \ -} while (0) - -#define __gpio_as_output(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - __gpio_port_as_output(p, o); \ -} while (0) - -#define __gpio_as_input(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - __gpio_port_as_input(p, o); \ -} while (0) - -#define __gpio_set_pin(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - writel((1 << o), GPIO_PXDATS(p)); \ -} while (0) - -#define __gpio_clear_pin(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - writel((1 << o), GPIO_PXDATC(p)); \ -} while (0) - -#define __gpio_get_pin(n) \ -({ \ - unsigned int p, o, v; \ - p = (n) / 32; \ - o = (n) % 32; \ - if (__gpio_get_port(p) & (1 << o)) \ - v = 1; \ - else \ - v = 0; \ - v; \ -}) - -#define __gpio_as_uart0() \ -do { \ - writel(0x06000000, GPIO_PXFUNS(3)); \ - writel(0x06000000, GPIO_PXSELS(3)); \ - writel(0x06000000, GPIO_PXPES(3)); \ -} while (0) - -#define __gpio_jtag_to_uart0() \ -do { \ - writel(0x80000000, GPIO_PXSELS(2)); \ -} while (0) - -/* Clock Control Register */ -#define __cpm_get_pllm() \ - ((readl(JZ4740_CPM_BASE + 0x10) & CPM_CPPCR_PLLM_MASK) \ - >> CPM_CPPCR_PLLM_BIT) -#define __cpm_get_plln() \ - ((readl(JZ4740_CPM_BASE + 0x10) & CPM_CPPCR_PLLN_MASK) \ - >> CPM_CPPCR_PLLN_BIT) -#define __cpm_get_pllod() \ - ((readl(JZ4740_CPM_BASE + 0x10) & CPM_CPPCR_PLLOD_MASK) \ - >> CPM_CPPCR_PLLOD_BIT) -#define __cpm_get_hdiv() \ - ((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_HDIV_MASK) \ - >> CPM_CPCCR_HDIV_BIT) -#define __cpm_get_pdiv() \ - ((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_PDIV_MASK) \ - >> CPM_CPCCR_PDIV_BIT) -#define __cpm_get_cdiv() \ - ((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_CDIV_MASK) \ - >> CPM_CPCCR_CDIV_BIT) -#define __cpm_get_mdiv() \ - ((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_MDIV_MASK) \ - >> CPM_CPCCR_MDIV_BIT) - -static inline unsigned int __cpm_get_pllout(void) -{ - uint32_t m, n, no, pllout; - uint32_t od[4] = {1, 2, 2, 4}; - - struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE; - uint32_t cppcr = readl(&cpm->cppcr); - - if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) { - m = __cpm_get_pllm() + 2; - n = __cpm_get_plln() + 2; - no = od[__cpm_get_pllod()]; - pllout = (CONFIG_SYS_EXTAL / (n * no)) * m; - } else - pllout = CONFIG_SYS_EXTAL; - - return pllout; -} - -extern void pll_init(void); -extern void sdram_init(void); -extern void calc_clocks(void); -extern void rtc_init(void); - -#endif /* !__ASSEMBLY__ */ -#endif /* __JZ4740_H__ */ -- 2.7.0

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