April 2016 - U-Boot

[U-Boot] [PATCH 0/6] Remove calls from net drivers to legacy miiphy_register() entry-point
by Joe Hershberger 20 Aug '16

20 Aug '16

This is an effort to migrate closer to the phylib approach so that a new DM approach can be developed from a single starting point. The more of this legacy code can be removed, the easier it will be to move forward. Joe Hershberger (6): common: Always include errno.h in common.h scripts: Add a cocci patch for miiphy_register net: mii: Use spatch to update miiphy_register net: mii: Changes not made by spatch net: mii: Fix changes made by spatch net: mii: Clean up legacy glue that is not used arch/m68k/include/asm/fec.h | 9 +- arch/mips/mach-au1x00/au1x00_eth.c | 27 ++++-- arch/powerpc/cpu/mpc8260/ether_fcc.c | 13 ++- arch/powerpc/cpu/mpc85xx/ether_fcc.c | 13 ++- arch/powerpc/cpu/mpc8xx/fec.c | 44 ++++++--- arch/powerpc/cpu/ppc4xx/miiphy.c | 11 +-- board/gdsys/405ep/io.c | 13 ++- board/gdsys/405ep/iocon.c | 27 +++++- board/gdsys/405ex/io64.c | 25 ++++- board/gdsys/mpc8308/hrcon.c | 27 +++++- board/gdsys/mpc8308/strider.c | 27 +++++- common/miiphyutil.c | 73 --------------- drivers/net/4xx_enet.c | 20 ++-- drivers/net/armada100_fec.c | 35 ++++--- drivers/net/at91_emac.c | 30 ++++-- drivers/net/bcm-sf2-eth-gmac.c | 18 ++-- drivers/net/bcm-sf2-eth.c | 12 ++- drivers/net/bcm-sf2-eth.h | 8 +- drivers/net/bfin_mac.c | 45 ++++++--- drivers/net/davinci_emac.c | 34 +++++-- drivers/net/eepro100.c | 36 +++++--- drivers/net/enc28j60.c | 28 ++++-- drivers/net/ep93xx_eth.c | 44 ++++++--- drivers/net/fsl_mcdmafec.c | 13 ++- drivers/net/ftmac110.c | 37 +++++--- drivers/net/lpc32xx_eth.c | 54 +++++------ drivers/net/macb.c | 32 +++++-- drivers/net/mcffec.c | 13 ++- drivers/net/mcfmii.c | 19 ++-- drivers/net/mpc512x_fec.c | 34 +++++-- drivers/net/mpc5xxx_fec.c | 34 +++++-- drivers/net/mvgbe.c | 35 +++++-- drivers/net/phy/miiphybb.c | 25 ++--- drivers/net/sh_eth.c | 12 ++- drivers/net/smc911x.c | 35 +++++-- drivers/qe/uec.c | 34 ++++--- include/common.h | 1 + include/miiphy.h | 20 +--- scripts/coccinelle/net/mdio_register.cocci | 142 +++++++++++++++++++++++++++++ 39 files changed, 787 insertions(+), 372 deletions(-) create mode 100644 scripts/coccinelle/net/mdio_register.cocci -- 1.7.11.5

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[U-Boot] [PATCH v3] mmc: add mmc partconf read capability
by Angelo Dureghello 17 Aug '16

17 Aug '16

This patch allows to read back the EXT_CSD[179] partition_config register, just specifying the dev param: U-Boot> mmc partconf 0 EXT_CSD[179], PARTITION_CONFIG register: BOOT_ACK: 0 BOOT_PARTITION_ENABLE: 0 PARTITION_ACCESS: 0 Signed-off-by: Angelo Dureghello <angelo(a)sysam.it> --- Changes for v2: - fixed commit message - added white lines in cmd/mmc.c - fixed help in cmd/mmc.c Changes for v3: - fixed command output to a single printf - fixed return codes - fixed macroes with parenthesis around parameter --- cmd/mmc.c | 35 +++++++++++++++++++++++++++++------ drivers/mmc/mmc.c | 31 +++++++++++++++++++++++++++++++ include/mmc.h | 6 ++++++ 3 files changed, 66 insertions(+), 6 deletions(-) diff --git a/cmd/mmc.c b/cmd/mmc.c index 39ef072..2bc7d42 100644 --- a/cmd/mmc.c +++ b/cmd/mmc.c @@ -697,6 +697,24 @@ static int do_mmc_boot_resize(cmd_tbl_t *cmdtp, int flag, printf("EMMC RPMB partition Size %d MB\n", rpmbsize); return CMD_RET_SUCCESS; } + +static int do_mmc_partconf_read(struct mmc *mmc) +{ + int err; + u8 ack, part_num, access; + + err = mmc_get_part_conf(mmc, &ack, &part_num, &access); + if (err) + return CMD_RET_FAILURE; + + printf("EXT_CSD[179], PARTITION_CONFIG register:\n" + "BOOT_ACK: %d\n" + "BOOT_PARTITION_ENABLE: %d\n" + "PARTITION_ACCESS: %d\n", ack, part_num, access); + + return CMD_RET_SUCCESS; +} + static int do_mmc_partconf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -704,13 +722,10 @@ static int do_mmc_partconf(cmd_tbl_t *cmdtp, int flag, struct mmc *mmc; u8 ack, part_num, access; - if (argc != 5) + if (argc != 2 && argc != 5) return CMD_RET_USAGE; dev = simple_strtoul(argv[1], NULL, 10); - ack = simple_strtoul(argv[2], NULL, 10); - part_num = simple_strtoul(argv[3], NULL, 10); - access = simple_strtoul(argv[4], NULL, 10); mmc = init_mmc_device(dev, false); if (!mmc) @@ -721,9 +736,17 @@ static int do_mmc_partconf(cmd_tbl_t *cmdtp, int flag, return CMD_RET_FAILURE; } + if (argc == 2) + return do_mmc_partconf_read(mmc); + + ack = simple_strtoul(argv[2], NULL, 10); + part_num = simple_strtoul(argv[3], NULL, 10); + access = simple_strtoul(argv[4], NULL, 10); + /* acknowledge to be sent during boot operation */ return mmc_set_part_conf(mmc, ack, part_num, access); } + static int do_mmc_rst_func(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -858,8 +881,8 @@ U_BOOT_CMD( " - Set the BOOT_BUS_WIDTH field of the specified device\n" "mmc bootpart-resize <dev> <boot part size MB> <RPMB part size MB>\n" " - Change sizes of boot and RPMB partitions of specified device\n" - "mmc partconf dev boot_ack boot_partition partition_access\n" - " - Change the bits of the PARTITION_CONFIG field of the specified device\n" + "mmc partconf dev [boot_ack boot_partition partition_access]\n" + " - Show or change the bits of the PARTITION_CONFIG field of the specified device\n" "mmc rst-function dev value\n" " - Change the RST_n_FUNCTION field of the specified device\n" " WARNING: This is a write-once field and 0 / 1 / 2 are the only valid values.\n" diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index d3c22ab..e4a0130 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1954,6 +1954,37 @@ int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access) } /* + * Read EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG) + * and returning the extracted fields BOOT_ACK, BOOT_PARTITION_ENABLE and + * PARTITION_ACCESS. + */ +int mmc_get_part_conf(struct mmc *mmc, u8 *ack, u8 *part_num, u8 *access) +{ + int err; + u8 part_conf; + + ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); + + mmc->erase_grp_size = 1; + mmc->part_config = MMCPART_NOAVAILABLE; + + if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4)) + return CMD_RET_FAILURE; + + err = mmc_send_ext_csd(mmc, ext_csd); + if (err) + return err; + + part_conf = ext_csd[EXT_CSD_PART_CONF]; + + *ack = EXT_CSD_EXTRACT_BOOT_ACK(part_conf); + *part_num = EXT_CSD_EXTRACT_BOOT_PART(part_conf); + *access = EXT_CSD_EXTRACT_PARTITION_ACCESS(part_conf); + + return CMD_RET_SUCCESS; +} + +/* * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value * for enable. Note that this is a write-once field for non-zero values. * diff --git a/include/mmc.h b/include/mmc.h index cdb56e7..4291596 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -222,6 +222,10 @@ #define EXT_CSD_BOOT_PART_NUM(x) (x << 3) #define EXT_CSD_PARTITION_ACCESS(x) (x << 0) +#define EXT_CSD_EXTRACT_BOOT_ACK(x) (((x) >> 6) & 1) +#define EXT_CSD_EXTRACT_BOOT_PART(x) (((x) >> 3) & 0x7) +#define EXT_CSD_EXTRACT_PARTITION_ACCESS(x) ((x) & 0x7) + #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3) #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2) #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x) @@ -428,6 +432,8 @@ int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, unsigned long rpmbsize); /* Function to modify the PARTITION_CONFIG field of EXT_CSD */ int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access); +/* Function to read back the PARTITION_CONFIG field of EXT_CSD */ +int mmc_get_part_conf(struct mmc *mmc, u8 *ack, u8 *part_num, u8 *access); /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */ int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode); /* Function to modify the RST_n_FUNCTION field of EXT_CSD */ -- 2.7.0.rc3

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[U-Boot] [PATCH v2 0/5] Enable caches for the RPi2
by Alexander Graf 11 Aug '16

11 Aug '16

This patch set converts the Raspberry Pi 2 system to properly make use of the caches available in it. Because we're running in HYP mode, we first need to teach U-Boot how to make use of HYP registers and the LPAE page layout which is mandated by hardware when running in HYP mode. Then while we're at it, also mark the frame buffer cached to speed up screen updates. With this patch set, my Raspberry Pi 3 running in AArch32 mode is a *lot* faster than without. Please verify that the code works on a RPi2 as well and doesn't break the original Pi. In theory it should work, but I only have a 3 to test on available here. v1 -> v2: - Move to KConfig - Adapt to new config name "CONFIG_ARMV7_LPAE" Alexander Graf (5): arm64: Add 32bit arm compatible dcache definitions arm: Add support for HYP mode and LPAE page tables lcd: Fix compile warning in 64bit mode RPi: Enable caches for rpi2 bcm2835 video: Map fb as cached arch/arm/cpu/armv7/Kconfig | 8 ++++ arch/arm/include/asm/system.h | 105 +++++++++++++++++++++++++++++++++++++++--- arch/arm/lib/cache-cp15.c | 66 +++++++++++++++++++++++--- arch/arm/mach-bcm283x/Kconfig | 1 + arch/arm/mach-bcm283x/init.c | 7 +++ common/lcd.c | 4 +- drivers/video/bcm2835.c | 6 +++ include/configs/rpi_2.h | 1 - 8 files changed, 182 insertions(+), 16 deletions(-) -- 1.8.5.6

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[U-Boot] [PATCH 1/3] mmc: fsl: reset to normal boot mode when eMMC fast boot
by Peng Fan 08 Aug '16

08 Aug '16

When booting in eMMC fast boot, MMC host does not exit from boot mode after bootrom loading image. So the first command 'CMD0' sent in uboot will pull down the CMD line to low and cause errors. This patch cleans the MMC boot register in "mmc_init" to put the MMC host back to normal mode. Also clear DLL_CTRL delay line settings at USDHC initialization to eliminate the pre-settings from boot rom. Signed-off-by: Peng Fan <van.freenix(a)gmail.com> Cc: Pantelis Antoniou <panto(a)antoniou-consulting.com> Cc: York Sun <york.sun(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- drivers/mmc/fsl_esdhc.c | 38 +++++++++++++++++++++++++++++--------- include/fsl_esdhc.h | 6 ++++++ 2 files changed, 35 insertions(+), 9 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 65ecff5..15cd419 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -57,21 +57,27 @@ struct fsl_esdhc { uint fevt; /* Force event register */ uint admaes; /* ADMA error status register */ uint adsaddr; /* ADMA system address register */ - char reserved2[100]; /* reserved */ - uint vendorspec; /* Vendor Specific register */ - char reserved3[56]; /* reserved */ + char reserved2[4]; + uint dllctrl; + uint dllstat; + uint clktunectrlstatus; + char reserved3[84]; + uint vendorspec; + uint mmcboot; + uint vendorspec2; + char reserved4[48]; uint hostver; /* Host controller version register */ - char reserved4[4]; /* reserved */ - uint dmaerraddr; /* DMA error address register */ char reserved5[4]; /* reserved */ - uint dmaerrattr; /* DMA error attribute register */ + uint dmaerraddr; /* DMA error address register */ char reserved6[4]; /* reserved */ + uint dmaerrattr; /* DMA error attribute register */ + char reserved7[4]; /* reserved */ uint hostcapblt2; /* Host controller capabilities register 2 */ - char reserved7[8]; /* reserved */ + char reserved8[8]; /* reserved */ uint tcr; /* Tuning control register */ - char reserved8[28]; /* reserved */ + char reserved9[28]; /* reserved */ uint sddirctl; /* SD direction control register */ - char reserved9[712]; /* reserved */ + char reserved10[712];/* reserved */ uint scr; /* eSDHC control register */ }; @@ -618,6 +624,20 @@ static int esdhc_init(struct mmc *mmc) while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout) udelay(1000); +#if defined(CONFIG_FSL_USDHC) + /* RSTA doesn't reset MMC_BOOT register, so manually reset it */ + esdhc_write32(&regs->mmcboot, 0x0); + /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */ + esdhc_write32(&regs->mixctrl, 0x0); + esdhc_write32(&regs->clktunectrlstatus, 0x0); + + /* Put VEND_SPEC to default value */ + esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT); + + /* Disable DLL_CTRL delay line */ + esdhc_write32(&regs->dllctrl, 0x0); +#endif + #ifndef ARCH_MXC /* Enable cache snooping */ esdhc_write32(&regs->scr, 0x00000040); diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index fa760a5..78c67c8 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -35,6 +35,12 @@ #define SYSCTL_RSTC 0x02000000 #define SYSCTL_RSTD 0x04000000 +#define VENDORSPEC_CKEN 0x00004000 +#define VENDORSPEC_PEREN 0x00002000 +#define VENDORSPEC_HCKEN 0x00001000 +#define VENDORSPEC_IPGEN 0x00000800 +#define VENDORSPEC_INIT 0x20007809 + #define IRQSTAT 0x0002e030 #define IRQSTAT_DMAE (0x10000000) #define IRQSTAT_AC12E (0x01000000) -- 2.6.2

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[U-Boot] [PATCH] mmc: send CMD0 before CMD1 for some MMC cards
by Yangbo Lu 02 Aug '16

02 Aug '16

When the MMC framework was added in u-boot, the mmc_go_idle was added before mmc_send_op_cond_iter in function mmc_send_op_cond annotating that some cards seemed to need this. Actually, we still need to do this in function mmc_complete_op_cond for those cards. This has been verified on Micron MTFC4GACAECN eMMC chip. Signed-off-by: Yangbo Lu <yangbo.lu(a)nxp.com> --- drivers/mmc/mmc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index ede5d6e..82e3268 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -418,6 +418,9 @@ static int mmc_complete_op_cond(struct mmc *mmc) uint start; int err; + /* Some cards seem to need this */ + mmc_go_idle(mmc); + mmc->op_cond_pending = 0; if (!(mmc->ocr & OCR_BUSY)) { start = get_timer(0); -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 1/2] board: ls1043ardb: move sec_init to board_init
by Aneesh Bansal 27 Jul '16

27 Jul '16

sec_init() which was earlier called in misc_init_r() is now done in board_init() before PPA init as SEC block will be used during PPA image validation. Signed-off-by: Aneesh Bansal <aneesh.bansal(a)nxp.com> --- The patchset is dependent on http://patchwork.ozlabs.org/patch/571339/ board/freescale/ls1043ardb/ls1043ardb.c | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index eff09aa..aa2c962 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -117,6 +117,23 @@ int board_init(void) enable_layerscape_ns_access(); #endif +#ifdef CONFIG_SECURE_BOOT + /* In case of Secure Boot, the IBR configures the SMMU + * to allow only Secure transactions. + * SMMU must be reset in bypass mode. + * Set the ClientPD bit and Clear the USFCFG Bit + */ + u32 val; + val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_SCR0, val); + val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_NSCR0, val); +#endif + +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif + #ifdef CONFIG_FSL_LS_PPA ppa_init_pre(&ppa_entry); @@ -136,21 +153,6 @@ int config_board_mux(void) int misc_init_r(void) { config_board_mux(); -#ifdef CONFIG_SECURE_BOOT - /* In case of Secure Boot, the IBR configures the SMMU - * to allow only Secure transactions. - * SMMU must be reset in bypass mode. - * Set the ClientPD bit and Clear the USFCFG Bit - */ - u32 val; - val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); - out_le32(SMMU_SCR0, val); - val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); - out_le32(SMMU_NSCR0, val); -#endif -#ifdef CONFIG_FSL_CAAM - return sec_init(); -#endif return 0; } #endif -- 1.8.1.4

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[U-Boot] [PATCH] armv8/fsl-layerscape: add IFC fixup for LS1043A with QSPI enabled
by Gong Qianyu 21 Jul '16

21 Jul '16

QSPI and IFC are pin-multiplexed on LS1043A. So if QSPI is enabled, IFC should be disabled. But just disable IFC driver in LS1043A Linux is not enough because mdio-mux will access IFC address space -- actually it accesses FPGA which is connected to IFC CS3. So disable the whole IFC node in Linux device tree. Signed-off-by: Gong Qianyu <Qianyu.Gong(a)nxp.com> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 4e4861d..5bb3048 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -204,4 +204,11 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_FSL_LSCH3 fdt_fixup_smmu(blob); #endif + +#ifdef CONFIG_LS1043A +#ifdef CONFIG_FSL_QSPI + do_fixup_by_compat(blob, "fsl,ifc", + "status", "disabled", 8 + 1, 1); +#endif +#endif } -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] armv8/ls1043a: Add MTD partition scheme
by Wenbin Song 20 Jul '16

20 Jul '16

Add and share the the MTD partition scheme with kernel by defualt bootargs. And add the "mtdparts" env. Signed-off-by: Wenbin Song <wenbin.song(a)nxp.com> --- include/configs/ls1043a_common.h | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index fd243b1..6964873 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -236,6 +236,21 @@ #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \ + "5m(kernel),1m(dtb),9m(file_system)" +#else +#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \ + "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \ + "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \ + "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \ + "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \ + "40m(nor_bank4_fit);7e800000.flash:" \ + "1m(nand_uboot),1m(nand_uboot_env)," \ + "20m(nand_fit);spi0.0:1m(uboot)," \ + "5m(kernel),1m(dtb),9m(file_system)" +#endif + /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ @@ -248,10 +263,13 @@ "kernel_start=0x61100000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ - "console=ttyAMA0,38400n8\0" + "console=ttyAMA0,38400n8\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ - "earlycon=uart8250,mmio,0x21c0500" + "earlycon=uart8250,mmio,0x21c0500 " \ + MTDPARTS_DEFAULT + #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ "$kernel_size && bootm $kernel_load" #define CONFIG_BOOTDELAY 10 -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] Revert "T2080QDS/PCIe: Soft Reset PCIe on T2080QDS for down-training issue"
by Zhao Qiang 20 Jul '16

20 Jul '16

This reverts commit 5066e62847bddf6030262ade2aa3e7bcdc930037. The reverted patch will block t2080RDB iNiC, it was a workaround for T2080QDS down-training issue, we need to revert it and find the root cause for T2080QDS down-training issue. Signed-off-by: Zhao Qiang <qiang.zhao(a)nxp.com> --- drivers/pci/fsl_pci_init.c | 15 --------------- include/configs/T208xQDS.h | 1 - 2 files changed, 16 deletions(-) diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 52792dc..1143178 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -444,21 +444,6 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) ltssm = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT; enabled = (ltssm == 0x11) ? 1 : 0; -#ifdef CONFIG_FSL_PCIE_RESET - int i; - /* assert PCIe reset */ - setbits_be32(&pci->pdb_stat, 0x08000000); - (void) in_be32(&pci->pdb_stat); - udelay(1000); - /* clear PCIe reset */ - clrbits_be32(&pci->pdb_stat, 0x08000000); - asm("sync;isync"); - for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) { - pci_hose_read_config_word(hose, dev, PCI_LTSSM, - &ltssm); - udelay(1000); - } -#endif } else { /* pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm); */ /* enabled = ltssm >= PCI_LTSSM_L0; */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 5957fa8..c895818 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -559,7 +559,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE2 /* PCIE controler 2 */ #define CONFIG_PCIE3 /* PCIE controler 3 */ #define CONFIG_PCIE4 /* PCIE controler 4 */ -#define CONFIG_FSL_PCIE_RESET #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] RFC: rockchip: video: Lower hpd wait time
by Sjoerd Simons 05 Jul '16

05 Jul '16

Waiting 30 seconds for the hpd to go high seems a bit much, especially on headless boots. Lowering the timeout to 300ms. Sending as RFC because frankly i don't know what a sensible timeout is here, but 30 seconds is clearly not it :) Signed-off-by: Sjoerd Simons <sjoerd.simons(a)collabora.co.uk> --- drivers/video/rockchip/rk_hdmi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c index 5fcb61a..8805c77 100644 --- a/drivers/video/rockchip/rk_hdmi.c +++ b/drivers/video/rockchip/rk_hdmi.c @@ -666,7 +666,7 @@ static int hdmi_wait_for_hpd(struct rk3288_hdmi *regs) if (hdmi_get_plug_in_status(regs)) return 0; udelay(100); - } while (get_timer(start) < 30000); + } while (get_timer(start) < 300); return -1; } -- 2.7.0

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