March 2016 - U-Boot

[U-Boot] [PATCH] dm: ti_qspi: Fix conversion of address to a pointer
by Lokesh Vutla 08 Mar '16

08 Mar '16

TI QSPI driver directly typecasts fdt_addr_t to a pointer. This is not strictly correct, as it gives a build warning when fdt_addr_t is u64. So, use map_physmem for a proper typecasts. This is inspired by commit 167efe01bc5a9 ("dm: ns16550: Use an address instead of a pointer for the uart base") Signed-off-by: Lokesh Vutla <lokeshvutla(a)ti.com> --- drivers/spi/ti_qspi.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 409a5c4..e69ec0d 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -534,11 +534,15 @@ static int ti_qspi_ofdata_to_platdata(struct udevice *bus) const void *blob = gd->fdt_blob; int node = bus->of_offset; fdt_addr_t addr; + void *mmap; - priv->base = (struct ti_qspi_regs *)dev_get_addr(bus); - priv->memory_map = (void *)dev_get_addr_index(bus, 1); + priv->base = map_physmem(dev_get_addr(bus), sizeof(struct ti_qspi_regs), + MAP_NOCACHE); + priv->memory_map = map_physmem(dev_get_addr_index(bus, 1), 0, + MAP_NOCACHE); addr = dev_get_addr_index(bus, 2); - priv->ctrl_mod_mmap = (addr == FDT_ADDR_T_NONE) ? NULL : (void *)addr; + mmap = map_physmem(dev_get_addr_index(bus, 2), 0, MAP_NOCACHE); + priv->ctrl_mod_mmap = (addr == FDT_ADDR_T_NONE) ? NULL : mmap; priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1); if (priv->max_hz < 0) { -- 2.1.4

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[U-Boot] [PATCH 0/6] ARM: DRA7: Add support for RevH evm
by Lokesh Vutla 08 Mar '16

08 Mar '16

DRA74-evm RevH and later versions uses 4GB DDR and populates this info in EEPROM. This series reads EEPROM and populates emif settings for 4GB ddr. If eeprom is not available or evm revision is < H, then it fall backs to default emif settings. This series depends on the ti common eeprom driver series posted recently. https://www.mail-archive.com/u-boot%40lists.denx.de/msg204549.html Tested on DRA7 RevH: http://pastebin.ubuntu.com/15291175/ DRA7 RevG: http://pastebin.ubuntu.com/15291197/ Lokesh Vutla (6): ti: common: dra7: Add standard access for board description EEPROM ARM: DRA7: Enable EEPROM support ARM: DRA7: Move emif settings to board specific files ARM: DRA7: EMIF: Add 4GB DDR settings ARM: DRA7: configs: Prepare for detecting memory > 2GB ARM: DRA7-evm: Update memory info in banks arch/arm/cpu/armv7/omap5/Kconfig | 1 + arch/arm/cpu/armv7/omap5/sdram.c | 149 +-------------------- board/ti/common/board_detect.c | 64 +++++++++ board/ti/common/board_detect.h | 56 ++++++++ board/ti/dra7xx/Kconfig | 3 + board/ti/dra7xx/evm.c | 279 ++++++++++++++++++++++++++++++++++++++- include/configs/dra7xx_evm.h | 9 ++ 7 files changed, 410 insertions(+), 151 deletions(-) -- 2.1.4

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[U-Boot] [PATCH] ARM: AM57xx: Update EMIF registers
by Lokesh Vutla 08 Mar '16

08 Mar '16

There are certain EMIF timing failures seen on the some x15 boards. Updating the EMIF settings to get rid of these timing failures. Signed-off-by: Lokesh Vutla <lokeshvutla(a)ti.com> --- board/ti/am57xx/board.c | 136 +++++++++++++++++++++++------------------------- 1 file changed, 65 insertions(+), 71 deletions(-) diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index d712ab0..9a8ee00 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -64,22 +64,22 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { .sdram_config_init = 0x61851b32, .sdram_config = 0x61851b32, - .sdram_config2 = 0x00000000, + .sdram_config2 = 0x8000000, .ref_ctrl = 0x000040F1, .ref_ctrl_final = 0x00001035, - .sdram_tim1 = 0xceef266b, - .sdram_tim2 = 0x328f7fda, - .sdram_tim3 = 0x027f88a8, + .sdram_tim1 = 0xcccf36ab, + .sdram_tim2 = 0x308f7fda, + .sdram_tim3 = 0x409f88a8, .read_idle_ctrl = 0x00050000, - .zq_config = 0x0007190b, + .zq_config = 0x5007190b, .temp_alert_config = 0x00000000, .emif_ddr_phy_ctlr_1_init = 0x0024400b, .emif_ddr_phy_ctlr_1 = 0x0e24400b, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, - .emif_ddr_ext_phy_ctrl_2 = 0x00740074, - .emif_ddr_ext_phy_ctrl_3 = 0x00780078, - .emif_ddr_ext_phy_ctrl_4 = 0x007c007c, - .emif_ddr_ext_phy_ctrl_5 = 0x007b007b, + .emif_ddr_ext_phy_ctrl_2 = 0x00910091, + .emif_ddr_ext_phy_ctrl_3 = 0x00950095, + .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, + .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, .emif_rd_wr_lvl_rmp_win = 0x00000000, .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, @@ -89,39 +89,35 @@ static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { /* Ext phy ctrl regs 1-35 */ static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { 0x10040100, - 0x00740074, - 0x00780078, - 0x007c007c, - 0x007b007b, - 0x00800080, - 0x00360036, + 0x00910091, + 0x00950095, + 0x009B009B, + 0x009E009E, + 0x00980098, 0x00340034, - 0x00360036, 0x00350035, - 0x00350035, - - 0x01ff01ff, - 0x01ff01ff, - 0x01ff01ff, - 0x01ff01ff, - 0x01ff01ff, - - 0x00430043, - 0x003e003e, - 0x004a004a, - 0x00470047, - 0x00400040, - + 0x00340034, + 0x00310031, + 0x00340034, + 0x007F007F, + 0x007F007F, + 0x007F007F, + 0x007F007F, + 0x007F007F, + 0x00480048, + 0x004A004A, + 0x00520052, + 0x00550055, + 0x00500050, 0x00000000, 0x00600020, 0x40011080, 0x08102040, - - 0x00400040, - 0x00400040, - 0x00400040, - 0x00400040, - 0x00400040, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, 0x0, 0x0, 0x0, @@ -132,22 +128,22 @@ static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { .sdram_config_init = 0x61851b32, .sdram_config = 0x61851b32, - .sdram_config2 = 0x00000000, + .sdram_config2 = 0x8000000, .ref_ctrl = 0x000040F1, .ref_ctrl_final = 0x00001035, - .sdram_tim1 = 0xceef266b, - .sdram_tim2 = 0x328f7fda, - .sdram_tim3 = 0x027f88a8, + .sdram_tim1 = 0xcccf36ab, + .sdram_tim2 = 0x308f7fda, + .sdram_tim3 = 0x409f88a8, .read_idle_ctrl = 0x00050000, - .zq_config = 0x0007190b, + .zq_config = 0x5007190b, .temp_alert_config = 0x00000000, .emif_ddr_phy_ctlr_1_init = 0x0024400b, .emif_ddr_phy_ctlr_1 = 0x0e24400b, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, - .emif_ddr_ext_phy_ctrl_2 = 0x00820082, - .emif_ddr_ext_phy_ctrl_3 = 0x008b008b, - .emif_ddr_ext_phy_ctrl_4 = 0x00800080, - .emif_ddr_ext_phy_ctrl_5 = 0x007e007e, + .emif_ddr_ext_phy_ctrl_2 = 0x00910091, + .emif_ddr_ext_phy_ctrl_3 = 0x00950095, + .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, + .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, .emif_rd_wr_lvl_rmp_win = 0x00000000, .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, @@ -156,37 +152,35 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = { 0x10040100, - 0x00820082, - 0x008b008b, - 0x00800080, - 0x007e007e, - 0x00800080, - 0x00370037, - 0x00390039, - 0x00360036, - 0x00370037, + 0x00910091, + 0x00950095, + 0x009B009B, + 0x009E009E, + 0x00980098, + 0x00340034, 0x00350035, - 0x01ff01ff, - 0x01ff01ff, - 0x01ff01ff, - 0x01ff01ff, - 0x01ff01ff, - 0x00540054, - 0x00540054, - 0x004e004e, - 0x004c004c, - 0x00400040, - + 0x00340034, + 0x00310031, + 0x00340034, + 0x007F007F, + 0x007F007F, + 0x007F007F, + 0x007F007F, + 0x007F007F, + 0x00480048, + 0x004A004A, + 0x00520052, + 0x00550055, + 0x00500050, 0x00000000, 0x00600020, 0x40011080, 0x08102040, - - 0x00400040, - 0x00400040, - 0x00400040, - 0x00400040, - 0x00400040, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, 0x0, 0x0, 0x0, -- 2.1.4

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[U-Boot] [PATCH 1/1] am33xx: Update serial platdata to update reg_offset to 0
by Mugunthan V N 08 Mar '16

08 Mar '16

With commit: d9a3bec682f9 "dm: ns16550: Add support for reg-offset property" reg_offset is added to the struct ns16550_platdata to be dt compatible with Linux kernel driver, TI AM335x evms are broken as the serial platdata updates wrong offsets. Correcting it with initializing reg_offset to zero. Signed-off-by: Mugunthan V N <mugunthanvnm(a)ti.com> --- Verified the patch on AM335x BBB ad AM335x EVMsk. --- arch/arm/cpu/armv7/am33xx/board.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index e8d5be3..2963b3b 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -40,14 +40,14 @@ DECLARE_GLOBAL_DATA_PTR; #if !CONFIG_IS_ENABLED(OF_CONTROL) static const struct ns16550_platdata am33xx_serial[] = { - { CONFIG_SYS_NS16550_COM1, 2, CONFIG_SYS_NS16550_CLK }, + { CONFIG_SYS_NS16550_COM1, 0, 2, CONFIG_SYS_NS16550_CLK }, # ifdef CONFIG_SYS_NS16550_COM2 - { CONFIG_SYS_NS16550_COM2, 2, CONFIG_SYS_NS16550_CLK }, + { CONFIG_SYS_NS16550_COM2, 0, 2, CONFIG_SYS_NS16550_CLK }, # ifdef CONFIG_SYS_NS16550_COM3 - { CONFIG_SYS_NS16550_COM3, 2, CONFIG_SYS_NS16550_CLK }, - { CONFIG_SYS_NS16550_COM4, 2, CONFIG_SYS_NS16550_CLK }, - { CONFIG_SYS_NS16550_COM5, 2, CONFIG_SYS_NS16550_CLK }, - { CONFIG_SYS_NS16550_COM6, 2, CONFIG_SYS_NS16550_CLK }, + { CONFIG_SYS_NS16550_COM3, 0, 2, CONFIG_SYS_NS16550_CLK }, + { CONFIG_SYS_NS16550_COM4, 0, 2, CONFIG_SYS_NS16550_CLK }, + { CONFIG_SYS_NS16550_COM5, 0, 2, CONFIG_SYS_NS16550_CLK }, + { CONFIG_SYS_NS16550_COM6, 0, 2, CONFIG_SYS_NS16550_CLK }, # endif # endif }; -- 2.7.2.333.g70bd996

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[U-Boot] [PATCH][v3] armv8/ls2080ardb: Enable VID support
by Rai Harninder 07 Mar '16

07 Mar '16

This patch enable VID support for ls2080ardb platform. It uses the common VID driver Signed-off-by: Rai Harninder <harninder.rai(a)nxp.com> --- Changes in v3: - Call adjust_vdd() so that the voltage gets adjusted during u-boot boot up itself Changes in v2 - Use CONFIG_FSL_LSCH3 instead of CONFIG_LAYERSCAPE since the latter is defined for other platforms as well - Modify patch description .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 ++++ board/freescale/common/vid.c | 15 ++++++++++++++- board/freescale/ls2080ardb/ls2080ardb.c | 8 ++++++++ include/configs/ls2080ardb.h | 16 ++++++++++++++++ 4 files changed, 42 insertions(+), 1 deletions(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 91f3ce8..4fd58ee 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -146,6 +146,10 @@ struct ccsr_gur { u8 res_008[0x20-0x8]; u32 gpporcr1; /* General-purpose POR configuration */ u32 gpporcr2; /* General-purpose POR configuration 2 */ +#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25 +#define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F +#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20 +#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F u32 dcfg_fusesr; /* Fuse status register */ u32 gpporcr3; u32 gpporcr4; diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index 1bd65a8..b037643 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -10,6 +10,8 @@ #include <asm/io.h> #ifdef CONFIG_LS1043A #include <asm/arch/immap_lsch2.h> +#elif defined(CONFIG_FSL_LSCH3) +#include <asm/arch/immap_lsch3.h> #else #include <asm/immap_85xx.h> #endif @@ -285,7 +287,7 @@ static int set_voltage(int i2caddress, int vdd) int adjust_vdd(ulong vdd_override) { int re_enable = disable_interrupts(); -#ifdef CONFIG_LS1043A +#if defined(CONFIG_LS1043A) || defined(CONFIG_FSL_LSCH3) struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); #else ccsr_gur_t __iomem *gur = @@ -362,7 +364,11 @@ int adjust_vdd(ulong vdd_override) } /* get the voltage ID from fuse status register */ +#ifdef CONFIG_FSL_LSCH3 + fusesr = in_le32(&gur->dcfg_fusesr); +#else fusesr = in_be32(&gur->dcfg_fusesr); +#endif /* * VID is used according to the table below * --------------------------------------- @@ -387,6 +393,13 @@ int adjust_vdd(ulong vdd_override) vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) & FSL_CHASSIS2_DCFG_FUSESR_VID_MASK; } +#elif defined(CONFIG_FSL_LSCH3) + vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) & + FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK; + if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) { + vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) & + FSL_CHASSIS3_DCFG_FUSESR_VID_MASK; + } #else vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) & FSL_CORENET_DCFG_FUSESR_ALTVID_MASK; diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index c63b639..952b8e5 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -122,6 +122,11 @@ int select_i2c_ch_pca9547(u8 ch) return 0; } +int i2c_multiplexer_select_vid_channel(u8 channel) +{ + return select_i2c_ch_pca9547(channel); +} + int config_board_mux(int ctrl_type) { u8 reg5; @@ -184,6 +189,9 @@ int misc_init_r(void) if (hwconfig("sdhc")) config_board_mux(MUX_TYPE_SDHC); + if (adjust_vdd(0)) + printf("Warning: Adjusting core voltage failed.\n"); + return 0; } diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 116dbcd..9a95f31 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -14,6 +14,22 @@ #define CONFIG_DISPLAY_BOARDINFO +#define I2C_MUX_CH_VOL_MONITOR 0xa +#define I2C_VOL_MONITOR_ADDR 0x38 +#define CONFIG_VOL_MONITOR_IR36021_READ +#define CONFIG_VOL_MONITOR_IR36021_SET + +#define CONFIG_VID_FLS_ENV "ls2080ardb_vdd_mv" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_VID +#endif +/* step the IR regulator in 5mV increments */ +#define IR_VDD_STEP_DOWN 5 +#define IR_VDD_STEP_UP 5 +/* The lowest and highest voltage allowed for LS2080ARDB */ +#define VDD_MV_MIN 819 +#define VDD_MV_MAX 1212 + #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); #endif -- 1.7.6.GIT

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[U-Boot] GSoC projects for Minnowboard MAX
by Simon Glass 07 Mar '16

07 Mar '16

Hi, Minnowboard is looking for GSoC projects this year. http://wiki.minnowboard.org/GSoC2016 There are a few things listed in README.x86 to be done. Any ideas? Regards, Simon

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[U-Boot] How do I tell buildman to use a /specific/ toolchain?
by Stephen Warren 07 Mar '16

07 Mar '16

Simon, I have 3 different ARM toolchains installed into /usr/bin via distro packages. How do I tell buildman which of those to use? I had originally thought that ~/.buildman's [toolchain] section contained CROSS_COMPILE-like values, so I tried: > [toolchain] > root: / > arm0-not-installed: arm-none-gnueabi- > arm1: arm-none-eabi- > arm2: arm-linux-gnueabihf- > arm3: arm-linux-gnueabi- > arch64: aarch64-linux-gnu- > > [toolchain-alias] > arm: arm1 > aarch64: aarch64 (I intended to change the "arm: arm1" line to point at arm1/2/3 based on which I wanted to use at a particular time). However, running "buildman --list-toolchains" and re-reading the docs shows me that the [toolchain] values are absolute directories that buildman searches for files named *-gcc: > - scanning path 'arm-none-gnueabi-' > - looking in 'arm-none-gnueabi-/.' > - looking in 'arm-none-gnueabi-/bin' > - looking in 'arm-none-gnueabi-/usr/bin' If buildman finds multiple toolchains, there doesn't seem to be a way to tell it which one to use. Am I missing something? I suppose a solution wouuld be to move the compiler binaries into different separate directories, and only list one of those directories in ~/.buildman. However, I can't do that for distro-packaged toolchains (well, I suppose I could manually mv everything all over the place, but that's really fragile since it'd break any time the package got upgraded or removed and re-installed). I think it makes sense to add new syntax into ~/.buildman to specify "don't do automagical searching, just use this CROSS_COMPILE value that I say". Does that sound reasonable? Automagic stuff makes for great defaults, but if it can't be overridden, it sucks when you actually know what you want.

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[U-Boot] [PATCH 00/12] Add SPI and QSPI boot for LS2080A
by Yuan Yao 07 Mar '16

07 Mar '16

From: Yuan Yao <yao.yuan(a)nxp.com> Yuan Yao (12): armv8: ls2080aqds: Select QSPI CLK div via SCFG configs: ls2080a_common: Remove duplicate NOR configs configs: ls2080aqds: Disable IFC NOR & QIXIS when QSPI configs: ls2080aqds: Enable QSPI flash support dm: dts: ls2080aqds: Add QSPI dts node armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND boot configs: ls2080a: Increase load image len in NAND boot ls2080aqds_nand_defconfig: Enable QSPI & its dependence armv8: ls2080aqds: Enable QSPI boot support ls2080aqds: Enable support for boot from QSPI freescale: cmd: qixis: tidy up the duplicated code LS2080QDS: QSPI boot: fix issues. arch/arm/dts/fsl-ls2080a-qds.dts | 14 +++++++ arch/arm/dts/fsl-ls2080a.dtsi | 10 +++++ arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 ++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 3 ++ board/freescale/common/qixis.c | 12 ++---- board/freescale/ls2080aqds/ls2080aqds.c | 16 ++++++++ common/board_f.c | 6 +-- configs/ls2080aqds_nand_defconfig | 9 +++++ configs/ls2080aqds_qspi_defconfig | 10 +++++ include/configs/ls2080a_common.h | 11 ++---- include/configs/ls2080a_simu.h | 7 ++++ include/configs/ls2080aqds.h | 43 +++++++++++++++++++++- 12 files changed, 124 insertions(+), 21 deletions(-) create mode 100644 configs/ls2080aqds_qspi_defconfig -- 2.1.0.27.g96db324

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[U-Boot] BeagleBone Black: u-boot 2016.03-rc2 worng fdt detection
by Matwey V. Kornilov 07 Mar '16

07 Mar '16

Hello, I am running u-boot 2016.03-rc2 on BeagleBone Black and it is incorrectly detected as BeagleBone Green. fdtfile=am335x-bonegreen.dtb => print board_name board_name=A335BNLT => print board_rev board_rev=t ue Similar issue was here on 2016.01.

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[U-Boot] [PATCH] MIPS: fix mips_cache fallback without __builtin_mips_cache
by Matthias Schiffer 07 Mar '16

07 Mar '16

The "R" constraint supplies the address of an variable in a register. Use "r" instead and adjust asm to supply the content of addr in a register instead. Fixes: 2b8bcc5a ("MIPS: avoid .set ISA for cache operations") Signed-off-by: Matthias Schiffer <mschiffer(a)universe-factory.net> Cc: Paul Burton <paul.burton(a)imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> --- Hi, I've noticed this when reading the code to understand how the cache instruction is used. I'm not sure if this bug had any practical consequences, or if nowadays all relevant compilers have __builtin_mips_cache anyways. Please keep me in Cc in follow-up mails, I'm not subscribed to the u-boot ML. Matthias arch/mips/include/asm/cacheops.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h index a3b07c6..002b839 100644 --- a/arch/mips/include/asm/cacheops.h +++ b/arch/mips/include/asm/cacheops.h @@ -16,7 +16,7 @@ static inline void mips_cache(int op, const volatile void *addr) #ifdef __GCC_HAVE_BUILTIN_MIPS_CACHE __builtin_mips_cache(op, addr); #else - __asm__ __volatile__("cache %0, %1" : : "i"(op), "R"(addr)); + __asm__ __volatile__("cache %0, 0(%1)" : : "i"(op), "r"(addr)); #endif } -- 2.7.2

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