March 2016 - U-Boot

[U-Boot] [PATCH 0/7 v4] support mapping PCI device ids to stream ids for MSIs
by Stuart Yoder 08 Mar '16

08 Mar '16

From: Stuart Yoder <stuart.yoder(a)nxp.com> A binding for PCI nodes has been finalized specifying how PCI device IDs can be mapped to MSI specifiers. See Documentation/devicetree/bindings/pci/pci-msi.txt in the kernel. For ls2080a and similar Layerscape SoCs, the MSI specifier is the stream id. A programmable table (LUT) in the PCI controller defines the hardware mapping of PCI requester IDs to stream IDs. This patch series implements support for this mapping. Patch 1 removes the obsolete available-stream-id support. Patch 2 updates stream ID partitioning info to be current Patch 3 updates pci.h so pci_get_hose_head() is available Patch 4 implements support for programming the LUT Patch 5 implements a simple stream ID allocator for PCI Patch 6 implements a function to set msi-map properties Patch 7 implements a function to iterate over all PCI buses and set up a LUT entry and msi-map for all discovered devices This patch series enables MSIs on ls2080a on v4.5-rc5 and later kernels. The obsolete support removed was unused in any upstream kernels. -v2 changes -in patch 7 removed skip of the host bridge when scanning the bus -v3 changes -patch 4: moved LUT #defines to immap_lsch3.h, made index allocator return an int -patch 5: return 0xffffffff on error -patch 7: fixed return value checks -v4 changes -put all device ID to stream ID mapping under LS2 #ifdefs Stuart Yoder (7): armv8: ls2080a: remove obsolete stream ID partitioning support armv8: ls2080a: update stream ID partitioning info pci: make pci_get_hose_head() available to external users pci/layerscape: add support for LUT pci/layerscape: add stream ID allocator pci/layerscape: fdt: function to set msi-map entries pci/layerscape: set LUT and msi-map for discovered PCI devices arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 113 ---------- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 + .../asm/arch-fsl-layerscape/ls2080a_stream_id.h | 55 +++-- drivers/pci/pcie_layerscape.c | 217 +++++++++++++------- include/pci.h | 1 + 5 files changed, 186 insertions(+), 204 deletions(-) -- 1.7.9.5

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[U-Boot] [PATCH 1/2] driver/ddr/fsl: add command/address parity for DDR4 UDIMM
by Shengzhou Liu 08 Mar '16

08 Mar '16

Add support of command/address parity for DDR4 UDIMM or discrete memory. It requires to configurate corresponding MR5[2:0] and TIMING_CFG_7[PAR_LAT]. Parity can be turned on/off by hwconfig, e.g. hwconfig=fsl_ddr:parity=on. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)nxp.com> --- doc/README.fsl-ddr | 8 +++++++ drivers/ddr/fsl/ctrl_regs.c | 52 +++++++++++++++++++++++++++++++++++++++------ drivers/ddr/fsl/options.c | 12 +++++++++-- include/fsl_ddr_sdram.h | 11 +++++++++- 4 files changed, 73 insertions(+), 10 deletions(-) diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index cd71ec8..80f91d3 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -143,6 +143,14 @@ platform hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,ecc=on + +Memory address parity on/off +============================ +address parity can be turned on/off by hwconfig, it's disabled by default. +Syntax is: +hwconfig=fsl_ddr:parity=on + + Table for dynamic ODT for DDR3 ============================== For single-slot system with quad-rank DIMM and dual-slot system, dynamic ODT may diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 0bfcd34..1f5b9fc 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -895,12 +895,10 @@ static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num, slow = get_ddr_freq(ctrl_num) < 1249000000; #endif - if (popts->registered_dimm_en) { + ap_en = popts->ap_en; + + if (popts->registered_dimm_en) rcw_en = 1; - ap_en = popts->ap_en; - } else { - ap_en = 0; - } x4_en = popts->x4_en ? 1 : 0; @@ -1135,6 +1133,7 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr, unsigned short esdmode5; /* Extended SDRAM mode 5 */ int rtt_park = 0; bool four_cs = false; + const unsigned int mclk_ps = get_memory_clk_period_ps(0); #if CONFIG_CHIP_SELECTS_PER_CTRL == 4 if ((ddr->cs[0].config & SDRAM_CS_CONFIG_EN) && @@ -1150,6 +1149,19 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr, esdmode5 = 0x00000400; /* Data mask enabled */ } + /* set command/address parity latency */ + if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { + if (mclk_ps >= 935) { + /* for DDR4-1600/1866/2133 */ + esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK; + } else if (mclk_ps >= 833) { + /* for DDR4-2400 */ + esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK; + } else { + printf("parity: mclk_ps = %d not supported\n", mclk_ps); + } + } + ddr->ddr_sdram_mode_9 = (0 | ((esdmode4 & 0xffff) << 16) | ((esdmode5 & 0xffff) << 0) @@ -1170,6 +1182,19 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr, } else { esdmode5 = 0x00000400; } + + if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { + if (mclk_ps >= 935) { + /* for DDR4-1600/1866/2133 */ + esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK; + } else if (mclk_ps >= 833) { + /* for DDR4-2400 */ + esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK; + } else { + printf("parity: the speed reserved\n"); + } + } + switch (i) { case 1: ddr->ddr_sdram_mode_11 = (0 @@ -1925,12 +1950,25 @@ static void set_timing_cfg_7(const unsigned int ctrl_num, const common_timing_params_t *common_dimm) { unsigned int txpr, tcksre, tcksrx; - unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd; + unsigned int cke_rst, cksre, cksrx, par_lat = 0, cs_to_cmd; + const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000)); tcksre = max(5U, picos_to_mclk(ctrl_num, 10000)); tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000)); - par_lat = 0; + + if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { + if (mclk_ps >= 935) { + /* parity latency 4 clocks in case of 1600/1866/2133 */ + par_lat = 4; + } else if (mclk_ps >= 833) { + /* parity latency 5 clocks for DDR4-2400 */ + par_lat = 5; + } else { + printf("parity: mclk_ps = %d not supported\n", mclk_ps); + } + } + cs_to_cmd = 0; if (txpr <= 200) diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c index 791d644..9ea80af 100644 --- a/drivers/ddr/fsl/options.c +++ b/drivers/ddr/fsl/options.c @@ -1002,8 +1002,16 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm, popts->twot_en = 0; popts->threet_en = 0; - /* for RDIMM, address parity enable */ - popts->ap_en = 1; + /* for RDIMM and DDR4 UDIMM/discrete memory, address parity enable */ + popts->ap_en = 0; /* 0 = disable, 1 = enable */ + + if (hwconfig_sub_f("fsl_ddr", "parity", buf)) { + if (hwconfig_subarg_cmp_f("fsl_ddr", "parity", "on", buf)) { + if (popts->registered_dimm_en || + (CONFIG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4)) + popts->ap_en = 1; + } + } /* * BSTTOPRE precharge interval diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 3699c04..cf316a4 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -123,6 +123,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define SDRAM_CFG2_FRC_SR 0x80000000 #define SDRAM_CFG2_D_INIT 0x00000010 +#define SDRAM_CFG2_AP_EN 0x00000020 #define SDRAM_CFG2_ODT_CFG_MASK 0x00600000 #define SDRAM_CFG2_ODT_NEVER 0 #define SDRAM_CFG2_ODT_ONLY_WRITE 1 @@ -177,6 +178,14 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 #define DDR_CDR2_VREF_RANGE_2 0x00000040 +/* DDR ERR_DISABLE */ +#define DDR_ERR_DISABLE_APED (1 << 8) /* Address parity error disable */ + +/* Mode Registers */ +#define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */ +#define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */ + + #if (defined(CONFIG_SYS_FSL_DDR_VER) && \ (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)) #ifdef CONFIG_SYS_FSL_DDR3L @@ -343,7 +352,7 @@ typedef struct memctl_options_s { /* mirrior DIMMs for DDR3 */ unsigned int mirrored_dimm; unsigned int quad_rank_present; - unsigned int ap_en; /* address parity enable for RDIMM */ + unsigned int ap_en; /* address parity enable for RDIMM/DDR4-UDIMM */ unsigned int x4_en; /* enable x4 devices */ /* Global Timing Parameters */ -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] ARM: uniphier: allow debug_ll_init() to do nothing for unknown SoCs
by Masahiro Yamada 08 Mar '16

08 Mar '16

This function should just return for unknown SoCs rather than writing unexpected values to registers. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- arch/arm/mach-uniphier/arm32/debug_ll.S | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-uniphier/arm32/debug_ll.S b/arch/arm/mach-uniphier/arm32/debug_ll.S index a70954c..8e4943c 100644 --- a/arch/arm/mach-uniphier/arm32/debug_ll.S +++ b/arch/arm/mach-uniphier/arm32/debug_ll.S @@ -175,6 +175,7 @@ proxstream2_end: b init_uart ph1_ld6b_end: #endif + mov pc, lr init_uart: addruart r0, r1, r2 -- 1.9.1

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[U-Boot] [PATCH] pinctrl: uniphier: guard uniphier directory with CONFIG_PINCTRL_UNIPHIER
by Masahiro Yamada 08 Mar '16

08 Mar '16

CONFIG_PINCTRL_UNIPHIER is more suitable than CONFIG_ARCH_UNIPHIER to guard the drivers/pinctrl/uniphier directory. The current CONFIG_PINCTRL_UNIPHIER_CORE is a bit long, so rename it into CONFIG_PINCTRL_UNIPHIER. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- drivers/pinctrl/Makefile | 2 +- drivers/pinctrl/uniphier/Kconfig | 14 +++++++------- drivers/pinctrl/uniphier/Makefile | 2 +- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index d7b6180..37dc904 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -9,5 +9,5 @@ obj-y += nxp/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o -obj-$(CONFIG_ARCH_UNIPHIER) += uniphier/ +obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ obj-$(CONFIG_PIC32_PINCTRL) += pinctrl_pic32.o diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig index 2ff616e..33d6763 100644 --- a/drivers/pinctrl/uniphier/Kconfig +++ b/drivers/pinctrl/uniphier/Kconfig @@ -1,42 +1,42 @@ if ARCH_UNIPHIER -config PINCTRL_UNIPHIER_CORE +config PINCTRL_UNIPHIER bool config PINCTRL_UNIPHIER_PH1_LD4 bool "UniPhier PH1-LD4 SoC pinctrl driver" depends on ARCH_UNIPHIER_PH1_LD4 default y - select PINCTRL_UNIPHIER_CORE + select PINCTRL_UNIPHIER config PINCTRL_UNIPHIER_PH1_PRO4 bool "UniPhier PH1-Pro4 SoC pinctrl driver" depends on ARCH_UNIPHIER_PH1_PRO4 default y - select PINCTRL_UNIPHIER_CORE + select PINCTRL_UNIPHIER config PINCTRL_UNIPHIER_PH1_SLD8 bool "UniPhier PH1-sLD8 SoC pinctrl driver" depends on ARCH_UNIPHIER_PH1_SLD8 default y - select PINCTRL_UNIPHIER_CORE + select PINCTRL_UNIPHIER config PINCTRL_UNIPHIER_PH1_PRO5 bool "UniPhier PH1-Pro5 SoC pinctrl driver" depends on ARCH_UNIPHIER_PH1_PRO5 default y - select PINCTRL_UNIPHIER_CORE + select PINCTRL_UNIPHIER config PINCTRL_UNIPHIER_PROXSTREAM2 bool "UniPhier ProXstream2 SoC pinctrl driver" depends on ARCH_UNIPHIER_PROXSTREAM2 default y - select PINCTRL_UNIPHIER_CORE + select PINCTRL_UNIPHIER config PINCTRL_UNIPHIER_PH1_LD6B bool "UniPhier PH1-LD6b SoC pinctrl driver" depends on ARCH_UNIPHIER_PH1_LD6B default y - select PINCTRL_UNIPHIER_CORE + select PINCTRL_UNIPHIER endif diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile index c5cdd84..3667bd3 100644 --- a/drivers/pinctrl/uniphier/Makefile +++ b/drivers/pinctrl/uniphier/Makefile @@ -2,7 +2,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_PINCTRL_UNIPHIER_CORE) += pinctrl-uniphier-core.o +obj-y += pinctrl-uniphier-core.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o -- 1.9.1

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[U-Boot] [PATCH] pinctrl: uniphier: set input-enable before pin-muxing
by Masahiro Yamada 08 Mar '16

08 Mar '16

While IECTRL is disabled, input signals are pulled-down internally. If pin-muxing is set up first, glitch signals (Low to High transition) might be input to hardware blocks. Bad case scenario: [1] The hardware block is already running before pinctrl is handled. (the reset is de-asserted by default or by a firmware, for example) [2] The pin-muxing is set up. The input signals to hardware block are pulled-down by the chip-internal biasing. [3] The pins are input-enabled. The signals from the board reach the hardware block. Actually, one invalid character is input to the UART blocks for such SoCs as PH1-LD4, PH1-sLD8, where UART devices start to run at the power on reset. To avoid such problems, pins should be input-enabled before muxing. [ ported from Linux commit bac7f4c1bf5e7c6ccd5bb71edc015b26c77f7460 ] Fixes: 5dc626f83619 ("pinctrl: uniphier: add UniPhier pinctrl core support") Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c index 37a920c..ffdccab 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c @@ -74,6 +74,9 @@ static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin, unsigned reg, reg_end, shift, mask; u32 tmp; + /* some pins need input-enabling */ + uniphier_pinconf_input_enable(dev, pin); + reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride; reg_end = reg + reg_stride; shift = pin * mux_bits % 32; @@ -94,9 +97,6 @@ static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin, if (priv->socdata->load_pinctrl) writel(1, priv->base + UNIPHIER_PINCTRL_LOAD_PINMUX); - - /* some pins need input-enabling */ - uniphier_pinconf_input_enable(dev, pin); } static int uniphier_pinmux_group_set(struct udevice *dev, -- 1.9.1

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[U-Boot] [PATCH] ARM: uniphier: fix build error when CONFIG_CMD_DDRMPHY_DUMP=y
by Masahiro Yamada 08 Mar '16

08 Mar '16

The build fails if compiled with CONFIG_CMD_DDRMPHY_DUMP=y since commit 46abfcc99e04 ("ARM: uniphier: rework struct uniphier_board_data"). Fixes: 46abfcc99e04 ("ARM: uniphier: rework struct uniphier_board_data") Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- arch/arm/mach-uniphier/dram/cmd_ddrmphy.c | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-) diff --git a/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c b/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c index c18f099..7ac9378 100644 --- a/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c +++ b/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c @@ -28,28 +28,14 @@ static int get_nr_ch(void) { const struct uniphier_board_data *bd = uniphier_get_board_param(); - return bd->dram_ch2_width ? 3 : 2; + return bd->dram_ch[2].size ? 3 : 2; } static int get_nr_datx8(int ch) { - unsigned int width; - const struct uniphier_board_data *bd = uniphier_get_board_param(); - switch (ch) { - case 0: - width = bd->dram_ch0_width; - break; - case 1: - width = bd->dram_ch1_width; - break; - default: - width = bd->dram_ch2_width; - break; - } - - return width / 8; + return bd->dram_ch[ch].width / 8; } static void print_bdl(void __iomem *reg, int n) -- 1.9.1

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[U-Boot] [PATCH] ARM: uniphier: document how-to-build for Ace and Sanji boards
by Masahiro Yamada 08 Mar '16

08 Mar '16

Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- doc/README.uniphier | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/doc/README.uniphier b/doc/README.uniphier index 6c3b092..8d043be 100644 --- a/doc/README.uniphier +++ b/doc/README.uniphier @@ -44,6 +44,14 @@ PH1-Pro4 reference board: $ make uniphier_pro4_defconfig $ make CROSS_COMPILE=arm-linux-gnueabi- +PH1-Pro4 Ace board: + $ make uniphier_pro4_defconfig + $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-pro4-ace + +PH1-Pro4 Sanji board: + $ make uniphier_pro4_defconfig + $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-pro4-sanji + PH1-Pro5 4KBOX Board: $ make uniphier_pxs2_ld6b_defconfig $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-pro5-4kbox -- 1.9.1

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[U-Boot] [PATCH 0/7 v3] support mapping PCI device ids to stream ids for MSIs
by Stuart Yoder 08 Mar '16

08 Mar '16

From: Stuart Yoder <stuart.yoder(a)nxp.com> A binding for PCI nodes has been finalized specifying how PCI device IDs can be mapped to MSI specifiers. See Documentation/devicetree/bindings/pci/pci-msi.txt in the kernel. For ls2080a and similar Layerscape SoCs, the MSI specifier is the stream id. A programmable table (LUT) in the PCI controller defines the hardware mapping of PCI requester IDs to stream IDs. This patch series implements support for this mapping. Patch 1 removes the obsolete available-stream-id support. Patch 2 updates stream ID partitioning info to be current Patch 3 updates pci.h so pci_get_hose_head() is available Patch 4 implements support for programming the LUT Patch 5 implements a simple stream ID allocator for PCI Patch 6 implements a function to set msi-map properties Patch 7 implements a function to iterate over all PCI buses and set up a LUT entry and msi-map for all discovered devices This patch series enables MSIs on ls2080a on v4.5-rc5 and later kernels. The obsolete support removed was unused in any upstream kernels. -v2 changes -in patch 7 removed skip of the host bridge when scanning the bus -v3 changes -patch 4: moved LUT #defines to immap_lsch3.h, made index allocator return an int -patch 5: return 0xffffffff on error -patch 7: fixed return value checks Stuart Yoder (7): armv8: ls2080a: remove obsolete stream ID partitioning support armv8: ls2080a: update stream ID partitioning info pci: make pci_get_hose_head() available to external users pci/layerscape: add support for LUT pci/layerscape: add stream ID allocator pci/layerscape: fdt: function to set msi-map entries pci/layerscape: set LUT and msi-map for discovered PCI devices arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 113 ---------- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 + .../asm/arch-fsl-layerscape/ls2080a_stream_id.h | 55 +++-- drivers/pci/pcie_layerscape.c | 215 +++++++++++++------- include/pci.h | 1 + 5 files changed, 184 insertions(+), 204 deletions(-) -- 1.7.9.5

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[U-Boot] Olimex-A20-EVB ethernet stops working with latest U-boot, works with tag v2016.01
by Ing. Damiano Bolla 08 Mar '16

08 Mar '16

Good morning all I updated to latest u-boot yesterday (git pull) and ethernet was not working reverted to tag v2016.01 with the command $ git checkout tags/v2016.01 rebuilt, uploaded and ethernet works As far as I can tell the only difference on the two tests (just a simple ping 192.168.1.1) is the u-boot version Ethernet cable was not moved and I manage to load u-boot using FEL I can do further tests is any of you is interested. Thanks, Damiano

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[U-Boot] [PATCH 1/3] vid: Return to default channel of the i2c multiplexer
by Wenbin Song 08 Mar '16

08 Mar '16

If the IR chip is connected to one of the channel of I2C-bus multiplexer, Set to the default channel after accessing the IR chip. Signed-off-by: Wenbin Song <wenbin.song(a)nxp.com> --- board/freescale/common/vid.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index 1bd65a8..a6a132a 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -454,6 +454,9 @@ int adjust_vdd(ulong vdd_override) exit: if (re_enable) enable_interrupts(); + + i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT); + return ret; } @@ -469,7 +472,7 @@ static int print_vdd(void) ret = find_ir_chip_on_i2c(); if (ret < 0) { printf("VID: Could not find voltage regulator on I2C.\n"); - return -1; + goto exit; } else { i2caddress = ret; debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress); @@ -481,11 +484,14 @@ static int print_vdd(void) vdd_last = read_voltage(i2caddress); if (vdd_last < 0) { printf("VID: Couldn't read sensor abort VID adjustment\n"); - return -1; + goto exit; } printf("VID: Core voltage is at %d mV\n", vdd_last); +exit: + i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT); + + return ret < 0 ? -1 : 0; - return 0; } static int do_vdd_override(cmd_tbl_t *cmdtp, -- 2.1.0.27.g96db324

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