March 2016 - U-Boot

[U-Boot] [PATCH v2 00/25] exynos: video: Convert exynos LCD driver to use driver model
by Simon Glass 26 May '16

26 May '16

This series converts the exynos LCD driver to work with driver model. Only the eDP display is converted - the MIPI display is left mostly alone as I do not have a device to test with. The conversion involves some refactoring to simplify the code, reduce the amount of global/static data and allow boards to be built without LCD support. The series is tested with snow, spring, pit and pi. It disables LCD on other exynos boards so that they will still build with these changes. Further work will be needed (by someone with a board) to convert the others. I am not sure when this series can be applied. The series also brings in device tree features from Linux v4.4. It would be useful to do a full sync with the kernel on these files, but this is really a job for the Samsung maintainer :-) The series is available at u-boot-dm/rkg-working. Changes in v2: - Rebase to master - Rebase to master Simon Glass (25): exynos: video: Move driver files into their own directory exynos: video: Drop dead code exynos: video: Remove use of vidinfo_t typedef exynos: video: Drop the static lcd_base_addr variable exynos: video: Drop static variables in exynos_fimd.c exynos: video: Drop static variables in exynos_fb.c exynos: video: Drop static variables in exynos_dp_lowlevel.c exynos: video: Move dsim_config_dt into a function exynos: video: Move struct exynos_platform_mipi_dsim into vidinfo exynos: video: Move mipi_lcd_device_dt into a function exynos: video: Combine LCD driver into one file exynos: pwm: Add a driver for the exynos5 PWM video: Add an enum for active low/high exynos: dts: Add pwm device tree node exynos: Allow tizen to be built without an LCD exynos: Allow CONFIG_MISC_COMMON to be build without an LCD exynos: Disable LCD display for boards we can't convert dts: Add clock and regulator binding files for max77802 exynos: Allow PWM0 pinmux to be set up exynos: Simplify calling of exynos_dp_phy_ctrl() exynos: dts: Add display-related device tree fragments exynos: video: Rename edp_device_info to exynos_dp_priv exynos: video: Rename variables for driver model exynos: video: Convert several boards to driver model for video exynos: video: Drop old unused code arch/arm/cpu/armv7/s5p-common/timer.c | 3 + arch/arm/dts/exynos5.dtsi | 3 +- arch/arm/dts/exynos5250-snow.dts | 44 ++ arch/arm/dts/exynos5250-spring.dts | 53 ++ arch/arm/dts/exynos5250.dtsi | 7 + arch/arm/dts/exynos5420-peach-pit.dts | 55 ++ arch/arm/dts/exynos54xx.dtsi | 11 +- arch/arm/dts/exynos5800-peach-pi.dts | 40 ++ arch/arm/mach-exynos/include/mach/cpu.h | 2 - arch/arm/mach-exynos/include/mach/dp_info.h | 5 +- arch/arm/mach-exynos/include/mach/mipi_dsim.h | 10 +- arch/arm/mach-exynos/include/mach/power.h | 2 +- arch/arm/mach-exynos/pinmux.c | 6 + arch/arm/mach-exynos/power.c | 2 +- board/samsung/common/board.c | 15 - board/samsung/common/exynos5-dt.c | 158 ----- board/samsung/common/misc.c | 10 + board/samsung/trats/trats.c | 2 + board/samsung/universal_c210/universal.c | 2 + configs/peach-pi_defconfig | 4 + configs/peach-pit_defconfig | 4 + configs/snow_defconfig | 4 + configs/spring_defconfig | 4 + drivers/pwm/Kconfig | 9 + drivers/pwm/Makefile | 1 + drivers/pwm/exynos_pwm.c | 120 ++++ drivers/video/Makefile | 6 +- drivers/video/exynos/Makefile | 12 + drivers/video/{ => exynos}/exynos_dp.c | 599 ++++++++++------- drivers/video/{ => exynos}/exynos_dp_lowlevel.c | 268 ++++---- drivers/video/exynos/exynos_dp_lowlevel.h | 89 +++ drivers/video/exynos/exynos_fb.c | 720 +++++++++++++++++++++ drivers/video/{ => exynos}/exynos_mipi_dsi.c | 71 +- .../video/{ => exynos}/exynos_mipi_dsi_common.c | 6 +- .../video/{ => exynos}/exynos_mipi_dsi_common.h | 0 .../video/{ => exynos}/exynos_mipi_dsi_lowlevel.c | 0 .../video/{ => exynos}/exynos_mipi_dsi_lowlevel.h | 0 drivers/video/{ => exynos}/exynos_pwm_bl.c | 0 drivers/video/exynos_dp_lowlevel.h | 68 -- drivers/video/exynos_fb.c | 330 ---------- drivers/video/exynos_fb.h | 41 -- drivers/video/exynos_fimd.c | 409 ------------ drivers/video/s6e8ax0.c | 4 +- drivers/video/simple_panel.c | 2 + include/configs/exynos5-common.h | 1 - include/configs/exynos5-dt-common.h | 5 +- include/configs/s5pc210_universal.h | 3 - include/configs/smdk5250.h | 3 + include/configs/smdk5420.h | 4 + include/configs/trats.h | 4 - include/configs/trats2.h | 4 - include/dt-bindings/clock/maxim,max77802.h | 22 + include/dt-bindings/regulator/maxim,max77802.h | 18 + include/exynos_lcd.h | 4 +- include/libtizen.h | 2 + include/video.h | 5 + lib/tizen/tizen.c | 2 + 57 files changed, 1804 insertions(+), 1474 deletions(-) create mode 100644 drivers/pwm/exynos_pwm.c create mode 100644 drivers/video/exynos/Makefile rename drivers/video/{ => exynos}/exynos_dp.c (50%) rename drivers/video/{ => exynos}/exynos_dp_lowlevel.c (77%) create mode 100644 drivers/video/exynos/exynos_dp_lowlevel.h create mode 100644 drivers/video/exynos/exynos_fb.c rename drivers/video/{ => exynos}/exynos_mipi_dsi.c (80%) rename drivers/video/{ => exynos}/exynos_mipi_dsi_common.c (99%) rename drivers/video/{ => exynos}/exynos_mipi_dsi_common.h (100%) rename drivers/video/{ => exynos}/exynos_mipi_dsi_lowlevel.c (100%) rename drivers/video/{ => exynos}/exynos_mipi_dsi_lowlevel.h (100%) rename drivers/video/{ => exynos}/exynos_pwm_bl.c (100%) delete mode 100644 drivers/video/exynos_dp_lowlevel.h delete mode 100644 drivers/video/exynos_fb.c delete mode 100644 drivers/video/exynos_fb.h delete mode 100644 drivers/video/exynos_fimd.c create mode 100644 include/dt-bindings/clock/maxim,max77802.h create mode 100644 include/dt-bindings/regulator/maxim,max77802.h -- 2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH 1/2 v2] driver/ddr/fsl: Add address parity support for DDR4 UDIMM/discrete
by Shengzhou Liu 25 May '16

25 May '16

Add support of address parity for DDR4 UDIMM or discrete memory. It requires to configurate corresponding MR5[2:0] and TIMING_CFG_7[PAR_LAT]. Parity can be turned on/off by hwconfig, e.g. hwconfig=fsl_ddr:parity=on. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)nxp.com> --- v2: Integrated York's comments. doc/README.fsl-ddr | 9 ++++++++ drivers/ddr/fsl/ctrl_regs.c | 55 ++++++++++++++++++++++++++++++++++++++++----- drivers/ddr/fsl/options.c | 15 +++++++++++-- include/fsl_ddr_sdram.h | 11 ++++++++- 4 files changed, 82 insertions(+), 8 deletions(-) diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index cd71ec8..cec5d94 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -123,6 +123,14 @@ ECC can be turned on/off by hwconfig. Syntax is hwconfig=fsl_ddr:ecc=off + +Memory address parity on/off +============================ +address parity can be turned on/off by hwconfig. +Syntax is: +hwconfig=fsl_ddr:parity=on + + Memory testing options for mpc85xx ================================== 1. Memory test can be done once U-Boot prompt comes up using mtest, or @@ -143,6 +151,7 @@ platform hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,ecc=on + Table for dynamic ODT for DDR3 ============================== For single-slot system with quad-rank DIMM and dual-slot system, dynamic ODT may diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 0bfcd34..9073917 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -895,11 +895,15 @@ static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num, slow = get_ddr_freq(ctrl_num) < 1249000000; #endif - if (popts->registered_dimm_en) { + if (popts->registered_dimm_en) rcw_en = 1; - ap_en = popts->ap_en; - } else { + + /* DDR4 can have address parity for UDIMM and discrete */ + if ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) && + (!popts->registered_dimm_en)) { ap_en = 0; + } else { + ap_en = popts->ap_en; } x4_en = popts->x4_en ? 1 : 0; @@ -1135,6 +1139,7 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr, unsigned short esdmode5; /* Extended SDRAM mode 5 */ int rtt_park = 0; bool four_cs = false; + const unsigned int mclk_ps = get_memory_clk_period_ps(0); #if CONFIG_CHIP_SELECTS_PER_CTRL == 4 if ((ddr->cs[0].config & SDRAM_CS_CONFIG_EN) && @@ -1150,6 +1155,19 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr, esdmode5 = 0x00000400; /* Data mask enabled */ } + /* set command/address parity latency */ + if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { + if (mclk_ps >= 935) { + /* for DDR4-1600/1866/2133 */ + esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK; + } else if (mclk_ps >= 833) { + /* for DDR4-2400 */ + esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK; + } else { + printf("parity: mclk_ps = %d not supported\n", mclk_ps); + } + } + ddr->ddr_sdram_mode_9 = (0 | ((esdmode4 & 0xffff) << 16) | ((esdmode5 & 0xffff) << 0) @@ -1170,6 +1188,20 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr, } else { esdmode5 = 0x00000400; } + + if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { + if (mclk_ps >= 935) { + /* for DDR4-1600/1866/2133 */ + esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK; + } else if (mclk_ps >= 833) { + /* for DDR4-2400 */ + esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK; + } else { + printf("parity: mclk_ps = %d not supported\n", + mclk_ps); + } + } + switch (i) { case 1: ddr->ddr_sdram_mode_11 = (0 @@ -1925,12 +1957,25 @@ static void set_timing_cfg_7(const unsigned int ctrl_num, const common_timing_params_t *common_dimm) { unsigned int txpr, tcksre, tcksrx; - unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd; + unsigned int cke_rst, cksre, cksrx, par_lat = 0, cs_to_cmd; + const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000)); tcksre = max(5U, picos_to_mclk(ctrl_num, 10000)); tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000)); - par_lat = 0; + + if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { + if (mclk_ps >= 935) { + /* parity latency 4 clocks in case of 1600/1866/2133 */ + par_lat = 4; + } else if (mclk_ps >= 833) { + /* parity latency 5 clocks for DDR4-2400 */ + par_lat = 5; + } else { + printf("parity: mclk_ps = %d not supported\n", mclk_ps); + } + } + cs_to_cmd = 0; if (txpr <= 200) diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c index 791d644..d0075ff 100644 --- a/drivers/ddr/fsl/options.c +++ b/drivers/ddr/fsl/options.c @@ -1002,8 +1002,19 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm, popts->twot_en = 0; popts->threet_en = 0; - /* for RDIMM, address parity enable */ - popts->ap_en = 1; + /* for RDIMM and DDR4 UDIMM/discrete memory, address parity enable */ + if (popts->registered_dimm_en) + popts->ap_en = 1; /* 0 = disable, 1 = enable */ + else + popts->ap_en = 0; /* disabled for DDR4 UDIMM/discrete default */ + + if (hwconfig_sub_f("fsl_ddr", "parity", buf)) { + if (hwconfig_subarg_cmp_f("fsl_ddr", "parity", "on", buf)) { + if (popts->registered_dimm_en || + (CONFIG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4)) + popts->ap_en = 1; + } + } /* * BSTTOPRE precharge interval diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 3699c04..cf316a4 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -123,6 +123,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define SDRAM_CFG2_FRC_SR 0x80000000 #define SDRAM_CFG2_D_INIT 0x00000010 +#define SDRAM_CFG2_AP_EN 0x00000020 #define SDRAM_CFG2_ODT_CFG_MASK 0x00600000 #define SDRAM_CFG2_ODT_NEVER 0 #define SDRAM_CFG2_ODT_ONLY_WRITE 1 @@ -177,6 +178,14 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 #define DDR_CDR2_VREF_RANGE_2 0x00000040 +/* DDR ERR_DISABLE */ +#define DDR_ERR_DISABLE_APED (1 << 8) /* Address parity error disable */ + +/* Mode Registers */ +#define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */ +#define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */ + + #if (defined(CONFIG_SYS_FSL_DDR_VER) && \ (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)) #ifdef CONFIG_SYS_FSL_DDR3L @@ -343,7 +352,7 @@ typedef struct memctl_options_s { /* mirrior DIMMs for DDR3 */ unsigned int mirrored_dimm; unsigned int quad_rank_present; - unsigned int ap_en; /* address parity enable for RDIMM */ + unsigned int ap_en; /* address parity enable for RDIMM/DDR4-UDIMM */ unsigned int x4_en; /* enable x4 devices */ /* Global Timing Parameters */ -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 0/5] Add QSPI support for LS2080A
by Yuan Yao 25 May '16

25 May '16

From: Yuan Yao <yao.yuan(a)nxp.com> There is the spansion S25FS-S family flash: s25fs256s1 on LS2080QDS QSPI. Yuan Yao (5): spi: fsl_qspi: Fix issues on arm64 spi: fsl_qspi: Assign AMBA mem according CS num in dts spi: fsl_qspi: Enable Spansion S25FS-S family flashes sf: Disable 4-KB erase command for SPANSION S25FS-S family armv8/ls1043a: update the node for QSPI support arch/arm/dts/fsl-ls1043a.dtsi | 5 +- drivers/mtd/spi/sf_internal.h | 5 ++ drivers/mtd/spi/spi_flash.c | 72 +++++++++++++++++++ drivers/spi/fsl_qspi.c | 159 ++++++++++++++++++++++++++++++++---------- 4 files changed, 202 insertions(+), 39 deletions(-) -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 1/3] armv8/ls1043: Add workaround for DDR erratum A-008850
by Shengzhou Liu 24 May '16

24 May '16

Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 18 ++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 + board/freescale/ls1043aqds/ddr.c | 21 +++++++++++++++++++++ board/freescale/ls1043aqds/ls1043aqds.c | 8 -------- board/freescale/ls1043ardb/ddr.c | 22 ++++++++++++++++++++++ board/freescale/ls1043ardb/ls1043ardb.c | 8 -------- include/fsl_ddr_sdram.h | 4 ++++ 7 files changed, 66 insertions(+), 16 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 213ce3a..816bf1b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -12,6 +12,8 @@ #include <asm/io.h> #include <asm/global_data.h> #include <asm/arch-fsl-layerscape/config.h> +#include <fsl_ddr_sdram.h> +#include <fsl_ddr.h> #ifdef CONFIG_CHAIN_OF_TRUST #include <fsl_validate.h> #endif @@ -231,6 +233,21 @@ static void erratum_a009660(void) #endif } +static void erratum_a008850(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008850 + /* part 1 of 2 */ + struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR; + struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + + /* disables propagation of barrier transactions to DDRC from CCI400 */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); + + /* disable the re-ordering in DDRC */ + ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); +#endif +} + void fsl_lsch2_early_init_f(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; @@ -255,6 +272,7 @@ void fsl_lsch2_early_init_f(void) CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); /* Erratum */ + erratum_a008850(); erratum_a009929(); erratum_a009660(); } diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index b0c112b..6ec7e50 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -176,6 +176,7 @@ #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 +#define CONFIG_SYS_FSL_ERRATUM_A008850 #define CONFIG_SYS_FSL_ERRATUM_A009663 #define CONFIG_SYS_FSL_ERRATUM_A009929 #define CONFIG_SYS_FSL_ERRATUM_A009942 diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c index 3d3c533..07d61f5 100644 --- a/board/freescale/ls1043aqds/ddr.c +++ b/board/freescale/ls1043aqds/ddr.c @@ -7,6 +7,8 @@ #include <common.h> #include <fsl_ddr_sdram.h> #include <fsl_ddr_dimm_params.h> +#include <fsl_ddr.h> +#include <asm/io.h> #ifdef CONFIG_FSL_DEEP_SLEEP #include <fsl_sleep.h> #endif @@ -105,6 +107,24 @@ found: #endif } +static void erratum_a008850(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008850 + /* part 2 of 2 */ + struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR; + struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + u32 tmp; + + /* enable propagation of barrier transactions to DDRC from CCI400 */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + + /* enable the re-ordering in DDRC */ + tmp = ddr_in32(&ddr->eor); + tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); + ddr_out32(&ddr->eor, tmp); +#endif +} + phys_size_t initdram(int board_type) { phys_size_t dram_size; @@ -116,6 +136,7 @@ phys_size_t initdram(int board_type) dram_size = fsl_ddr_sdram(); #endif + erratum_a008850(); #ifdef CONFIG_FSL_DEEP_SLEEP fsl_dp_ddr_restore(); diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index a72fe52..4ccfc79 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -305,14 +305,6 @@ int misc_init_r(void) int board_init(void) { - struct ccsr_cci400 *cci = (struct ccsr_cci400 *) - CONFIG_SYS_CCI400_ADDR; - - /* Set CCI-400 control override register to enable barrier - * transaction */ - out_le32(&cci->ctrl_ord, - CCI400_CTRLORD_EN_BARRIER); - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); board_retimer_init(); diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c index 11bc0f2..9aa9d18 100644 --- a/board/freescale/ls1043ardb/ddr.c +++ b/board/freescale/ls1043ardb/ddr.c @@ -6,6 +6,8 @@ #include <common.h> #include <fsl_ddr_sdram.h> +#include <fsl_ddr.h> +#include <asm/io.h> #include <fsl_ddr_dimm_params.h> #include "ddr.h" #ifdef CONFIG_FSL_DEEP_SLEEP @@ -167,6 +169,24 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, } #endif +static void erratum_a008850(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008850 + /* part 2 of 2 */ + struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR; + struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + u32 tmp; + + /* enable propagation of barrier transactions to DDRC from CCI400 */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + + /* enable the re-ordering in DDRC */ + tmp = ddr_in32(&ddr->eor); + tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); + ddr_out32(&ddr->eor, tmp); +#endif +} + phys_size_t initdram(int board_type) { phys_size_t dram_size; @@ -177,6 +197,8 @@ phys_size_t initdram(int board_type) #else dram_size = fsl_ddr_sdram_size(); #endif + erratum_a008850(); + #ifdef CONFIG_FSL_DEEP_SLEEP fsl_dp_ddr_restore(); #endif diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index 66d974a..1e2ef83 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -82,14 +82,6 @@ int board_early_init_f(void) int board_init(void) { - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; - - /* - * Set CCI-400 control override register to enable barrier - * transaction - */ - out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); - #ifdef CONFIG_FSL_IFC init_final_memctl_regs(); #endif diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index cf316a4..44ae7fb 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -146,6 +146,10 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define WR_DATA_DELAY_SHIFT 10 #endif +/* DDR_EOR register */ +#define DDR_EOR_RD_REOD_DIS 0x07000000 +#define DDR_EOR_WD_REOD_DIS 0x00100000 + /* DDR_MD_CNTL */ #define MD_CNTL_MD_EN 0x80000000 #define MD_CNTL_CS_SEL_CS0 0x00000000 -- 2.1.0.27.g96db324

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[U-Boot] [PATCH v3 00/11] arm: rpi: Enable USB and Ethernet driver model Raspberry Pi
by Simon Glass 23 May '16

23 May '16

Raspberry Pi uses a DWC2 USB controller and a SMSC USB Ethernet adaptor. Driver model support for these was recently merged. This series does the following: - Move Raspberry Pi to use device tree control (u-boot-dtb.bin instead of u-boot.bin) - Remove GPIO platform data (now uses device tree) - Remove serial platform data (now uses device tree) - Enable CONFIG_DM_ETH and CONFIG_DM_USB on Raspberry Pi With Ethernet active the device list looks something like this: U-Boot> dm tree Class Probed Name ---------------------------------------- root [ + ] root_driver simple_bus [ + ] |-- soc gpio [ ] | |-- gpio@7e200000 serial [ + ] | |-- uart@7e201000 usb [ + ] | `-- usb@7e980000 usb_hub [ + ] | `-- usb_hub usb_hub [ + ] | `-- usb_hub eth [ + ] | `-- smsc95xx_eth simple_bus [ ] `-- clocks Changes in v3: - Drop applied patches from series - Drop patch to introduce usbethaddr for driver model - Rename binding file to pl01x.txt Changes in v2: - Add support for Raspberry Pi 2 Simon Glass (11): dm: serial: Update binding for PL01x serial UART arm: rpi: Define CONFIG_TFTP_TSIZE to show tftp size info arm: rpi: Bring in kernel device tree files arm: rpi: Device tree modifications for U-Boot arm: rpi: Add device tree files for Raspberry Pi 2 arm: rpi: Enable device tree control for Rasberry Pi arm: rpi: Enable device tree control for Rasberry Pi 2 arm: rpi: Drop the UART console platform data arm: rpi: Drop the GPIO platform data arm: rpi: Move to driver model for USB arm: rpi: Use driver model for Ethernet arch/arm/dts/Makefile | 3 + arch/arm/dts/bcm2835-rpi-b.dts | 24 ++++ arch/arm/dts/bcm2835.dtsi | 35 +++++ arch/arm/dts/bcm2836-rpi-2-b.dts | 30 +++++ arch/arm/dts/bcm2836.dtsi | 42 ++++++ arch/arm/dts/bcm283x-common.dtsi | 157 ++++++++++++++++++++++ arch/arm/dts/bcm283x-rpi.dtsi | 49 +++++++ arch/arm/dts/stv0991.dts | 2 +- arch/arm/mach-bcm283x/include/mach/gpio.h | 5 - board/raspberrypi/rpi/rpi.c | 24 ---- configs/rpi_2_defconfig | 6 + configs/rpi_defconfig | 6 + doc/device-tree-bindings/arm/bcm/brcm,bcm2835.txt | 8 ++ doc/device-tree-bindings/arm/bcm/brcm,bcm2836.txt | 10 ++ doc/device-tree-bindings/serial/pl01x.txt | 55 +++++++- drivers/gpio/bcm2835_gpio.c | 20 +++ drivers/serial/serial_pl01x.c | 6 +- include/configs/rpi-common.h | 6 +- include/dt-bindings/pinctrl/bcm2835.h | 27 ++++ 19 files changed, 474 insertions(+), 41 deletions(-) create mode 100644 arch/arm/dts/bcm2835-rpi-b.dts create mode 100644 arch/arm/dts/bcm2835.dtsi create mode 100644 arch/arm/dts/bcm2836-rpi-2-b.dts create mode 100644 arch/arm/dts/bcm2836.dtsi create mode 100644 arch/arm/dts/bcm283x-common.dtsi create mode 100644 arch/arm/dts/bcm283x-rpi.dtsi create mode 100644 doc/device-tree-bindings/arm/bcm/brcm,bcm2835.txt create mode 100644 doc/device-tree-bindings/arm/bcm/brcm,bcm2836.txt create mode 100644 include/dt-bindings/pinctrl/bcm2835.h -- 2.5.0.rc2.392.g76e840b

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[U-Boot] Issue with USB mass storage (thumb drives)
by Schrempf Frieder 20 May '16

20 May '16

Hello, I'm using U-Boot on a custom i.MX6 board and I'm having problems while reading (large) files from USB thumb drives. I wouldn't really mind if this only happened with some specific USB device, but the problem occurs with 3 out of 4 tested thumb drives while loading a 100M test file. The devices that work seem to be rather old ones. The same issue is also reported here: https://community.freescale.com/thread/377911 I can reproduce this behaviour with u-boot-imx v2014.04 and with mainline u-boot v2015.10 and v2016.01. Can someone tell me if this is a known issue? What could be the reason for this and how can I get this working? Thanks! U-Boot 2016.01 (Feb 02 2016 - 10:31:32 +0100) CPU: Freescale i.MX6SOLO rev1.3 at 792MHz CPU: Industrial temperature grade (-40C to 105C) at 31C Reset cause: POR Board: MX6EXCEET DRAM: 1 GiB NAND: 256 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 SF: Detected EN25Q80 with page size 256 Bytes, erase size 4 KiB, total 1 MiB No panel detected: default to Hannstar-XGA Display: Hannstar-XGA (1024x768) In: serial Out: serial Err: serial Net: Found Micrel KS8051/KS8081 PHY FEC Hit any key to stop autoboot: 0 => usb start starting USB... USB0: Port not available. USB1: USB EHCI 1.00 scanning bus 1 for devices... 2 USB Device(s) found scanning usb for storage devices... 1 Storage Device(s) found scanning usb for ethernet devices... 0 Ethernet Device(s) found => fatload usb 0 0x18000000 test.file reading test.file EHCI timed out on TD - token=0xac008d80 EHCI timed out on TD - token=0x80008d80 EHCI timed out on TD - token=0x80008d80 EHCI timed out on TD - token=0x80008d80 EHCI timed out on TD - token=0x128d80 EHCI timed out on TD - token=0x80008d80 EHCI timed out on TD - token=0x80008d80 EHCI timed out on TD - token=0x80008d80 EHCI timed out on TD - token=0x801f8c80 EHCI timed out on TD - token=0x80008d80 EHCI timed out on TD - token=0x80008d80 EHCI timed out on TD - token=0x80008d80 EHCI timed out on TD - token=0x801f8c80 EHCI timed out on TD - token=0x80008d80 EHCI timed out on TD - token=0x80008d80 EHCI timed out on TD - token=0x80008d80 EHCI timed out on TD - token=0x801f8c80 EHCI timed out on TD - token=0x80008d80 EHCI timed out on TD - token=0x80008d80 EHCI timed out on TD - token=0x80008d80 EHCI timed out on TD - token=0x801f8c80 EHCI timed out on TD - token=0x80008d80 EHCI timed out on TD - token=0x80008d80 EHCI timed out on TD - token=0x80008d80 Error reading cluster ** Unable to read file test.file **

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[U-Boot] [PATCH 1/4] spi: fsl_qspi: Fix issues on arm64
by Yuan Yao 19 May '16

19 May '16

From: Yuan Yao <yao.yuan(a)nxp.com> The address value and size value get from dts "reg" property have type of u64 on arm64. If we assign those values to "u32" variables, driver can't work correctly. Converting the type of those variables to fdt_xxx_t. Signed-off-by: Yuan Yao <yao.yuan(a)freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> Signed-off-by: Yuan Yao <yao.yuan(a)nxp.com> --- drivers/spi/fsl_qspi.c | 46 +++++++++++++++++++++++++++------------------- 1 file changed, 27 insertions(+), 19 deletions(-) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index cb8d929..96fb909 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -92,9 +92,9 @@ DECLARE_GLOBAL_DATA_PTR; struct fsl_qspi_platdata { u32 flags; u32 speed_hz; - u32 reg_base; - u32 amba_base; - u32 amba_total_size; + fdt_addr_t reg_base; + fdt_addr_t amba_base; + fdt_size_t amba_total_size; u32 flash_num; u32 num_chipselect; }; @@ -940,8 +940,13 @@ static int fsl_qspi_probe(struct udevice *bus) priv->flags = plat->flags; priv->speed_hz = plat->speed_hz; - priv->amba_base[0] = plat->amba_base; - priv->amba_total_size = plat->amba_total_size; + /* + * QSPI SFADR width is 32bits, the max dest addr is 4GB-1. + * AMBA memory zone should be located on the 0~4GB space + * even on a 64bits cpu. + */ + priv->amba_base[0] = (u32)plat->amba_base; + priv->amba_total_size = (u32)plat->amba_total_size; priv->flash_num = plat->flash_num; priv->num_chipselect = plat->num_chipselect; @@ -984,10 +989,7 @@ static int fsl_qspi_probe(struct udevice *bus) static int fsl_qspi_ofdata_to_platdata(struct udevice *bus) { - struct reg_data { - u32 addr; - u32 size; - } regs_data[2]; + struct fdt_resource res_regs, res_mem; struct fsl_qspi_platdata *plat = bus->platdata; const void *blob = gd->fdt_blob; int node = bus->of_offset; @@ -996,10 +998,16 @@ static int fsl_qspi_ofdata_to_platdata(struct udevice *bus) if (fdtdec_get_bool(blob, node, "big-endian")) plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG; - ret = fdtdec_get_int_array(blob, node, "reg", (u32 *)regs_data, - sizeof(regs_data)/sizeof(u32)); + ret = fdt_get_named_resource(blob, node, "reg", "reg-names", + "QuadSPI", &res_regs); + if (ret) { + debug("Error: can't get regs base addresses(ret = %d)!\n", ret); + return -ENOMEM; + } + ret = fdt_get_named_resource(blob, node, "reg", "reg-names", + "QuadSPI-memory", &res_mem); if (ret) { - debug("Error: can't get base addresses (ret = %d)!\n", ret); + debug("Error: can't get AMBA base addresses(ret = %d)!\n", ret); return -ENOMEM; } @@ -1017,16 +1025,16 @@ static int fsl_qspi_ofdata_to_platdata(struct udevice *bus) plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs", FSL_QSPI_MAX_CHIPSELECT_NUM); - plat->reg_base = regs_data[0].addr; - plat->amba_base = regs_data[1].addr; - plat->amba_total_size = regs_data[1].size; + plat->reg_base = res_regs.start; + plat->amba_base = res_mem.start; + plat->amba_total_size = res_mem.end - res_mem.start + 1; plat->flash_num = flash_num; - debug("%s: regs=<0x%x> <0x%x, 0x%x>, max-frequency=%d, endianess=%s\n", + debug("%s: regs=<0x%llx> <0x%llx, 0x%llx>, max-frequency=%d, endianess=%s\n", __func__, - plat->reg_base, - plat->amba_base, - plat->amba_total_size, + (u64)plat->reg_base, + (u64)plat->amba_base, + (u64)plat->amba_total_size, plat->speed_hz, plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le" ); -- 2.1.0.27.g96db324

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[U-Boot] Remove sh2, sh3, sh4 architecture?
by Simon Glass 17 May '16

17 May '16

Hi, It looks like these have no maintainer and have not been converted to generic board. Should we remove the 'sh' architecture? Regards, Simon

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[U-Boot] Converting openrisc to generic board
by Simon Glass 15 May '16

15 May '16

Hi Stefan, I would like to remove all the arch/*/lib/board.c files soon. Can you please take a look at converting openrisc to use generic board? doc/README.generic-board Thanks! Simon

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[U-Boot] [PATCH] dm: gpio: handle GPIO_ACTIVE_LOW flag in DT
by Eric Nelson 07 May '16

07 May '16

Device tree parsing of GPIO nodes is currently ignoring flags. Add support for GPIO_ACTIVE_LOW by checking for the presence of the flag and setting the desc->flags field to the driver model constant GPIOD_ACTIVE_LOW. Signed-off-by: Eric Nelson <eric(a)nelint.com> --- drivers/gpio/gpio-uclass.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index b58d4e6..6d30612 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -6,6 +6,7 @@ #include <common.h> #include <dm.h> +#include <dt-bindings/gpio/gpio.h> #include <errno.h> #include <fdtdec.h> #include <malloc.h> @@ -118,12 +119,16 @@ static int gpio_find_and_xlate(struct gpio_desc *desc, { struct dm_gpio_ops *ops = gpio_get_ops(desc->dev); + desc->flags = 0; /* Use the first argument as the offset by default */ - if (args->args_count > 0) + if (args->args_count > 0) { desc->offset = args->args[0]; + if ((args->args_count > 1) && + (args->args[1] & GPIO_ACTIVE_LOW)) + desc->flags = GPIOD_ACTIVE_LOW; + } else desc->offset = -1; - desc->flags = 0; return ops->xlate ? ops->xlate(desc->dev, desc, args) : 0; } -- 2.6.2

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