March 2016 - U-Boot

[U-Boot] [PATCH] mvebu: usb: Add missing controller reset after initialization
by Phil Sutter 24 Mar '16

24 Mar '16

In order to allow for Linux properly register the integrated EHCI host, we have to reset it after initialization. Without this, enumeration fails if 'usb start' wasn't issued prior to booting Linux. Signed-off-by: Phil Sutter <phil(a)nwl.cc> --- arch/arm/mach-mvebu/cpu.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 5c62fd5..cb885f8 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -281,6 +281,8 @@ static void set_cbar(u32 addr) (((addr) & 0xF) << 6)) #define MV_USB_X3_PHY_CHANNEL(dev, reg) (MV_USB_X3_BASE((dev) + 1) | \ (((reg) & 0xF) << 2)) +#define MV_USB_CMD_REG(dev) (MVEBU_AXP_USB_BASE + (dev * 0x1000) + 0x140) +#define MV_USB_MODE_REG(dev) (MVEBU_AXP_USB_BASE + (dev * 0x1000) + 0x1A8) static void setup_usb_phys(void) { @@ -313,6 +315,16 @@ static void setup_usb_phys(void) setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12)); udelay(40); clrbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12)); + + /* disable (bit 0) and reset (bit 1) controller */ + /* XXX: do this in two steps? */ + clrsetbits_le32(MV_USB_CMD_REG(dev), BIT(0), BIT(1)); + + while(readl(MV_USB_CMD_REG(dev)) & BIT(1)) + ; + + /* set host mode (device mode is (0x2 | 1 << 3)) */ + writel(0x3, MV_USB_MODE_REG(dev)); } } -- 2.5.3

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[U-Boot] [PATCH 1/2] tools: kwboot: Clean up usage text
by Kevin Smith 24 Mar '16

24 Mar '16

Usage text was getting unwieldy and somewhat incorrect. The usage summary implied that some options were mutually exclusive (e.g. -q or -s). Clean up the summary to just include the important ones, and include a generic "[OPTIONS]" instead. Signed-off-by: Kevin Smith <kevin.smith(a)elecsyscorp.com> Cc: Stefan Roese <sr(a)denx.de> --- tools/kwboot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/kwboot.c b/tools/kwboot.c index c5f4492..6d1f66e 100644 --- a/tools/kwboot.c +++ b/tools/kwboot.c @@ -674,7 +674,7 @@ static void kwboot_usage(FILE *stream, char *progname) { fprintf(stream, - "Usage: %s [-d | -a | -q <req-delay> | -s <resp-timeo> | -b <image> | -D <image> ] [ -t ] [-B <baud> ] <TTY>\n", + "Usage: %s [OPTIONS] [-b <image> | -D <image> ] [-B <baud> ] <TTY>\n", progname); fprintf(stream, "\n"); fprintf(stream, -- 2.4.6

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[U-Boot] [PATCH] arm: mvebu: db-88f6820: Drop obsolete binary.0 placeholder
by Andreas Färber 24 Mar '16

24 Mar '16

It has been superseded in kwbimage.cfg in favor of an SPL in commit 9e30b31d20f0b793465d07f056b3d9885f578c0d (arm: mvebu: db-88f6820: Add SPL support with DDR init code). Found via code review. Cc: Stefan Roese <sr(a)denx.de> Signed-off-by: Andreas Färber <afaerber(a)suse.de> --- board/Marvell/db-88f6820-gp/binary.0 | 16 ---------------- 1 file changed, 16 deletions(-) delete mode 100644 board/Marvell/db-88f6820-gp/binary.0 diff --git a/board/Marvell/db-88f6820-gp/binary.0 b/board/Marvell/db-88f6820-gp/binary.0 deleted file mode 100644 index 57a4cbf..0000000 --- a/board/Marvell/db-88f6820-gp/binary.0 +++ /dev/null @@ -1,16 +0,0 @@ --------- -WARNING: --------- -This file should contain the bin_hdr generated by the original Marvell -U-Boot implementation. As this is currently not included in this -U-Boot version, we have added this placeholder, so that the U-Boot -image can be generated without errors. - -If you have a known to be working bin_hdr for your board, then you -just need to replace this text file here with the binary header -and recompile U-Boot. - -In a few weeks, mainline U-Boot will get support to generate the -bin_hdr with the DDR training code itself. By implementing this code -as SPL U-Boot. Then this file will not be needed any more and will -get removed. -- 2.6.2

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[U-Boot] [PATCH 1/3] arm: mvebu: Add some SPI CS attributes
by Stefan Roese 24 Mar '16

24 Mar '16

These attribute defines may be used to map an area of memory for direct access to the specific SPI devices. See SPI Direct Access Mode for further information. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Luka Perkov <luka.perkov(a)sartura.hr> --- arch/arm/mach-mvebu/include/mach/cpu.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index 017d55f..dd58b4a 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -47,6 +47,9 @@ enum cpu_attrib { CPU_ATTR_DRAM_CS3 = 0x07, CPU_ATTR_NANDFLASH = 0x2f, CPU_ATTR_SPIFLASH = 0x1e, + CPU_ATTR_SPI0_CS0 = 0x1e, + CPU_ATTR_SPI0_CS1 = 0x5e, + CPU_ATTR_SPI1_CS2 = 0x9a, CPU_ATTR_BOOTROM = 0x1d, CPU_ATTR_PCIE_IO = 0xe0, CPU_ATTR_PCIE_MEM = 0xe8, -- 2.7.1

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[U-Boot] [PATCH] fpga: altera: Add StratixV support
by Stefan Roese 24 Mar '16

24 Mar '16

This patch adds support for programming of the StratixV FPGAs. Programming is done in this case (board theadorable) via SPI. The board may provide board specific code for bitstream programming. This StratixV support will be used by the theadorable board. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Tom Rini <trini(a)konsulko.com> --- drivers/fpga/Makefile | 1 + drivers/fpga/altera.c | 3 ++ drivers/fpga/stratixv.c | 103 ++++++++++++++++++++++++++++++++++++++++++++++++ include/altera.h | 20 ++++++++++ 4 files changed, 127 insertions(+) create mode 100644 drivers/fpga/stratixv.c diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 6aa24d4..fec3fec 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -17,5 +17,6 @@ obj-y += altera.o obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o +obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o endif diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index a5bfe5d..135a357 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -37,6 +37,9 @@ static const struct altera_fpga { { Altera_StratixII, "StratixII", StratixII_load, StratixII_dump, StratixII_info }, #endif +#if defined(CONFIG_FPGA_STRATIX_V) + { Altera_StratixV, "StratixV", stratixv_load, NULL, NULL }, +#endif #if defined(CONFIG_FPGA_SOCFPGA) { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL }, #endif diff --git a/drivers/fpga/stratixv.c b/drivers/fpga/stratixv.c new file mode 100644 index 0000000..cc035eb --- /dev/null +++ b/drivers/fpga/stratixv.c @@ -0,0 +1,103 @@ +/* + * Copyright (C) 2016 Stefan Roese <sr(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <altera.h> +#include <spi.h> +#include <asm/io.h> +#include <asm/errno.h> + +/* Write the RBF data to FPGA via SPI */ +static int program_write(int spi_bus, int spi_dev, const void *rbf_data, + unsigned long rbf_size) +{ + struct spi_slave *slave; + int ret; + + debug("%s (%d): data=%p size=%ld\n", + __func__, __LINE__, rbf_data, rbf_size); + + /* FIXME: How to get the max. SPI clock and SPI mode? */ + slave = spi_setup_slave(spi_bus, spi_dev, 27777777, SPI_MODE_3); + if (!slave) + return -1; + + if (spi_claim_bus(slave)) + return -1; + + ret = spi_xfer(slave, rbf_size * 8, rbf_data, (void *)rbf_data, + SPI_XFER_BEGIN | SPI_XFER_END); + + spi_release_bus(slave); + + return ret; +} + +/* + * This is the interface used by FPGA driver. + * Return 0 for sucess, non-zero for error. + */ +int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) +{ + altera_board_specific_func *pfns = desc->iface_fns; + int cookie = desc->cookie; + int spi_bus; + int spi_dev; + int ret = 0; + + if ((u32)rbf_data & 0x3) { + puts("FPGA: Unaligned data, realign to 32bit boundary.\n"); + return -EINVAL; + } + + /* Run the pre configuration function if there is one */ + if (pfns->pre) + (pfns->pre)(cookie); + + /* Establish the initial state */ + if (pfns->config) { + /* De-assert nCONFIG */ + (pfns->config)(false, true, cookie); + + /* nConfig minimum low pulse width is 2us */ + udelay(200); + + /* Assert nCONFIG */ + (pfns->config)(true, true, cookie); + + /* nCONFIG high to first rising clock on DCLK min 1506 us */ + udelay(1600); + } + + /* Write the RBF data to FPGA */ + if (pfns->write) { + /* + * Use board specific data function to write bitstream + * into the FPGA + */ + ret = (pfns->write)(rbf_data, rbf_size, true, cookie); + } else { + /* + * Use common SPI functions to write bitstream into the + * FPGA + */ + spi_bus = COOKIE2SPI_BUS(cookie); + spi_dev = COOKIE2SPI_DEV(cookie); + ret = program_write(spi_bus, spi_dev, rbf_data, rbf_size); + } + if (ret) + return ret; + + /* Check done pin */ + if (pfns->done) { + ret = (pfns->done)(cookie); + + if (ret) + printf("Error: DONE not set (ret=%d)!\n", ret); + } + + return ret; +} diff --git a/include/altera.h b/include/altera.h index c2991ad..48d3eb7 100644 --- a/include/altera.h +++ b/include/altera.h @@ -10,6 +10,19 @@ #ifndef _ALTERA_H_ #define _ALTERA_H_ +/* + * For the StratixV FPGA programming via SPI, the following + * information is coded in the 32bit cookie: + * Bit 31 ... Bit 0 + * SPI-Bus | SPI-Dev | Config-Pin | Done-Pin + */ +#define FPGA_COOKIE(bus, dev, config, done) \ + (((bus) << 24) | ((dev) << 16) | ((config) << 8) | (done)) +#define COOKIE2SPI_BUS(c) (((c) >> 24) & 0xff) +#define COOKIE2SPI_DEV(c) (((c) >> 16) & 0xff) +#define COOKIE2CONFIG(c) (((c) >> 8) & 0xff) +#define COOKIE2DONE(c) ((c) & 0xff) + enum altera_iface { /* insert all new types after this */ min_altera_iface_type, @@ -40,6 +53,8 @@ enum altera_family { Altera_CYC2, /* StratixII Family */ Altera_StratixII, + /* StratixV Family */ + Altera_StratixV, /* SoCFPGA Family */ Altera_SoCFPGA, @@ -89,6 +104,7 @@ typedef struct { Altera_done_fn done; Altera_clk_fn clk; Altera_data_fn data; + Altera_write_fn write; Altera_abort_fn abort; Altera_post_fn post; } altera_board_specific_func; @@ -97,4 +113,8 @@ typedef struct { int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size); #endif +#ifdef CONFIG_FPGA_STRATIX_V +int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size); +#endif + #endif /* _ALTERA_H_ */ -- 2.7.1

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[U-Boot] [PATCH] gpio: Add DM GPIO driver for Marvell MVEBU
by Stefan Roese 24 Mar '16

24 Mar '16

This patch adds a DM GPIO driver for the Marvell MVEBU SoCs. There are other non-DM drivers that might be used on these platforms. But this patch creates a new DM driver. Which will be used by all Armada XP/38x boards. Other MVEBU SoC (Kirkwood / Orion) may follow once they support DM as well. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Dirk Eibach <dirk.eibach(a)gdsys.cc> Cc: Phil Sutter <phil(a)nwl.cc> Cc: Kevin Smith <kevin.smith(a)elecsyscorp.com> Cc: Luka Perkov <luka.perkov(a)sartura.hr> Cc: Tom Rini <trini(a)konsulko.com> --- drivers/gpio/Kconfig | 7 +++ drivers/gpio/Makefile | 1 + drivers/gpio/mvebu_gpio.c | 119 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 127 insertions(+) create mode 100644 drivers/gpio/mvebu_gpio.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 845dc72..6147aa3 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -90,4 +90,11 @@ config PIC32_GPIO help Say yes here to support Microchip PIC32 GPIOs. +config MVEBU_GPIO + bool "Marvell MVEBU GPIO driver" + depends on DM_GPIO && ARCH_MVEBU + default y + help + Say yes here to support Marvell MVEBU (Armada XP/38x) GPIOs. + endmenu diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 845a6d4..54d1706 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -47,3 +47,4 @@ obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o +obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o diff --git a/drivers/gpio/mvebu_gpio.c b/drivers/gpio/mvebu_gpio.c new file mode 100644 index 0000000..9564ce2 --- /dev/null +++ b/drivers/gpio/mvebu_gpio.c @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2016 Stefan Roese <sr(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <errno.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define MVEBU_GPIOS_PER_BANK 32 + +struct mvebu_gpio_regs { + u32 data_out; + u32 io_conf; + u32 blink_en; + u32 in_pol; + u32 data_in; +}; + +struct mvebu_gpio_priv { + struct mvebu_gpio_regs *regs; + char name[2]; +}; + +static int mvebu_gpio_direction_input(struct udevice *dev, unsigned int gpio) +{ + struct mvebu_gpio_priv *priv = dev_get_priv(dev); + struct mvebu_gpio_regs *regs = priv->regs; + + setbits_le32(&regs->io_conf, BIT(gpio)); + + return 0; +} + +static int mvebu_gpio_direction_output(struct udevice *dev, unsigned gpio, + int value) +{ + struct mvebu_gpio_priv *priv = dev_get_priv(dev); + struct mvebu_gpio_regs *regs = priv->regs; + + clrbits_le32(&regs->io_conf, BIT(gpio)); + + return 0; +} + +static int mvebu_gpio_get_function(struct udevice *dev, unsigned gpio) +{ + struct mvebu_gpio_priv *priv = dev_get_priv(dev); + struct mvebu_gpio_regs *regs = priv->regs; + u32 val; + + val = readl(&regs->io_conf) & BIT(gpio); + if (val) + return GPIOF_INPUT; + else + return GPIOF_OUTPUT; +} + +static int mvebu_gpio_set_value(struct udevice *dev, unsigned gpio, + int value) +{ + struct mvebu_gpio_priv *priv = dev_get_priv(dev); + struct mvebu_gpio_regs *regs = priv->regs; + + if (value) + setbits_le32(&regs->data_out, BIT(gpio)); + else + clrbits_le32(&regs->data_out, BIT(gpio)); + + return 0; +} + +static int mvebu_gpio_get_value(struct udevice *dev, unsigned gpio) +{ + struct mvebu_gpio_priv *priv = dev_get_priv(dev); + struct mvebu_gpio_regs *regs = priv->regs; + + return !!(readl(&regs->data_in) & BIT(gpio)); +} + +static int mvebu_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct mvebu_gpio_priv *priv = dev_get_priv(dev); + + priv->regs = (struct mvebu_gpio_regs *)dev_get_addr(dev); + uc_priv->gpio_count = MVEBU_GPIOS_PER_BANK; + priv->name[0] = 'A' + dev->req_seq; + uc_priv->bank_name = priv->name; + + return 0; +} + +static const struct dm_gpio_ops mvebu_gpio_ops = { + .direction_input = mvebu_gpio_direction_input, + .direction_output = mvebu_gpio_direction_output, + .get_function = mvebu_gpio_get_function, + .get_value = mvebu_gpio_get_value, + .set_value = mvebu_gpio_set_value, +}; + +static const struct udevice_id mvebu_gpio_ids[] = { + { .compatible = "marvell,orion-gpio" }, + { } +}; + +U_BOOT_DRIVER(gpio_mvebu) = { + .name = "gpio_mvebu", + .id = UCLASS_GPIO, + .of_match = mvebu_gpio_ids, + .ops = &mvebu_gpio_ops, + .probe = mvebu_gpio_probe, + .priv_auto_alloc_size = sizeof(struct mvebu_gpio_priv), +}; -- 2.7.1

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[U-Boot] [PATCH v0 0/5] Some improvements for mvebu/a38x
by dirk.eibach＠gdsys.cc 24 Mar '16

24 Mar '16

From: Dirk Eibach <dirk.eibach(a)gdsys.cc> Dirk Eibach (5): pci: mvebu: Fix Armada 38x support arm: mvebu: Add gpio support arm: mvebu: Fix SAR1_CPU_CORE_MASK arm: mvebu: Fix ddr3_init() cpu config spi: Add support for Armada 38x second controller arch/arm/mach-mvebu/include/mach/gpio.h | 41 ++++++++++++++++- arch/arm/mach-mvebu/include/mach/soc.h | 1 + .../ddr/marvell/a38x/ddr3_hws_hw_training_def.h | 7 +-- drivers/ddr/marvell/a38x/ddr3_init.c | 2 - drivers/pci/pci_mvebu.c | 22 ++++----- drivers/spi/kirkwood_spi.c | 52 +++++++++++++++++++--- 6 files changed, 98 insertions(+), 27 deletions(-) -- 2.1.3

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[U-Boot] [PATCH] arm: mvebu: enable generic distro boot config
by Dennis Gilmore 24 Mar '16

24 Mar '16

Switch all of the mvebu boards to support disto generic booting This will enable Fedora, Debian and other distros to support mvebu systems easier. Tested on SolidRun ClearFog Signed-off-by: Dennis Gilmore <dgilmore(a)redhat.com> --- include/configs/clearfog.h | 5 --- include/configs/mv-common.h | 86 ++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 85 insertions(+), 6 deletions(-) diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h index f0de827..926b3c5 100644 --- a/include/configs/clearfog.h +++ b/include/configs/clearfog.h @@ -104,11 +104,6 @@ #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ #define CONFIG_SYS_ALT_MEMTEST -/* Keep device tree and initrd in lower memory so the kernel can access them */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0x10000000\0" \ - "initrd_high=0x10000000\0" - /* SPL */ /* * Select the boot device here diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index d12d725..e219243 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -57,7 +57,7 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ 115200,230400, 460800, 921600 } /* auto boot */ -#define CONFIG_BOOTDELAY 3 /* default enable autoboot */ +#define CONFIG_BOOTDELAY 2 /* default enable autoboot */ #define CONFIG_PREBOOT #define CONFIG_OF_LIBFDT /* Device tree support */ @@ -152,4 +152,88 @@ #define CONFIG_LZO #endif +#ifndef CONFIG_SPL_BUILD +#include <config_distro_defaults.h> + +/* +* 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc. +* 32M uncompressed kernel, 16M compressed kernel, 1M fdt, +* 1M script, 1M pxe and the ramdisk at the end. +*/ +#define SDRAM_OFFSET(x) 0x0##x + +#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(2000000)) +#define FDT_ADDR_R __stringify(SDRAM_OFFSET(3000000)) +#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(3100000)) +#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000)) +#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3300000)) + +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0xa000000\0" \ + "kernel_addr_r=" KERNEL_ADDR_R "\0" \ + "fdt_addr_r=" FDT_ADDR_R "\0" \ + "scriptaddr=" SCRIPT_ADDR_R "\0" \ + "pxefile_addr_r=" PXEFILE_ADDR_R "\0" \ + "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" + +#ifdef CONFIG_MMC +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_DEVICES_MMC(func) +#endif + +#ifdef CONFIG_CMD_SATA +#define BOOT_TARGET_DEVICES_SATA(func) func(SATA, sata, 0) func(SATA, sata, 1) +#define CONFIG_PREBOOT "sata init" +#else +#define BOOT_TARGET_DEVICES_SATA(func) +#endif + +#ifdef CONFIG_USB_STORAGE +#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) +#else +#define BOOT_TARGET_DEVICES_USB(func) +#endif + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_SATA(func) \ + BOOT_TARGET_DEVICES_USB(func) \ + func(PXE, pxe, na) + +#include <config_distro_bootcmd.h> + +#ifdef CONFIG_USB_KEYBOARD +#define CONSOLE_STDIN_SETTINGS \ + "preboot=usb start\0" \ + "stdin=serial,usbkbd\0" +#else +#define CONSOLE_STDIN_SETTINGS \ + "stdin=serial\0" +#endif + +#ifdef CONFIG_VIDEO +#define CONSOLE_STDOUT_SETTINGS \ + "stdout=serial,vga\0" \ + "stderr=serial,vga\0" +#else +#define CONSOLE_STDOUT_SETTINGS \ + "stdout=serial\0" \ + "stderr=serial\0" +#endif + +#define CONSOLE_ENV_SETTINGS \ + CONSOLE_STDIN_SETTINGS \ + CONSOLE_STDOUT_SETTINGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONSOLE_ENV_SETTINGS \ + MEM_LAYOUT_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "console=ttyS0,115200\0" \ + BOOTENV +#else /* ifndef CONFIG_SPL_BUILD */ +#define CONFIG_EXTRA_ENV_SETTINGS +#endif + #endif /* _MV_COMMON_H */ -- 2.5.0

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[U-Boot] [PATCH 0/4] ARM: sheevaplug: misc fixes
by Peter Korsgaard 24 Mar '16

24 Mar '16

Hi, The following patch series fixes a number of issues I noticed while updating a sheevaplug from 2013.10 to 2016.01: Peter Korsgaard (4): ARM: sheevaplug: unbreak default environment ARM: sheevaplug: unbreak kernel bootargs / mtdparts command by dropping double mtdparts= ARM: sheevaplug: drop unneded 'usb start' from boot command ARM: sheevaplug: correct nand partition layout -- Bye, Peter Korsgaard

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[U-Boot] [T1040] Boot location and NOR flash memory mapping
by Valentin Longchamp 24 Mar '16

24 Mar '16

Hello, We are currently designing a board based on the T1040 CPU from Freescale/NXP. I am preparing its u-boot support and bring-up tools (JTAG) as well as contributing to the hardware design. We base our work (both HW and SW) on the 1040RDB dev board as our reference design. We want to use a parallel ("classical", not SPI) NOR Flash to boot from and to store our RCW/PBL and u-boot. I have a question regarding the Boot location address when booting from the NOR flash. From the documentation, it is clear that the RCW and PBL instructions are read from the NOR (when cfg_rcw_src and RCW[PBI_SRC] are defined accordingly) through CS0 at from the address 0x0000_0000 (RM 27.5.1, PBL Starting addresses). I have not found a clear indication about this in the doc, but I guess that the PBL manages to minimally configure the IFC NOR controller to make sure the addresses it accesses trigger the CS0 and drives the address lines to access address 0 and counting up. My understanding is that we must thus make sure that the NOR Flash's CS is connected to the CS0. For the actual boot location (i.e. when the cores start to execute code, after the RCW/PBL sequence), as stated in section 4.3.3 in the RM (Boot Space Translation), the cores execute the code that is located in the 4K page located at address 0x0_FFFF_F000, starting with the reset vector at address 0x0_FFFF_FFFC, which are located in the default boot location (0x0_FF80_0000 to 0x0_FFFF_FFFF). My conclusion is that somehow, the IFC NOR controller is again configured so that the accesses to this memory range will trigger the CS0 NOR access (in the T1040RDB RCW/PBL, I have seen no indication that another boot window than the default one is use, since the boot space translation capability is unused). But since the NOR boot section (24.6.1) does not give any details, I have no idea how this works. Now u-boot, for its T1040RDB support, uses a memory mapping for the NOR Flash that is not aligned with the above boot location mapping. The 128 MB of the NOR flash are mapped from 0xE800_0000 to 0xEFFF_FFFF. My guess about this "change" it that it is to avoid the memory conflict with CCSR that is located at 0x0_FE00_0000 by default when the NOR is bigger than 16 MB. I think this mapping is only relevant later in the u-boot boot sequence, when the TLBs and LAWs are configured but not at boot time. I have two questions about this NOR boot mechanism: - how are the NOR accesses really happening (or how is the IFC NOR configured) at boot time to read the RCW/PBL and the boot code at boot location ? I ask this in order to make sure that our HW design will allow us to boot from the NOR Flash (i.e. how we connect the NOR address bus to the IFC) - what about CONFIG_SYS_TEXT_BASE ? I see that it defined according the later "u-boot" memory mapping. Why this one and not the "boot time" one ? Thanks your answers Valentin

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