March 2016 - U-Boot

[U-Boot] [PATCH] imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask
by Peng Fan 25 Mar '16

25 Mar '16

From: Ye Li <ye.li(a)nxp.com> Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register the bit[17] for mmdc_ch0 is reserved and its proper state should be 1. When clear this bit, the periph_clk_sel cannot be set and that CDHIPR[periph_clk_sel_busy] handshake never clears. Signed-off-by: Ye Li <ye.li(a)nxp.com> Signed-off-by: Peng Fan <van.freenix(a)gmail.com> --- arch/arm/cpu/armv7/mx6/soc.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 91a3deb..bdd41b0 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -278,7 +278,10 @@ static void clear_mmdc_ch_mask(void) reg = readl(&mxc_ccm->ccdr); /* Clear MMDC channel mask */ - reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); + if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6SL)) + reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK); + else + reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); writel(reg, &mxc_ccm->ccdr); } -- 2.6.2

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[U-Boot] [PATCH v4 0/3] net: phy: Force master mode for RTL8211C on some boards
by Michael Haas 25 Mar '16

25 Mar '16

This patch is required to get reliable 1000BASE-T operation on some boards using the RTL8211C(L) PHY. Following discussions on v2 of this patch, I have removed the incorrect check for the RTL8211C(L). Affected boards now have to define CONFIG_RTL8211X_PHY_FORCE_MASTER to benefit from the fix. Note that this patch requires Karsten Merkers '[PATCH] net: phy: Realtek RTL8211B/C PHY ID fix' as well as Hans de Goede's recent u-boot-sunxi pull request, specifically 1eae8f66ff749409eb96e2f3f3387c56232d0b8a and fc8991c61c393ce6a9d3dfc97cb56dbbd9e8cbba. Michael Changes in v4: - Squashed previously separate commit introducing KCONFIG variable into commit containing main code change (Hans de Goede's suggestion) - Changed KCONFIG description according to Karsten Merker's suggestions plus some clarification of my own - Changed commit message according to Karsten Merker's suggestions - Changed commit summary according to Chen-Yu Tsai's suggestion, modified to fit the 70 character limit - Changed commit summary according to Chen-Yu Tsai's suggestion, modified to fit the 70 character limit Changes in v3: - Remove incorrect detection of RTL8211CL and use #ifdef instead (thanks to Karsten Merker) - Introduced constants for register bits Changes in v2: - Removed accidental inclusion of Karsten's patch in my first submission of this series. - Fix a typo in the code: 6 -> & Michael Haas (3): net: phy: Optionally force master mode for RTL PHY sunxi: A20-Olimex-SOM-EVB: Force 8211CL to master sunxi: A20-OLinuXino-Lime2: Force 8211CL to master configs/A20-OLinuXino-Lime2_defconfig | 1 + configs/A20-Olimex-SOM-EVB_defconfig | 1 + drivers/net/Kconfig | 21 +++++++++++++++++++++ drivers/net/phy/realtek.c | 13 ++++++++++++- 4 files changed, 35 insertions(+), 1 deletion(-) -- 2.7.2

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Re: [U-Boot] [PATCH 1/2] sunxi: Add conditional magic sram poke for A33
by Ian Campbell 25 Mar '16

25 Mar '16

On Fri, 2016-03-25 at 01:10 +0100, Karsten Merker wrote: > > - if ((version & 0xffff0000) == 0x16500000) > > + /* > > + * Ideally this would be a switch case, bit we do not know exactly > > s/bit/but/ Other than that, both patches: Acked-by: Ian Campbell < ijc(a)hellion.org.uk > Ian.

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[U-Boot] [PATCH] driver: net: ldpaa_eth: return number of buffer seeded
by Prabhakar Kushwaha 25 Mar '16

25 Mar '16

if buffer < 7, return number of buffer seeded to QBMAN. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> Reported-by: Jose Rivera <german.rivera(a)nxp.com> --- drivers/net/ldpaa_eth/ldpaa_eth.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c index 8a00bc3..274bcea 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.c +++ b/drivers/net/ldpaa_eth/ldpaa_eth.c @@ -665,7 +665,7 @@ err_alloc: if (i) goto release_bufs; - return 0; + return i; } static int ldpaa_dpbp_seed(uint16_t bpid) -- 1.9.1

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[U-Boot] [PATCH 1/5] ARM: bcm2835: move CONFIG_BCM283* to Kconfig
by Stephen Warren 25 Mar '16

25 Mar '16

Signed-off-by: Stephen Warren <swarren(a)wwwdotorg.org> --- This series depends on: * My series beginning with "ARM: bcm283x: don't always define CONFIG_BCM2835" * My patch "serial: add BCM283x mini UART driver". * Alexander Graf's arm64 page table/cache series starting with "arm64: Add 32bit arm compatible dcache definitions". --- arch/arm/mach-bcm283x/Kconfig | 12 +++++++++++- include/configs/rpi.h | 1 - include/configs/rpi_2.h | 1 - 3 files changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig index 1a7baf69e590..dc6770437ec6 100644 --- a/arch/arm/mach-bcm283x/Kconfig +++ b/arch/arm/mach-bcm283x/Kconfig @@ -1,3 +1,11 @@ +config BCM2835 + bool "Broadcom BCM2835 SoC support" + depends on ARCH_BCM283X + +config BCM2836 + bool "Broadcom BCM2836 SoC support" + depends on ARCH_BCM283X + menu "Broadcom BCM283X family" depends on ARCH_BCM283X @@ -7,12 +15,14 @@ choice config TARGET_RPI bool "Raspberry Pi" + select BCM2835 select CPU_ARM1176 config TARGET_RPI_2 bool "Raspberry Pi 2" - select CPU_V7 select ARMV7_LPAE + select BCM2836 + select CPU_V7 endchoice diff --git a/include/configs/rpi.h b/include/configs/rpi.h index a788ce42e44c..86422e390da2 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -7,7 +7,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_BCM2835 #define CONFIG_SYS_CACHELINE_SIZE 32 #include "rpi-common.h" diff --git a/include/configs/rpi_2.h b/include/configs/rpi_2.h index 13dc8de14315..0917e8650864 100644 --- a/include/configs/rpi_2.h +++ b/include/configs/rpi_2.h @@ -8,7 +8,6 @@ #define __CONFIG_H #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_BCM2836 #define CONFIG_SYS_CACHELINE_SIZE 64 #include "rpi-common.h" -- 2.7.3

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[U-Boot] [PATCH 1/2] sunxi: Add conditional magic sram poke for A33
by Hans de Goede 24 Mar '16

24 Mar '16

I noticed that for certain SoC versions boot0 does a magic poke when build for A33. I'm not aware of this actually being necessary anywhere, but better safe then sorry. Signed-off-by: Hans de Goede <hdegoede(a)redhat.com> --- arch/arm/cpu/armv7/sunxi/board.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 7653148..73c8727 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -120,18 +120,30 @@ void s_init(void) */ #if defined CONFIG_MACH_SUN6I setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800); -#elif defined CONFIG_MACH_SUN8I_A23 - uint version; +#elif defined CONFIG_MACH_SUN8I + __maybe_unused uint version; /* Unlock sram version info reg, read it, relock */ setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15)); - version = readl(SUNXI_SRAMC_BASE + 0x24); + version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16; clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15)); - if ((version & 0xffff0000) == 0x16500000) + /* + * Ideally this would be a switch case, bit we do not know exactly + * which versions there are and which version needs which settings, + * so reproduce the per SoC code from the BSP. + */ +#if defined CONFIG_MACH_SUN8I_A23 + if (version == 0x1650) setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800); else /* 0x1661 ? */ setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0); +#elif defined CONFIG_MACH_SUN8I_A33 + if (version != 0x1667) + setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0); +#endif + /* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */ + /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */ #endif #if defined CONFIG_MACH_SUN6I || \ -- 2.7.3

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[U-Boot] Need help debugging problem with u-boot cache_v7.c when build with gcc6
by Hans de Goede 24 Mar '16

24 Mar '16

Hi All, For details see: https://bugzilla.redhat.com/show_bug.cgi?id=1318788 We could really use a hand from someone who knows the cache code flushing code well and can check if the generated assembly works as intended. The preferred method of communication for this is through bugzilla. Thanks & Regards, Hans

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[U-Boot] [PATCH v2] arm: socfpga: migration of CONFIG_SPI_FLASH_BAR
by Denis Bakhvalov 24 Mar '16

24 Mar '16

CONFIG_SPI_FLASH_BAR was deleted from socfpga_common.h and placed in socfpga_*_defconfig where it makes sense. Signed-off-by: Denis Bakhvalov <dendibakh(a)gmail.com> Reported-by: Denis Bakhvalov <dendibakh(a)gmail.com> Cc: Marek Vasut <marex(a)denx.de> Acked-by: Marek Vasut <marex(a)denx.de> --- Changes for v2: - Diff was generated from u-boot-socfpga configs/socfpga_arria5_defconfig | 1 + configs/socfpga_cyclone5_defconfig | 1 + configs/socfpga_de0_nano_soc_defconfig | 1 + configs/socfpga_mcvevk_defconfig | 1 + configs/socfpga_sockit_defconfig | 1 + configs/socfpga_socrates_defconfig | 1 + configs/socfpga_sr1500_defconfig | 1 + include/configs/socfpga_common.h | 2 -- 8 files changed, 7 insertions(+), 2 deletions(-) diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index 7b60d95..505a68d 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -19,6 +19,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_BAR=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 6a487f4..df19a95 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -19,6 +19,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_BAR=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index cfcae5d..bb37825 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -19,5 +19,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y +CONFIG_SPI_FLASH_BAR=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index b6f6a65..8a76aa1 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -19,5 +19,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y +CONFIG_SPI_FLASH_BAR=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index f45c3ed..36bb1e1 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -19,6 +19,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_BAR=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index e25d09b..937f14f 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -23,5 +23,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y +CONFIG_SPI_FLASH_BAR=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index d499a14..83eada3 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -17,6 +17,7 @@ CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_BAR=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 56d32e6..2ad0287 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -93,7 +93,6 @@ #define CONFIG_CMD_SPI #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_BAR /* * The base address is configurable in QSys, each board must specify the * base address based on it's particular FPGA configuration. Please note @@ -219,7 +218,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #endif #define CONFIG_CQSPI_DECODER 0 #define CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_BAR /* * Designware SPI support -- 1.9.1

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[U-Boot] [PATCH 0/3] ARM: DRA7: Fix fastboot command
by Semen Protsenko 24 Mar '16

24 Mar '16

Hi All, This series reverts recently added patches that break fastboot command. I propose to keep it this way until issue is found and fixed. When I'm trying to run fastboot command, next error occurs: => fas 0 data abort pc : [<dff7825e>] lr : [<00000020>] reloc pc : [<8081f25e>] lr : [<a08a7020>] ... Resetting CPU ... My board information: CPU : DRA752 ES1.0 Board: DRA74x EVM REV E.0 I2C: ready DRAM: 1.5 GiB MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1 SCSI: SATA link 0 timeout. AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl SATA mode

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[U-Boot] [RFC PATCH] ARM: asm: types: Introduce DMA_ADDR_T_64BIT
by Lokesh Vutla 24 Mar '16

24 Mar '16

dma_addr_t holds any valid DMA address. If the DMA API only uses 32-bit addresses, dma_addr_t need only be 32 bits wide. Bus addresses, e.g., PCI BARs, may be wider than 32 bits, but drivers do memory-mapped I/O to ioremapped kernel virtual addresses, so they don't care about the size of the actual bus addresses. Also 32 bit ARM systems with LPAE enabled can use 64bit address space, but DMA still use 32bit address like in case of DRA7 and Keystone platforms. This is inspired from the Linux kernel types implementation[1] [1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/includ… Signed-off-by: Lokesh Vutla <lokeshvutla(a)ti.com> --- arch/arm/include/asm/types.h | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h index 388058e..d108915 100644 --- a/arch/arm/include/asm/types.h +++ b/arch/arm/include/asm/types.h @@ -46,16 +46,29 @@ typedef unsigned long long u64; #endif /* CONFIG_ARM64 */ #ifdef CONFIG_PHYS_64BIT -typedef unsigned long long dma_addr_t; typedef unsigned long long phys_addr_t; typedef unsigned long long phys_size_t; #else /* DMA addresses are 32-bits wide */ -typedef u32 dma_addr_t; typedef unsigned long phys_addr_t; typedef unsigned long phys_size_t; #endif +/* + * A dma_addr_t can hold any valid DMA address, i.e., any address returned + * by the DMA API. + * + * If the DMA API only uses 32-bit addresses, dma_addr_t need only be 32 + * bits wide. Bus addresses, e.g., PCI BARs, may be wider than 32 bits, + * but drivers do memory-mapped I/O to ioremapped kernel virtual addresses, + * so they don't care about the size of the actual bus addresses. + */ +#ifdef CONFIG_DMA_ADDR_T_64BIT +typedef unsigned long long dma_addr_t; +#else +typedef u32 dma_addr_t; +#endif + #endif /* __KERNEL__ */ typedef unsigned long resource_size_t; -- 2.1.4

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