March 2016 - U-Boot

[U-Boot] [PATCH] ARM: uniphier: make u-boot-with-spl.bin really available
by Masahiro Yamada 31 Mar '16

31 Mar '16

Commit d085ecd61b99 ("ARM: uniphier: switch to raw U-Boot image") claimed that u-boot-with-spl.bin would be useful in its commit log, but it was not available because the commit missed to define CONFIG_SPL_MAX_SIZE. Without it, CONFIG_SPL_PAD_TO is not defined either (see include/config_fallbacks.h). So, the SPL image is not padded correctly. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- include/configs/uniphier.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 5f3d6b8..da80c00 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -279,5 +279,6 @@ #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" #define CONFIG_SPL_MAX_FOOTPRINT 0x10000 +#define CONFIG_SPL_MAX_SIZE 0x10000 #endif /* __CONFIG_UNIPHIER_COMMON_H__ */ -- 1.9.1

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[U-Boot] [PATCH] mtd: nand: denali: max_banks calculation changed in revision 5.1
by Masahiro Yamada 31 Mar '16

31 Mar '16

From: Graham Moore <grmoore(a)opensource.altera.com> Read Denali hardware revision number and use it to calculate max_banks, The encoding of max_banks changed in Denali revision 5.1. [ Linux commit : 271707b1d817f5104e02b2bd1bab43f0c8759418 ] Signed-off-by: Graham Moore <grmoore(a)opensource.altera.com> [Brian: parentheses around macro arg] Signed-off-by: Brian Norris <computersforpeace(a)gmail.com> [Masahiro: import from Linux and adjust ioread32() to readl() ] Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- drivers/mtd/nand/denali.c | 11 ++++++++++- drivers/mtd/nand/denali.h | 2 ++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 018d14f..5894fcc 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -431,7 +431,16 @@ static void find_valid_banks(struct denali_nand_info *denali) static void detect_max_banks(struct denali_nand_info *denali) { uint32_t features = readl(denali->flash_reg + FEATURES); - denali->max_banks = 2 << (features & FEATURES__N_BANKS); + /* + * Read the revision register, so we can calculate the max_banks + * properly: the encoding changed from rev 5.0 to 5.1 + */ + u32 revision = MAKE_COMPARABLE_REVISION( + readl(denali->flash_reg + REVISION)); + if (revision < REVISION_5_1) + denali->max_banks = 2 << (features & FEATURES__N_BANKS); + else + denali->max_banks = 1 << (features & FEATURES__N_BANKS); } static void detect_partition_feature(struct denali_nand_info *denali) diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h index 93b5725..db1457a 100644 --- a/drivers/mtd/nand/denali.h +++ b/drivers/mtd/nand/denali.h @@ -166,6 +166,8 @@ #define REVISION 0x370 #define REVISION__VALUE 0xffff +#define MAKE_COMPARABLE_REVISION(x) swab16((x) & REVISION__VALUE) +#define REVISION_5_1 0x00000501 #define ONFI_DEVICE_FEATURES 0x380 #define ONFI_DEVICE_FEATURES__VALUE 0x003f -- 1.9.1

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[U-Boot] [PATCH V4 1/3] arm: discard relocation entries for secure text
by Peng Fan 31 Mar '16

31 Mar '16

The code such as PSCI in section named secure is bundled with u-boot image, and when bootm, the code will be copied to their runtime address same to compliation/linking address - CONFIG_ARMV7_SECURE_BASE. When compile the PSCI code and link it into the u-boot image, there will be relocation entries in .rel.dyn section for PSCI. Actually, we do not needs these relocation entries. If still keep the relocation entries in .rel.dyn section, r0 at line 103 and 106 in arch/arm/lib/relocate.S may be an invalid address which may not support read/write for one SoC. 102 /* relative fix: increase location by offset */ 103 add r0, r0, r4 104 ldr r1, [r0] 105 add r1, r1, r4 106 str r1, [r0] So discard them to avoid touching the relocation entry in arch/arm/lib/relocate.S. Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> Cc: Tom Warren <twarren(a)nvidia.com> Cc: York Sun <yorksun(a)freescale.com> Cc: Hans De Goede <hdegoede(a)redhat.com> Cc: Ian Campbell <ijc(a)hellion.org.uk> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> Cc: Tom Rini <trini(a)konsulko.com> Cc: Jan Kiszka <jan.kiszka(a)siemens.com> Cc: Stefano Babic <sbabic(a)denx.de> --- Changes v4: none V2 thread: http://lists.denx.de/pipermail/u-boot/2015-October/230755.html Changes v3: Move the relocation entries to the very begining and discard them. V1 thread: http://lists.denx.de/pipermail/u-boot/2015-October/229426.html Changes V2: Refine commit msg. Discard the relocation entry section for secure text. arch/arm/cpu/u-boot.lds | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 03cd9f6..d48a905 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -14,6 +14,23 @@ OUTPUT_ARCH(arm) ENTRY(_start) SECTIONS { + /* + * Discard the relocation entries for secure text. + * The secure code is bundled with u-boot image, so there will + * be relocations entries for the secure code, since we use + * "-mword-relocations" to compile and "-pie" to link into the + * final image. We do not need the relocation entries for secure + * code, because secure code will not be relocated, it only needs + * to be copied from loading address to CONFIG_ARMV7_SECURE_BASE, + * which is the linking and running address for secure code. + * If keep the relocation entries in .rel.dyn section, + * "relocation offset + linking address" may locates into an + * address that is reserved by SoC, then will trigger data abort. + * + * The reason that move .rel._secure at the beginning, is to + * avoid hole in the final image. + */ + /DISCARD/ : { *(.rel._secure*) } . = 0x00000000; . = ALIGN(4); -- 1.8.4

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[U-Boot] [PATCH] spi: Support 4 byte address only SPI flash
by Tim Chick 31 Mar '16

31 Mar '16

Add support to use 4 byte addresses for SPI flash, configured with SPI_FLASH_USE_4B_ADDR. The Macronix MX25L25735F only supports 4 byte addresses, but has the same ID as the MX25L25635E, which supports 3 and 4 byte address modes. When using the MX25L25735F, flash reads and writes were corrupted with no notification to the user. When in 4 byte mode, SPI_FLASH_BAR is not required. CONFIG_SPI_FLASH_USE_4B_ADDR - use 4 byte addresses for all SPI flash data read, write and erase operations. CONFIG_SPI_FLASH_LARGE_NONE - dummy option if SPI_FLASH_BAR and SPI_FLASH_USE_4B_ADDR are not selected Signed-off-by: Tim Chick <tim.chick(a)mediatek.com> --- drivers/mtd/spi/Kconfig | 34 ++++++++++++++++++++++++++++++++++ drivers/mtd/spi/sf_internal.h | 5 +++++ drivers/mtd/spi/spi_flash.c | 11 +++++++++-- 3 files changed, 48 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index 3f7433c..70d73d47 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -34,6 +34,24 @@ config SPI_FLASH If unsure, say N +choice + prompt "Large SPI flash support" + default SPI_FLASH_LARGE_NONE + help + Large SPI flash support + + Choose scheme to use SPI flash chip larger than 16MBytes. + SPI flash normally uses 3 bytes of addressing, limit the + directly addressable flash size to 16MBytes. +config SPI_FLASH_LARGE_NONE + bool "None" + depends on SPI_FLASH + help + For SPI flash chips 16MByte or smaller + + This is a dummy option, and no special method is used to + address large flash chips. Only the bottom 16MByte of + any flash chip will be addressable. config SPI_FLASH_BAR bool "SPI flash Bank/Extended address register support" depends on SPI_FLASH @@ -42,6 +60,22 @@ config SPI_FLASH_BAR Bank/Extended address registers are used to access the flash which has size > 16MiB in 3-byte addressing. +config SPI_FLASH_USE_4B_ADDR + bool "Use 4 byte flash address instead of 3 bytes" + depends on SPI_FLASH + help + Some SPI flash chips only support 4 byte addresses. Always use + 4-byte addresses. SPI_FLASH_BAR should be turned off, as 4 byte + address allows 4GB of flash space. + + Selecting this option for a flash chip which is not 4 byte address + only will cause flash reads and writes to be corrupted. Most flash + chips support 3 byte mode. + + If unsure, say N + +endchoice + if SPI_FLASH config SPI_FLASH_ATMEL diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 007a5a0..4d05a7b 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -54,7 +54,12 @@ enum spi_nor_option_flags { }; #define SPI_FLASH_3B_ADDR_LEN 3 +#define SPI_FLASH_4B_ADDR_LEN 4 +#ifdef CONFIG_SPI_FLASH_USE_4B_ADDR +#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_4B_ADDR_LEN) +#else #define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN) +#endif #define SPI_FLASH_16MB_BOUN 0x1000000 /* CFI Manufacture ID's */ diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 44d9e9b..10594cc 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -25,9 +25,16 @@ DECLARE_GLOBAL_DATA_PTR; static void spi_flash_addr(u32 addr, u8 *cmd) { /* cmd[0] is actual command */ +#ifdef CONFIG_SPI_FLASH_USE_4B_ADDR + cmd[1] = addr >> 24; + cmd[2] = addr >> 16; + cmd[3] = addr >> 8; + cmd[4] = addr >> 0; +#else cmd[1] = addr >> 16; cmd[2] = addr >> 8; cmd[3] = addr >> 0; +#endif } static int read_sr(struct spi_flash *flash, u8 *rs) @@ -1180,13 +1187,13 @@ int spi_flash_scan(struct spi_flash *flash) puts("\n"); #endif -#ifndef CONFIG_SPI_FLASH_BAR +#if !(defined CONFIG_SPI_FLASH_BAR) && !(defined CONFIG_SPI_FLASH_USE_4B_ADDR) if (((flash->dual_flash == SF_SINGLE_FLASH) && (flash->size > SPI_FLASH_16MB_BOUN)) || ((flash->dual_flash > SF_SINGLE_FLASH) && (flash->size > SPI_FLASH_16MB_BOUN << 1))) { puts("SF: Warning - Only lower 16MiB accessible,"); - puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); + puts(" Full access #define CONFIG_SPI_FLASH_BAR or CONFIG_SPI_FLASH_USE_4B_ADDR\n"); } #endif -- 2.1.4

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[U-Boot] [PATCH v5 0/3] net: phy: Force master mode for RTL8211C on some boards
by Michael Haas 31 Mar '16

31 Mar '16

This patch is required to get reliable 1000BASE-T operation on some boards using the RTL8211C(L) PHY. Following discussions on v2 of this patch, I have removed the incorrect check for the RTL8211C(L). Affected boards now have to define CONFIG_RTL8211X_PHY_FORCE_MASTER to benefit from the fix. Note that this patch requires Karsten Merkers '[PATCH] net: phy: Realtek RTL8211B/C PHY ID fix' as well as Hans de Goede's recent u-boot-sunxi pull request, specifically 1eae8f66ff749409eb96e2f3f3387c56232d0b8a and fc8991c61c393ce6a9d3dfc97cb56dbbd9e8cbba. Michael Changes in v5: - Improve formatting of Kconfig help text. No content change. Change suggested by Karsten Merker. - Fix order of defconfig entry (suggested by Karsten Marker) Series-changes: 4 - Changed commit summary according to Chen-Yu Tsai's suggestion, modified to fit the 70 character limit - Fix order of defconfig entry (suggested by Karsten Marker) Changes in v4: - Squashed previously separate commit introducing KCONFIG variable into commit containing main code change (Hans de Goede's suggestion) - Changed KCONFIG description according to Karsten Merker's suggestions plus some clarification of my own - Changed commit message according to Karsten Merker's suggestions - Changed commit summary according to Chen-Yu Tsai's suggestion, modified to fit the 70 character limit Changes in v3: - Remove incorrect detection of RTL8211CL and use #ifdef instead (thanks to Karsten Merker) - Introduced constants for register bits Changes in v2: - Removed accidental inclusion of Karsten's patch in my first submission of this series. - Fix a typo in the code: 6 -> & Michael Haas (3): net: phy: Optionally force master mode for RTL PHY sunxi: A20-Olimex-SOM-EVB: Force 8211CL to master sunxi: A20-OLinuXino-Lime2: Force 8211CL to master configs/A20-OLinuXino-Lime2_defconfig | 1 + configs/A20-Olimex-SOM-EVB_defconfig | 1 + drivers/net/Kconfig | 21 +++++++++++++++++++++ drivers/net/phy/realtek.c | 13 ++++++++++++- 4 files changed, 35 insertions(+), 1 deletion(-) -- 2.7.2

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[U-Boot] [PATCH] ARM64: zynqmp: Enable EFI partition support
by Michal Simek 31 Mar '16

31 Mar '16

Enable EFI partition support for ZynqMP. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- include/configs/xilinx_zynqmp.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 8c760967f6d6..8cea61080d49 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -71,6 +71,7 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_FS_GENERIC #define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION #define CONFIG_MP #define CONFIG_CMD_MII -- 1.9.1

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[U-Boot] [PATCH 1/2] ARM: zynq: Enable FLASH_BAR for microzed and zybo
by Michal Simek 31 Mar '16

31 Mar '16

Enable FLASH_BAR for these targets to be in sync with all zynq boards. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- configs/zynq_microzed_defconfig | 1 + configs/zynq_zybo_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index 4c5152fa73e7..1d70e43df0c8 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -15,6 +15,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ZYNQ_SDHCI=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index 470c9cbb1252..ee7e23b36fca 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -15,6 +15,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ZYNQ_SDHCI=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_ZYNQ_GEM=y CONFIG_DEBUG_UART=y -- 1.9.1

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[U-Boot] [PATCH 1/6] ARM64: zynqmp: Decrease boot delay
by Michal Simek 31 Mar '16

31 Mar '16

From: Soren Brinkmann <soren.brinkmann(a)xilinx.com> Synchronize it with zynq platform. Signed-off-by: Soren Brinkmann <soren.brinkmann(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- include/configs/xilinx_zynqmp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 4e066cdfd233..b60239614fad 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -168,7 +168,7 @@ #define CONFIG_PREBOOT "run bootargs" #define CONFIG_BOOTCOMMAND "run $modeboot" -#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOTDELAY 3 #define CONFIG_BOARD_LATE_INIT -- 1.9.1

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[U-Boot] [PATCH 1/2] microblaze: Read information about timer/interrupts from DT
by Michal Simek 31 Mar '16

31 Mar '16

Read information about timer and interrupts from DT. This is the first small step to move timer and intc to DM. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/microblaze/cpu/interrupts.c | 25 +++++++++++++++++++++++++ arch/microblaze/cpu/timer.c | 39 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 63 insertions(+), 1 deletion(-) diff --git a/arch/microblaze/cpu/interrupts.c b/arch/microblaze/cpu/interrupts.c index b6d6610f2fd7..e5d8894f5447 100644 --- a/arch/microblaze/cpu/interrupts.c +++ b/arch/microblaze/cpu/interrupts.c @@ -10,10 +10,13 @@ #include <common.h> #include <command.h> +#include <fdtdec.h> #include <malloc.h> #include <asm/microblaze_intc.h> #include <asm/asm.h> +DECLARE_GLOBAL_DATA_PTR; + void enable_interrupts(void) { debug("Enable interrupts for the whole CPU\n"); @@ -113,10 +116,32 @@ int interrupt_init(void) { int i; +#ifdef CONFIG_OF_CONTROL + const void *blob = gd->fdt_blob; + int node = 0; + + debug("INTC: Initialization\n"); + + node = fdt_node_offset_by_compatible(blob, node, + "xlnx,xps-intc-1.00.a"); + if (node != -1) { + fdt_addr_t base = fdtdec_get_addr(blob, node, "reg"); + if (base == FDT_ADDR_T_NONE) + return -1; + + debug("INTC: Base addr %lx\n", base); + intc = (microblaze_intc_t *)base; + irq_no = fdtdec_get_int(blob, node, "xlnx,num-intr-inputs", 0); + debug("INTC: IRQ NO %x\n", irq_no); + } else { + return node; + } +#else #if defined(CONFIG_SYS_INTC_0_ADDR) && defined(CONFIG_SYS_INTC_0_NUM) intc = (microblaze_intc_t *)CONFIG_SYS_INTC_0_ADDR; irq_no = CONFIG_SYS_INTC_0_NUM; #endif +#endif if (irq_no) { vecs = calloc(1, sizeof(struct irq_action) * irq_no); if (vecs == NULL) { diff --git a/arch/microblaze/cpu/timer.c b/arch/microblaze/cpu/timer.c index 3960bbb08a84..c0fc7c0f3ca1 100644 --- a/arch/microblaze/cpu/timer.c +++ b/arch/microblaze/cpu/timer.c @@ -7,9 +7,12 @@ */ #include <common.h> +#include <fdtdec.h> #include <asm/microblaze_timer.h> #include <asm/microblaze_intc.h> +DECLARE_GLOBAL_DATA_PTR; + volatile int timestamp = 0; microblaze_timer_t *tmr; @@ -29,8 +32,10 @@ void __udelay(unsigned long usec) while ((get_timer(0) - i) < (usec / 1000)) ; } else { +#ifndef CONFIG_OF_CONTROL for (i = 0; i < (usec * XILINX_CLOCK_FREQ / 10000000); i++) ; +#endif } } @@ -47,12 +52,44 @@ int timer_init (void) u32 preload = 0; u32 ret = 0; +#ifdef CONFIG_OF_CONTROL + const void *blob = gd->fdt_blob; + int node = 0; + u32 cell[2]; + + debug("TIMER: Initialization\n"); + + node = fdt_node_offset_by_compatible(blob, node, + "xlnx,xps-timer-1.00.a"); + if (node != -1) { + fdt_addr_t base = fdtdec_get_addr(blob, node, "reg"); + if (base == FDT_ADDR_T_NONE) + return -1; + + debug("TIMER: Base addr %lx\n", base); + tmr = (microblaze_timer_t *)base; + + ret = fdtdec_get_int_array(blob, node, "interrupts", + cell, ARRAY_SIZE(cell)); + if (ret) + return ret; + + irq = cell[0]; + debug("TIMER: IRQ %x\n", irq); + + preload = fdtdec_get_int(blob, node, "clock-frequency", 0); + preload /= CONFIG_SYS_HZ; + } else { + return node; + } + +#else #if defined(CONFIG_SYS_TIMER_0_ADDR) && defined(CONFIG_SYS_INTC_0_NUM) preload = XILINX_CLOCK_FREQ / CONFIG_SYS_HZ; irq = CONFIG_SYS_TIMER_0_IRQ; tmr = (microblaze_timer_t *) (CONFIG_SYS_TIMER_0_ADDR); #endif - +#endif if (tmr && preload && irq >= 0) { tmr->loadreg = preload; tmr->control = TIMER_INTERRUPT | TIMER_RESET; -- 1.9.1

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[U-Boot] [PATCH] ARM: zynq: Fix default ps7_init_gpl.c/h for ZYBO
by Michal Simek 31 Mar '16

31 Mar '16

From: Michal Simek <monstr(a)monstr.eu> There is incorrect setting for USB which didn't work with origin ps7_init_gpl.X files. Use default setting for Digilent Zybo projects with HDMI in PL. Signed-off-by: Michal Simek <monstr(a)monstr.eu> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c | 1581 +++++++++++++++++---- board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h | 9 +- 2 files changed, 1344 insertions(+), 246 deletions(-) diff --git a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c index 2c0fecac43f3..83daf7bf15b8 100644 --- a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c +++ b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c @@ -310,11 +310,11 @@ unsigned long ps7_clock_init_data_3_0[] = { /* .. SRCSEL = 0x0 */ /* .. ==> 0XF8000154[5:4] = 0x00000000U */ /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. DIVISOR = 0x14 */ - /* .. ==> 0XF8000154[13:8] = 0x00000014U */ - /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ + /* .. DIVISOR = 0xa */ + /* .. ==> 0XF8000154[13:8] = 0x0000000AU */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ /* .. */ - EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001402U), + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U), /* .. .. START: TRACE CLOCK */ /* .. .. FINISH: TRACE CLOCK */ /* .. .. CLKACT = 0x1 */ @@ -339,39 +339,39 @@ unsigned long ps7_clock_init_data_3_0[] = { /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ /* .. .. */ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U), - /* .. .. SRCSEL = 0x3 */ - /* .. .. ==> 0XF8000180[5:4] = 0x00000003U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000030U */ - /* .. .. DIVISOR0 = 0x6 */ - /* .. .. ==> 0XF8000180[13:8] = 0x00000006U */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U */ + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0x7 */ + /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */ /* .. .. DIVISOR1 = 0x1 */ /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ /* .. .. */ - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100630U), - /* .. .. SRCSEL = 0x2 */ - /* .. .. ==> 0XF8000190[5:4] = 0x00000002U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000020U */ - /* .. .. DIVISOR0 = 0x35 */ - /* .. .. ==> 0XF8000190[13:8] = 0x00000035U */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00003500U */ - /* .. .. DIVISOR1 = 0x2 */ - /* .. .. ==> 0XF8000190[25:20] = 0x00000002U */ - /* .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00203520U), + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0x5 */ + /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U), /* .. .. SRCSEL = 0x0 */ /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. .. DIVISOR0 = 0xa */ - /* .. .. ==> 0XF80001A0[13:8] = 0x0000000AU */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ + /* .. .. DIVISOR0 = 0x14 */ + /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ /* .. .. DIVISOR1 = 0x1 */ /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ /* .. .. */ - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00100A00U), + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U), /* .. .. CLK_621_TRUE = 0x1 */ /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ @@ -667,9 +667,9 @@ unsigned long ps7_ddr_init_data_3_0[] = { /* .. .. reg_ddrc_burst_rdwr = 0x4 */ /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */ - /* .. .. reg_ddrc_pre_cke_x1024 = 0x101 */ - /* .. .. ==> 0XF8006034[13:4] = 0x00000101U */ - /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U */ + /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */ + /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */ + /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */ /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */ /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */ /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */ @@ -677,7 +677,7 @@ unsigned long ps7_ddr_init_data_3_0[] = { /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */ /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */ /* .. .. */ - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011014U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U), /* .. .. reg_ddrc_force_low_pri_n = 0x0 */ /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ @@ -2020,6 +2020,35 @@ unsigned long ps7_mio_init_data_3_0[] = { /* .. FINISH: DDRIOB SETTINGS */ /* .. START: MIO PROGRAMMING */ /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000700[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000700[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000700[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000700[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000700[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000700[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000700[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000700[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000700[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ /* .. ==> 0XF8000704[0:0] = 0x00000000U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ /* .. L0_SEL = 1 */ @@ -2194,6 +2223,267 @@ unsigned long ps7_mio_init_data_3_0[] = { /* .. */ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800071C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800071C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800071C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800071C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800071C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800071C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800071C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800071C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800071C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000720[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000720[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000720[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000720[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000720[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000720[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000720[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000720[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000720[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000724[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000724[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000724[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000724[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000724[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000724[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000724[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000724[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000724[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000728[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000728[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000728[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000728[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000728[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000728[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000728[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000728[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000728[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800072C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800072C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800072C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800072C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800072C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800072C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800072C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF800072C[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800072C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000730[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000730[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000730[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000730[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000730[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000730[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000730[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000730[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000730[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000734[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000734[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000734[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000734[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000734[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000734[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000734[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000734[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000734[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000738[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000738[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000738[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000738[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000738[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000738[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000738[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000738[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000738[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800073C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800073C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800073C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800073C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800073C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800073C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800073C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF800073C[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800073C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ /* .. ==> 0XF8000740[0:0] = 0x00000000U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ /* .. L0_SEL = 1 */ @@ -3063,6 +3353,35 @@ unsigned long ps7_mio_init_data_3_0[] = { /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ /* .. */ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007B8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007B8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007B8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007B8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007B8[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007B8[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007B8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF80007B8[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007B8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U), /* .. TRI_ENABLE = 1 */ /* .. ==> 0XF80007BC[0:0] = 0x00000001U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ @@ -3139,6 +3458,64 @@ unsigned long ps7_mio_init_data_3_0[] = { /* .. */ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U), /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007C8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007C8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007C8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007C8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007C8[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007C8[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007C8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007C8[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007C8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007CC[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007CC[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007CC[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007CC[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007CC[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007CC[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007CC[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007CC[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007CC[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U), + /* .. TRI_ENABLE = 0 */ /* .. ==> 0XF80007D0[0:0] = 0x00000000U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ /* .. L0_SEL = 0 */ @@ -3277,11 +3654,11 @@ unsigned long ps7_peripherals_init_data_3_0[] = { /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */ /* .. */ EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), - /* .. CD = 0x3e */ - /* .. ==> 0XE0001018[15:0] = 0x0000003EU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU */ + /* .. CD = 0x7c */ + /* .. ==> 0XE0001018[15:0] = 0x0000007CU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */ /* .. */ - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000003EU), + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU), /* .. STPBRK = 0x0 */ /* .. ==> 0XE0001000[8:8] = 0x00000000U */ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ @@ -3329,29 +3706,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = { /* .. */ EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U), /* .. FINISH: UART REGISTERS */ - /* .. START: TPIU WIDTH IN CASE OF EMIO */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0XC5ACCE55 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. .. START: TRACE CURRENT PORT SIZE */ - /* .. .. a = 2 */ - /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U), - /* .. .. FINISH: TRACE CURRENT PORT SIZE */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0X0 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */ /* .. START: QSPI REGISTERS */ /* .. Holdb_dr = 1 */ /* .. ==> 0XE000D000[19:19] = 0x00000001U */ @@ -3390,24 +3744,50 @@ unsigned long ps7_peripherals_init_data_3_0[] = { /* .. .. .. .. START: DIR MODE BANK 0 */ /* .. .. .. .. FINISH: DIR MODE BANK 0 */ /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. DIRECTION_1 = 0x4000 */ + /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U), /* .. .. .. .. FINISH: DIR MODE BANK 1 */ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x4000 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. OP_ENABLE_1 = 0x4000 */ + /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U), /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x0 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U), /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ @@ -3420,6 +3800,14 @@ unsigned long ps7_peripherals_init_data_3_0[] = { /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x4000 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ @@ -3660,29 +4048,6 @@ unsigned long ps7_post_config_3_0[] = { /* .. */ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), /* .. FINISH: ENABLING LEVEL SHIFTER */ - /* .. START: TPIU WIDTH IN CASE OF EMIO */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0XC5ACCE55 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. .. START: TRACE CURRENT PORT SIZE */ - /* .. .. a = 2 */ - /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U), - /* .. .. FINISH: TRACE CURRENT PORT SIZE */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0X0 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */ /* .. START: FPGA RESETS TO 0 */ /* .. reserved_3 = 0 */ /* .. ==> 0XF8000240[31:25] = 0x00000000U */ @@ -3759,6 +4124,8 @@ unsigned long ps7_post_config_3_0[] = { /* .. .. FINISH: AFI2 REGISTERS */ /* .. .. START: AFI3 REGISTERS */ /* .. .. FINISH: AFI3 REGISTERS */ + /* .. .. START: AFI2 SECURE REGISTER */ + /* .. .. FINISH: AFI2 SECURE REGISTER */ /* .. FINISH: AFI REGISTERS */ /* .. START: LOCK IT BACK */ /* .. LOCK_KEY = 0X767B */ @@ -4110,11 +4477,11 @@ unsigned long ps7_clock_init_data_2_0[] = { /* .. SRCSEL = 0x0 */ /* .. ==> 0XF8000154[5:4] = 0x00000000U */ /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. DIVISOR = 0x14 */ - /* .. ==> 0XF8000154[13:8] = 0x00000014U */ - /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ + /* .. DIVISOR = 0xa */ + /* .. ==> 0XF8000154[13:8] = 0x0000000AU */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ /* .. */ - EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001402U), + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U), /* .. .. START: TRACE CLOCK */ /* .. .. FINISH: TRACE CLOCK */ /* .. .. CLKACT = 0x1 */ @@ -4139,39 +4506,39 @@ unsigned long ps7_clock_init_data_2_0[] = { /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ /* .. .. */ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U), - /* .. .. SRCSEL = 0x3 */ - /* .. .. ==> 0XF8000180[5:4] = 0x00000003U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000030U */ - /* .. .. DIVISOR0 = 0x6 */ - /* .. .. ==> 0XF8000180[13:8] = 0x00000006U */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U */ + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0x7 */ + /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */ /* .. .. DIVISOR1 = 0x1 */ /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ /* .. .. */ - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100630U), - /* .. .. SRCSEL = 0x2 */ - /* .. .. ==> 0XF8000190[5:4] = 0x00000002U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000020U */ - /* .. .. DIVISOR0 = 0x35 */ - /* .. .. ==> 0XF8000190[13:8] = 0x00000035U */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00003500U */ - /* .. .. DIVISOR1 = 0x2 */ - /* .. .. ==> 0XF8000190[25:20] = 0x00000002U */ - /* .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00203520U), + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0x5 */ + /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U), /* .. .. SRCSEL = 0x0 */ /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. .. DIVISOR0 = 0xa */ - /* .. .. ==> 0XF80001A0[13:8] = 0x0000000AU */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ + /* .. .. DIVISOR0 = 0x14 */ + /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ /* .. .. DIVISOR1 = 0x1 */ /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ /* .. .. */ - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00100A00U), + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U), /* .. .. CLK_621_TRUE = 0x1 */ /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ @@ -4491,9 +4858,9 @@ unsigned long ps7_ddr_init_data_2_0[] = { /* .. .. reg_ddrc_burst_rdwr = 0x4 */ /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */ - /* .. .. reg_ddrc_pre_cke_x1024 = 0x101 */ - /* .. .. ==> 0XF8006034[13:4] = 0x00000101U */ - /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U */ + /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */ + /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */ + /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */ /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */ /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */ /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */ @@ -4501,7 +4868,7 @@ unsigned long ps7_ddr_init_data_2_0[] = { /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */ /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */ /* .. .. */ - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011014U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U), /* .. .. reg_ddrc_force_low_pri_n = 0x0 */ /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ @@ -5981,6 +6348,35 @@ unsigned long ps7_mio_init_data_2_0[] = { /* .. FINISH: DDRIOB SETTINGS */ /* .. START: MIO PROGRAMMING */ /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000700[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000700[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000700[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000700[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000700[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000700[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000700[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000700[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000700[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ /* .. ==> 0XF8000704[0:0] = 0x00000000U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ /* .. L0_SEL = 1 */ @@ -6155,6 +6551,267 @@ unsigned long ps7_mio_init_data_2_0[] = { /* .. */ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800071C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800071C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800071C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800071C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800071C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800071C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800071C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800071C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800071C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000720[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000720[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000720[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000720[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000720[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000720[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000720[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000720[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000720[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000724[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000724[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000724[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000724[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000724[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000724[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000724[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000724[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000724[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000728[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000728[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000728[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000728[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000728[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000728[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000728[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000728[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000728[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800072C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800072C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800072C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800072C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800072C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800072C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800072C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF800072C[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800072C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000730[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000730[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000730[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000730[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000730[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000730[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000730[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000730[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000730[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000734[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000734[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000734[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000734[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000734[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000734[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000734[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000734[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000734[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000738[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000738[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000738[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000738[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000738[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000738[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000738[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000738[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000738[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800073C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800073C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800073C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800073C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800073C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800073C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800073C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF800073C[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800073C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ /* .. ==> 0XF8000740[0:0] = 0x00000000U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ /* .. L0_SEL = 1 */ @@ -7024,6 +7681,35 @@ unsigned long ps7_mio_init_data_2_0[] = { /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ /* .. */ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007B8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007B8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007B8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007B8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007B8[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007B8[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007B8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF80007B8[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007B8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U), /* .. TRI_ENABLE = 1 */ /* .. ==> 0XF80007BC[0:0] = 0x00000001U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ @@ -7100,6 +7786,64 @@ unsigned long ps7_mio_init_data_2_0[] = { /* .. */ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U), /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007C8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007C8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007C8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007C8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007C8[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007C8[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007C8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007C8[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007C8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007CC[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007CC[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007CC[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007CC[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007CC[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007CC[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007CC[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007CC[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007CC[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U), + /* .. TRI_ENABLE = 0 */ /* .. ==> 0XF80007D0[0:0] = 0x00000000U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ /* .. L0_SEL = 0 */ @@ -7238,11 +7982,11 @@ unsigned long ps7_peripherals_init_data_2_0[] = { /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */ /* .. */ EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), - /* .. CD = 0x3e */ - /* .. ==> 0XE0001018[15:0] = 0x0000003EU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU */ + /* .. CD = 0x7c */ + /* .. ==> 0XE0001018[15:0] = 0x0000007CU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */ /* .. */ - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000003EU), + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU), /* .. STPBRK = 0x0 */ /* .. ==> 0XE0001000[8:8] = 0x00000000U */ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ @@ -7296,29 +8040,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = { /* .. */ EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U), /* .. FINISH: UART REGISTERS */ - /* .. START: TPIU WIDTH IN CASE OF EMIO */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0XC5ACCE55 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. .. START: TRACE CURRENT PORT SIZE */ - /* .. .. a = 2 */ - /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U), - /* .. .. FINISH: TRACE CURRENT PORT SIZE */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0X0 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */ /* .. START: QSPI REGISTERS */ /* .. Holdb_dr = 1 */ /* .. ==> 0XE000D000[19:19] = 0x00000001U */ @@ -7357,24 +8078,50 @@ unsigned long ps7_peripherals_init_data_2_0[] = { /* .. .. .. .. START: DIR MODE BANK 0 */ /* .. .. .. .. FINISH: DIR MODE BANK 0 */ /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. DIRECTION_1 = 0x4000 */ + /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U), /* .. .. .. .. FINISH: DIR MODE BANK 1 */ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x4000 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. OP_ENABLE_1 = 0x4000 */ + /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U), /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x0 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U), /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ @@ -7387,6 +8134,14 @@ unsigned long ps7_peripherals_init_data_2_0[] = { /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x4000 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ @@ -7619,31 +8374,8 @@ unsigned long ps7_post_config_2_0[] = { /* .. ==> 0XF8000900[3:2] = 0x00000003U */ /* .. ==> MASK : 0x0000000CU VAL : 0x0000000CU */ /* .. */ - EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), - /* .. FINISH: ENABLING LEVEL SHIFTER */ - /* .. START: TPIU WIDTH IN CASE OF EMIO */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0XC5ACCE55 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. .. START: TRACE CURRENT PORT SIZE */ - /* .. .. a = 2 */ - /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U), - /* .. .. FINISH: TRACE CURRENT PORT SIZE */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0X0 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */ + EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), + /* .. FINISH: ENABLING LEVEL SHIFTER */ /* .. START: FPGA RESETS TO 0 */ /* .. reserved_3 = 0 */ /* .. ==> 0XF8000240[31:25] = 0x00000000U */ @@ -8071,11 +8803,11 @@ unsigned long ps7_clock_init_data_1_0[] = { /* .. SRCSEL = 0x0 */ /* .. ==> 0XF8000154[5:4] = 0x00000000U */ /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. DIVISOR = 0x14 */ - /* .. ==> 0XF8000154[13:8] = 0x00000014U */ - /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ + /* .. DIVISOR = 0xa */ + /* .. ==> 0XF8000154[13:8] = 0x0000000AU */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ /* .. */ - EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001402U), + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U), /* .. .. START: TRACE CLOCK */ /* .. .. FINISH: TRACE CLOCK */ /* .. .. CLKACT = 0x1 */ @@ -8100,39 +8832,39 @@ unsigned long ps7_clock_init_data_1_0[] = { /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ /* .. .. */ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U), - /* .. .. SRCSEL = 0x3 */ - /* .. .. ==> 0XF8000180[5:4] = 0x00000003U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000030U */ - /* .. .. DIVISOR0 = 0x6 */ - /* .. .. ==> 0XF8000180[13:8] = 0x00000006U */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U */ + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0x7 */ + /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */ /* .. .. DIVISOR1 = 0x1 */ /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ /* .. .. */ - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100630U), - /* .. .. SRCSEL = 0x2 */ - /* .. .. ==> 0XF8000190[5:4] = 0x00000002U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000020U */ - /* .. .. DIVISOR0 = 0x35 */ - /* .. .. ==> 0XF8000190[13:8] = 0x00000035U */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00003500U */ - /* .. .. DIVISOR1 = 0x2 */ - /* .. .. ==> 0XF8000190[25:20] = 0x00000002U */ - /* .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00203520U), + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0x5 */ + /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U), /* .. .. SRCSEL = 0x0 */ /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. .. DIVISOR0 = 0xa */ - /* .. .. ==> 0XF80001A0[13:8] = 0x0000000AU */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ + /* .. .. DIVISOR0 = 0x14 */ + /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ /* .. .. DIVISOR1 = 0x1 */ /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ /* .. .. */ - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00100A00U), + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U), /* .. .. CLK_621_TRUE = 0x1 */ /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ @@ -8452,9 +9184,9 @@ unsigned long ps7_ddr_init_data_1_0[] = { /* .. .. reg_ddrc_burst_rdwr = 0x4 */ /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */ - /* .. .. reg_ddrc_pre_cke_x1024 = 0x101 */ - /* .. .. ==> 0XF8006034[13:4] = 0x00000101U */ - /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U */ + /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */ + /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */ + /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */ /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */ /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */ /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */ @@ -8462,7 +9194,7 @@ unsigned long ps7_ddr_init_data_1_0[] = { /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */ /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */ /* .. .. */ - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011014U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U), /* .. .. reg_ddrc_force_low_pri_n = 0x0 */ /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ @@ -9875,6 +10607,35 @@ unsigned long ps7_mio_init_data_1_0[] = { /* .. FINISH: DDRIOB SETTINGS */ /* .. START: MIO PROGRAMMING */ /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000700[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000700[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000700[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000700[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000700[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000700[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000700[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000700[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000700[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ /* .. ==> 0XF8000704[0:0] = 0x00000000U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ /* .. L0_SEL = 1 */ @@ -10049,6 +10810,267 @@ unsigned long ps7_mio_init_data_1_0[] = { /* .. */ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800071C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800071C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800071C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800071C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800071C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800071C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800071C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800071C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800071C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000720[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000720[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000720[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000720[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000720[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000720[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000720[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000720[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000720[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000724[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000724[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000724[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000724[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000724[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000724[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000724[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000724[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000724[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000728[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000728[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000728[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000728[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000728[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000728[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000728[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000728[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000728[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800072C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800072C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800072C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800072C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800072C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800072C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800072C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF800072C[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800072C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000730[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000730[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000730[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000730[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000730[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000730[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000730[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000730[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000730[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000734[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000734[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000734[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000734[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000734[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000734[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000734[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000734[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000734[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000738[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000738[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000738[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000738[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000738[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000738[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000738[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000738[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000738[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800073C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800073C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800073C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800073C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800073C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800073C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800073C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF800073C[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800073C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ /* .. ==> 0XF8000740[0:0] = 0x00000000U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ /* .. L0_SEL = 1 */ @@ -10918,6 +11940,35 @@ unsigned long ps7_mio_init_data_1_0[] = { /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ /* .. */ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007B8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007B8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007B8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007B8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007B8[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007B8[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007B8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF80007B8[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007B8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U), /* .. TRI_ENABLE = 1 */ /* .. ==> 0XF80007BC[0:0] = 0x00000001U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ @@ -10994,6 +12045,64 @@ unsigned long ps7_mio_init_data_1_0[] = { /* .. */ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U), /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007C8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007C8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007C8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007C8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007C8[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007C8[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007C8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007C8[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007C8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007CC[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007CC[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007CC[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007CC[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007CC[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007CC[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007CC[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007CC[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007CC[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U), + /* .. TRI_ENABLE = 0 */ /* .. ==> 0XF80007D0[0:0] = 0x00000000U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ /* .. L0_SEL = 0 */ @@ -11132,11 +12241,11 @@ unsigned long ps7_peripherals_init_data_1_0[] = { /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */ /* .. */ EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), - /* .. CD = 0x3e */ - /* .. ==> 0XE0001018[15:0] = 0x0000003EU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU */ + /* .. CD = 0x7c */ + /* .. ==> 0XE0001018[15:0] = 0x0000007CU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */ /* .. */ - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000003EU), + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU), /* .. STPBRK = 0x0 */ /* .. ==> 0XE0001000[8:8] = 0x00000000U */ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ @@ -11190,29 +12299,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = { /* .. */ EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U), /* .. FINISH: UART REGISTERS */ - /* .. START: TPIU WIDTH IN CASE OF EMIO */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0XC5ACCE55 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. .. START: TRACE CURRENT PORT SIZE */ - /* .. .. a = 2 */ - /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U), - /* .. .. FINISH: TRACE CURRENT PORT SIZE */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0X0 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */ /* .. START: QSPI REGISTERS */ /* .. Holdb_dr = 1 */ /* .. ==> 0XE000D000[19:19] = 0x00000001U */ @@ -11251,24 +12337,50 @@ unsigned long ps7_peripherals_init_data_1_0[] = { /* .. .. .. .. START: DIR MODE BANK 0 */ /* .. .. .. .. FINISH: DIR MODE BANK 0 */ /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. DIRECTION_1 = 0x4000 */ + /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U), /* .. .. .. .. FINISH: DIR MODE BANK 1 */ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x4000 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. OP_ENABLE_1 = 0x4000 */ + /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U), /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x0 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U), /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ @@ -11281,6 +12393,14 @@ unsigned long ps7_peripherals_init_data_1_0[] = { /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x4000 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ @@ -11515,29 +12635,6 @@ unsigned long ps7_post_config_1_0[] = { /* .. */ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), /* .. FINISH: ENABLING LEVEL SHIFTER */ - /* .. START: TPIU WIDTH IN CASE OF EMIO */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0XC5ACCE55 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. .. START: TRACE CURRENT PORT SIZE */ - /* .. .. a = 2 */ - /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U), - /* .. .. FINISH: TRACE CURRENT PORT SIZE */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0X0 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */ /* .. START: FPGA RESETS TO 0 */ /* .. reserved_3 = 0 */ /* .. ==> 0XF8000240[31:25] = 0x00000000U */ diff --git a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h index 62b8a5846b62..22d9fd9250e8 100644 --- a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h +++ b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h @@ -62,7 +62,7 @@ extern unsigned long *ps7_peripherals_init_data; #define USB0_FREQ 60000000 #define USB1_FREQ 60000000 #define SDIO_FREQ 50000000 -#define UART_FREQ 50000000 +#define UART_FREQ 100000000 #define SPI_FREQ 10000000 #define I2C_FREQ 108333336 #define WDT_FREQ 108333336 @@ -71,9 +71,10 @@ extern unsigned long *ps7_peripherals_init_data; #define PCAP_FREQ 200000000 #define TPIU_FREQ 200000000 #define FPGA0_FREQ 100000000 -#define FPGA1_FREQ 175000000 -#define FPGA2_FREQ 12264151 -#define FPGA3_FREQ 100000000 +#define FPGA1_FREQ 142857132 +#define FPGA2_FREQ 200000000 +#define FPGA3_FREQ 50000000 + /* For delay calculation using global registers*/ #define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 -- 1.9.1

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