December 2016 - U-Boot

[U-Boot] [PATCH v2 2/2] test/py: Create tests for ext4 and fat testing on sandbox
by Stefan Brüns 11 Feb '17

11 Feb '17

From: Stefan BrÃ¼ns <stefan.bruens(a)rwth-aachen.de> The following checks are currently implemented: 1. listing a directory 2. verifying size of a file 3. veryfying md5sum for a file region 4. reading the beginning of a file Signed-off-by: Stefan Brüns <stefan.bruens(a)rwth-aachen.de> --- test/py/tests/test_fs.py | 357 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 357 insertions(+) create mode 100644 test/py/tests/test_fs.py diff --git a/test/py/tests/test_fs.py b/test/py/tests/test_fs.py new file mode 100644 index 0000000000..7aaf8debaf --- /dev/null +++ b/test/py/tests/test_fs.py @@ -0,0 +1,357 @@ +# Copyright (c) 2016, Stefan Bruens <stefan.bruens(a)rwth-aachen.de> +# +# SPDX-License-Identifier: GPL-2.0 + +# Test U-Boot's filesystem implementations +# +# The tests are currently covering the ext4 and fat filesystem implementations. +# +# Following functionality is currently checked: +# - Listing a directory and checking for a set of files +# - Verifying the size of a file +# - Reading sparse and non-sparse files +# - File content verification using md5sums + + +from distutils.spawn import find_executable +import hashlib +import pytest +import os +import random +import re +import u_boot_utils as util + +(a)pytest.fixture(scope='session') +def prereq_commands(): + """Detect required commands to run file system tests.""" + for command in ['mkfs', 'mount', 'umount']: + if find_executable(command) is None: + pytest.skip('Filesystem tests, "{0}" not in PATH'.format(command)) + +""" +Scenarios: + hostfs: access image contents through the sandbox hostfs + facility, using the filesytem implementation of + the sandbox host, e.g. Linux kernel + generic: test u-boots native filesystem implementations, + using the 'generic' command names, e.g. 'load' + TODO - + fscommands: test u-boots native filesystem implementations, + using the fs specific commands, e.g. 'ext4load' +""" +(a)pytest.fixture(scope='class', params=['generic', 'hostfs']) +def scenario(request): + request.cls.scenario = request.param + return request.param + + +""" +Dictionary of files to use during filesystem tests. The files +are keyed by the filenames. The value is an array of strides, each tuple +contains the the start offset (inclusive) and end offset (exclusive). +""" +files = { + 'empty.file' : [(0, 0)], + '1MB.file' : [(0, 1e6)], + '1MB.sparse.file' : [(1e6-1, 1e6)], + '32MB.sparse.file' : [(0, 1e6), (4e6, 5e6), (31e6, 32e6)], + # Creating a 2.5 GB file on FAT is exceptionally slow, disable it for now + # '2_5GB.sparse.file' : [(0, 1e6), (1e9, 1e9+1e6), (2.5e9-1e6, 2.5e9)], +} + +"""Options to pass to mkfs.""" +mkfs_opts = { + 'fat' :'-t vfat', + 'ext4' : '-t ext4 -F', +} + +class FsImage: + def __init__(self, fstype, imagepath, mountpath): + """Create a new filesystem image. + + Args: + fstype: filesystem type (string) + imagepath: full path to image file + mountpath: mountpoint directory + """ + self.fstype = fstype + self.imagepath = imagepath + self.mountpath = mountpath + self.md5s = {} + with open(self.imagepath, 'w') as fd: + fd.truncate(0) + fd.seek(3e9) + fd.write(bytes([0])) + + def mkfs(self, log): + mkfsopts = mkfs_opts.get(self.fstype) + util.run_and_log(log, + 'mkfs {0} {1}'.format(mkfsopts, self.imagepath)) + + def create_file(self, log, filename, strides): + """Create a single file in the filesystem. Each file + is defined by one or more strides, which is filled with + random data. For each stride, the md5sum is calculated + and stored. + """ + md5sums = [] + with open(self.mountpath + '/' + filename, 'w') as fd: + for stride in strides: + length = int(stride[1] - stride[0]) + data = bytearray(random.getrandbits(8) for _ in xrange(length)) + md5 = hashlib.md5(data).hexdigest() + md5sums.append(md5) + log.info('{0}: write {1} bytes @ {2} : {3}'.format( + filename, int(stride[1] - stride[0]), + int(stride[0]), md5)) + fd.seek(stride[0]) + fd.write(data); + self.md5s[filename] = md5sums + + def create_files(self, log): + with log.section('Create initial files'): + for filename in files: + self.create_file(log, filename, files[filename]) + log.info('Created test files in "{0}"'.format(self.mountpath)) + util.run_and_log(log, 'ls -la {0}'.format(self.mountpath)) + util.run_and_log(log, 'sync {0}'.format(self.mountpath)) + + def mount(self, log): + if not os.path.exists(self.mountpath): + os.mkdir(self.mountpath) + log.info('Mounting {0} at {1}'.format(self.imagepath, self.mountpath)) + if self.fstype == 'ext4': + cmd = 'sudo -n mount -o loop,rw {0} {1}'.format(self.imagepath, self.mountpath) + else: + cmd = 'sudo -n mount -o loop,rw,umask=000 {0} {1}'.format(self.imagepath, self.mountpath) + util.run_and_log(log, cmd) + if self.fstype == 'ext4': + cmd = 'sudo -n chmod og+rw {0}'.format(self.mountpath) + return util.run_and_log(log, cmd) + + def unmount(self, log): + log.info('Unmounting {0}'.format(self.imagepath)) + cmd = 'sudo -n umount -l {0}'.format(self.mountpath) + util.run_and_log(log, cmd, ignore_errors=True) + + +(a)pytest.fixture(scope='module', params=['fat', 'ext4']) +def fsimage(prereq_commands, u_boot_config, u_boot_log, request): + """Filesystem image instance.""" + datadir = u_boot_config.result_dir + '/' + fstype = request.param + imagepath = datadir + '3GB.' + fstype + '.img' + mountpath = datadir + 'mnt_' + fstype + + with u_boot_log.section('Create image "{0}"'.format(imagepath)): + fsimage = FsImage(fstype, imagepath, mountpath) + fsimage.mkfs(u_boot_log) + + yield fsimage + fsimage.unmount(u_boot_log) + +(a)pytest.fixture(scope='module') +def populated_image(fsimage, u_boot_log): + """Filesystem populated with files required for tests.""" + try: + fsimage.mount(u_boot_log) + except Exception as e: + pytest.skip('{0}: could not mount "{1}"'.format( + fsimage.fstype, fsimage.imagepath)) + yield None + + fsimage.create_files(u_boot_log) + fsimage.unmount(u_boot_log) + yield fsimage + +(a)pytest.fixture(scope='function') +def boundimage(populated_image, u_boot_console, request): + """Filesystem image instance which is accessible from inside + the running U-Boot instance.""" + image = populated_image + request.cls.image = image + if request.cls.scenario == 'hostfs': + image.mount(u_boot_console.log) + image.rootpath = image.mountpath + '/' + yield image + image.unmount(u_boot_console.log) + else: + output = u_boot_console.run_command_list( + ['host bind 0 {0}'.format(image.imagepath)]) + image.rootpath = '/' + yield image + output = u_boot_console.run_command_list(['host bind 0 ']) + + +def test_fs_prepare_image(u_boot_config, fsimage, request): + """Dummy test to create an image file with filesystem. + Useful to isolate fixture setup from actual tests.""" + if not fsimage: + pytest.fail('Failed to create image') + +def test_fs_populate_image(populated_image, request): + """Dummy test to create initial filesystem contents.""" + if not populated_image: + pytest.fail('Failed create initial image content') + +(a)pytest.mark.usefixtures('u_boot_console', 'scenario', 'boundimage') +class TestFilesystems: + ignore_cleanup_errors = True + filesize_regex = re.compile('^filesize=([A-Fa-f0-9]+)') + md5sum_regex = re.compile('^md5 for .* ==> ([A-Fa-f0-9]{32})') + dirlist_regex = re.compile('\s+(\d+)\s+(\S+.file\S*)') + + commands = { + 'fat' : { + 'listcmd' : 'ls', + 'readcmd' : 'load', + 'sizecmd' : 'size', + 'writecmd' : 'size', + }, + 'ext4' : { + 'listcmd' : 'ls', + 'readcmd' : 'load', + 'sizecmd' : 'size', + 'writecmd' : 'size', + }, + } + + cmd_parameters = { + 'hostfs' : { + 'prefix' : 'host ', + 'interface' : 'hostfs -', + }, + 'generic' : { + 'prefix' : '', + 'interface' : 'host 0:0', + }, + } + + def get_filesize(self, filename): + """Get the size of the given file.""" + strides = files[filename] + return int(strides[-1][1]) + + def check_dirlist(self, string, filenames): + """Check if the output string returned by a list command + contains all given filenames.""" + m = self.dirlist_regex.findall(string) + assert(m) + for i, e in enumerate(m): + m[i] = (int(e[0]), e[1].lower()) + for f in filenames: + e = (self.get_filesize(f), f.lower()) + assert(e in m) + + def check_filesize(self, string, size): + """Check if the output string returned by a size command + matches the expected file size.""" + m = self.filesize_regex.match(string) + assert(m) + assert(int(m.group(1), 16) == size) + + def check_md5sum(self, string, md5): + """Check if the output string returned by the md5sum + command matches the expected md5.""" + m = self.md5sum_regex.match(string) + assert(m) + assert(len(m.group(1)) == 32) + assert(m.group(1) == md5) + + def run_listcmd(self, dirname): + """Run the scenario and filesystem specific list command + for the given directory name.""" + cmd = '{0}{1} {2} {3}'.format( + self.fs_params.get('prefix'), + self.fs_commands.get('listcmd'), + self.fs_params.get('interface'), + self.image.rootpath + dirname) + with self.console.log.section('List "{0}"'.format(dirname)): + output = self.console.run_command_list([cmd]) + return output[0] + + def run_readcmd(self, filename, offset, length): + """Run the scenario and filesystem specific read command + for the given file.""" + cmd = '{0}{1} {2} {3} {4} 0x{5:x} 0x{6:x}'.format( + self.fs_params.get('prefix'), + self.fs_commands.get('readcmd'), + self.fs_params.get('interface'), + '0', # address + self.image.rootpath + filename, + length, offset) + with self.console.log.section('Read file "{0}"'.format(filename)): + output = self.console.run_command_list( + [cmd, 'env print filesize', + 'md5sum 0 $filesize', 'env set filesize']) + return output[1:3] + + def run_sizecmd(self, filename): + """Run the scenario and filesystem specific size command + for the given file.""" + cmd = '{0}{1} {2} {3}'.format( + self.fs_params.get('prefix'), + self.fs_commands.get('sizecmd'), + self.fs_params.get('interface'), + self.image.rootpath + filename) + with self.console.log.section('Get size of "{0}"'.format(filename)): + output = self.console.run_command_list( + [cmd, 'env print filesize', 'env set filesize']) + return output[1] + + def setup(self): + self.fs_params = self.cmd_parameters.get(self.scenario) + self.fs_commands = self.commands.get(self.image.fstype) + + @pytest.mark.parametrize('dirname', ['', './']) + def test_fs_ls(self, u_boot_console, dirname): + """Check the contents of the given directory.""" + if self.image.fstype == 'fat' and dirname == './': + pytest.skip("FAT has no '.' entry in the root directory") + self.console = u_boot_console + self.setup() + + output = self.run_listcmd(dirname) + self.check_dirlist(output, files.keys()) + + @pytest.mark.parametrize('filename', files.keys()) + def test_fs_filesize(self, u_boot_console, filename): + """Check the filesize of the given file.""" + self.console = u_boot_console + self.setup() + + filesize = self.get_filesize(filename) + + output = self.run_sizecmd(filename) + self.check_filesize(output, filesize) + + @pytest.mark.parametrize('filename', files.keys()) + def test_fs_read(self, u_boot_console, filename): + """Read all defined strides of the given file and checks + its contents.""" + self.console = u_boot_console + self.setup() + + md5s = self.image.md5s[filename] + + for i, stride in enumerate(files[filename]): + length = int(stride[1]) - int(stride[0]) + offset = int(stride[0]) + output = self.run_readcmd(filename, offset, length) + self.check_filesize(output[0], length) + self.console.log.info('md5: {0}'.format(md5s[i])) + self.check_md5sum(output[1], md5s[i]) + + @pytest.mark.parametrize('filename', files.keys()) + def test_fs_read_head(self, u_boot_console, filename): + """Check reading the head of the given file, up to the first + 4 Megabyte (or less for smaller files). Also reads sparse + regions of a file.""" + self.console = u_boot_console + self.setup() + + filesize = self.get_filesize(filename) + filesize = min(filesize, int(4e6)) + + output = self.run_readcmd(filename, 0, filesize) + self.check_filesize(output[0], filesize) -- 2.11.0

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[U-Boot] [PATCH v2 0/4] Allow disabling non-FIT image loading from SPL
by Andrew F. Davis 10 Feb '17

10 Feb '17

Hello all, To address a needed feature brought up by Andreas[0], we need a way to disable SPL from loading non-FIT images. The function spl_parse_image_header is common to all SPL loading paths (common/spl/spl_(nand|net|nor|etc..)) so we add the check here, much like the existing CONFIG_SPL_ABORT_ON_RAW_IMAGE. My original attempt was to add CONFIG_SPL_PANIC_ON_MKIMAGE, but then if other formats are added, flaws in restricting image types may be introduced, so we would like a single option to restrict all non-FIT types vs disabling types individually. Thanks, Andrew [0] https://www.mail-archive.com/u-boot@lists.denx.de/msg219253.html Changes from v1: - Changed to abort on non-FIT so other boot methods can be attempted. - Made this a default if SPL_FIT_SIGNATURE is selected. Andrew F. Davis (4): Introduce CONFIG_SPL_ABORT_ON_NON_FIT_IMAGE ARM: AM57xx: Disable non-FIT based image loading for HS devices ARM: AM437x: Disable non-FIT based image loading for HS devices ARM: DRA7xx: Disable non-FIT based image loading for HS devices Kconfig | 9 +++++++++ common/spl/spl.c | 5 +++++ configs/am43xx_hs_evm_defconfig | 1 + configs/am57xx_hs_evm_defconfig | 1 + configs/dra7xx_hs_evm_defconfig | 1 + 5 files changed, 17 insertions(+) -- 2.10.1

2 12

[U-Boot] [PATCH v2] net:phy:MSCC Add Support for VSC8530-VSC8531-VSC8540-VSC8541
by John Haechten 09 Feb '17

09 Feb '17

net:phy:MSCC Add Support for VSC8530-VSC8531-VSC8540-VSC8541 Signed-off-by: John Haechten <john.haechten(a)microsemi.com> --- drivers/net/phy/Makefile | 1 + drivers/net/phy/mscc.c | 509 ++++++++++++++++++++++++++++++++++++ drivers/net/phy/phy.c | 3 + include/config_phylib_all_drivers.h | 1 + include/configs/am335x_evm.h | 3 + include/phy.h | 1 + 6 files changed, 518 insertions(+) create mode 100644 drivers/net/phy/mscc.c diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 1e299b9..d372971 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -27,3 +27,4 @@ obj-$(CONFIG_PHY_TERANETICS) += teranetics.o obj-$(CONFIG_PHY_TI) += ti.o obj-$(CONFIG_PHY_XILINX) += xilinx_phy.o obj-$(CONFIG_PHY_VITESSE) += vitesse.o +obj-$(CONFIG_PHY_MSCC) += mscc.o diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c new file mode 100644 index 0000000..e665b50 --- /dev/null +++ b/drivers/net/phy/mscc.c @@ -0,0 +1,509 @@ +/* + * Microsemi PHY drivers + * + * SPDX-License-Identifier: The MIT License (MIT) + * + * Copyright (c) 2016 Microsemi Corporation + * + * Author: John Haechten + * + */ + +#include <miiphy.h> +#include <bitfield.h> + +/* Microsemi PHY ID's */ +#define PHY_ID_VSC8530 0x00070560 +#define PHY_ID_VSC8531 0x00070570 +#define PHY_ID_VSC8540 0x00070760 +#define PHY_ID_VSC8541 0x00070770 + +/* Microsemi VSC85xx PHY Register Pages */ +#define MSCC_EXT_PAGE_ACCESS 31 /* Page Access Register */ +#define MSCC_PHY_PAGE_STD 0x0000 /* Standard registers */ +#define MSCC_PHY_PAGE_EXT1 0x0001 /* Extended registers - page 1 */ +#define MSCC_PHY_PAGE_EXT2 0x0002 /* Extended registers - page 2 */ +#define MSCC_PHY_PAGE_EXT3 0x0003 /* Extended registers - page 3 */ +#define MSCC_PHY_PAGE_EXT4 0x0004 /* Extended registers - page 4 */ +#define MSCC_PHY_PAGE_GPIO 0x0010 /* GPIO registers */ +#define MSCC_PHY_PAGE_TEST 0x2A30 /* TEST Page registers */ +#define MSCC_PHY_PAGE_TR 0x52B5 /* Token Ring Page registers */ + +/* Std Page Register 28 - PHY AUX Control/Status */ +#define MIIM_AUX_CNTRL_STAT_REG 28 +#define MIIM_AUX_CNTRL_STAT_ACTIPHY_TO (0x0004) +#define MIIM_AUX_CNTRL_STAT_F_DUPLEX (0x0020) +#define MIIM_AUX_CNTRL_STAT_SPEED_MASK (0x0018) +#define MIIM_AUX_CNTRL_STAT_SPEED_POS (3) +#define MIIM_AUX_CNTRL_STAT_SPEED_10M (0x0) +#define MIIM_AUX_CNTRL_STAT_SPEED_100M (0x1) +#define MIIM_AUX_CNTRL_STAT_SPEED_1000M (0x2) + +/* Std Page Register 23 - Extended PHY CTRL_1 */ +#define MSCC_PHY_EXT_PHY_CNTL_1_REG 23 +#define MAC_IF_SELECTION_MASK (0x1800) +#define MAC_IF_SELECTION_GMII (0) +#define MAC_IF_SELECTION_RMII (1) +#define MAC_IF_SELECTION_RGMII (2) +#define MAC_IF_SELECTION_POS (11) +#define MAC_IF_SELECTION_WIDTH (2) + +/* Extended Page 2 Register 20E2 */ +#define MSCC_PHY_RGMII_CNTL_REG 20 +#define VSC_FAST_LINK_FAIL2_ENA_MASK (0x8000) +#define RX_CLK_OUT_MASK (0x0800) +#define RX_CLK_OUT_POS (11) +#define RX_CLK_OUT_WIDTH (1) +#define RX_CLK_OUT_NORMAL (0) +#define RX_CLK_OUT_DISABLE (1) +#define RGMII_RX_CLK_DELAY_POS (4) +#define RGMII_RX_CLK_DELAY_WIDTH (3) +#define RGMII_RX_CLK_DELAY_MASK (0x0070) +#define RGMII_TX_CLK_DELAY_POS (0) +#define RGMII_TX_CLK_DELAY_WIDTH (3) +#define RGMII_TX_CLK_DELAY_MASK (0x0007) + +/* Extended Page 2 Register 27E2 */ +#define MSCC_PHY_WOL_MAC_CONTROL 27 +#define EDGE_RATE_CNTL_POS (5) +#define EDGE_RATE_CNTL_WIDTH (3) +#define EDGE_RATE_CNTL_MASK (0x00E0) +#define RMII_CLK_OUT_ENABLE_POS (4) +#define RMII_CLK_OUT_ENABLE_WIDTH (1) +#define RMII_CLK_OUT_ENABLE_MASK (0x10) + +/* Token Ring Page 0x52B5 Registers */ +#define MSCC_PHY_REG_TR_ADDR_16 16 +#define MSCC_PHY_REG_TR_DATA_17 17 +#define MSCC_PHY_REG_TR_DATA_18 18 + +/* Token Ring - Read Value in */ +#define MSCC_PHY_TR_16_READ (0xA000) +/* Token Ring - Write Value out */ +#define MSCC_PHY_TR_16_WRITE (0x8000) + +/* Token Ring Registers */ +#define MSCC_PHY_TR_LINKDETCTRL_POS (3) +#define MSCC_PHY_TR_LINKDETCTRL_WIDTH (2) +#define MSCC_PHY_TR_LINKDETCTRL_VAL (3) +#define MSCC_PHY_TR_LINKDETCTRL_MASK (0x0018) +#define MSCC_PHY_TR_LINKDETCTRL_ADDR (0x07F8) + +#define MSCC_PHY_TR_VGATHRESH100_POS (0) +#define MSCC_PHY_TR_VGATHRESH100_WIDTH (7) +#define MSCC_PHY_TR_VGATHRESH100_VAL (0x0018) +#define MSCC_PHY_TR_VGATHRESH100_MASK (0x007f) +#define MSCC_PHY_TR_VGATHRESH100_ADDR (0x0FA4) + +#define MSCC_PHY_TR_VGAGAIN10_U_POS (0) +#define MSCC_PHY_TR_VGAGAIN10_U_WIDTH (1) +#define MSCC_PHY_TR_VGAGAIN10_U_MASK (0x0001) +#define MSCC_PHY_TR_VGAGAIN10_U_VAL (0) + +#define MSCC_PHY_TR_VGAGAIN10_L_POS (12) +#define MSCC_PHY_TR_VGAGAIN10_L_WIDTH (4) +#define MSCC_PHY_TR_VGAGAIN10_L_MASK (0xf000) +#define MSCC_PHY_TR_VGAGAIN10_L_VAL (0x0001) +#define MSCC_PHY_TR_VGAGAIN10_ADDR (0x0F92) + +/* General Timeout Values */ +#define MSCC_PHY_RESET_TIMEOUT (100) +#define MSCC_PHY_MICRO_TIMEOUT (500) + +/* RGMII/GMII Clock Delay (Skew) Options */ enum vsc_phy_rgmii_skew { + VSC_PHY_RGMII_DELAY_200_PS, + VSC_PHY_RGMII_DELAY_800_PS, + VSC_PHY_RGMII_DELAY_1100_PS, + VSC_PHY_RGMII_DELAY_1700_PS, + VSC_PHY_RGMII_DELAY_2000_PS, + VSC_PHY_RGMII_DELAY_2300_PS, + VSC_PHY_RGMII_DELAY_2600_PS, + VSC_PHY_RGMII_DELAY_3400_PS, +}; + +/* MAC i/f Clock Edge Rage Control (Slew), See Reg27E2 */ enum +vsc_phy_clk_slew { + VSC_PHY_CLK_SLEW_RATE_0, + VSC_PHY_CLK_SLEW_RATE_1, + VSC_PHY_CLK_SLEW_RATE_2, + VSC_PHY_CLK_SLEW_RATE_3, + VSC_PHY_CLK_SLEW_RATE_4, + VSC_PHY_CLK_SLEW_RATE_5, + VSC_PHY_CLK_SLEW_RATE_6, + VSC_PHY_CLK_SLEW_RATE_7, +}; + + +static int mscc_vsc8531_vsc8541_init_scripts(struct phy_device *phydev) +{ + u16 reg_val; + + /* Set to Access Token Ring Registers */ + phy_write(phydev, MDIO_DEVAD_NONE, + MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); + + /* Update LinkDetectCtrl default to optimized values */ + /* Determined during Silicon Validation Testing */ + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, + (MSCC_PHY_TR_LINKDETCTRL_ADDR | MSCC_PHY_TR_16_READ)); + reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17); + reg_val = bitfield_replace(reg_val, MSCC_PHY_TR_LINKDETCTRL_POS, + MSCC_PHY_TR_LINKDETCTRL_WIDTH, + MSCC_PHY_TR_LINKDETCTRL_VAL); + + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17, reg_val); + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, + (MSCC_PHY_TR_LINKDETCTRL_ADDR | MSCC_PHY_TR_16_WRITE)); + + /* Update VgaThresh100 defaults to optimized values */ + /* Determined during Silicon Validation Testing */ + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, + (MSCC_PHY_TR_VGATHRESH100_ADDR | MSCC_PHY_TR_16_READ)); + + reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18); + reg_val = bitfield_replace(reg_val, MSCC_PHY_TR_VGATHRESH100_POS, + MSCC_PHY_TR_VGATHRESH100_WIDTH, + MSCC_PHY_TR_VGATHRESH100_VAL); + + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18, reg_val); + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, + (MSCC_PHY_TR_VGATHRESH100_ADDR | MSCC_PHY_TR_16_WRITE)); + + /* Update VgaGain10 defaults to optimized values */ + /* Determined during Silicon Validation Testing */ + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, + (MSCC_PHY_TR_VGAGAIN10_ADDR | MSCC_PHY_TR_16_READ)); + + reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18); + reg_val = bitfield_replace(reg_val, MSCC_PHY_TR_VGAGAIN10_U_POS, + MSCC_PHY_TR_VGAGAIN10_U_WIDTH, + MSCC_PHY_TR_VGAGAIN10_U_VAL); + + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18, reg_val); + reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17); + reg_val = bitfield_replace(reg_val, MSCC_PHY_TR_VGAGAIN10_L_POS, + MSCC_PHY_TR_VGAGAIN10_L_WIDTH, + MSCC_PHY_TR_VGAGAIN10_L_VAL); + + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17, reg_val); + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, + (MSCC_PHY_TR_VGAGAIN10_ADDR | MSCC_PHY_TR_16_WRITE)); + + /* Set back to Access Standard Page Registers */ + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_STD); + + return 0; +} + +static int mscc_parse_status(struct phy_device *phydev) { + u16 speed; + u16 mii_reg; + + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_AUX_CNTRL_STAT_REG); + + if (mii_reg & MIIM_AUX_CNTRL_STAT_F_DUPLEX) + phydev->duplex = DUPLEX_FULL; + else + phydev->duplex = DUPLEX_HALF; + + speed = mii_reg & MIIM_AUX_CNTRL_STAT_SPEED_MASK; + speed = speed >> MIIM_AUX_CNTRL_STAT_SPEED_POS; + + switch (speed) { + case MIIM_AUX_CNTRL_STAT_SPEED_1000M: + phydev->speed = SPEED_1000; + break; + case MIIM_AUX_CNTRL_STAT_SPEED_100M: + phydev->speed = SPEED_100; + break; + case MIIM_AUX_CNTRL_STAT_SPEED_10M: + phydev->speed = SPEED_10; + break; + default: + phydev->speed = SPEED_10; + break; + } + + return 0; +} + +static int mscc_startup(struct phy_device *phydev) { + int retval; + + retval = genphy_update_link(phydev); + + if (retval) + return retval; + + return mscc_parse_status(phydev); +} + +static int mscc_phy_soft_reset(struct phy_device *phydev) { + int retval = 0; + u16 timeout = MSCC_PHY_RESET_TIMEOUT; + u16 reg_val = 0; + + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_STD); + + reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, (reg_val | BMCR_RESET)); + + reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); + + while ((reg_val & BMCR_RESET) && (timeout > 0)) { + reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); + timeout--; + udelay(1000); /* 1 ms */ + } + + if (timeout == 0) { + printf("MSCC PHY Soft_Reset Error: mac i/f = 0x%x\n", + phydev->interface); + retval = -ETIME; + } + + return retval; +} + +static int vsc8531_vsc8541_mac_config(struct phy_device *phydev) { + u16 reg_val = 0; + u16 mac_if = 0; + u16 rx_clk_out = 0; + + /* For VSC8530/31 the only MAC modes are RMII/RGMII. */ + /* For VSC8540/41 the only MAC modes are (G)MII and RMII/RGMII. */ + /* Setup MAC Configuration */ + switch (phydev->interface) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_GMII: + /* Set Reg23.12:11=0 */ + mac_if = MAC_IF_SELECTION_GMII; + /* Set Reg20E2.11=1 */ + rx_clk_out = RX_CLK_OUT_DISABLE; + break; + + case PHY_INTERFACE_MODE_RMII: + /* Set Reg23.12:11=1 */ + mac_if = MAC_IF_SELECTION_RMII; + /* Set Reg20E2.11=0 */ + rx_clk_out = RX_CLK_OUT_NORMAL; + break; + + case PHY_INTERFACE_MODE_RGMII: + /* Set Reg23.12:11=2 */ + mac_if = MAC_IF_SELECTION_RGMII; + /* Set Reg20E2.11=0 */ + rx_clk_out = RX_CLK_OUT_NORMAL; + break; + + default: + printf("MSCC PHY - INVALID MAC i/f Config: mac i/f = 0x%x\n", + phydev->interface); + return -EINVAL; + } + + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_STD); + + reg_val = phy_read(phydev, MDIO_DEVAD_NONE, + MSCC_PHY_EXT_PHY_CNTL_1_REG); + /* Set MAC i/f bits Reg23.12:11 */ + reg_val = bitfield_replace(reg_val, MAC_IF_SELECTION_POS, + MAC_IF_SELECTION_WIDTH, mac_if); + /* Update Reg23.12:11 */ + phy_write(phydev, MDIO_DEVAD_NONE, + MSCC_PHY_EXT_PHY_CNTL_1_REG, reg_val); + /* Setup ExtPg_2 Register Access */ + phy_write(phydev, MDIO_DEVAD_NONE, + MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXT2); + /* Read Reg20E2 */ + reg_val = phy_read(phydev, MDIO_DEVAD_NONE, + MSCC_PHY_RGMII_CNTL_REG); + reg_val = bitfield_replace(reg_val, RX_CLK_OUT_POS, + RX_CLK_OUT_WIDTH, rx_clk_out); + /* Update Reg20E2.11 */ + phy_write(phydev, MDIO_DEVAD_NONE, + MSCC_PHY_RGMII_CNTL_REG, reg_val); + /* Before leaving - Change back to Std Page Register Access */ + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_STD); + + return 0; +} + +static int vsc8531_config(struct phy_device *phydev) { + int retval = -EINVAL; + u16 reg_val; + u16 rmii_clk_out; + enum vsc_phy_rgmii_skew rx_clk_skew = VSC_PHY_RGMII_DELAY_1700_PS; + enum vsc_phy_rgmii_skew tx_clk_skew = VSC_PHY_RGMII_DELAY_800_PS; + enum vsc_phy_clk_slew edge_rate = VSC_PHY_CLK_SLEW_RATE_4; + + /* For VSC8530/31 and VSC8540/41 the init scripts are the same */ + mscc_vsc8531_vsc8541_init_scripts(phydev); + + /* For VSC8530/31 the only MAC modes are RMII/RGMII. */ + switch (phydev->interface) { + case PHY_INTERFACE_MODE_RMII: + case PHY_INTERFACE_MODE_RGMII: + retval = vsc8531_vsc8541_mac_config(phydev); + if (retval != 0) + return retval; + + retval = mscc_phy_soft_reset(phydev); + if (retval != 0) + return retval; + break; + default: + printf("PHY 8530/31 MAC i/f Config Error: mac i/f = 0x%x\n", + phydev->interface); + return -EINVAL; + } + /* Default RMII Clk Output to 0=OFF/1=ON */ + rmii_clk_out = 0; + + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_EXT2); + reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG); + + /* Reg20E2 - Update RGMII RX_Clk Skews. */ + reg_val = bitfield_replace(reg_val, RGMII_RX_CLK_DELAY_POS, + RGMII_RX_CLK_DELAY_WIDTH, rx_clk_skew); + /* Reg20E2 - Update RGMII TX_Clk Skews. */ + reg_val = bitfield_replace(reg_val, RGMII_TX_CLK_DELAY_POS, + RGMII_TX_CLK_DELAY_WIDTH, tx_clk_skew); + + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG, reg_val); + + reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_WOL_MAC_CONTROL); + /* Reg27E2 - Update Clk Slew Rate. */ + reg_val = bitfield_replace(reg_val, EDGE_RATE_CNTL_POS, + EDGE_RATE_CNTL_WIDTH, edge_rate); + /* Reg27E2 - Update RMII Clk Out. */ + reg_val = bitfield_replace(reg_val, RMII_CLK_OUT_ENABLE_POS, + RMII_CLK_OUT_ENABLE_WIDTH, rmii_clk_out); + /* Update Reg27E2 */ + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_WOL_MAC_CONTROL, reg_val); + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_STD); + + return genphy_config_aneg(phydev); +} + +static int vsc8541_config(struct phy_device *phydev) { + int retval = -EINVAL; + u16 reg_val; + u16 rmii_clk_out; + enum vsc_phy_rgmii_skew rx_clk_skew = VSC_PHY_RGMII_DELAY_1700_PS; + enum vsc_phy_rgmii_skew tx_clk_skew = VSC_PHY_RGMII_DELAY_800_PS; + enum vsc_phy_clk_slew edge_rate = VSC_PHY_CLK_SLEW_RATE_4; + + /* For VSC8530/31 and VSC8540/41 the init scripts are the same */ + mscc_vsc8531_vsc8541_init_scripts(phydev); + + /* For VSC8540/41 the only MAC modes are (G)MII and RMII/RGMII. */ + switch (phydev->interface) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_GMII: + case PHY_INTERFACE_MODE_RMII: + case PHY_INTERFACE_MODE_RGMII: + retval = vsc8531_vsc8541_mac_config(phydev); + if (retval != 0) + return retval; + + retval = mscc_phy_soft_reset(phydev); + if (retval != 0) + return retval; + break; + default: + printf("PHY 8541 MAC i/f config Error: mac i/f = 0x%x\n", + phydev->interface); + return -EINVAL; + } + /* Default RMII Clk Output to 0=OFF/1=ON */ + rmii_clk_out = 0; + + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_EXT2); + reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG); + /* Reg20E2 - Update RGMII RX_Clk Skews. */ + reg_val = bitfield_replace(reg_val, RGMII_RX_CLK_DELAY_POS, + RGMII_RX_CLK_DELAY_WIDTH, rx_clk_skew); + /* Reg20E2 - Update RGMII TX_Clk Skews. */ + reg_val = bitfield_replace(reg_val, RGMII_TX_CLK_DELAY_POS, + RGMII_TX_CLK_DELAY_WIDTH, tx_clk_skew); + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG, reg_val); + + reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_WOL_MAC_CONTROL); + /* Reg27E2 - Update Clk Slew Rate. */ + reg_val = bitfield_replace(reg_val, EDGE_RATE_CNTL_POS, + EDGE_RATE_CNTL_WIDTH, edge_rate); + /* Reg27E2 - Update RMII Clk Out. */ + reg_val = bitfield_replace(reg_val, RMII_CLK_OUT_ENABLE_POS, + RMII_CLK_OUT_ENABLE_WIDTH, rmii_clk_out); + /* Update Reg27E2 */ + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_WOL_MAC_CONTROL, reg_val); + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_STD); + + return genphy_config_aneg(phydev); +} + +static struct phy_driver VSC8530_driver = { + .name = "Microsemi VSC8530", + .uid = PHY_ID_VSC8530, + .mask = 0x000ffff0, + .features = PHY_BASIC_FEATURES, + .config = &vsc8531_config, + .startup = &mscc_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver VSC8531_driver = { + .name = "Microsemi VSC8531", + .uid = PHY_ID_VSC8531, + .mask = 0x000ffff0, + .features = PHY_GBIT_FEATURES, + .config = &vsc8531_config, + .startup = &mscc_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver VSC8540_driver = { + .name = "Microsemi VSC8540", + .uid = PHY_ID_VSC8540, + .mask = 0x000ffff0, + .features = PHY_BASIC_FEATURES, + .config = &vsc8541_config, + .startup = &mscc_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver VSC8541_driver = { + .name = "Microsemi VSC8541", + .uid = PHY_ID_VSC8541, + .mask = 0x000ffff0, + .features = PHY_GBIT_FEATURES, + .config = &vsc8541_config, + .startup = &mscc_startup, + .shutdown = &genphy_shutdown, +}; + +int phy_mscc_init(void) +{ + phy_register(&VSC8530_driver); + phy_register(&VSC8531_driver); + phy_register(&VSC8540_driver); + phy_register(&VSC8541_driver); + + return 0; +} diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 80bdfb6..8db6574 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -512,6 +512,9 @@ int phy_init(void) #ifdef CONFIG_PHY_XILINX phy_xilinx_init(); #endif +#ifdef CONFIG_PHY_MSCC + phy_mscc_init(); +#endif return 0; } diff --git a/include/config_phylib_all_drivers.h b/include/config_phylib_all_drivers.h index 12828c6..d2965ed 100644 --- a/include/config_phylib_all_drivers.h +++ b/include/config_phylib_all_drivers.h @@ -14,6 +14,7 @@ #ifdef CONFIG_PHYLIB +#define CONFIG_PHY_MSCC #define CONFIG_PHY_VITESSE #define CONFIG_PHY_MARVELL #define CONFIG_PHY_MICREL diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index ec70b72..694e249 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -433,6 +433,9 @@ #define CONFIG_PHY_SMSC /* Enable Atheros phy driver */ #define CONFIG_PHY_ATHEROS +/* Enable MSCC phy driver */ +#define CONFIG_PHY_MSCC + /* * NOR Size = 16 MiB diff --git a/include/phy.h b/include/phy.h index 268d9a1..5477496 100644 --- a/include/phy.h +++ b/include/phy.h @@ -266,6 +266,7 @@ int phy_teranetics_init(void); int phy_ti_init(void); int phy_vitesse_init(void); int phy_xilinx_init(void); +int phy_mscc_init(void); int board_phy_config(struct phy_device *phydev); int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id); -- 1.9.1

3 3

[U-Boot] [PATCH v2] net: phy: Improve the Marvell 151x constants
by Joe Hershberger 09 Feb '17

09 Feb '17

Use some constants for the phy configuration instead of so many magic numbers. Signed-off-by: Joe Hershberger <joe.hershberger(a)ni.com> --- Changes in v2: -Fixed changed name from last-minute checkpatch line-length change drivers/net/phy/marvell.c | 47 ++++++++++++++++++++++++++++++++++++----------- 1 file changed, 36 insertions(+), 11 deletions(-) diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index 4eeb0f6..ac13a67 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -82,6 +82,21 @@ #define MIIM_88E1310_PHY_RGMII_CTRL 21 #define MIIM_88E1310_PHY_PAGE 22 +/* 88E151x PHY defines */ +/* Page 3 registers */ +#define MIIM_88E151x_LED_FUNC_CTRL 16 +#define MIIM_88E151x_LED_FLD_SZ 4 +#define MIIM_88E151x_LED0_OFFS (0 * MIIM_88E151x_LED_FLD_SZ) +#define MIIM_88E151x_LED1_OFFS (1 * MIIM_88E151x_LED_FLD_SZ) +#define MIIM_88E151x_LED0_ACT 3 +#define MIIM_88E151x_LED1_100_1000_LINK 6 +#define MIIM_88E151x_LED_TIMER_CTRL 18 +#define MIIM_88E151x_INT_EN_OFFS 7 +/* Page 18 registers */ +#define MIIM_88E151x_GENERAL_CTRL 20 +#define MIIM_88E151x_MODE_SGMII 1 +#define MIIM_88E151x_RESET_OFFS 15 + /* Marvell 88E1011S */ static int m88e1011s_config(struct phy_device *phydev) { @@ -289,7 +304,7 @@ static int m88e1518_config(struct phy_device *phydev) */ /* EEE initialization */ - phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00ff); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00ff); phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B); phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144); phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28); @@ -298,21 +313,23 @@ static int m88e1518_config(struct phy_device *phydev) phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D); phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C); phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159); - phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); /* SGMII-to-Copper mode initialization */ if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { /* Select page 18 */ - phy_write(phydev, MDIO_DEVAD_NONE, 22, 18); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 18); /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */ - m88e1518_phy_writebits(phydev, 20, 0, 3, 1); + m88e1518_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL, + 0, 3, MIIM_88E151x_MODE_SGMII); /* PHY reset is necessary after changing MODE[2:0] */ - m88e1518_phy_writebits(phydev, 20, 15, 1, 1); + m88e1518_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL, + MIIM_88E151x_RESET_OFFS, 1, 1); /* Reset page selection */ - phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0); udelay(100); } @@ -324,17 +341,25 @@ static int m88e1518_config(struct phy_device *phydev) static int m88e1510_config(struct phy_device *phydev) { /* Select page 3 */ - phy_write(phydev, MDIO_DEVAD_NONE, 22, 3); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, + MIIM_88E1118_PHY_LED_PAGE); /* Enable INTn output on LED[2] */ - m88e1518_phy_writebits(phydev, 18, 7, 1, 1); + m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_TIMER_CTRL, + MIIM_88E151x_INT_EN_OFFS, 1, 1); /* Configure LEDs */ - m88e1518_phy_writebits(phydev, 16, 0, 4, 3); /* LED[0]:0011 (ACT) */ - m88e1518_phy_writebits(phydev, 16, 4, 4, 6); /* LED[1]:0110 (LINK) */ + /* LED[0]:0011 (ACT) */ + m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_FUNC_CTRL, + MIIM_88E151x_LED0_OFFS, MIIM_88E151x_LED_FLD_SZ, + MIIM_88E151x_LED0_ACT); + /* LED[1]:0110 (LINK 100/1000 Mbps) */ + m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_FUNC_CTRL, + MIIM_88E151x_LED1_OFFS, MIIM_88E151x_LED_FLD_SZ, + MIIM_88E151x_LED1_100_1000_LINK); /* Reset page selection */ - phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0); return m88e1518_config(phydev); } -- 1.7.11.5

1 1

[U-Boot] [PATCH] net: phy: vitesse: Fix cis8204 RGMII_ID code
by Phil Edworthy 09 Feb '17

09 Feb '17

Commit 79e86ccb3786c8b20004db3fa10a70049456f580 "vitesse: remove duplicated argument to ||" correctly removed a redundant check. However, I believe that the original code was simply wrong, and should have been checking against RGMII_ID. To fix this and avoid similar problems in the future, use the phy_interface_is_rgmii helper function. Signed-off-by: Phil Edworthy <phil.edworthy(a)renesas.com> --- This has _not_ been tested in any way, shape or form! It was picked up when converting PHY code to use the phy_interface_is_rgmii helper function. --- drivers/net/phy/vitesse.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c index 2635b82..11f4b66 100644 --- a/drivers/net/phy/vitesse.c +++ b/drivers/net/phy/vitesse.c @@ -128,9 +128,7 @@ static int cis8204_config(struct phy_device *phydev) genphy_config_aneg(phydev); - if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) || - (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) || - (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)) + if (phy_interface_is_rgmii(phydev)) phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII); -- 2.7.4

3 2

[U-Boot] [PATCH v3 0/3] net: phy: Add Marvell M88E1512
by Phil Edworthy 09 Feb '17

09 Feb '17

These patches add support for the Marvell M88E1512 PHY. It turns out that it behaves exactly the same as 88E1518, so it's just a matter of fixing up the uid/mask. Phil Edworthy (3): net: phy: Fix mask so that we can identify Marvell 88E1518 net: phy: Add support for Marvell M88E1512 net: phy: Marvell: Use phy_interface_is_rgmii helper function drivers/net/phy/marvell.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) -- 2.7.4

3 7

[U-Boot] [PATCH] net: phy: ti: Fix dp83867 RGMII_TXID interface path
by Phil Edworthy 09 Feb '17

09 Feb '17

There is code that is specifically for RGMII_TXID interface, but this will never get used because the code checks that the RGMII interface is RGMII_ID to RGMII_RXID; RGMII_TXID is after this. To fix this and avoid similar problems in the future, use the phy_interface_is_rgmii helper function. Signed-off-by: Phil Edworthy <phil.edworthy(a)renesas.com> --- This has _not_ been tested in any way, shape or form! It was picked up when converting PHY code to use the phy_interface_is_rgmii helper function. --- drivers/net/phy/ti.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c index c55dd97..5e2b2dd 100644 --- a/drivers/net/phy/ti.c +++ b/drivers/net/phy/ti.c @@ -246,8 +246,7 @@ static int dp83867_config(struct phy_device *phydev) phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0); } - if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) && - (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) { + if (phy_interface_is_rgmii(phydev)) { val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL, DP83867_DEVADDR, phydev->addr); -- 2.7.4

3 2

[U-Boot] [PATCH v2 0/3] net: macb: Add option and clock support
by Wenyou Yang 09 Feb '17

09 Feb '17

The CONFIG_MACB option is added in KConfig to be used to select the Cadence MACB Ethernet driver, and the clock is supported. Changes in v2: - Use positive logic, #ifdef...#else...#endif. - Remove unnecessary splitting the signature of macb_mdc_clk_div() and others. - Add Acked-by tag. Wenyou Yang (3): net: Kconfig: Add CONFIG_MACB option net: macb: Add the clock support net: macb: Remove redundant #ifdef CONFIG_DM_ETH drivers/net/Kconfig | 10 ++++++++++ drivers/net/macb.c | 44 +++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 51 insertions(+), 3 deletions(-) -- 2.7.4

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[U-Boot] [PATCH 1/3] dts: rk3288: correct sdram setting for miniarm
by Jacob Chen 08 Feb '17

08 Feb '17

miniarm board use lpddr3 Signed-off-by: Jacob Chen <jacob2.chen(a)rock-chips.com> --- arch/arm/dts/rk3288-miniarm.dts | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/dts/rk3288-miniarm.dts b/arch/arm/dts/rk3288-miniarm.dts index 9083028..3dd40e6 100644 --- a/arch/arm/dts/rk3288-miniarm.dts +++ b/arch/arm/dts/rk3288-miniarm.dts @@ -17,14 +17,14 @@ }; &dmc { - rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa - 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 - 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 - 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 - 0x5 0x0>; - rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 - 0xa60 0x40 0x10 0x0>; - rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; + rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d + 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 + 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 + 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4 + 0x8 0x1f4>; + rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076 + 0x0 0xc3 0x6 0x2>; + rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>; }; -- 1.9.1

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[U-Boot] [PATCH] board: freescale: ls2080a: Intergrate and enable PPA on LS2080A
by Abhimanyu Saini 07 Feb '17

07 Feb '17

Integrate and enable PPA on LS2080ARDB, LS2080AQDS, LS2088ARDB and LS2088AQDS boards. Signed-off-by: Abhimanyu Saini <abhimanyu.saini(a)nxp.com> --- board/freescale/ls2080aqds/ls2080aqds.c | 6 ++++++ board/freescale/ls2080ardb/ls2080ardb.c | 6 ++++++ include/configs/ls2080aqds.h | 10 ++++++++++ include/configs/ls2080ardb.h | 10 ++++++++++ 4 files changed, 32 insertions(+) diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 73a61fd..811b9a6 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -19,6 +19,9 @@ #include <asm/arch/soc.h> #include <hwconfig.h> #include <fsl_sec.h> +#ifdef CONFIG_FSL_LS_PPA +#include <asm/arch/ppa.h> +#endif #include "../common/qixis.h" #include "ls2080aqds_qixis.h" @@ -223,6 +226,9 @@ int board_init(void) #endif select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); rtc_enable_32khz_output(); +#ifdef CONFIG_FSL_LS_PPA + ppa_init(); +#endif return 0; } diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 02954ef..339fa78 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -19,6 +19,9 @@ #include <i2c.h> #include <asm/arch/soc.h> #include <fsl_sec.h> +#ifdef CONFIG_FSL_LS_PPA +#include <asm/arch/ppa.h> +#endif #include "../common/qixis.h" #include "ls2080ardb_qixis.h" @@ -184,6 +187,9 @@ int board_init(void) /* invert AQR405 IRQ pins polarity */ out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK); #endif +#ifdef CONFIG_FSL_LS_PPA + ppa_init(); +#endif return 0; } diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 838568f..5573e94 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -14,6 +14,16 @@ unsigned long get_board_sys_clk(void); unsigned long get_board_ddr_clk(void); #endif +#define CONFIG_FSL_LS_PPA +#if defined(CONFIG_FSL_LS_PPA) +#define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT + +#define CONFIG_SYS_LS_PPA_FW_IN_XIP +#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP +#define CONFIG_SYS_LS_PPA_FW_ADDR 0x580a00000 +#endif +#endif + #define CONFIG_SYS_FSL_CLK #ifdef CONFIG_FSL_QSPI diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 31df781..d411a4f 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -12,6 +12,16 @@ #undef CONFIG_CONS_INDEX #define CONFIG_CONS_INDEX 2 +#define CONFIG_FSL_LS_PPA +#if defined(CONFIG_FSL_LS_PPA) +#define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT + +#define CONFIG_SYS_LS_PPA_FW_IN_XIP +#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP +#define CONFIG_SYS_LS_PPA_FW_ADDR 0x580a00000 +#endif +#endif + #define I2C_MUX_CH_VOL_MONITOR 0xa #define I2C_VOL_MONITOR_ADDR 0x38 #define CONFIG_VOL_MONITOR_IR36021_READ -- 1.9.1

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