December 2016 - U-Boot

[U-Boot] [PATCH] imgtec: Update MAINTAINERS for more config files
by Tom Rini 12 Dec '16

12 Dec '16

Cover all of the boston and malta variations. Signed-off-by: Tom Rini <trini(a)konsulko.com> --- board/imgtec/boston/MAINTAINERS | 5 ++++- board/imgtec/malta/MAINTAINERS | 2 ++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/board/imgtec/boston/MAINTAINERS b/board/imgtec/boston/MAINTAINERS index 30dd481a26db..ec850d2f9144 100644 --- a/board/imgtec/boston/MAINTAINERS +++ b/board/imgtec/boston/MAINTAINERS @@ -3,4 +3,7 @@ M: Paul Burton <paul.burton(a)imgtec.com> S: Maintained F: board/imgtec/boston/ F: include/configs/boston.h -F: configs/boston_defconfig +F: configs/boston32r2_defconfig +F: configs/boston32r2el_defconfig +F: configs/boston64r2_defconfig +F: configs/boston64r2el_defconfig diff --git a/board/imgtec/malta/MAINTAINERS b/board/imgtec/malta/MAINTAINERS index a0b3284992d7..052ec67b14f5 100644 --- a/board/imgtec/malta/MAINTAINERS +++ b/board/imgtec/malta/MAINTAINERS @@ -3,5 +3,7 @@ M: Paul Burton <paul.burton(a)imgtec.com> S: Maintained F: board/imgtec/malta/ F: include/configs/malta.h +F: configs/malta64_defconfig +F: configs/malta64el_defconfig F: configs/malta_defconfig F: configs/maltael_defconfig -- 1.9.1

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[U-Boot] [PATCH] board: topic: Detect RAM size at boot
by Mike Looijmans 12 Dec '16

12 Dec '16

Miami boards can have memory sizes of 256M, 512M or 1GB. To prevent requiring separate bootloaders for each variant, just detect the RAM size at boot time instead of relying on the devicetree information. Signed-off-by: Mike Looijmans <mike.looijmans(a)topic.nl> --- board/topic/zynq/board.c | 39 +++++++++++++++++++++++++++++++++++++++ configs/topic_miami_defconfig | 1 + configs/topic_miamiplus_defconfig | 1 + 3 files changed, 41 insertions(+) diff --git a/board/topic/zynq/board.c b/board/topic/zynq/board.c index a95c9d1..8a5765e 100644 --- a/board/topic/zynq/board.c +++ b/board/topic/zynq/board.c @@ -1 +1,40 @@ +/* + * (C) Copyright 2016 Topic Embedded Products + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Miami boards can have memory sizes of 256M, 512M or 1GB. To prevent needing + * separate bootloaders for each variant, just detect the RAM size at boot time + * instead of relying on the devicetree information. + */ +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_SYS_SDRAM_SIZE topic_get_sdram_size() +#define CONFIG_SYS_SDRAM_SIZE_MAX 0x40000000u + +static unsigned int topic_get_sdram_size(void); + #include "../../xilinx/zynq/board.c" + +#include <fdt_support.h> + +int ft_board_setup(void *blob, bd_t *bd) +{ + fdt_fixup_memory(blob, (u64)CONFIG_SYS_SDRAM_BASE, (u64)gd->ram_size); + + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; +} + +unsigned int topic_get_sdram_size(void) +{ + /* Detect and fix ram size */ + return get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE_MAX); +} diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig index 3d6161e..8a02668 100644 --- a/configs/topic_miami_defconfig +++ b/configs/topic_miami_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_EMBED=y +CONFIG_OF_BOARD_SETUP=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ZYNQ_SDHCI=y CONFIG_SPI_FLASH=y diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig index 3160f00..08bfab2 100644 --- a/configs/topic_miamiplus_defconfig +++ b/configs/topic_miamiplus_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_EMBED=y +CONFIG_OF_BOARD_SETUP=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ZYNQ_SDHCI=y CONFIG_SPI_FLASH=y -- 1.9.1

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[U-Boot] [PATCH v2 0/5] net: phy: Add Marvell M88E1512
by Phil Edworthy 12 Dec '16

12 Dec '16

These patches add support for the Marvell M88E1512 PHY. Phil Edworthy (5): net: phy: Fix mask so that we can identify Marvell 88E1518 net: phy: Add support for Marvell M88E1512 net: phy: Marvell 88E151x: Add support for RGMII net: phy: Marvell 88E151x: Increase delay after init net: phy: Marvell: Use phy_interface_is_rgmii helper function drivers/net/phy/marvell.c | 32 +++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-) -- 2.7.4

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[U-Boot] [PATCH v3 0/6] arm64: mvebu: Armada-8K family patches
by kostap＠marvell.com 12 Dec '16

12 Dec '16

From: Konstantin Porotchkin <kostap(a)marvell.com> This set of patches is adding more features for bards based on new Marvell MoChi platforms - Armada-70x0 and Armada-80x0. The patches were applied on top of Stefan's mvebu-related patch set v2 with the last patch named "dm: core: Add dev_get_addr_size_index() to retrieve addr and size". The test was done on Armada-70x0 and Armada-80x0 development boards equipped with SoC release A1. Since the SPI and I2C channels mapping between A0 and A1 releases were changed, the execution of added features on A0 boards will fail. Currently 2 major features were added: - BUBT command support - Pin controller driver for A8K family Changes for v3: - Move patch change log to comments section (all files) - Fix the bubt command implementation: - Minor syntax fixes - Replace zero function pointers with stubs - Replace board-specific macros with platform-specific ones Konstantin Porotchkin (6): arm64: mvebu: Modify the A8K SPI and I2C config in DTS arm64: mvebu: Add bubt command for flash image burn arm64: mvebu: pinctrl: Add pin control driver for A8K family arm64: mvebu: Add pin control nodes to A8K family DTS files arm64: mvebu: Enable BUBT command support in A8K default config arm64: mvebu: Enable pin control support in A8K default config arch/arm/dts/armada-7040-db.dts | 64 +- arch/arm/dts/armada-8040-db.dts | 114 ++- arch/arm/dts/armada-ap806.dtsi | 18 + arch/arm/dts/armada-cp110-master.dtsi | 32 + arch/arm/dts/armada-cp110-slave.dtsi | 19 + arch/arm/include/asm/arch-armada8k/soc-info.h | 17 + cmd/Kconfig | 3 + cmd/Makefile | 2 + cmd/mvebu/Kconfig | 52 ++ cmd/mvebu/Makefile | 8 + cmd/mvebu/bubt.c | 767 +++++++++++++++++++++ configs/mvebu_db-88f7040_defconfig | 2 + configs/mvebu_db-88f8040_defconfig | 2 + .../pinctrl/marvell,armada-apn806-pinctrl.txt | 25 + .../pinctrl/marvell,armada-cp110-pinctrl.txt | 270 ++++++++ .../pinctrl/marvell,mvebu-pinctrl.txt | 113 +++ doc/mvebu/cmd/bubt.txt | 64 ++ drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/mvebu/Kconfig | 7 + drivers/pinctrl/mvebu/Makefile | 7 + drivers/pinctrl/mvebu/pinctrl-mvebu.c | 179 +++++ drivers/pinctrl/mvebu/pinctrl-mvebu.h | 31 + 23 files changed, 1734 insertions(+), 64 deletions(-) create mode 100644 arch/arm/include/asm/arch-armada8k/soc-info.h create mode 100644 cmd/mvebu/Kconfig create mode 100644 cmd/mvebu/Makefile create mode 100644 cmd/mvebu/bubt.c create mode 100644 doc/device-tree-bindings/pinctrl/marvell,armada-apn806-pinctrl.txt create mode 100644 doc/device-tree-bindings/pinctrl/marvell,armada-cp110-pinctrl.txt create mode 100644 doc/device-tree-bindings/pinctrl/marvell,mvebu-pinctrl.txt create mode 100644 doc/mvebu/cmd/bubt.txt create mode 100644 drivers/pinctrl/mvebu/Kconfig create mode 100644 drivers/pinctrl/mvebu/Makefile create mode 100644 drivers/pinctrl/mvebu/pinctrl-mvebu.c create mode 100644 drivers/pinctrl/mvebu/pinctrl-mvebu.h -- 2.7.4

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[U-Boot] [PATCH 0/3] arm64: mvebu: Linux kernel boot support
by kostap＠marvell.com 12 Dec '16

12 Dec '16

From: Konstantin Porotchkin <kostap(a)marvell.com> This set of patches adds features for allowing Linux kernel boot and root on NFS for Marvell A8K family boards. These changes were tested when applied on top of previously sent series of patches named: "arm64: mvebu: Armada-8K family patches" version 2. Changes in this patch series: - Add support for L3 cache flush preventing from data corruption after turning off d-cache and MMU as part of the boot cleanup - Add support for PCIe on Armada-7040 DB (required for NFS support using PCIe NIC due to yet missing port for the PPv2 ETH driver) - Add hush parser support on A8K boards for allowing bootcmd configuration using CLI scripting Konstantin Porotchkin (3): arm64: mvebu: Add L3 cache flush functionality to A8K family arm64: mvebu: Enable PCIe support in Armada-7040 configuration arm64: mvebu: Enable hush parser in A8K default configuration arch/arm/include/asm/arch-armada8k/cache_llc.h | 21 ++++++++++++++ arch/arm/mach-mvebu/armada8k/Makefile | 1 + arch/arm/mach-mvebu/armada8k/cache_llc.S | 39 ++++++++++++++++++++++++++ configs/mvebu_db-88f7040_defconfig | 4 +++ configs/mvebu_db-88f8040_defconfig | 1 + 5 files changed, 66 insertions(+) create mode 100644 arch/arm/include/asm/arch-armada8k/cache_llc.h create mode 100644 arch/arm/mach-mvebu/armada8k/cache_llc.S -- 2.7.4

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[U-Boot] [PATCH v2 1/2] common: miiphyutil: Add helper function for mdio bus name
by Michal Simek 12 Dec '16

12 Dec '16

The most of ethernet drivers are using this mdio registration sequence. strcpy(priv->bus->name, "emac"); mdio_register(priv->bus); Where driver can be used only with one MDIO bus because only unique name should be used. Other drivers are using unique device name for MDIO registration to support multiple instances. snprintf(priv->bus->name, sizeof(bus->name), "%s", name); With DM dev->seq is used more even in logs (like random MAC address generation: printf("\nWarning: %s (eth%d) using random MAC address - %pM\n", dev->name, dev->seq, pdata->enetaddr); ) where eth%d prefix is used. Simplify driver code to register mdio device with dev->seq number to simplify mdio registration and reduce code duplication across all drivers. With DM_SEQ_ALIAS enabled dev->seq reflects alias setting. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> Acked-by: Joe Hershberger <joe.hershberger(a)ni.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: - Add kernel-doc format for mdio_register_seq (Reported-by: Simon) For example: Board: Xilinx Zynq Net: ZYNQ GEM: e000b000, phyaddr 7, interface rgmii-id Warning: ethernet@e000b000 (eth0) using random MAC address - 7a:fc:90:53:6a:41 eth0: ethernet@e000b000ZYNQ GEM: e000c000, phyaddr ffffffff, interface rgmii-id Warning: ethernet@e000c000 (eth3) using random MAC address - 1a:ff:d7:1a:a1:b2 , eth3: ethernet@e000c000 ** Bad device size - mmc 0 ** Checking if uenvcmd is set ... Hit any key to stop autoboot: 0 Zynq> mdio list eth0: 17 - Marvell 88E1111S <--> ethernet@e000b000 eth3: 17 - Marvell 88E1111S <--> ethernet@e000c000 Zynq> --- common/miiphyutil.c | 12 ++++++++++++ include/miiphy.h | 9 +++++++++ 2 files changed, 21 insertions(+) diff --git a/common/miiphyutil.c b/common/miiphyutil.c index aca18db52a00..8eb0f761bb01 100644 --- a/common/miiphyutil.c +++ b/common/miiphyutil.c @@ -107,6 +107,18 @@ int mdio_register(struct mii_dev *bus) return 0; } +int mdio_register_seq(struct mii_dev *bus, int seq) +{ + int ret; + + /* Setup a unique name for each mdio bus */ + ret = snprintf(bus->name, MDIO_NAME_LEN, "eth%d", seq); + if (ret < 0) + return ret; + + return mdio_register(bus); +} + int mdio_unregister(struct mii_dev *bus) { if (!bus) diff --git a/include/miiphy.h b/include/miiphy.h index 83141b4a6ae1..fe8928a3a9d0 100644 --- a/include/miiphy.h +++ b/include/miiphy.h @@ -48,6 +48,15 @@ void miiphy_listdev(void); struct mii_dev *mdio_alloc(void); void mdio_free(struct mii_dev *bus); int mdio_register(struct mii_dev *bus); + +/** + * mdio_register_seq - Register mdio bus with sequence number + * @bus: mii device structure + * @seq: sequence number + * + * Return: 0 if success, negative value if error + */ +int mdio_register_seq(struct mii_dev *bus, int seq); int mdio_unregister(struct mii_dev *bus); void mdio_list_devices(void); -- 1.9.1

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[U-Boot] [PATCH v2 0/3] Add generic FDT memory bank decoding and gd initialization
by Nathan Rossi 12 Dec '16

12 Dec '16

Currently most boards that have static memory config (which cannot be detected automatically) use CONFIG_SYS_SDRAM_SIZE to define the size of memory which is hard coded into U-Boot. With the addition of device tree support into U-Boot, boards that have device tree data can instead query the memory bank information from the embedded or appended device tree. This allows for more dynamic memory configuration and avoids the need to hard code memory configuration into U-Boot. The first patch of this series adds two helper functions for handling the memory bank decoding and initialization of global data which can be used by boards in their dram_init and dram_init_banksize functions. The purpose of these helper functions is to provide generic functions that handle the decoding and setup of memory and memory banks for boards that intend to use this mechanism. The series also changes the zynq and zynqmp board implementations to use these functions to resolve a issue with static variable use. Changes in v2: * Make fdtdec_setup_memory_banksize() return value consistent * Add more detail into the function documentation Nathan Rossi (3): fdt: add memory bank decoding functions for board setup ARM: zynq: Replace board specific with generic memory bank decoding ARM64: zynqmp: Replace board specific with generic memory bank decoding board/xilinx/zynq/board.c | 112 ++----------------------------------------- board/xilinx/zynqmp/zynqmp.c | 112 ++----------------------------------------- include/fdtdec.h | 34 +++++++++++++ lib/fdtdec.c | 54 +++++++++++++++++++++ 4 files changed, 94 insertions(+), 218 deletions(-) -- 2.10.2

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[U-Boot] [PATCH 0/3] Add generic FDT memory bank decoding and gd initialization
by Nathan Rossi 12 Dec '16

12 Dec '16

This series adds two functions for handling the memory bank decoding and initialization of global data for use by boards in their dram_init and dram_init_banksize functions. The series also changes the zynq and zynqmp board implementations to use these functions to resolve a issue with static variable use. Nathan Rossi (3): fdt: add memory bank decoding functions for board setup ARM: zynq: Replace board specific with generic memory bank decoding ARM64: zynqmp: Replace board specific with generic memory bank decoding board/xilinx/zynq/board.c | 112 ++----------------------------------------- board/xilinx/zynqmp/zynqmp.c | 112 ++----------------------------------------- include/fdtdec.h | 25 ++++++++++ lib/fdtdec.c | 54 +++++++++++++++++++++ 4 files changed, 85 insertions(+), 218 deletions(-) -- 2.10.2

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[U-Boot] post_codes in u-boot?
by Haleigh Novak 12 Dec '16

12 Dec '16

Hello All, I am currently deciphering post_code ouput on a machine running Yocto with a bios of coreboot with a payload of SeaBIOS and another (i think) u-boot, in searching online for one of the post_code values I stumbled on a post (http://lists.denx.de/pipermail/u-boot/2016-January/241577.html) noting that u-boot has post codes of its own. I was wondering if there was a consolidation of most (if not all) of the post_codes used, like there sort of is in coreboot at /src/console/post_code.h; or if there is not would someone mind giving me a direction on what function(s) u-boot uses to post the u-boot post_codes; i.e. coreboot utilizes a function called post_code as well as asm code and some of the binaries have their own post codes - is there anything like that in u-boot? Thank you for your time. HN

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[U-Boot] [PATCH] ARM: dts: tegra: Sync paz00 with Linux 4.8
by Misha Komarovskiy 11 Dec '16

11 Dec '16

Sync with Linux 4.8 dts plus vdd_bl regulator to fix backlight start, display timings and USB controller aliases fix. Signed-off-by: Misha Komarovskiy <zombah(a)gmail.com> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> Cc: Simon Glass <sjg(a)chromium.org> Cc: Tom Warren <twarren(a)nvidia.com> Cc: Stephen Warren <swarren(a)nvidia.com> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> --- arch/arm/dts/tegra20-paz00.dts | 597 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 568 insertions(+), 29 deletions(-) diff --git a/arch/arm/dts/tegra20-paz00.dts b/arch/arm/dts/tegra20-paz00.dts index cf6bd70..ecf9fbd 100644 --- a/arch/arm/dts/tegra20-paz00.dts +++ b/arch/arm/dts/tegra20-paz00.dts @@ -1,5 +1,6 @@ /dts-v1/; +#include <dt-bindings/input/input.h> #include "tegra20.dtsi" / { @@ -11,7 +12,13 @@ }; aliases { - usb0 = "/usb@c5008000"; + rtc0 = "/i2c@7000d000/tps6586x@34"; + rtc1 = "/rtc@7000e000"; + serial0 = &uarta; + serial1 = &uartc; + usb0 = "/usb@c5000000"; + usb1 = "/usb@c5004000"; + usb2 = "/usb@c5008000"; mmc0 = "/sdhci@c8000600"; mmc1 = "/sdhci@c8000000"; }; @@ -26,19 +33,475 @@ status = "okay"; rgb { status = "okay"; - nvidia,panel = <&lcd_panel>; + + nvidia,panel = <&panel>; + + display-timings { + timing@0 { + /* PAZ00 has 1024x600 */ + clock-frequency = <54030000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <24>; + hsync-len = <136>; + vback-porch = <3>; + vfront-porch = <61>; + vsync-len = <6>; + hsync-active = <1>; + }; + }; + }; + }; + + hdmi@54280000 { + status = "okay"; + + vdd-supply = <&hdmi_vdd_reg>; + pll-supply = <&hdmi_pll_reg>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) + GPIO_ACTIVE_HIGH>; + }; + }; + + pinmux@70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata", "atc", "atd", "ate", + "dap2", "gmb", "gmc", "gmd", "spia", + "spib", "spic", "spid", "spie"; + nvidia,function = "gmi"; + }; + atb { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + }; + crtp { + nvidia,pins = "crtp"; + nvidia,function = "crt"; + }; + csus { + nvidia,pins = "csus"; + nvidia,function = "pllc_out1"; + }; + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; + nvidia,function = "rsvd1"; + }; + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + gpu { + nvidia,pins = "gpu", "sdb", "sdd"; + nvidia,function = "pwm"; + }; + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + gpv { + nvidia,pins = "gpv", "slxa", "slxk"; + nvidia,function = "pcie"; + }; + hdint { + nvidia,pins = "hdint", "pta"; + nvidia,function = "hdmi"; + }; + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + irrx { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uarta"; + }; + kbca { + nvidia,pins = "kbca", "kbcc", "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + kbcb { + nvidia,pins = "kbcb", "kbcd"; + nvidia,function = "sdio2"; + }; + lcsn { + nvidia,pins = "lcsn", "ld0", "ld1", "ld2", + "ld3", "ld4", "ld5", "ld6", "ld7", + "ld8", "ld9", "ld10", "ld11", "ld12", + "ld13", "ld14", "ld15", "ld16", "ld17", + "ldc", "ldi", "lhp0", "lhp1", "lhp2", + "lhs", "lm0", "lm1", "lpp", "lpw0", + "lpw1", "lpw2", "lsc0", "lsc1", "lsck", + "lsda", "lsdi", "lspi", "lvp0", "lvp1", + "lvs"; + nvidia,function = "displaya"; + }; + owc { + nvidia,pins = "owc"; + nvidia,function = "owr"; + }; + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + sdc { + nvidia,pins = "sdc"; + nvidia,function = "twc"; + }; + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + slxc { + nvidia,pins = "slxc", "slxd"; + nvidia,function = "spi4"; + }; + spdi { + nvidia,pins = "spdi", "spdo"; + nvidia,function = "rsvd2"; + }; + spif { + nvidia,pins = "spif", "uac"; + nvidia,function = "rsvd4"; + }; + spig { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + uaa { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; + }; + uad { + nvidia,pins = "uad"; + nvidia,function = "spdif"; + }; + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + conf_ata { + nvidia,pins = "ata", "atb", "atc", "atd", "ate", + "cdev1", "cdev2", "dap1", "dap2", "dtf", + "gma", "gmb", "gmc", "gmd", "gme", + "gpu", "gpu7", "gpv", "i2cp", "pta", + "rm", "sdio1", "slxk", "spdo", "uac", + "uda"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + conf_ck32 { + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", + "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + }; + conf_crtp { + nvidia,pins = "crtp", "dap3", "dap4", "dtb", + "dtc", "dte", "slxa", "slxc", "slxd", + "spdi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_csus { + nvidia,pins = "csus", "spia", "spib", "spid", + "spif"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_ddc { + nvidia,pins = "ddc", "irrx", "irtx", "kbca", + "kbcb", "kbcc", "kbcd", "kbce", "kbcf", + "spic", "spig", "uaa", "uab"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + conf_dta { + nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd", + "spie", "spih", "uad", "uca", "ucb"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_hdint { + nvidia,pins = "hdint", "ld0", "ld1", "ld2", + "ld3", "ld4", "ld5", "ld6", "ld7", + "ld8", "ld9", "ld10", "ld11", "ld12", + "ld13", "ld14", "ld15", "ld16", "ld17", + "ldc", "ldi", "lhs", "lsc0", "lspi", + "lvs", "pmc"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + conf_lc { + nvidia,pins = "lc", "ls"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + }; + conf_lcsn { + nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2", + "lm0", "lm1", "lpp", "lpw0", "lpw1", + "lpw2", "lsc1", "lsck", "lsda", "lsdi", + "lvp0", "lvp1", "sdb"; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_ld17_0 { + nvidia,pins = "ld17_0", "ld19_18", "ld21_20", + "ld23_22"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; }; }; }; + i2s@70002800 { + status = "okay"; + }; + serial@70006000 { - clock-frequency = < 216000000 >; + status = "okay"; + }; + + serial@70006200 { + status = "okay"; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + + lvds_ddc: i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + alc5632: alc5632@1e { + compatible = "realtek,alc5632"; + reg = <0x1e>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + hdmi_ddc: i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + nvec@7000c500 { + compatible = "nvidia,nvec"; + reg = <0x7000c500 0x100>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <80000>; + request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + slave-addr = <138>; + clocks = <&tegra_car TEGRA20_CLK_I2C3>, + <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; + clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 67>; + reset-names = "i2c"; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: tps6586x@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&p5valw_reg>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + sys_reg: sys { + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + sm0 { + regulator-name = "+1.2vs_sm0,vdd_core"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + sm1 { + regulator-name = "+1.0vs_sm1,vdd_cpu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + sm2_reg: sm2 { + regulator-name = "+3.7vs_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + /* LDO0 is not connected to anything */ + + ldo1 { + regulator-name = "+1.1vs_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo2 { + regulator-name = "+1.2vs_ldo2,vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo3 { + regulator-name = "+3.3vs_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo4 { + regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo5 { + regulator-name = "+2.85vs_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo6 { + /* + * Research indicates this should be + * 1.8v; other boards that use this + * rail for the same purpose need it + * set to 1.8v. The schematic signal + * name is incorrect; perhaps copied + * from an incorrect NVIDIA reference. + */ + regulator-name = "+2.85vs_ldo6,avdd_vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + hdmi_vdd_reg: ldo7 { + regulator-name = "+3.3vs_ldo7,avdd_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + hdmi_pll_reg: ldo8 { + regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo9 { + regulator-name = "+2.85vs_ldo9,vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo_rtc { + regulator-name = "+3.3vs_rtc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + adt7461@4c { + compatible = "adi,adt7461"; + reg = <0x4c>; + }; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <0>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <0>; + nvidia,sys-clock-req-active-high; + }; + + usb@c5000000 { + status = "okay"; + }; + + usb-phy@c5000000 { + status = "okay"; + }; + + usb@c5004000 { + status = "okay"; + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) + GPIO_ACTIVE_LOW>; + }; + + usb-phy@c5004000 { + status = "okay"; + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) + GPIO_ACTIVE_LOW>; }; usb@c5008000 { status = "okay"; }; + usb-phy@c5008000 { + status = "okay"; + }; + sdhci@c8000000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>; @@ -53,6 +516,19 @@ non-removable; }; + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_bl_reg>; + pwms = <&pwm 0 5000000>; + + brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>; + default-brightness-level = <10>; + + backlight-boot-off; + }; + clocks { compatible = "simple-bus"; #address-cells = <1>; @@ -60,38 +536,101 @@ clk32k_in: clock@0 { compatible = "fixed-clock"; - reg=<0>; + reg = <0>; #clock-cells = <0>; clock-frequency = <32768>; }; }; - pwm: pwm@7000a000 { - status = "okay"; + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + wakeup-source; + }; }; - lcd_panel: panel { - /* PAZ00 has 1024x600 */ - clock = <54030000>; - xres = <1024>; - yres = <600>; - right-margin = <160>; - left-margin = <24>; - hsync-len = <136>; - upper-margin = <3>; - lower-margin = <61>; - vsync-len = <6>; - hsync-active-high; - nvidia,bits-per-pixel = <16>; - nvidia,pwm = <&pwm 0 0>; - nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(U, 4) - GPIO_ACTIVE_HIGH>; - nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(M, 6) - GPIO_ACTIVE_HIGH>; - nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0) - GPIO_ACTIVE_HIGH>; - nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(A, 4) - GPIO_ACTIVE_HIGH>; - nvidia,panel-timings = <400 4 203 17 15>; + gpio-leds { + compatible = "gpio-leds"; + + wifi { + label = "wifi-led"; + gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; + linux,default-trigger = "rfkill0"; + }; + }; + + panel: panel { + compatible = "samsung,ltn101nt05", "simple-panel"; + + ddc-i2c-bus = <&lvds_ddc>; + power-supply = <&vdd_pnl_reg>; + enable-gpios = <&gpio TEGRA_GPIO(M, 6) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + p5valw_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "+5valw"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vdd_pnl_reg: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "+3VS,vdd_pnl"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_bl_reg: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + sound { + compatible = "nvidia,tegra-audio-alc5632-paz00", + "nvidia,tegra-audio-alc5632"; + + nvidia,model = "Compal PAZ00"; + + nvidia,audio-routing = + "Int Spk", "SPKOUT", + "Int Spk", "SPKOUTN", + "Headset Mic", "MICBIAS1", + "MIC1", "Headset Mic", + "Headset Stereophone", "HPR", + "Headset Stereophone", "HPL", + "DMICDAT", "Digital Mic"; + + nvidia,audio-codec = <&alc5632>; + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) + GPIO_ACTIVE_HIGH>; + + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; }; }; -- 2.1.4

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