December 2016 - U-Boot

[U-Boot] [RFC PATCH 0/4] sunxi: add support for Allwinner V3s
by Icenowy Zheng 05 Jan '17

05 Jan '17

Hello everyone, As I received my Lichee Pi Zero board (come with Allwinner V3s), I now ported mainline u-boot to it, as I cannot bear the BSP provided by Allwinner ;-) Allwinner V3s is a low-end single-core Cortex-A7 SoC, with 64MB integrated DRAM, originally targeted on cameras. Its LQFP package and integrated DRAM makes it easily for any amateur to design and solder a board for it. This patchset contains 4 patches, they depends on the following patch: http://lists.denx.de/pipermail/u-boot/2016-December/276960.html and http://lists.denx.de/pipermail/u-boot/2016-December/276961.html . The first patch introduces DDR2 support to the H3-like DRAM controller driver in the U-Boot, which is the situation the integrated DRAM in V3s meet. The second patch adds the basic code for V3s support, and introduces the SPL for it. With this patch, the code can compile, but cannot run. The third patch introduces a "stub" device tree for V3s and the Lichee Pi Zero board. As they have now no mainline kernel support, the devicetree is only written to enable the UART on the chip. the fourth patch specially changed some memory space settings for U-Boot for V3s, which made it suitable for the 64MiB integrated DRAM.

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[U-Boot] [PATCH v2] sunxi: add support for Lichee Pi One device
by Icenowy Zheng 05 Jan '17

05 Jan '17

Lichee Pi One is a low-cost Allwinner A13 based development board, with two SD slots, a USB2.0 OTG port, a USB2.0 host port (or onboard Wi-Fi card), optional headers for LCD and CSI and two GPIO headers. Add support for this board. Signed-off-by: Icenowy Zheng <icenowy(a)aosc.xyz> --- Changes since v1: - Squashed into one patch - removed CONSOLE_MUX in defconfig arch/arm/dts/Makefile | 1 + arch/arm/dts/sun5i-a13-licheepi-one.dts | 224 ++++++++++++++++++++++++++++++++ configs/LicheePi_One_defconfig | 25 ++++ 3 files changed, 250 insertions(+) create mode 100644 arch/arm/dts/sun5i-a13-licheepi-one.dts create mode 100644 configs/LicheePi_One_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 3ee608b5b4..c1ecf72c3d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -203,6 +203,7 @@ dtb-$(CONFIG_MACH_SUN5I) += \ sun5i-a13-hsg-h702.dtb \ sun5i-a13-inet-86vs.dtb \ sun5i-a13-inet-98v-rev2.dtb \ + sun5i-a13-licheepi-one.dtb \ sun5i-a13-olinuxino.dtb \ sun5i-a13-olinuxino-micro.dtb \ sun5i-a13-q8-tablet.dtb \ diff --git a/arch/arm/dts/sun5i-a13-licheepi-one.dts b/arch/arm/dts/sun5i-a13-licheepi-one.dts new file mode 100644 index 0000000000..54d0fec858 --- /dev/null +++ b/arch/arm/dts/sun5i-a13-licheepi-one.dts @@ -0,0 +1,224 @@ +/* + * Copyright 2016 Icenowy Zheng <icenowy(a)aosc.xyz> + * + * Based on sun5i-a13-olinuxino.dts, which is + * Copyright 2012 Maxime Ripard <maxime.ripard(a)free-electrons.com> + * Copyright 2013 Hans de Goede <hdegoede(a)redhat.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-a13.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + model = "Lichee Pi One"; + compatible = "licheepi,licheepi-one", "allwinner,sun5i-a13"; + + aliases { + serial0 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + red { + label ="licheepi:red:usr"; + gpios = <&pio 2 5 GPIO_ACTIVE_LOW>; + }; + + green { + label ="licheepi:green:usr"; + gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + blue { + label ="licheepi:blue:usr"; + gpios = <&pio 2 4 GPIO_ACTIVE_LOW>; + }; + + }; +}; + +&cpu0 { + cpu-supply = <&reg_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "disabled"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "disabled"; +}; + +&lradc { + vref-supply = <&reg_ldo2>; + status = "okay"; + + button@984 { + label = "Home"; + linux,code = <KEY_HOMEPAGE>; + channel = <0>; + voltage = <984126>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>; + vmmc-supply = <&reg_vcc3v3>; + bus-width = <4>; + broken-cd; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_a>; + vmmc-supply = <&reg_vcc3v3>; + bus-width = <4>; + broken-cd; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +#include "axp209.dtsi" + +&reg_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd-cpu"; +}; + +&reg_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +&reg_ldo1 { + regulator-name = "vdd-rtc"; +}; + +&reg_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +&reg_ldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "csi-1.8v"; +}; + +&reg_ldo4 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "csi-2.8v"; +}; + +&reg_usb0_vbus { + gpio = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_b>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + pinctrl-names = "default"; + usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ + usb0_vbus-supply = <&reg_usb0_vbus>; + usb1_vbus-supply = <&reg_vcc5v0>; + status = "okay"; +}; diff --git a/configs/LicheePi_One_defconfig b/configs/LicheePi_One_defconfig new file mode 100644 index 0000000000..b14d0316e7 --- /dev/null +++ b/configs/LicheePi_One_defconfig @@ -0,0 +1,25 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_MACH_SUN5I=y +CONFIG_DRAM_CLK=408 +CONFIG_DRAM_MBUS_CLK=204 +CONFIG_DRAM_ZQ=121 +CONFIG_DRAM_ODT_EN=y +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_USB0_VBUS_PIN="PC12" +CONFIG_USB0_VBUS_DET="PG1" +CONFIG_USB0_ID_DET="PG2" +CONFIG_AXP_GPIO=y +# CONFIG_VIDEO is not set +CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-licheepi-one" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2" +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_AXP_ALDO3_VOLT=1800 +CONFIG_AXP_ALDO4_VOLT=2800 +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_MUSB_HOST=y -- 2.11.0

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[U-Boot] [PATCH 1/2] sunxi: power: add AXP803 support
by Icenowy Zheng 05 Jan '17

05 Jan '17

The A64 uses the AXP803 as its PMIC. Signed-off-by: Icenowy Zheng <icenowy(a)aosc.xyz> --- arch/arm/mach-sunxi/Makefile | 3 + arch/arm/mach-sunxi/pmic_bus.c | 6 +- arch/arm/mach-sunxi/rsb.c | 2 +- board/sunxi/board.c | 31 ++--- drivers/power/Kconfig | 87 ++++++++------ drivers/power/Makefile | 1 + drivers/power/axp803.c | 255 +++++++++++++++++++++++++++++++++++++++++ drivers/power/axp818.c | 2 +- include/axp803.h | 73 ++++++++++++ include/axp_pmic.h | 3 + 10 files changed, 413 insertions(+), 50 deletions(-) create mode 100644 drivers/power/axp803.c create mode 100644 include/axp803.h diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 128091e4e6..dcf2b5245d 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -19,9 +19,11 @@ endif obj-$(CONFIG_MACH_SUN6I) += prcm.o obj-$(CONFIG_MACH_SUN8I) += prcm.o obj-$(CONFIG_MACH_SUN9I) += prcm.o +obj-$(CONFIG_MACH_SUN50I) += prcm.o obj-$(CONFIG_MACH_SUN6I) += p2wi.o obj-$(CONFIG_MACH_SUN8I) += rsb.o obj-$(CONFIG_MACH_SUN9I) += rsb.o +obj-$(CONFIG_MACH_SUN50I) += rsb.o obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o @@ -37,6 +39,7 @@ obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o gtbus_sun9i.o obj-$(CONFIG_AXP152_POWER) += pmic_bus.o obj-$(CONFIG_AXP209_POWER) += pmic_bus.o obj-$(CONFIG_AXP221_POWER) += pmic_bus.o +obj-$(CONFIG_AXP803_POWER) += pmic_bus.o obj-$(CONFIG_AXP809_POWER) += pmic_bus.o obj-$(CONFIG_AXP818_POWER) += pmic_bus.o diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c index 7c57f02792..0ac64a97cf 100644 --- a/arch/arm/mach-sunxi/pmic_bus.c +++ b/arch/arm/mach-sunxi/pmic_bus.c @@ -36,7 +36,7 @@ int pmic_bus_init(void) if (!needs_init) return 0; -#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER +#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER # ifdef CONFIG_MACH_SUN6I p2wi_init(); ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR, @@ -62,7 +62,7 @@ int pmic_bus_read(u8 reg, u8 *data) return i2c_read(AXP152_I2C_ADDR, reg, 1, data, 1); #elif defined CONFIG_AXP209_POWER return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1); -#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER +#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER # ifdef CONFIG_MACH_SUN6I return p2wi_read(reg, data); # else @@ -77,7 +77,7 @@ int pmic_bus_write(u8 reg, u8 data) return i2c_write(AXP152_I2C_ADDR, reg, 1, &data, 1); #elif defined CONFIG_AXP209_POWER return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1); -#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER +#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER # ifdef CONFIG_MACH_SUN6I return p2wi_write(reg, data); # else diff --git a/arch/arm/mach-sunxi/rsb.c b/arch/arm/mach-sunxi/rsb.c index 6fd11f1529..28d05e962a 100644 --- a/arch/arm/mach-sunxi/rsb.c +++ b/arch/arm/mach-sunxi/rsb.c @@ -20,7 +20,7 @@ static int rsb_set_device_mode(void); static void rsb_cfg_io(void) { -#ifdef CONFIG_MACH_SUN8I +#if defined CONFIG_MACH_SUN8I || defined CONFIG_MACH_SUN50I sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB); sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB); sunxi_gpio_set_pull(SUNXI_GPL(0), 1); diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 53656383d5..3435b80c14 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -487,26 +487,27 @@ void sunxi_board_init(void) #endif #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ - defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ - defined CONFIG_AXP818_POWER + defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || \ + defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER power_failed = axp_init(); -#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ - defined CONFIG_AXP818_POWER +#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || \ + defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT); #endif power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT); power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT); -#if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER) +#if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP803_POWER) && \ + !defined(CONFIG_AXP818_POWER) power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT); #endif -#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ - defined CONFIG_AXP818_POWER +#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || \ + defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT); #endif -#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ - defined CONFIG_AXP818_POWER +#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || \ + defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT); #endif power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT); @@ -517,8 +518,8 @@ void sunxi_board_init(void) power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT); #endif -#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \ - defined(CONFIG_AXP818_POWER) +#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP803_POWER) || \ + defined(CONFIG_AXP809_POWER) || defined(CONFIG_AXP818_POWER) power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT); power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT); #if !defined CONFIG_AXP809_POWER @@ -530,13 +531,17 @@ void sunxi_board_init(void) power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT); #endif -#ifdef CONFIG_AXP818_POWER +#if defined CONFIG_AXP803_POWER || defined CONFIG_AXP818_POWER power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT); power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT); +#endif + +#ifdef CONFIG_AXP818_POWER power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT); #endif -#if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER +#if defined CONFIG_AXP803_POWER || defined CONFIG_AXP809_POWER || \ + defined CONFIG_AXP818_POWER power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON)); #endif #endif diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index f2c5629be2..e6f5903a17 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -11,8 +11,9 @@ choice depends on ARCH_SUNXI default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 + default AXP803_POWER if MACH_SUN50I default AXP818_POWER if MACH_SUN8I_A83T - default SUNXI_NO_PMIC if MACH_SUN8I_H3 || MACH_SUN50I + default SUNXI_NO_PMIC if MACH_SUN8I_H3 config SUNXI_NO_PMIC bool "board without a pmic" @@ -43,6 +44,13 @@ config AXP221_POWER Select this to enable support for the axp221/axp223 pmic found on most A23 and A31 boards. +config AXP803_POWER + bool "axp803 pmic support" + depends on MACH_SUN50I + select CMD_POWEROFF + ---help--- + Say y here to enable support for the axp803 pmic found on A64 boards. + config AXP809_POWER bool "axp809 pmic support" depends on MACH_SUN9I @@ -69,25 +77,25 @@ endchoice config AXP_DCDC1_VOLT int "axp pmic dcdc1 voltage" - depends on AXP221_POWER || AXP809_POWER || AXP818_POWER - default 3300 if AXP818_POWER + depends on AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER + default 3300 if AXP818_POWER || MACH_SUN50I default 3000 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I ---help--- Set the voltage (mV) to program the axp pmic dcdc1 at, set to 0 to disable dcdc1. On A23 / A31 / A33 (axp221) boards dcdc1 is used for generic 3.3V IO voltage for external devices like the lcd-panal and sdcard interfaces, etc. On most boards dcdc1 is undervolted to 3.0V to - save battery. On A31 devices dcdc1 is also used for VCC-IO. On A83T - dcdc1 is used for VCC-IO, nand, usb0, sd , etc. On A80 dcdc1 normally - powers some of the pingroups, NAND/eMMC, SD/MMC, and USB OTG. + save battery. On A31 devices dcdc1 is also used for VCC-IO. On A83T and + A64 dcdc1 is used for VCC-IO, nand, usb0, sd , etc. On A80 dcdc1 + normally powers some of the pingroups, NAND/eMMC, SD/MMC, and USB OTG. config AXP_DCDC2_VOLT int "axp pmic dcdc2 voltage" - depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER + depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER default 900 if AXP818_POWER default 1400 if AXP152_POWER || AXP209_POWER default 1200 if MACH_SUN6I - default 1100 if MACH_SUN8I + default 1100 if MACH_SUN8I || MACH_SUN50I default 0 if MACH_SUN9I ---help--- Set the voltage (mV) to program the axp pmic dcdc2 at, set to 0 to @@ -97,15 +105,17 @@ config AXP_DCDC2_VOLT On A23/A33 boards dcdc2 is used for VDD-SYS and should be 1.1V. On A80 boards dcdc2 powers the GPU and can be left off. On A83T boards dcdc2 is used for VDD-CPUA(cluster 0) and should be 0.9V. + On A64 boards dcdc2 is used with dcdc3 for VDD-CPU and should be 1.1V. config AXP_DCDC3_VOLT int "axp pmic dcdc3 voltage" - depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER + depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER default 900 if AXP809_POWER || AXP818_POWER default 1500 if AXP152_POWER default 1250 if AXP209_POWER default 1200 if MACH_SUN6I || MACH_SUN8I - ---help--- + default 1100 if MACH_SUN50I +---help--- Set the voltage (mV) to program the axp pmic dcdc3 at, set to 0 to disable dcdc3. On A10(s) / A13 / A20 boards with an axp209 dcdc3 is VDD-INT-DLL and @@ -114,39 +124,42 @@ config AXP_DCDC3_VOLT On A23 / A31 / A33 boards dcdc3 is VDD-CPU and should be 1.2V. On A80 boards dcdc3 is used for VDD-CPUA(cluster 0) and should be 0.9V. On A83T boards dcdc3 is used for VDD-CPUB(cluster 1) and should be 0.9V. + On A64 boards dcdc3 is used with dcdc2 for VDD-CPU and should be 1.1V. config AXP_DCDC4_VOLT int "axp pmic dcdc4 voltage" - depends on AXP152_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER + depends on AXP152_POWER || AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER default 1250 if AXP152_POWER default 1200 if MACH_SUN6I default 0 if MACH_SUN8I default 900 if MACH_SUN9I + default 0 if MACH_SUN50I ---help--- Set the voltage (mV) to program the axp pmic dcdc4 at, set to 0 to disable dcdc4. On A10s boards with an axp152 dcdc4 is VDD-INT-DLL and should be 1.25V. On A31 boards dcdc4 is used for VDD-SYS and should be 1.2V. - On A23 / A33 boards dcdc4 is unused and should be disabled. + On A23 / A33 / A64 boards dcdc4 is unused and should be disabled. On A80 boards dcdc4 powers VDD-SYS, HDMI, USB OTG and should be 0.9V. On A83T boards dcdc4 is used for VDD-GPU. config AXP_DCDC5_VOLT int "axp pmic dcdc5 voltage" - depends on AXP221_POWER || AXP809_POWER || AXP818_POWER - default 1500 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I + depends on AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER + default 1500 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I || MACH_SUN50I ---help--- Set the voltage (mV) to program the axp pmic dcdc5 at, set to 0 to disable dcdc5. - On A23 / A31 / A33 / A80 / A83T boards dcdc5 is VCC-DRAM and + On A23 / A31 / A33 / A64 / A80 / A83T boards dcdc5 is VCC-DRAM and should be 1.5V, 1.35V if DDR3L is used. config AXP_ALDO1_VOLT int "axp pmic (a)ldo1 voltage" - depends on AXP221_POWER || AXP809_POWER || AXP818_POWER + depends on AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER default 0 if MACH_SUN6I default 1800 if MACH_SUN8I_A83T default 3000 if MACH_SUN8I || MACH_SUN9I + default 2800 if MACH_SUN50I ---help--- Set the voltage (mV) to program the axp pmic aldo1 at, set to 0 to disable aldo1. @@ -155,14 +168,16 @@ config AXP_ALDO1_VOLT On A80 boards aldo1 powers the USB hosts and should be 3.0V. On A83T / H8 boards aldo1 is used for MIPI CSI, DSI, HDMI, EFUSE, and should be 1.8V. + On A64 boards aldo1 powers PE pingroup and CSI and should be 2.8V. config AXP_ALDO2_VOLT int "axp pmic (a)ldo2 voltage" - depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER + depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER default 3000 if AXP152_POWER || AXP209_POWER default 0 if MACH_SUN6I || MACH_SUN9I default 1800 if MACH_SUN8I_A83T default 2500 if MACH_SUN8I + default 1800 if MACH_SUN50I ---help--- Set the voltage (mV) to program the axp pmic aldo2 at, set to 0 to disable aldo2. @@ -173,17 +188,19 @@ config AXP_ALDO2_VOLT On A80 boards aldo2 powers PB pingroup and camera IO and can be left off. On A83T / H8 boards aldo2 powers VDD-DLL, VCC18-PLL, CPVDD, VDD18-ADC, LPDDR2, and the codec. It should be 1.8V. + On A64 boards aldo2 powers PL pingroup and should be 1.8V. config AXP_ALDO3_VOLT int "axp pmic (a)ldo3 voltage" - depends on AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER + depends on AXP209_POWER || AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER default 0 if AXP209_POWER || MACH_SUN9I - default 3000 if MACH_SUN6I || MACH_SUN8I + default 3000 if MACH_SUN6I || MACH_SUN8I || MACH_SUN50I ---help--- Set the voltage (mV) to program the axp pmic aldo3 at, set to 0 to disable aldo3. On A10(s) / A13 / A20 boards aldo3 should be 2.8V. - On A23 / A31 / A33 boards aldo3 is VCC-PLL and AVCC and should be 3.0V. + On A23 / A31 / A33 / A64 boards aldo3 is VCC-PLL and AVCC + and should be 3.0V. On A80 boards aldo3 is normally not used. On A83T / H8 boards aldo3 is AVCC, VCC-PL, and VCC-LED, and should be 3.0V. @@ -199,17 +216,19 @@ config AXP_ALDO4_VOLT config AXP_DLDO1_VOLT int "axp pmic dldo1 voltage" - depends on AXP221_POWER || AXP809_POWER || AXP818_POWER + depends on AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER + default 3300 if MACH_SUN50I default 0 ---help--- Set the voltage (mV) to program the axp pmic dldo1 at, set to 0 to disable dldo1. On sun6i (A31) boards with ethernet dldo1 is often used to power the ethernet phy. On A23, A33 and A80 boards this is often - used to power the wifi. + used to power the wifi. On A64 boards this is often used to power the + HDMI. config AXP_DLDO2_VOLT int "axp pmic dldo2 voltage" - depends on AXP221_POWER || AXP809_POWER || AXP818_POWER + depends on AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER default 3000 if MACH_SUN9I default 0 ---help--- @@ -219,7 +238,7 @@ config AXP_DLDO2_VOLT config AXP_DLDO3_VOLT int "axp pmic dldo3 voltage" - depends on AXP221_POWER || AXP818_POWER + depends on AXP221_POWER || AXP803_POWER || AXP818_POWER default 0 ---help--- Set the voltage (mV) to program the axp pmic dldo3 at, set to 0 to @@ -227,7 +246,7 @@ config AXP_DLDO3_VOLT config AXP_DLDO4_VOLT int "axp pmic dldo4 voltage" - depends on AXP221_POWER || AXP818_POWER + depends on AXP221_POWER || AXP803_POWER || AXP818_POWER default 0 ---help--- Set the voltage (mV) to program the axp pmic dldo4 at, set to 0 to @@ -235,15 +254,17 @@ config AXP_DLDO4_VOLT config AXP_ELDO1_VOLT int "axp pmic eldo1 voltage" - depends on AXP221_POWER || AXP809_POWER || AXP818_POWER + depends on AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER + default 1800 if MACH_SUN50I default 0 ---help--- Set the voltage (mV) to program the axp pmic eldo1 at, set to 0 to disable eldo1. + On A64 boards it's used for the codec and should be 1.8V. config AXP_ELDO2_VOLT int "axp pmic eldo2 voltage" - depends on AXP221_POWER || AXP809_POWER || AXP818_POWER + depends on AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER default 0 ---help--- Set the voltage (mV) to program the axp pmic eldo2 at, set to 0 to @@ -251,7 +272,7 @@ config AXP_ELDO2_VOLT config AXP_ELDO3_VOLT int "axp pmic eldo3 voltage" - depends on AXP221_POWER || AXP809_POWER || AXP818_POWER + depends on AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER default 3000 if MACH_SUN9I default 0 ---help--- @@ -263,8 +284,8 @@ config AXP_ELDO3_VOLT config AXP_FLDO1_VOLT int "axp pmic fldo1 voltage" - depends on AXP818_POWER - default 0 if MACH_SUN8I_A83T + depends on AXP803_POWER || AXP818_POWER + default 0 ---help--- Set the voltage (mV) to program the axp pmic fldo1 at, set to 0 to disable fldo1. @@ -273,11 +294,13 @@ config AXP_FLDO1_VOLT config AXP_FLDO2_VOLT int "axp pmic fldo2 voltage" - depends on AXP818_POWER + depends on AXP803_POWER || AXP818_POWER + default 1100 if MACH_SUN50I default 900 if MACH_SUN8I_A83T ---help--- Set the voltage (mV) to program the axp pmic fldo2 at, set to 0 to disable fldo2. + On A64 boards fldo2 is VCC-CPUS and should be 1.1V. On A83T / H8 boards fldo2 is VCC-CPUS and should be 0.9V. config AXP_FLDO3_VOLT @@ -290,7 +313,7 @@ config AXP_FLDO3_VOLT config AXP_SW_ON bool "axp pmic sw on" - depends on AXP809_POWER || AXP818_POWER + depends on AXP803_POWER || AXP809_POWER || AXP818_POWER default n ---help--- Enable to turn on axp pmic sw. diff --git a/drivers/power/Makefile b/drivers/power/Makefile index b43523e628..1449e875ce 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_AS3722_POWER) += as3722.o obj-$(CONFIG_AXP152_POWER) += axp152.o obj-$(CONFIG_AXP209_POWER) += axp209.o obj-$(CONFIG_AXP221_POWER) += axp221.o +obj-$(CONFIG_AXP803_POWER) += axp803.o obj-$(CONFIG_AXP809_POWER) += axp809.o obj-$(CONFIG_AXP818_POWER) += axp818.o obj-$(CONFIG_EXYNOS_TMU) += exynos-tmu.o diff --git a/drivers/power/axp803.c b/drivers/power/axp803.c new file mode 100644 index 0000000000..ac65a5c7ec --- /dev/null +++ b/drivers/power/axp803.c @@ -0,0 +1,255 @@ +/* + * AXP803 driver based on AXP818 driver + * + * Based on axp818.c + * (C) Copyright 2015 Vishnu Patekar <vishnuptekar0510(a)gmail.com> + * + * Based on axp221.c + * (C) Copyright 2014 Hans de Goede <hdegoede(a)redhat.com> + * (C) Copyright 2013 Oliver Schinagl <oliver(a)schinagl.nl> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <asm/arch/gpio.h> +#include <asm/arch/pmic_bus.h> +#include <axp_pmic.h> + +static u8 axp803_mvolt_to_cfg(int mvolt, int min, int max, int div) +{ + if (mvolt < min) + mvolt = min; + else if (mvolt > max) + mvolt = max; + + return (mvolt - min) / div; +} + +int axp_set_dcdc1(unsigned int mvolt) +{ + int ret; + u8 cfg = axp803_mvolt_to_cfg(mvolt, 1600, 3400, 100); + + if (mvolt == 0) + return pmic_bus_clrbits(AXP803_OUTPUT_CTRL1, + AXP803_OUTPUT_CTRL1_DCDC1_EN); + + ret = pmic_bus_write(AXP803_DCDC1_CTRL, cfg); + if (ret) + return ret; + + return pmic_bus_setbits(AXP803_OUTPUT_CTRL1, + AXP803_OUTPUT_CTRL1_DCDC1_EN); +} + +int axp_set_dcdc2(unsigned int mvolt) +{ + int ret; + u8 cfg; + + if (mvolt >= 1220) + cfg = 70 + axp803_mvolt_to_cfg(mvolt, 1220, 1300, 20); + else + cfg = axp803_mvolt_to_cfg(mvolt, 500, 1200, 10); + + if (mvolt == 0) + return pmic_bus_clrbits(AXP803_OUTPUT_CTRL1, + AXP803_OUTPUT_CTRL1_DCDC2_EN); + + ret = pmic_bus_write(AXP803_DCDC2_CTRL, cfg); + if (ret) + return ret; + + return pmic_bus_setbits(AXP803_OUTPUT_CTRL1, + AXP803_OUTPUT_CTRL1_DCDC2_EN); +} + +int axp_set_dcdc3(unsigned int mvolt) +{ + int ret; + u8 cfg; + + if (mvolt >= 1220) + cfg = 70 + axp803_mvolt_to_cfg(mvolt, 1220, 1300, 20); + else + cfg = axp803_mvolt_to_cfg(mvolt, 500, 1200, 10); + + if (mvolt == 0) + return pmic_bus_clrbits(AXP803_OUTPUT_CTRL1, + AXP803_OUTPUT_CTRL1_DCDC3_EN); + + ret = pmic_bus_write(AXP803_DCDC3_CTRL, cfg); + if (ret) + return ret; + + return pmic_bus_setbits(AXP803_OUTPUT_CTRL1, + AXP803_OUTPUT_CTRL1_DCDC3_EN); +} + +int axp_set_dcdc5(unsigned int mvolt) +{ + int ret; + u8 cfg; + + if (mvolt >= 1140) + cfg = 32 + axp803_mvolt_to_cfg(mvolt, 1140, 1840, 20); + else + cfg = axp803_mvolt_to_cfg(mvolt, 800, 1120, 10); + + if (mvolt == 0) + return pmic_bus_clrbits(AXP803_OUTPUT_CTRL1, + AXP803_OUTPUT_CTRL1_DCDC5_EN); + + ret = pmic_bus_write(AXP803_DCDC5_CTRL, cfg); + if (ret) + return ret; + + return pmic_bus_setbits(AXP803_OUTPUT_CTRL1, + AXP803_OUTPUT_CTRL1_DCDC5_EN); +} + +int axp_set_aldo(int aldo_num, unsigned int mvolt) +{ + int ret; + u8 cfg; + + if (aldo_num < 1 || aldo_num > 3) + return -EINVAL; + + if (mvolt == 0) + return pmic_bus_clrbits(AXP803_OUTPUT_CTRL3, + AXP803_OUTPUT_CTRL3_ALDO1_EN << (aldo_num - 1)); + + cfg = axp803_mvolt_to_cfg(mvolt, 700, 3300, 100); + ret = pmic_bus_write(AXP803_ALDO1_CTRL + (aldo_num - 1), cfg); + if (ret) + return ret; + + return pmic_bus_setbits(AXP803_OUTPUT_CTRL3, + AXP803_OUTPUT_CTRL3_ALDO1_EN << (aldo_num - 1)); +} + +/* TODO: re-work other AXP drivers to consolidate ALDO functions. */ +int axp_set_aldo1(unsigned int mvolt) +{ + return axp_set_aldo(1, mvolt); +} + +int axp_set_aldo2(unsigned int mvolt) +{ + return axp_set_aldo(2, mvolt); +} + +int axp_set_aldo3(unsigned int mvolt) +{ + return axp_set_aldo(3, mvolt); +} + +int axp_set_dldo(int dldo_num, unsigned int mvolt) +{ + int ret; + u8 cfg; + + if (dldo_num < 1 || dldo_num > 4) + return -EINVAL; + + if (mvolt == 0) + return pmic_bus_clrbits(AXP803_OUTPUT_CTRL2, + AXP803_OUTPUT_CTRL2_DLDO1_EN << (dldo_num - 1)); + + cfg = axp803_mvolt_to_cfg(mvolt, 700, 3300, 100); + if (dldo_num == 2 && mvolt > 3300) + cfg += 1 + axp803_mvolt_to_cfg(mvolt, 3400, 4200, 200); + ret = pmic_bus_write(AXP803_DLDO1_CTRL + (dldo_num - 1), cfg); + if (ret) + return ret; + + return pmic_bus_setbits(AXP803_OUTPUT_CTRL2, + AXP803_OUTPUT_CTRL2_DLDO1_EN << (dldo_num - 1)); +} + +int axp_set_eldo(int eldo_num, unsigned int mvolt) +{ + int ret; + u8 cfg; + + if (eldo_num < 1 || eldo_num > 3) + return -EINVAL; + + if (mvolt == 0) + return pmic_bus_clrbits(AXP803_OUTPUT_CTRL2, + AXP803_OUTPUT_CTRL2_ELDO1_EN << (eldo_num - 1)); + + cfg = axp803_mvolt_to_cfg(mvolt, 700, 1900, 50); + ret = pmic_bus_write(AXP803_ELDO1_CTRL + (eldo_num - 1), cfg); + if (ret) + return ret; + + return pmic_bus_setbits(AXP803_OUTPUT_CTRL2, + AXP803_OUTPUT_CTRL2_ELDO1_EN << (eldo_num - 1)); +} + +int axp_set_fldo(int fldo_num, unsigned int mvolt) +{ + int ret; + u8 cfg; + + if (fldo_num < 1 || fldo_num > 2) + return -EINVAL; + + if (mvolt == 0) + return pmic_bus_clrbits(AXP803_OUTPUT_CTRL3, + AXP803_OUTPUT_CTRL3_FLDO1_EN << (fldo_num - 1)); + + cfg = axp803_mvolt_to_cfg(mvolt, 700, 1450, 50); + ret = pmic_bus_write(AXP803_FLDO1_CTRL + (fldo_num - 1), cfg); + if (ret) + return ret; + + return pmic_bus_setbits(AXP803_OUTPUT_CTRL3, + AXP803_OUTPUT_CTRL3_FLDO1_EN << (fldo_num - 1)); +} + +int axp_set_sw(bool on) +{ + if (on) + return pmic_bus_setbits(AXP803_OUTPUT_CTRL2, + AXP803_OUTPUT_CTRL2_SW_EN); + + return pmic_bus_clrbits(AXP803_OUTPUT_CTRL2, + AXP803_OUTPUT_CTRL2_SW_EN); +} + +int axp_init(void) +{ + u8 axp_chip_id; + int ret; + + ret = pmic_bus_init(); + if (ret) + return ret; + + ret = pmic_bus_read(AXP803_CHIP_ID, &axp_chip_id); + if (ret) + return ret; + + if (!(axp_chip_id == 0x51)) + return -ENODEV; + else + return ret; + + return 0; +} + +int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + pmic_bus_write(AXP803_SHUTDOWN, AXP803_SHUTDOWN_POWEROFF); + + /* infinite loop during shutdown */ + while (1) {} + + /* not reached */ + return 0; +} diff --git a/drivers/power/axp818.c b/drivers/power/axp818.c index af4d7a6903..ad0c330ca5 100644 --- a/drivers/power/axp818.c +++ b/drivers/power/axp818.c @@ -162,7 +162,7 @@ int axp_set_dldo(int dldo_num, unsigned int mvolt) cfg = axp818_mvolt_to_cfg(mvolt, 700, 3300, 100); if (dldo_num == 2 && mvolt > 3300) cfg += 1 + axp818_mvolt_to_cfg(mvolt, 3400, 4200, 200); - ret = pmic_bus_write(AXP818_ELDO1_CTRL + (dldo_num - 1), cfg); + ret = pmic_bus_write(AXP818_DLDO1_CTRL + (dldo_num - 1), cfg); if (ret) return ret; diff --git a/include/axp803.h b/include/axp803.h new file mode 100644 index 0000000000..b382f3a5ec --- /dev/null +++ b/include/axp803.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2016 Icenowy Zheng <icenowy(a)aosc.xyz> + * + * Based on axp818.h, which is: + * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510(a)gmail.com> + * + * X-Powers AXP803 Power Management IC driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define AXP803_CHIP_ID 0x03 + +#define AXP803_OUTPUT_CTRL1 0x10 +#define AXP803_OUTPUT_CTRL1_DCDC1_EN (1 << 0) +#define AXP803_OUTPUT_CTRL1_DCDC2_EN (1 << 1) +#define AXP803_OUTPUT_CTRL1_DCDC3_EN (1 << 2) +#define AXP803_OUTPUT_CTRL1_DCDC4_EN (1 << 3) +#define AXP803_OUTPUT_CTRL1_DCDC5_EN (1 << 4) +#define AXP803_OUTPUT_CTRL1_DCDC6_EN (1 << 5) +#define AXP803_OUTPUT_CTRL2 0x12 +#define AXP803_OUTPUT_CTRL2_ELDO1_EN (1 << 0) +#define AXP803_OUTPUT_CTRL2_ELDO2_EN (1 << 1) +#define AXP803_OUTPUT_CTRL2_ELDO3_EN (1 << 2) +#define AXP803_OUTPUT_CTRL2_DLDO1_EN (1 << 3) +#define AXP803_OUTPUT_CTRL2_DLDO2_EN (1 << 4) +#define AXP803_OUTPUT_CTRL2_DLDO3_EN (1 << 5) +#define AXP803_OUTPUT_CTRL2_DLDO4_EN (1 << 6) +#define AXP803_OUTPUT_CTRL2_SW_EN (1 << 7) +#define AXP803_OUTPUT_CTRL3 0x13 +#define AXP803_OUTPUT_CTRL3_FLDO1_EN (1 << 2) +#define AXP803_OUTPUT_CTRL3_FLDO2_EN (1 << 3) +#define AXP803_OUTPUT_CTRL3_ALDO1_EN (1 << 5) +#define AXP803_OUTPUT_CTRL3_ALDO2_EN (1 << 6) +#define AXP803_OUTPUT_CTRL3_ALDO3_EN (1 << 7) + +#define AXP803_DLDO1_CTRL 0x15 +#define AXP803_DLDO2_CTRL 0x16 +#define AXP803_DLDO3_CTRL 0x17 +#define AXP803_DLDO4_CTRL 0x18 +#define AXP803_ELDO1_CTRL 0x19 +#define AXP803_ELDO2_CTRL 0x1a +#define AXP803_ELDO3_CTRL 0x1b +#define AXP803_FLDO1_CTRL 0x1c +#define AXP803_FLDO2_CTRL 0x1d +#define AXP803_DCDC1_CTRL 0x20 +#define AXP803_DCDC2_CTRL 0x21 +#define AXP803_DCDC3_CTRL 0x22 +#define AXP803_DCDC4_CTRL 0x23 +#define AXP803_DCDC5_CTRL 0x24 +#define AXP803_DCDC6_CTRL 0x25 + +#define AXP803_ALDO1_CTRL 0x28 +#define AXP803_ALDO2_CTRL 0x29 +#define AXP803_ALDO3_CTRL 0x2a + +#define AXP803_SHUTDOWN 0x32 +#define AXP803_SHUTDOWN_POWEROFF (1 << 7) + +/* For axp_gpio.c */ +#define AXP_POWER_STATUS 0x00 +#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5) +#define AXP_VBUS_IPSOUT 0x30 +#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2) +#define AXP_MISC_CTRL 0x8f +#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4) +#define AXP_GPIO0_CTRL 0x90 +#define AXP_GPIO1_CTRL 0x92 +#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */ +#define AXP_GPIO_CTRL_OUTPUT_HIGH 0x01 /* Drive pin high */ +#define AXP_GPIO_CTRL_INPUT 0x02 /* Input */ +#define AXP_GPIO_STATE 0x94 +#define AXP_GPIO_STATE_OFFSET 0 diff --git a/include/axp_pmic.h b/include/axp_pmic.h index d789ad8086..8cb4d5763c 100644 --- a/include/axp_pmic.h +++ b/include/axp_pmic.h @@ -16,6 +16,9 @@ #ifdef CONFIG_AXP221_POWER #include <axp221.h> #endif +#ifdef CONFIG_AXP803_POWER +#include <axp803.h> +#endif #ifdef CONFIG_AXP809_POWER #include <axp809.h> #endif -- 2.11.0

2 3

[U-Boot] [PATCH 00/24] Lift mpc85xx config options to Kconfig
by York Sun 05 Jan '17

05 Jan '17

In this set, more mpc85xx config options are moved into Kconfig, including some shared configuration for DDR, crypto, mmc, etc. York Sun (24): powerpc: E500: Move CONFIG_E500 and CONFIG_E500MC to Kconfig powerpc: mpc85xx: Move CONFIG_SYS_NUM_TLBCAMS to Kconfig powerpc: mpc85xx: Move CONFIG_SYS_PPC_E500_DEBUG_TLB to Kconfig crypto: Move SYS_FSL_SEC_COMPAT into driver Kconfig crypto: Move CONFIG_SYS_FSL_SEC_LE and _BE to Kconfig powerpc: mpc85xx: Remove variant SoCs T1020/T1022/T1013/T1014 powerpc: T1023RDB: Remove macro CONFIG_T1023RDB powerpc: T1024RDB: Remove macro CONFIG_T1024RDB powerpc: T1040QDS: Remove macro CONFIG_T1040QDS powerpc: T2080QDS: Remove macro T2080QDS powerpc: T2080RDB: Remove macro CONFIG_T2080RDB powerpc: T2081QDS: Remove macro T2081QDS powerpc: T104xQDS: Remove macro CONFIG_T104xD4QDS fsl_ddr: Move DDR config options to driver Kconfig arm: layerscape: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig mmc: move CONFIG_SYS_FSL_ERRATUM_ESDHC* to Kconfig powerpc: mpc85xx: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig ddr: fsl: Move macro CONFIG_NUM_DDR_CONTROLLERS to Kconfig ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and CONFIG_SYS_NUM_DDR_CTRLS ddr: fsl: Move CONFIG_SYS_FSL_DDR_VER to Kconfig powerpc: mpc85xx: Remove unused ifdef in config header powerpc: E6500: Move macro CONFIG_E6500 to Kconfig powerpc: mpc85xx: Move CONFIG_SYS_FSL_QORIQ_CHASSIS* to Kconfig powerpc: mpc85xx: Move macro CONFIG_SYS_PPC64 to Kconfig README | 9 - arch/arm/Kconfig | 14 + arch/arm/cpu/armv7/ls102xa/Kconfig | 61 +- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 87 ++- arch/arm/include/asm/arch-fsl-layerscape/config.h | 30 +- arch/arm/include/asm/arch-ls102xa/config.h | 6 - arch/powerpc/Kconfig | 7 + arch/powerpc/cpu/mpc83xx/Kconfig | 6 + arch/powerpc/cpu/mpc85xx/Kconfig | 648 +++++++++++++++++++++- arch/powerpc/cpu/mpc85xx/Makefile | 4 - arch/powerpc/cpu/mpc85xx/cmd_errata.c | 2 +- arch/powerpc/cpu/mpc85xx/cpu.c | 22 +- arch/powerpc/cpu/mpc85xx/cpu_init.c | 18 +- arch/powerpc/cpu/mpc86xx/Kconfig | 4 + arch/powerpc/include/asm/config.h | 11 - arch/powerpc/include/asm/config_mpc85xx.h | 331 +---------- arch/powerpc/include/asm/config_mpc86xx.h | 2 - arch/powerpc/include/asm/fsl_secure_boot.h | 7 +- arch/powerpc/include/asm/immap_85xx.h | 6 +- board/freescale/b4860qds/ddr.c | 4 +- board/freescale/corenet_ds/ddr.c | 6 +- board/freescale/t102xrdb/Makefile | 2 +- board/freescale/t102xrdb/ddr.c | 2 +- board/freescale/t102xrdb/eth_t102xrdb.c | 10 +- board/freescale/t102xrdb/t102xrdb.c | 22 +- board/freescale/t102xrdb/t102xrdb.h | 2 +- board/freescale/t208xqds/Makefile | 4 +- board/freescale/t208xqds/eth_t208xqds.c | 32 +- board/freescale/t208xqds/t208xqds.c | 8 +- board/freescale/t208xrdb/Makefile | 2 +- configs/MPC8349EMDS_defconfig | 1 + configs/MPC8536DS_36BIT_defconfig | 1 + configs/MPC8536DS_SDCARD_defconfig | 1 + configs/MPC8536DS_SPIFLASH_defconfig | 1 + configs/MPC8536DS_defconfig | 1 + configs/MPC8548CDS_36BIT_defconfig | 1 + configs/MPC8548CDS_defconfig | 1 + configs/MPC8548CDS_legacy_defconfig | 1 + configs/MPC8572DS_36BIT_defconfig | 1 + configs/MPC8572DS_defconfig | 1 + configs/MPC8610HPCD_defconfig | 1 + configs/MPC8641HPCN_36BIT_defconfig | 1 + configs/MPC8641HPCN_defconfig | 1 + configs/T1023RDB_NAND_defconfig | 3 +- configs/T1023RDB_SDCARD_defconfig | 3 +- configs/T1023RDB_SECURE_BOOT_defconfig | 2 +- configs/T1023RDB_SPIFLASH_defconfig | 3 +- configs/T1023RDB_defconfig | 2 +- configs/T1024QDS_DDR4_SECURE_BOOT_defconfig | 2 +- configs/T1024QDS_DDR4_defconfig | 2 +- configs/T1024QDS_NAND_defconfig | 1 + configs/T1024QDS_SDCARD_defconfig | 1 + configs/T1024QDS_SECURE_BOOT_defconfig | 1 + configs/T1024QDS_SPIFLASH_defconfig | 1 + configs/T1024QDS_defconfig | 1 + configs/T1024RDB_NAND_defconfig | 3 +- configs/T1024RDB_SDCARD_defconfig | 3 +- configs/T1024RDB_SECURE_BOOT_defconfig | 2 +- configs/T1024RDB_SPIFLASH_defconfig | 3 +- configs/T1024RDB_defconfig | 2 +- configs/T1040D4RDB_NAND_defconfig | 3 +- configs/T1040D4RDB_SDCARD_defconfig | 3 +- configs/T1040D4RDB_SECURE_BOOT_defconfig | 2 +- configs/T1040D4RDB_SPIFLASH_defconfig | 3 +- configs/T1040D4RDB_defconfig | 2 +- configs/T1040QDS_DDR4_defconfig | 2 +- configs/T1040QDS_SECURE_BOOT_defconfig | 1 + configs/T1040QDS_defconfig | 1 + configs/T1040RDB_NAND_defconfig | 1 + configs/T1040RDB_SDCARD_defconfig | 1 + configs/T1040RDB_SECURE_BOOT_defconfig | 1 + configs/T1040RDB_SPIFLASH_defconfig | 1 + configs/T1040RDB_defconfig | 1 + configs/T1042D4RDB_NAND_defconfig | 3 +- configs/T1042D4RDB_SDCARD_defconfig | 3 +- configs/T1042D4RDB_SECURE_BOOT_defconfig | 2 +- configs/T1042D4RDB_SPIFLASH_defconfig | 3 +- configs/T1042D4RDB_defconfig | 2 +- configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig | 1 + configs/T1042RDB_PI_NAND_defconfig | 1 + configs/T1042RDB_PI_SDCARD_defconfig | 1 + configs/T1042RDB_PI_SPIFLASH_defconfig | 1 + configs/T1042RDB_PI_defconfig | 1 + configs/T1042RDB_SECURE_BOOT_defconfig | 1 + configs/T1042RDB_defconfig | 1 + configs/ls1046aqds_defconfig | 1 - configs/ls1046aqds_nand_defconfig | 2 +- configs/ls1046aqds_qspi_defconfig | 1 - configs/ls1046aqds_sdcard_ifc_defconfig | 2 +- configs/ls1046aqds_sdcard_qspi_defconfig | 2 +- configs/ls1046ardb_emmc_defconfig | 2 +- configs/ls1046ardb_qspi_defconfig | 1 - configs/ls1046ardb_sdcard_defconfig | 2 +- configs/ls2080a_emu_defconfig | 2 +- configs/ls2080aqds_SECURE_BOOT_defconfig | 2 +- configs/ls2080aqds_defconfig | 2 +- configs/ls2080aqds_nand_defconfig | 2 +- configs/ls2080aqds_qspi_defconfig | 2 +- configs/ls2080ardb_SECURE_BOOT_defconfig | 2 +- configs/ls2080ardb_defconfig | 3 +- configs/ls2080ardb_nand_defconfig | 2 +- configs/sbc8548_PCI_33_PCIE_defconfig | 1 + configs/sbc8548_PCI_33_defconfig | 1 + configs/sbc8548_PCI_66_PCIE_defconfig | 1 + configs/sbc8548_PCI_66_defconfig | 1 + configs/sbc8548_defconfig | 1 + configs/xpedite517x_defconfig | 1 + configs/xpedite520x_defconfig | 1 + configs/xpedite537x_defconfig | 1 + drivers/Kconfig | 2 + drivers/crypto/fsl/Kconfig | 39 ++ drivers/ddr/fsl/Kconfig | 172 ++++++ drivers/ddr/fsl/Makefile | 2 +- drivers/ddr/fsl/arm_ddr_gen3.c | 6 +- drivers/ddr/fsl/ctrl_regs.c | 6 +- drivers/ddr/fsl/fsl_ddr_gen4.c | 6 +- drivers/ddr/fsl/interactive.c | 14 +- drivers/ddr/fsl/main.c | 30 +- drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 6 +- drivers/ddr/fsl/options.c | 30 +- drivers/ddr/fsl/util.c | 28 +- drivers/mmc/Kconfig | 12 + drivers/net/fm/Makefile | 2 - include/configs/B4860QDS.h | 7 +- include/configs/BSC9131RDB.h | 4 - include/configs/BSC9132QDS.h | 4 - include/configs/C29XPCIE.h | 3 - include/configs/MPC8308RDB.h | 1 - include/configs/MPC8349EMDS.h | 9 +- include/configs/MPC8536DS.h | 6 - include/configs/MPC8540ADS.h | 6 - include/configs/MPC8541CDS.h | 4 - include/configs/MPC8544DS.h | 6 - include/configs/MPC8548CDS.h | 6 - include/configs/MPC8555CDS.h | 4 - include/configs/MPC8560ADS.h | 4 - include/configs/MPC8568MDS.h | 6 - include/configs/MPC8569MDS.h | 6 - include/configs/MPC8572DS.h | 4 - include/configs/MPC8610HPCD.h | 2 - include/configs/MPC8641HPCN.h | 2 - include/configs/P1010RDB.h | 4 - include/configs/P1022DS.h | 4 - include/configs/P1023RDB.h | 3 - include/configs/P2041RDB.h | 6 +- include/configs/T102xQDS.h | 8 +- include/configs/T102xRDB.h | 51 +- include/configs/T1040QDS.h | 10 +- include/configs/T104xRDB.h | 9 +- include/configs/T208xQDS.h | 8 +- include/configs/T208xRDB.h | 7 +- include/configs/T4240RDB.h | 7 +- include/configs/UCP1020.h | 7 - include/configs/colibri_vf.h | 2 - include/configs/controlcenterd.h | 4 - include/configs/corenet_ds.h | 6 +- include/configs/cyrus.h | 6 +- include/configs/hrcon.h | 1 - include/configs/km/kmp204x-common.h | 6 +- include/configs/mx6_common.h | 2 - include/configs/mx7_common.h | 2 - include/configs/p1_p2_rdb_pc.h | 6 - include/configs/p1_twr.h | 6 - include/configs/pcm052.h | 3 - include/configs/qemu-ppce500.h | 4 - include/configs/s32v234evb.h | 2 - include/configs/sbc8548.h | 4 - include/configs/sbc8641d.h | 2 - include/configs/socrates.h | 4 - include/configs/strider.h | 1 - include/configs/t4qds.h | 7 +- include/configs/ts4800.h | 2 - include/configs/vf610twr.h | 2 - include/configs/xpedite517x.h | 2 - include/configs/xpedite520x.h | 4 - include/configs/xpedite537x.h | 4 - include/configs/xpedite550x.h | 4 - include/fsl_ddr.h | 3 +- include/fsl_sec.h | 2 +- scripts/config_whitelist.txt | 85 --- 180 files changed, 1220 insertions(+), 1016 deletions(-) create mode 100644 drivers/ddr/fsl/Kconfig -- 2.7.4

3 51

[U-Boot] [PATCH 2/2] armv8: ls1012a: Add support of PPA
by Prabhakar Kushwaha 05 Jan '17

05 Jan '17

The PPA implements PSCI which requires for power managment. Added support of PPA for LS1012AQDS, LS1012ARDB and LS1012AFRDM. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini(a)nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> --- board/freescale/ls1012afrdm/ls1012afrdm.c | 6 ++++++ board/freescale/ls1012aqds/ls1012aqds.c | 7 +++++++ board/freescale/ls1012ardb/ls1012ardb.c | 6 ++++++ include/configs/ls1012afrdm.h | 11 +++++++++++ include/configs/ls1012aqds.h | 11 +++++++++++ include/configs/ls1012ardb.h | 11 +++++++++++ 6 files changed, 52 insertions(+) diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c index c2432c3..789cae2 100644 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -9,6 +9,9 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> +#ifdef CONFIG_FSL_LS_PPA +#include <asm/arch/ppa.h> +#endif #include <asm/arch/soc.h> #include <hwconfig.h> #include <environment.h> @@ -74,6 +77,9 @@ int board_init(void) gd->env_addr = (ulong)&default_environment[0]; #endif +#ifdef CONFIG_FSL_LS_PPA + ppa_init(); +#endif return 0; } diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index 1562edd..7283d15 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -10,6 +10,9 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> +#ifdef CONFIG_FSL_LS_PPA +#include <asm/arch/ppa.h> +#endif #include <asm/arch/fdt.h> #include <asm/arch/soc.h> #include <ahci.h> @@ -114,6 +117,10 @@ int board_init(void) #ifdef CONFIG_ENV_IS_NOWHERE gd->env_addr = (ulong)&default_environment[0]; #endif + +#ifdef CONFIG_FSL_LS_PPA + ppa_init(); +#endif return 0; } diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index bc05fbe..fbd4bc4 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -9,6 +9,9 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> +#ifdef CONFIG_FSL_LS_PPA +#include <asm/arch/ppa.h> +#endif #include <asm/arch/soc.h> #include <hwconfig.h> #include <ahci.h> @@ -110,6 +113,9 @@ int board_init(void) gd->env_addr = (ulong)&default_environment[0]; #endif +#ifdef CONFIG_FSL_LS_PPA + ppa_init(); +#endif return 0; } diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index f6f88e8..cf5d07c 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -9,6 +9,17 @@ #include "ls1012a_common.h" +#if defined(CONFIG_FSL_LS_PPA) +#define CONFIG_ARMV8_PSCI +#define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#define SEC_FIRMWARE_ERET_ADDR_REVERT + +#define CONFIG_SYS_LS_PPA_FW_IN_XIP +#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP +#define CONFIG_SYS_LS_PPA_FW_ADDR 0x40500000 +#endif +#endif + /* DDR */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index 0cc1791..8eeafa7 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -9,6 +9,17 @@ #include "ls1012a_common.h" +#if defined(CONFIG_FSL_LS_PPA) +#define CONFIG_ARMV8_PSCI +#define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#define SEC_FIRMWARE_ERET_ADDR_REVERT + +#define CONFIG_SYS_LS_PPA_FW_IN_XIP +#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP +#define CONFIG_SYS_LS_PPA_FW_ADDR 0x40500000 +#endif +#endif + /* DDR */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index 15410dd..04865ec 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -9,6 +9,17 @@ #include "ls1012a_common.h" +#if defined(CONFIG_FSL_LS_PPA) +#define CONFIG_ARMV8_PSCI +#define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#define SEC_FIRMWARE_ERET_ADDR_REVERT + +#define CONFIG_SYS_LS_PPA_FW_IN_XIP +#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP +#define CONFIG_SYS_LS_PPA_FW_ADDR 0x40500000 +#endif +#endif + /* DDR */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 -- 2.7.4

3 2

[U-Boot] [PATCH 1/5] common/Kconfig: remove NOR_BOOT's depends on NOR
by Zhiqiang Hou 05 Jan '17

05 Jan '17

From: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> Remove this dependency to make the NOR_BOOT available for other SoCs which do not have the config NOR, not only for am335x. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> --- common/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/common/Kconfig b/common/Kconfig index c69c141..7fd6c49 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -101,7 +101,6 @@ menu "Boot media" config NOR_BOOT bool "Support for booting from NOR flash" - depends on NOR help Enabling this will make a U-Boot binary that is capable of being booted via NOR. In this case we will enable certain pinmux early -- 2.1.0.27.g96db324

6 13

[U-Boot] [PATCH 1/2][RESEND] armv8:ls2080a: Reorganise NAND_BOOT code in config flag
by Priyanka Jain 04 Jan '17

04 Jan '17

Add CONFIG_NAND_BOOT config flag to organise NAND_BOOT specific code in config flag like -nand-boot specfic errata errata_rcw_src() -CONFIG_SYS_NAND_U_BOOT_DST,etc Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +- configs/ls2080aqds_nand_defconfig | 2 +- configs/ls2080ardb_nand_defconfig | 2 +- include/configs/ls2080a_common.h | 4 ++++ include/configs/ls2080aqds.h | 4 +++- 5 files changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index d43361f..73a751d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -134,7 +134,7 @@ void erratum_a009635(void) static void erratum_rcw_src(void) { -#if defined(CONFIG_SPL) +#if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT) u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE; u32 val; diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index 2161815..5e7bea5 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -12,7 +12,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, NAND_BOOT, LS2080A" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index e40152e..d6633c3 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -12,7 +12,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, NAND_BOOT, LS2080A" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 2cae966..3828058 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -250,6 +250,7 @@ unsigned long long get_qixis_addr(void); #define CONFIG_PANIC_HANG /* do not reset board on panic */ +#ifdef CONFIG_SPL #define CONFIG_SPL_BSS_START_ADDR 0x80100000 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 #define CONFIG_SPL_FRAMEWORK @@ -259,11 +260,14 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" #define CONFIG_SPL_TEXT_BASE 0x1800a000 +#ifdef CONFIG_NAND_BOOT #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST +#endif #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 #define CONFIG_SYS_MONITOR_LEN (640 * 1024) +#endif #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 838568f..a87d13a 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -202,7 +202,8 @@ unsigned long get_board_ddr_clk(void); FTIM2_GPCM_TWP(0x3E)) #define CONFIG_SYS_CS3_FTIM3 0x0 -#if defined(CONFIG_SPL) && defined(CONFIG_NAND) +#if defined(CONFIG_SPL) +#if defined(CONFIG_NAND_BOOT) #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR @@ -238,6 +239,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SPL_PAD_TO 0x20000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024) #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024) +#endif #else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -- 1.7.4.1

2 2

[U-Boot] [PATCH v6 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 GIC node
by Wenbin song 04 Jan '17

04 Jan '17

The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] is used to choose which offset will be used. If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment is used. The rev1.0 silicon only supports the CIG offset with 4K alignment. GIC offset is decided by SVR and GIC_ADDR_BIT bit. Overriding the weak smp_kick_all_cpus, the new impletment is able to detect GIC offset. Signed-off-by: Wenbin Song <wenbin.song(a)nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu(a)nxp.com> --- Changes in v6: Add comments around checking the revision. Changes in v5: Replace fix_gic_off with get_gic_off. Add #if condition to check CONFIG_GICV2 and CONFIG_GICV3 on smp_kick_all_cpus. Fixup gic node with 64K alignment when running on rev1.1 with GIC_ADDR_BIT cleared. --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 ++ arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 71 ++++++++++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 57 +++++++++++++++-- arch/arm/include/asm/arch-fsl-layerscape/config.h | 26 +++++++- .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 +- 5 files changed, 154 insertions(+), 7 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 94ec8d5..f415868 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -135,4 +135,8 @@ config SYS_FSL_DDR4 help Enable Freescale DDR4 controller. +config HAS_FEATURE_GIC4K_ALIGN + bool + default y if ARCH_LS1043A + endmenu diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 1a8321b..9936be1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -126,6 +126,74 @@ void fsl_fdt_disable_usb(void *blob) } } +#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN +static void fdt_fixup_gic(void *blob) +{ + int offset, err; + u64 reg[8]; + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + unsigned int rev; + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; + int align_4k = 1; + + rev = gur_in32(&gur->svr) & 0xff; + /* + * For ls1043a rev1.0, the GIC offset aligns with 4K. + * For ls1043a rev1.1 or more higher, the GIC offset + * is decided by gic_align register. + */ + + if (rev > REV1_0) { + /* + * The GIC_ADDR_BIT on gic_align was set by + * PBI to select GIC offset. + */ + rev = scfg_in32(&scfg->gic_align) & (0x01 << GIC_ADDR_BIT); + if (!rev) + align_4k = 0; + } + + offset = fdt_subnode_offset(blob, 0, "interrupt-controller@1400000"); + if (offset < 0) { + printf("WARNING: fdt_subnode_offset can't find node %s: %s\n", + "interrupt-controller@1400000", fdt_strerror(offset)); + return; + } + + /* Fixup gic node align with 4K */ + if (align_4k) { + reg[0] = cpu_to_fdt64(GICD_BASE_4K); + reg[1] = cpu_to_fdt64(GICD_SIZE_4K); + reg[2] = cpu_to_fdt64(GICC_BASE_4K); + reg[3] = cpu_to_fdt64(GICC_SIZE_4K); + reg[4] = cpu_to_fdt64(GICH_BASE_4K); + reg[5] = cpu_to_fdt64(GICH_SIZE_4K); + reg[6] = cpu_to_fdt64(GICV_BASE_4K); + reg[7] = cpu_to_fdt64(GICV_SIZE_4K); + } else { + /* Fixup gic node align with 64K */ + reg[0] = cpu_to_fdt64(GICD_BASE); + reg[1] = cpu_to_fdt64(GICD_SIZE); + reg[2] = cpu_to_fdt64(GICC_BASE); + reg[3] = cpu_to_fdt64(GICC_SIZE); + reg[4] = cpu_to_fdt64(GICH_BASE); + reg[5] = cpu_to_fdt64(GICH_SIZE); + reg[6] = cpu_to_fdt64(GICV_BASE); + reg[7] = cpu_to_fdt64(GICV_SIZE); + } + + err = fdt_setprop(blob, offset, "reg", reg, sizeof(reg)); + if (err < 0) { + printf("WARNING: fdt_setprop can't set %s from node %s: %s\n", + "reg", "interrupt-controller@1400000", + fdt_strerror(err)); + return; + } + + return; +} +#endif + void ft_cpu_setup(void *blob, bd_t *bd) { #ifdef CONFIG_FSL_LSCH2 @@ -170,4 +238,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #endif fsl_fdt_disable_usb(blob); +#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN + fdt_fixup_gic(blob); +#endif } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 5d0b7a4..d50096c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -14,6 +14,55 @@ #include <asm/arch/mp.h> #endif + +/* Get GIC offset +* For LS1043a rev1.0, GIC base address align with 4k. +* For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT] +* is set, GIC base address align with 4K, or else align +* with 64k. +* output: +* for GICv2: +* x0-> the base address of GICD +* x1-> the base address of GICC +* for GICv3: +* x0-> the base address of GICD +*/ +ENTRY(get_gic_offset) + ldr x0, =GICD_BASE +#ifdef CONFIG_GICV2 + ldr x1, =GICC_BASE +#endif +#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN + ldr x3, =DCFG_CCSR_SVR + ldr w3, [x3] + rev w3, w3 + ands w3, w3, #0xff + cmp w3, #REV1_0 + b.eq 1f + ldr x3, =SCFG_GIC400_ALIGN + ldr w3, [x3] + rev w3, w3 + tbnz w3, #GIC_ADDR_BIT, 1f + ret +1: + ldr x0, =GICD_BASE_4K + ldr x1, =GICC_BASE_4K +#endif + ret +ENDPROC(get_gic_offset) + +ENTRY(smp_kick_all_cpus) + /* Kick secondary cpus up by SGI 0 interrupt */ +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) + mov x29, lr /* Save LR */ + bl get_gic_offset + bl gic_kick_secondary_cpus + mov lr, x29 /* Restore LR */ +#endif + ret +ENDPROC(smp_kick_all_cpus) + + ENTRY(lowlevel_init) mov x29, lr /* Save LR */ @@ -105,15 +154,14 @@ ENTRY(lowlevel_init) /* Initialize GIC Secure Bank Status */ #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) branch_if_slave x0, 1f - ldr x0, =GICD_BASE + bl get_gic_offset bl gic_init_secure 1: #ifdef CONFIG_GICV3 ldr x0, =GICR_BASE bl gic_init_secure_percpu #elif defined(CONFIG_GICV2) - ldr x0, =GICD_BASE - ldr x1, =GICC_BASE + bl get_gic_offset bl gic_init_secure_percpu #endif #endif @@ -335,7 +383,8 @@ ENTRY(secondary_boot_func) #if defined(CONFIG_GICV3) gic_wait_for_interrupt_m x0 #elif defined(CONFIG_GICV2) - ldr x0, =GICC_BASE + bl get_gic_offset + mov x0, x1 gic_wait_for_interrupt_m x0, w1 #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 4201e0f..35f67dd 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -172,8 +172,30 @@ #define SMMU_BASE 0x09000000 /* Generic Interrupt Controller Definitions */ -#define GICD_BASE 0x01401000 -#define GICC_BASE 0x01402000 +#define GICD_BASE 0x01410000 +#define GICC_BASE 0x01420000 +#define GICH_BASE 0x01440000 +#define GICV_BASE 0x01460000 +#define GICD_SIZE 0x10000 +#define GICC_SIZE 0x20000 +#define GICH_SIZE 0x20000 +#define GICV_SIZE 0x20000 +#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN +#define GICD_BASE_4K 0x01401000 +#define GICC_BASE_4K 0x01402000 +#define GICH_BASE_4K 0x01404000 +#define GICV_BASE_4K 0x01406000 +#define GICD_SIZE_4K 0x1000 +#define GICC_SIZE_4K 0x2000 +#define GICH_SIZE_4K 0x2000 +#define GICV_SIZE_4K 0x2000 +#endif + +#define DCFG_CCSR_SVR 0x1ee00a4 +#define REV1_0 0x10 +#define REV1_1 0x11 +#define GIC_ADDR_BIT 31 +#define SCFG_GIC400_ALIGN 0x1570188 #define CONFIG_SYS_FSL_ERRATUM_A008850 #define CONFIG_SYS_FSL_ERRATUM_A009663 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index d88543d..1dfef53 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -359,7 +359,8 @@ struct ccsr_scfg { u32 qspi_cfg; u8 res_160[0x180-0x160]; u32 dmamcr; - u8 res_184[0x18c-0x184]; + u8 res_184[0x188-0x184]; + u32 gic_align; u32 debug_icid; u8 res_190[0x1a4-0x190]; u32 snpcnfgcr; -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] powerpc/t2080: DDR controller erratum A-009942
by Hamish Martin 04 Jan '17

04 Jan '17

This erratum is already implemented for other ARM based QorIQ platforms with the Gen4 DDR controller. Port the fix to the Gen3 controller and enable it for T2080 and T2081. Reviewed-by: Chris Packham <chris.packham(a)alliedtelesis.co.nz> Signed-off-by: Hamish Martin <hamish.martin(a)alliedtelesis.co.nz> Cc: York Sun <york.sun(a)nxp.com> --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++ arch/powerpc/include/asm/config_mpc85xx.h | 1 + drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 17 +++++++++++++++++ 3 files changed, 21 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 3b06ae42e4bc..94b6dcca96b6 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -329,6 +329,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A009663 puts("Work-around for Erratum A009663 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 + puts("Work-around for Erratum A009942 enabled\n"); +#endif return 0; } diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 6d845e859f4a..9e1cd80e16e0 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -910,6 +910,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_FSL_ERRATUM_A007186 #define CONFIG_SYS_FSL_ERRATUM_A006379 +#define CONFIG_SYS_FSL_ERRATUM_A009942 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #define CONFIG_SYS_FSL_SFP_VER_3_0 diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index 653b7f0c770c..a88884377f80 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -39,6 +39,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003 u32 save1, save2; #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 + ulong ddr_freq; + u32 tmp; +#endif switch (ctrl_num) { case 0: @@ -183,6 +187,19 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->debug[21], 0x24000000); #endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 + ddr_freq = get_ddr_freq(ctrl_num) / 1000000; + tmp = in_be32(&ddr->debug[28]); + if (ddr_freq <= 1333) + out_be32(&ddr->debug[28], tmp | 0x0080006a); + else if (ddr_freq <= 1600) + out_be32(&ddr->debug[28], tmp | 0x0070006f); + else if (ddr_freq <= 1867) + out_be32(&ddr->debug[28], tmp | 0x00700076); + else if (ddr_freq <= 2133) + out_be32(&ddr->debug[28], tmp | 0x0060007b); +#endif + /* * For RDIMMs, JEDEC spec requires clocks to be stable before reset is * deasserted. Clocks start when any chip select is enabled and clock -- 2.10.1

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[U-Boot] [PATCH RESEND v2 1/2] spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible
by Vignesh R 04 Jan '17

04 Jan '17

According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit data interface writes until the last word of an indirect transfer otherwise indirect writes is known to fails sometimes. So, make sure that QSPI indirect writes are 32 bit sized except for the last write. If the txbuf is unaligned then use bounce buffer to avoid data aborts. So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER for all boards that use Cadence QSPI driver. [1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf Signed-off-by: Vignesh R <vigneshr(a)ti.com> Reviewed-by: Marek Vasut <marex(a)denx.de> --- Resend v2: Rebased on latest rc. Link to v2:https://patchwork.ozlabs.org/patch/698614/ drivers/spi/cadence_qspi_apb.c | 26 ++++++++++++++++++++------ include/configs/k2g_evm.h | 1 + include/configs/socfpga_common.h | 1 + include/configs/stv0991.h | 1 + 4 files changed, 23 insertions(+), 6 deletions(-) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index df6a91fc9f7b..5d5b6f0d350b 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -30,6 +30,7 @@ #include <linux/errno.h> #include <wait_bit.h> #include <spi.h> +#include <bouncebuf.h> #include "cadence_qspi.h" #define CQSPI_REG_POLL_US 1 /* 1us */ @@ -724,6 +725,17 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, unsigned int remaining = n_tx; unsigned int write_bytes; int ret; + struct bounce_buffer bb; + u8 *bb_txbuf; + + /* + * Handle non-4-byte aligned accesses via bounce buffer to + * avoid data abort. + */ + ret = bounce_buffer_start(&bb, (void *)txbuf, n_tx, GEN_BB_READ); + if (ret) + return ret; + bb_txbuf = bb.bounce_buffer; /* Configure the indirect read transfer bytes */ writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES); @@ -734,11 +746,11 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, while (remaining > 0) { write_bytes = remaining > page_size ? page_size : remaining; - /* Handle non-4-byte aligned access to avoid data abort. */ - if (((uintptr_t)txbuf % 4) || (write_bytes % 4)) - writesb(plat->ahbbase, txbuf, write_bytes); - else - writesl(plat->ahbbase, txbuf, write_bytes >> 2); + writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2); + if (write_bytes % 4) + writesb(plat->ahbbase, + bb_txbuf + rounddown(write_bytes, 4), + write_bytes % 4); ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL, CQSPI_REG_SDRAMLEVEL_WR_MASK << @@ -748,7 +760,7 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, goto failwr; } - txbuf += write_bytes; + bb_txbuf += write_bytes; remaining -= write_bytes; } @@ -759,6 +771,7 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, printf("Indirect write completion error (%i)\n", ret); goto failwr; } + bounce_buffer_stop(&bb); /* Clear indirect completion status */ writel(CQSPI_REG_INDIRECTWR_DONE, @@ -769,6 +782,7 @@ failwr: /* Cancel the indirect write */ writel(CQSPI_REG_INDIRECTWR_CANCEL, plat->regbase + CQSPI_REG_INDIRECTWR); + bounce_buffer_stop(&bb); return ret; } diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index 2da0d8dd7f00..4f9c42abac7e 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -78,6 +78,7 @@ #define CONFIG_CADENCE_QSPI #define CONFIG_CQSPI_REF_CLK 384000000 #define CONFIG_CQSPI_DECODER 0x0 +#define CONFIG_BOUNCE_BUFFER #endif #endif /* __CONFIG_K2G_EVM_H */ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 58a655084491..e50c2fac8d99 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -208,6 +208,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() #endif #define CONFIG_CQSPI_DECODER 0 +#define CONFIG_BOUNCE_BUFFER /* * Designware SPI support diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index bfd1bd719285..09a3064bd6d6 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -74,6 +74,7 @@ #ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */ #define CONFIG_CQSPI_DECODER 0 #define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000 +#define CONFIG_BOUNCE_BUFFER #endif -- 2.11.0

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