December 2016 - U-Boot

[U-Boot] [PATCH] rockchip: Fix veyron-minnie's Kconfig description
by Martin Michlmayr 12 Jan '17

12 Jan '17

The veyron-minnie Kconfig referred to jerry by mistake. Signed-off-by: Martin Michlmayr <tbm(a)cyrius.com> --- arch/arm/mach-rockchip/rk3288/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 223ae41..54545f3 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -61,7 +61,7 @@ config TARGET_CHROMEBIT_MICKEY config TARGET_CHROMEBOOK_MINNIE bool "Google/Rockchip Veyron-Minnie Chromebook" help - Jerry is a RK3288-based convertible clamshell device with 2 USB 3.0 + Minnie is a RK3288-based convertible clamshell device with 2 USB 3.0 ports, micro HDMI, a 10.1-inch 1280x800 EDP display, micro-SD card, HD camera, touchpad, WiFi and Bluetooth. It includes a Chrome OS EC (Cortex-M3) to provide access to the keyboard and battery -- 2.1.4 -- Martin Michlmayr http://www.cyrius.com/

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[U-Boot] [PATCH 00/18] imx: add i.MX7ULP support
by Peng Fan 12 Jan '17

12 Jan '17

This patchset is to add i.MX7 ULP support default enabling OF_CONTROL. i.MX7ULP has different architecture with i.MX7D/S, so not reuse the code in imx-common. Also there are some new IPs, such lpi2c/lpuart/ rapid gpio2p and etc. Peng Fan (15): imx: mx7ulp: Add mx7ulp to Kconfig imx: mx7ulp: add registers header file imx: mx7ulp: add iomux driver to support IOMUXC0 and IOMUXC1 imx: mx7ulp: Add clock framework and functions imx: mx7ulp: Add soc level initialization codes and functions imx: mx7ulp: handle all the lpuarts in get_lpuart_clk gpio: Add Rapid GPIO2P driver for i.MX7ULP wdog: Add the watchdog driver for MX7ULP. pinctrl: Add i.MX7ULP pinctrl driver i2c: lpi2c: add lpi2c driver for i.MX7ULP serial: Add support for i.MX7ULP arm: dts: add i.MX7ULP dtsi file mmc: fsl_esdhc: support i.MX7ULP imx: imx7ulp: add EVK board support imx: mx7ulp_evk: enable mmc/regulator support Ye Li (3): imx: mx7ulp: Implement the clock functions for i2c driver mxc_ocotp: Update driver to support OCOTP controller on i.MX7ULP mx7ulp: Add iomux pins header file arch/arm/Kconfig | 7 + arch/arm/cpu/armv7/Makefile | 3 +- arch/arm/cpu/armv7/mx7ulp/Kconfig | 17 + arch/arm/cpu/armv7/mx7ulp/Makefile | 8 + arch/arm/cpu/armv7/mx7ulp/clock.c | 354 +++++++ arch/arm/cpu/armv7/mx7ulp/iomux.c | 70 ++ arch/arm/cpu/armv7/mx7ulp/pcc.c | 286 ++++++ arch/arm/cpu/armv7/mx7ulp/scg.c | 1086 ++++++++++++++++++++++ arch/arm/cpu/armv7/mx7ulp/soc.c | 290 ++++++ arch/arm/dts/Makefile | 2 + arch/arm/dts/imx7ulp-evk.dts | 426 +++++++++ arch/arm/dts/imx7ulp-pinfunc.h | 882 ++++++++++++++++++ arch/arm/dts/imx7ulp-uboot.dtsi | 43 + arch/arm/dts/imx7ulp.dtsi | 598 ++++++++++++ arch/arm/include/asm/arch-mx7ulp/clock.h | 42 + arch/arm/include/asm/arch-mx7ulp/gpio.h | 22 + arch/arm/include/asm/arch-mx7ulp/imx-regs.h | 1166 ++++++++++++++++++++++++ arch/arm/include/asm/arch-mx7ulp/imx_lpi2c.h | 520 +++++++++++ arch/arm/include/asm/arch-mx7ulp/iomux.h | 95 ++ arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h | 910 ++++++++++++++++++ arch/arm/include/asm/arch-mx7ulp/pcc.h | 377 ++++++++ arch/arm/include/asm/arch-mx7ulp/scg.h | 342 +++++++ arch/arm/include/asm/arch-mx7ulp/sys_proto.h | 24 + board/freescale/mx7ulp_evk/Kconfig | 12 + board/freescale/mx7ulp_evk/Makefile | 10 + board/freescale/mx7ulp_evk/imximage.cfg | 131 +++ board/freescale/mx7ulp_evk/mx7ulp_evk.c | 77 ++ configs/mx7ulp_evk_defconfig | 25 + drivers/gpio/Kconfig | 7 + drivers/gpio/Makefile | 1 + drivers/gpio/imx_rgpio2p.c | 224 +++++ drivers/i2c/Kconfig | 6 + drivers/i2c/Makefile | 1 + drivers/i2c/imx_lpi2c.c | 462 ++++++++++ drivers/misc/mxc_ocotp.c | 50 + drivers/mmc/fsl_esdhc.c | 8 + drivers/pinctrl/nxp/Kconfig | 14 + drivers/pinctrl/nxp/Makefile | 1 + drivers/pinctrl/nxp/pinctrl-imx.c | 10 +- drivers/pinctrl/nxp/pinctrl-imx.h | 3 + drivers/pinctrl/nxp/pinctrl-imx7ulp.c | 41 + drivers/serial/Kconfig | 5 + drivers/serial/Makefile | 1 + drivers/serial/serial_imxlpuart.c | 261 ++++++ drivers/watchdog/Kconfig | 8 + drivers/watchdog/Makefile | 1 + drivers/watchdog/ulp_wdog.c | 92 ++ include/configs/mx7ulp_evk.h | 128 +++ include/dt-bindings/clock/imx7ulp-clock.h | 161 ++++ 49 files changed, 9305 insertions(+), 5 deletions(-) create mode 100644 arch/arm/cpu/armv7/mx7ulp/Kconfig create mode 100644 arch/arm/cpu/armv7/mx7ulp/Makefile create mode 100644 arch/arm/cpu/armv7/mx7ulp/clock.c create mode 100644 arch/arm/cpu/armv7/mx7ulp/iomux.c create mode 100644 arch/arm/cpu/armv7/mx7ulp/pcc.c create mode 100644 arch/arm/cpu/armv7/mx7ulp/scg.c create mode 100644 arch/arm/cpu/armv7/mx7ulp/soc.c create mode 100644 arch/arm/dts/imx7ulp-evk.dts create mode 100644 arch/arm/dts/imx7ulp-pinfunc.h create mode 100644 arch/arm/dts/imx7ulp-uboot.dtsi create mode 100644 arch/arm/dts/imx7ulp.dtsi create mode 100644 arch/arm/include/asm/arch-mx7ulp/clock.h create mode 100644 arch/arm/include/asm/arch-mx7ulp/gpio.h create mode 100644 arch/arm/include/asm/arch-mx7ulp/imx-regs.h create mode 100644 arch/arm/include/asm/arch-mx7ulp/imx_lpi2c.h create mode 100644 arch/arm/include/asm/arch-mx7ulp/iomux.h create mode 100644 arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h create mode 100644 arch/arm/include/asm/arch-mx7ulp/pcc.h create mode 100644 arch/arm/include/asm/arch-mx7ulp/scg.h create mode 100644 arch/arm/include/asm/arch-mx7ulp/sys_proto.h create mode 100644 board/freescale/mx7ulp_evk/Kconfig create mode 100644 board/freescale/mx7ulp_evk/Makefile create mode 100644 board/freescale/mx7ulp_evk/imximage.cfg create mode 100644 board/freescale/mx7ulp_evk/mx7ulp_evk.c create mode 100644 configs/mx7ulp_evk_defconfig create mode 100644 drivers/gpio/imx_rgpio2p.c create mode 100644 drivers/i2c/imx_lpi2c.c create mode 100644 drivers/pinctrl/nxp/pinctrl-imx7ulp.c create mode 100644 drivers/serial/serial_imxlpuart.c create mode 100644 drivers/watchdog/ulp_wdog.c create mode 100644 include/configs/mx7ulp_evk.h create mode 100644 include/dt-bindings/clock/imx7ulp-clock.h -- 2.6.2

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[U-Boot] [PATCH] arm64: rk3399: update rockchip_get_cru API
by Kever Yang 12 Jan '17

12 Jan '17

rk3399 has two clock-controller: cru and pmucru, update the rockchip_get_crui() API, and rockchip_get_clk() do not used for other module. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- arch/arm/mach-rockchip/rk3399/clk_rk3399.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c index 7663591..ce706a6 100644 --- a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c @@ -11,10 +11,10 @@ #include <asm/arch/clock.h> #include <asm/arch/cru_rk3399.h> -int rockchip_get_clk(struct udevice **devp) +static int rockchip_get_cruclk(struct udevice **devp) { return uclass_get_device_by_driver(UCLASS_CLK, - DM_GET_DRIVER(rockchip_rk3399_pmuclk), devp); + DM_GET_DRIVER(clk_rk3399), devp); } void *rockchip_get_cru(void) @@ -23,7 +23,7 @@ void *rockchip_get_cru(void) struct udevice *dev; int ret; - ret = rockchip_get_clk(&dev); + ret = rockchip_get_cruclk(&dev); if (ret) return ERR_PTR(ret); -- 1.9.1

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[U-Boot] Accessing nested device tree nodes via phandle
by Vlad Zakharov 12 Jan '17

12 Jan '17

Hi everybody, I am working on reorganization of device trees for ARC boards in U-Boot in order to create a common device tree blob for both Linux and U-Boot. And I've struggled with a kind of problem and need some help. On AXS10x motherboard clocks for various peripherals are managed by one hardware block, so clock nodes in Linux device tree are grouped into one "clocks" node like this: ---------------------------------->8------------------------------------ clocks { i2cclk: i2cclk { compatible = "fixed-clock"; clock-frequency = <50000000>; #clock-cells = <0>; }; ... ... ... uartclk: uartclk { compatible = "fixed-clock"; clock-frequency = <33333333>; #clock-cells = <0>; }; }; ---------------------------------->8------------------------------------ And then some of them a referenced via phandle from other nodes, e.g. &uartclk is referenced from uart node. When I try to create such hierarchy in U-Boot I find that uart driver is not able to get clock via phandle and corresponding uart doesn't work. As I understand that is because children clocks nodes, i.e. "uartclk" in my case, never got bound as it's parent node "clocks" never got bound too. So when I add "compatible" and "u-boot,dm-pre-reloc" properties to "clocks" parent node everything works fine, e.g.: ---------------------------------->8------------------------------------ clocks { compatible = "simple-bus"; u-boot,dm-pre-reloc; uartclk: uartclk { compatible = "fixed-clock"; clock-frequency = <33333333>; #clock-cells = <0>; }; ... ... ... }; ---------------------------------->8------------------------------------ Please correct me if I wrongly interpret such behavior. I wonder if it the only approach to implement Linux-like hierarchy for ARC? Or I am mistaken and in fact can use pure Linux device tree without adding properties, described above? Thank you! -- Best regards, Vlad Zakharov <vzakhar(a)synopsys.com>

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[U-Boot] [PATCH v3 0/4] mmc: sdhci: Add support for frequency constrained peripheral interfaces
by stefan.herbrechtsmeier＠weidmueller.de 11 Jan '17

11 Jan '17

From: Stefan Herbrechtsmeier <stefan.herbrechtsmeier(a)weidmueller.de> The sdhci controller assumes that the base clock frequency is fully supported by the peripheral and doesn't support hardware limitations. Distinguish between base clock of the host controller and maximal supported peripheral clock frequency of the peripheral interface. This is needed for the zynq platform to support two sdhci ports with different IO routings. Changes in v3: - Rename arguments of sdhci_setup_cfg function from max_clk/min_clk to f_max/f_min Changes in v2: - Remove unused index from get uart clock function - Remove unused index from get sdio clock function - Introduce common get clock function Stefan Herbrechtsmeier (4): mmc: sdhci: Distinguish between base clock and maximum peripheral frequency serial: zynq: Remove unused index from get uart clock function mmc: zynq: Determine base clock frequency via clock framework mmc: zynq: Add fdt max-frequency support arch/arm/mach-zynq/clk.c | 51 +++++++++++++++++++++++++++-------- arch/arm/mach-zynq/include/mach/clk.h | 3 ++- drivers/mmc/atmel_sdhci.c | 7 +++-- drivers/mmc/bcm2835_sdhci.c | 3 ++- drivers/mmc/ftsdc021_sdhci.c | 3 ++- drivers/mmc/kona_sdhci.c | 3 ++- drivers/mmc/msm_sdhci.c | 2 ++ drivers/mmc/mv_sdhci.c | 3 ++- drivers/mmc/pci_mmc.c | 1 + drivers/mmc/pic32_sdhci.c | 4 ++- drivers/mmc/rockchip_sdhci.c | 4 +-- drivers/mmc/s5p_sdhci.c | 5 ++-- drivers/mmc/sdhci.c | 34 ++++++++++++----------- drivers/mmc/spear_sdhci.c | 3 ++- drivers/mmc/zynq_sdhci.c | 40 ++++++++++++++++++++++++++- drivers/serial/serial_zynq.c | 2 +- include/sdhci.h | 13 ++++----- 17 files changed, 133 insertions(+), 48 deletions(-) -- 2.7.4 Kommanditgesellschaft - Sitz: Detmold - Amtsgericht Lemgo HRA 2790 - Komplementärin: Weidmüller Interface Führungsgesellschaft mbH - Sitz: Detmold - Amtsgericht Lemgo HRB 3924; Geschäftsführer: José Carlos Álvarez Tobar, Elke Eckstein, Dr. Peter Köhler, Jörg Timmermann; USt-ID-Nr. DE124599660

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[U-Boot] [PATCH] mx6sx: Add initial support for UDOO Neo Board
by Breno Lima 10 Jan '17

10 Jan '17

UDOO Neo Board is a development board from Seco that has three models: - UDOO Neo Basic - UDOO Neo Basic Kick Starter - UDOO Neo Extended - UDOO Neo Full All versions are based on the i.MX6 SoloX processor. For more details about the UDOO Neo board, please refer to: http://www.udoo.org/udoo-neo/ This work is based on a previous commit of Francesco Montefoschi <francesco.monte(a)gmail.com>: https://github.com/fmntf/u-boot/commit/877b71184a5105e708024f232d36aed57496… Only tested on the UDOO Neo Full board. Signed-off-by: Breno Lima <breno.lima(a)nxp.com> --- arch/arm/cpu/armv7/mx6/Kconfig | 5 + board/udoo/neo/Kconfig | 12 ++ board/udoo/neo/MAINTAINERS | 7 + board/udoo/neo/Makefile | 6 + board/udoo/neo/neo.c | 441 +++++++++++++++++++++++++++++++++++++++++ configs/udoo_neo_defconfig | 30 +++ include/configs/udoo_neo.h | 94 +++++++++ 7 files changed, 595 insertions(+) create mode 100644 board/udoo/neo/Kconfig create mode 100644 board/udoo/neo/MAINTAINERS create mode 100644 board/udoo/neo/Makefile create mode 100644 board/udoo/neo/neo.c create mode 100644 configs/udoo_neo_defconfig create mode 100644 include/configs/udoo_neo.h diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 762a581..ea8b693 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -192,6 +192,10 @@ config TARGET_UDOO bool "udoo" select SUPPORT_SPL +config TARGET_UDOO_NEO + bool "UDOO Neo" + select SUPPORT_SPL + config TARGET_WANDBOARD bool "wandboard" select SUPPORT_SPL @@ -253,6 +257,7 @@ source "board/technexion/pico-imx6ul/Kconfig" source "board/tbs/tbs2910/Kconfig" source "board/tqc/tqma6/Kconfig" source "board/udoo/Kconfig" +source "board/udoo/neo/Kconfig" source "board/wandboard/Kconfig" source "board/warp/Kconfig" diff --git a/board/udoo/neo/Kconfig b/board/udoo/neo/Kconfig new file mode 100644 index 0000000..8f474df --- /dev/null +++ b/board/udoo/neo/Kconfig @@ -0,0 +1,12 @@ +if TARGET_UDOO_NEO + +config SYS_VENDOR + default "udoo" + +config SYS_BOARD + default "neo" + +config SYS_CONFIG_NAME + default "udoo_neo" + +endif diff --git a/board/udoo/neo/MAINTAINERS b/board/udoo/neo/MAINTAINERS new file mode 100644 index 0000000..743fe33 --- /dev/null +++ b/board/udoo/neo/MAINTAINERS @@ -0,0 +1,7 @@ +UDOO NEO BOARD +M: Breno Lima <breno.lima(a)nxp.com> +M: Francesco Montefoschi <francesco.montefoschi(a)udoo.org> +S: Maintained +F: board/udoo/neo/ +F: include/configs/udoo_neo.h +F: configs/udoo_neo_defconfig diff --git a/board/udoo/neo/Makefile b/board/udoo/neo/Makefile new file mode 100644 index 0000000..150cbc1 --- /dev/null +++ b/board/udoo/neo/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2015 UDOO Team +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := neo.o diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c new file mode 100644 index 0000000..7f17469 --- /dev/null +++ b/board/udoo/neo/neo.c @@ -0,0 +1,441 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * Copyright (C) Jasbir Matharu + * Copyright (C) UDOO Team + * + * Author: Breno Lima <breno.lima(a)nxp.com> + * Author: Francesco Montefoschi <francesco.monte(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <asm/arch/crm_regs.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <spl.h> +#include <linux/sizes.h> +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR; + +enum { + UDOO_NEO_TYPE_BASIC, + UDOO_NEO_TYPE_BASIC_KS, + UDOO_NEO_TYPE_FULL, + UDOO_NEO_TYPE_EXTENDED, +}; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm) + +#define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) +#define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) | \ + MUX_MODE_SION) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* CD pin */ + MX6_PAD_SD1_DATA0__GPIO6_IO_2 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* Power */ + MX6_PAD_SD1_CMD__GPIO6_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const board_recognition_pads[] = { + /*Connected to R184*/ + MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG, + /*Connected to R185*/ + MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG, +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + /* Configured for WLAN */ + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_b_pad = { + MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +static iomux_v3_cfg_t const peri_3v3_pads[] = { + MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + /* + * Because kernel set WDOG_B mux before pad with the commone pinctrl + * framwork now and wdog reset will be triggered once set WDOG_B mux + * with default pad setting, we set pad setting here to workaround this. + * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set + * as GPIO mux firstly here to workaround it. + */ + imx_iomux_v3_setup_pad(wdog_b_pad); + + /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */ + imx_iomux_v3_setup_multiple_pads(peri_3v3_pads, + ARRAY_SIZE(peri_3v3_pads)); + + /* Active high for ncp692 */ + gpio_direction_output(IMX_GPIO_NR(4, 16) , 1); + + return 0; +} + +static int get_board_value(void) +{ + int r184, r185; + + imx_iomux_v3_setup_multiple_pads(board_recognition_pads, + ARRAY_SIZE(board_recognition_pads)); + + gpio_direction_input(IMX_GPIO_NR(4, 13)); + gpio_direction_input(IMX_GPIO_NR(4, 0)); + + r184 = gpio_get_value(IMX_GPIO_NR(4, 13)); + r185 = gpio_get_value(IMX_GPIO_NR(4, 0)); + + /* + * Machine selection - + * Machine r184, r185 + * --------------------------------- + * Basic 0 0 + * Basic Ks 0 1 + * Full 1 0 + * Extended 1 1 + */ + + return (r184 << 1) + r185; +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC2_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR, 0, 4}, +}; + +#define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1) +#define USDHC2_CD_GPIO IMX_GPIO_NR(6, 2) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ +#ifndef CONFIG_SPL_BUILD + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gpio_direction_input(USDHC2_CD_GPIO); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers\ + (%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning:\ + failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +#else + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + u32 val; + u32 port; + + val = readl(&src_regs->sbmr1); + + if ((val & 0xc0) != 0x40) { + printf("Not boot from USDHC!\n"); + return -EINVAL; + } + + port = (val >> 11) & 0x3; + printf("port %d\n", port); + switch (port) { + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; + gpio_direction_input(USDHC2_CD_GPIO); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + case 2: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR; + break; + } + + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +#endif +} + +char *board_string(void) +{ + switch (get_board_value()) { + case UDOO_NEO_TYPE_BASIC: + return "BASIC"; + case UDOO_NEO_TYPE_BASIC_KS: + return "BASICKS"; + case UDOO_NEO_TYPE_FULL: + return "FULL"; + case UDOO_NEO_TYPE_EXTENDED: + return "EXTENDED"; + } + return "UNDEFINED"; +} + +int checkboard(void) +{ + printf("Board: UDOO Neo %s\n", board_string()); + return 0; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + setenv("board_name", board_string()); +#endif + + return 0; +} + +#ifdef CONFIG_SPL_BUILD + +#include <libfdt.h> +#include <asm/arch/mx6-ddr.h> + +static const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000028, + .dram_dqm1 = 0x00000028, + .dram_dqm2 = 0x00000028, + .dram_dqm3 = 0x00000028, + .dram_ras = 0x00000020, + .dram_cas = 0x00000020, + .dram_odt0 = 0x00000020, + .dram_odt1 = 0x00000020, + .dram_sdba2 = 0x00000000, + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + .dram_sdclk_0 = 0x00000030, + .dram_sdqs0 = 0x00000028, + .dram_sdqs1 = 0x00000028, + .dram_sdqs2 = 0x00000028, + .dram_sdqs3 = 0x00000028, + .dram_reset = 0x00000020, +}; + +static const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000020, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000028, + .grp_b1ds = 0x00000028, + .grp_ctlds = 0x00000020, + .grp_ddr_type = 0x000c0000, + .grp_b2ds = 0x00000028, + .grp_b3ds = 0x00000028, +}; + +static const struct mx6_mmdc_calibration neo_mmcd_calib = { + .p0_mpwldectrl0 = 0x000E000B, + .p0_mpwldectrl1 = 0x000E0010, + .p0_mpdgctrl0 = 0x41600158, + .p0_mpdgctrl1 = 0x01500140, + .p0_mprddlctl = 0x3A383E3E, + .p0_mpwrdlctl = 0x3A383C38, +}; + +static const struct mx6_mmdc_calibration neo_basic_mmcd_calib = { + .p0_mpwldectrl0 = 0x001E0022, + .p0_mpwldectrl1 = 0x001C0019, + .p0_mpdgctrl0 = 0x41540150, + .p0_mpdgctrl1 = 0x01440138, + .p0_mprddlctl = 0x403E4644, + .p0_mpwrdlctl = 0x3C3A4038, +}; + +/* MT41K256M16 */ +static struct mx6_ddr3_cfg neo_mem_ddr = { + .mem_speed = 1600, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +/* MT41K128M16 */ +static struct mx6_ddr3_cfg neo_basic_mem_ddr = { + .mem_speed = 1600, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xFFFFFFFF, &ccm->CCGR0); + writel(0xFFFFFFFF, &ccm->CCGR1); + writel(0xFFFFFFFF, &ccm->CCGR2); + writel(0xFFFFFFFF, &ccm->CCGR3); + writel(0xFFFFFFFF, &ccm->CCGR4); + writel(0xFFFFFFFF, &ccm->CCGR5); + writel(0xFFFFFFFF, &ccm->CCGR6); + writel(0xFFFFFFFF, &ccm->CCGR7); +} + +static void spl_dram_init(void) +{ + int board = get_board_value(); + + struct mx6_ddr_sysinfo sysinfo = { + .dsize = 1, /* width of data bus: 1 = 32 bits */ + .cs_density = 24, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 2, + .rtt_nom = 2, /* RTT_Nom = RZQ/2 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + }; + + mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs); + if (board == UDOO_NEO_TYPE_BASIC || board == UDOO_NEO_TYPE_BASIC_KS) + mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib, + &neo_basic_mem_ddr); + else + mx6_dram_cfg(&sysinfo, &neo_mmcd_calib, &neo_mem_ddr); +} + +void board_init_f(ulong dummy) +{ + ccgr_init(); + + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} + +#endif diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig new file mode 100644 index 0000000..3304afb --- /dev/null +++ b/configs/udoo_neo_defconfig @@ -0,0 +1,30 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_UDOO_NEO=y +CONFIG_SPL_EXT_SUPPORT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6SX" +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_DHCP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_LIBFDT=y diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h new file mode 100644 index 0000000..81e0481 --- /dev/null +++ b/include/configs/udoo_neo.h @@ -0,0 +1,94 @@ +/* + * Copyright 2014-2015 Freescale Semiconductor, Inc. + * Copyright Jasbir Matharu + * Copyright 2015 UDOO Team + * + * Configuration settings for the UDOO NEO board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <config_distro_defaults.h> +#include "mx6_common.h" + +#include "imx6_spl.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_MXC_UART + +/* MMC Configuration */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +/* Command definition */ +#define CONFIG_MXC_UART_BASE UART1_BASE +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC2*/ + +/* Linux only */ +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc0,115200\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=undefined\0" \ + "fdt_addr=0x83000000\0" \ + "ip_dyn=yes\0" \ + "mmcdev=0\0" \ + "mmcrootfstype=ext4\0" \ + "mmcautodetect=no\0" \ + "findfdt="\ + "if test $board_name = BASIC; then " \ + "setenv fdt_file imx6sx-udoo-neo-basic.dtb; fi; " \ + "if test $board_name = BASICKS; then " \ + "setenv fdt_file imx6sx-udoo-neo-basic.dtb; fi; " \ + "if test $board_name = FULL; then " \ + "setenv fdt_file imx6sx-udoo-neo-full.dtb; fi; " \ + "if test $board_name = EXTENDED; then " \ + "setenv fdt_file imx6sx-udoo-neo-extended.dtb; fi; " \ + "if test $fdt_file = UNDEFINED; then " \ + "echo WARNING: Could not determine dtb to use; fi; \0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "ramdisk_addr_r=0x83000000\0" \ + "ramdiskaddr=0x83000000\0" \ + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) + +#define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ + "run distro_bootcmd" + +#include <config_distro_bootcmd.h> + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000) +#define CONFIG_STACKSIZE SZ_128K + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment organization */ +#define CONFIG_ENV_OFFSET (8 * SZ_64K) +#define CONFIG_ENV_SIZE SZ_8K +#define CONFIG_ENV_IS_IN_MMC + +#endif /* __CONFIG_H */ -- 2.7.4

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[U-Boot] [PATCH v1 0/2] ARM: dts: at91: add dts files for the boards of SAMA5D3
by Wenyou Yang 10 Jan '17

10 Jan '17

The purpose of the patchset is add the dts files for boards, sama5d3 Xplained board and sama5d3xek board. Wenyou Yang (2): ARM: at91: dt: add dts files for sama5d3ek board ARM: at91: dt: add dts file for sama5d3 Xplained arch/arm/dts/Makefile | 7 + arch/arm/dts/at91-sama5d3_xplained.dts | 341 ++++++++ arch/arm/dts/sama5d3.dtsi | 1505 ++++++++++++++++++++++++++++++++ arch/arm/dts/sama5d31.dtsi | 16 + arch/arm/dts/sama5d31ek.dts | 52 ++ arch/arm/dts/sama5d33.dtsi | 14 + arch/arm/dts/sama5d33ek.dts | 45 + arch/arm/dts/sama5d34.dtsi | 16 + arch/arm/dts/sama5d34ek.dts | 62 ++ arch/arm/dts/sama5d35.dtsi | 18 + arch/arm/dts/sama5d35ek.dts | 55 ++ arch/arm/dts/sama5d36.dtsi | 20 + arch/arm/dts/sama5d36ek.dts | 57 ++ arch/arm/dts/sama5d36ek_cmp.dts | 55 ++ arch/arm/dts/sama5d3_can.dtsi | 74 ++ arch/arm/dts/sama5d3_emac.dtsi | 55 ++ arch/arm/dts/sama5d3_gmac.dtsi | 88 ++ arch/arm/dts/sama5d3_lcd.dtsi | 215 +++++ arch/arm/dts/sama5d3_mci2.dtsi | 59 ++ arch/arm/dts/sama5d3_tcb1.dtsi | 39 + arch/arm/dts/sama5d3_uart.dtsi | 79 ++ arch/arm/dts/sama5d3xcm.dtsi | 123 +++ arch/arm/dts/sama5d3xcm_cmp.dtsi | 166 ++++ arch/arm/dts/sama5d3xdm.dtsi | 41 + arch/arm/dts/sama5d3xmb.dtsi | 221 +++++ arch/arm/dts/sama5d3xmb_cmp.dtsi | 230 +++++ 26 files changed, 3653 insertions(+) create mode 100644 arch/arm/dts/at91-sama5d3_xplained.dts create mode 100644 arch/arm/dts/sama5d3.dtsi create mode 100644 arch/arm/dts/sama5d31.dtsi create mode 100644 arch/arm/dts/sama5d31ek.dts create mode 100644 arch/arm/dts/sama5d33.dtsi create mode 100644 arch/arm/dts/sama5d33ek.dts create mode 100644 arch/arm/dts/sama5d34.dtsi create mode 100644 arch/arm/dts/sama5d34ek.dts create mode 100644 arch/arm/dts/sama5d35.dtsi create mode 100644 arch/arm/dts/sama5d35ek.dts create mode 100644 arch/arm/dts/sama5d36.dtsi create mode 100644 arch/arm/dts/sama5d36ek.dts create mode 100644 arch/arm/dts/sama5d36ek_cmp.dts create mode 100644 arch/arm/dts/sama5d3_can.dtsi create mode 100644 arch/arm/dts/sama5d3_emac.dtsi create mode 100644 arch/arm/dts/sama5d3_gmac.dtsi create mode 100644 arch/arm/dts/sama5d3_lcd.dtsi create mode 100644 arch/arm/dts/sama5d3_mci2.dtsi create mode 100644 arch/arm/dts/sama5d3_tcb1.dtsi create mode 100644 arch/arm/dts/sama5d3_uart.dtsi create mode 100644 arch/arm/dts/sama5d3xcm.dtsi create mode 100644 arch/arm/dts/sama5d3xcm_cmp.dtsi create mode 100644 arch/arm/dts/sama5d3xdm.dtsi create mode 100644 arch/arm/dts/sama5d3xmb.dtsi create mode 100644 arch/arm/dts/sama5d3xmb_cmp.dtsi -- 2.7.4

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[U-Boot] [PATCH] sunxi: makes an invisible option for H3-like DRAM controllers
by Icenowy Zheng 09 Jan '17

09 Jan '17

Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like DesignWare DRAM controller, which do not have official free DRAM initialization code, but can use modified dram_sun8i_h3.c. Add a invisible option for easier DRAM initialization code reuse. Signed-off-by: Icenowy Zheng <icenowy(a)aosc.xyz> --- arch/arm/include/asm/arch-sunxi/dram.h | 2 +- arch/arm/mach-sunxi/Makefile | 2 +- board/sunxi/Kconfig | 7 +++++++ 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h index e0be744dba..c5456658a3 100644 --- a/arch/arm/include/asm/arch-sunxi/dram.h +++ b/arch/arm/include/asm/arch-sunxi/dram.h @@ -24,7 +24,7 @@ #include <asm/arch/dram_sun8i_a33.h> #elif defined(CONFIG_MACH_SUN8I_A83T) #include <asm/arch/dram_sun8i_a83t.h> -#elif defined(CONFIG_MACH_SUN8I_H3) +#elif defined(CONFIG_SUNXI_H3_DW_DRAM) #include <asm/arch/dram_sun8i_h3.h> #elif defined(CONFIG_MACH_SUN9I) #include <asm/arch/dram_sun9i.h> diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index e73114ee64..dc737db4b9 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -48,6 +48,6 @@ obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o obj-$(CONFIG_MACH_SUN8I_A83T) += dram_sun8i_a83t.o -obj-$(CONFIG_MACH_SUN8I_H3) += dram_sun8i_h3.o +obj-$(CONFIG_SUNXI_H3_DW_DRAM) += dram_sun8i_h3.o obj-$(CONFIG_MACH_SUN9I) += dram_sun9i.o endif diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index e1d4ab148f..4ddd992684 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -42,6 +42,12 @@ config SUNXI_GEN_SUN6I separate ahb reset control registers, custom pmic bus, new style watchdog, etc. +config SUNXI_H3_DW_DRAM + bool + ---help--- + Select this for sunxi SoCs which uses a DRAM controller like the + DesignWare controller used in H3, mainly SoCs after H3, which do + not have official open-source DRAM initialization code. choice prompt "Sunxi SoC Variant" @@ -113,6 +119,7 @@ config MACH_SUN8I_H3 select ARCH_SUPPORT_PSCI select SUNXI_GEN_SUN6I select SUPPORT_SPL + select SUNXI_H3_DW_DRAM select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT config MACH_SUN9I -- 2.11.0

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[U-Boot] [PATCH v2 0/14] sunxi: Add support for the CHIP Pro
by Maxime Ripard 09 Jan '17

09 Jan '17

The CHIP Pro is a SoM made by NextThing Co, and that embeds a GR8 SIP, an AXP209 PMIC, a WiFi BT chip and a 512MB SLC NAND. Since the first Allwinner device coming whit an SLC NAND that doesn't have the shortcomings (and breakages) the MLC NAND has, we can finally enable the NAND support on a board by default. This is the occasion to introduce a bunch of additions needed imo to be able to come up with a sane NAND support for our users. The biggest pain point is that the BROM uses a different ECC and randomizer configuration than for the rest of the NAND. In order to lessen the number of bitflips, you also need to pad with random data the SPL image. Since it's quite tedious to do right (and most users won't be able to figure it out) and since if it is not done right, it will eventually turn into an unusable system (which is bad UX), we think that the best solution is to generate an SPL image that already embeds all this. We'll possible have to do the same thing for the U-Boot image (at least for the random padding) on MLC NANDs. The only drawback from that is that you need to flash it raw, instead of using the usual nand write, but it's just a different command, nothing major anyway. In order to flash it, from a device switched in FEL, on your host: sunxi-fel spl spl/sunxi-spl.bin sunxi-fel write 0x4a000000 u-boot-dtb.bin sunxi-fel write 0x43000000 spl/sunxi-spl-with-ecc.bin sunxi-fel exe 0x4a000000 And on the board, once u-boot is running (assuming the NAND is already erased): nand write.raw.noverify 0x43000000 0 40 nand write.raw.noverify 0x43000000 0x400000 40 nand write 0x4a000000 0x800000 0xc0000 I also encountered some weird bug in the private libgcc that prevents U-Boot from loading. Disabling CONFIG_USE_PRIVATE_LIBGCC fixes that. Let me know what you think, Maxime Changes from v1: - Allowed to build lib/bch.c for the host, and used that in the image builder - Fixed a bug in the NAND driver - Wrote a documentation on how to flash a NAND image on an Allwinner board - Fixed a few compilation breakages and issues - Moved U-boot offset out of the config header and into Kconfig - Moved the environment into UBI - Moved the environment selection to Kconfig - Moved the CMD_MTDPARTS options to Kconfig - Provide MTDIDS_DEFAULT and MTDPARTS_DEFAULT options through Kconfig - Added the tags from everyone Boris Brezillon (1): mtd: nand: add support for the TC58NVG2S0H chip Hans de Goede (1): sunxi: Enable UBI and NAND support Maxime Ripard (12): nand: sunxi: Fix modulo by zero error bch: Allow to build for the host tools: sunxi: Add spl image builder common: Move environment choice to Kconfig cmd: Add Kconfig option for CMD_MTDPARTS and related options mtd: sunxi: Select the U-Boot location config option mtd: sunxi: Change U-Boot offset sunxi: Add the default mtdids and mtdparts to our env nand: sunxi: Add options for the SPL NAND configuration scripts: sunxi: Build an raw SPL image sunxi: Sync GR8 DTS and AXP209 with the kernel sunxi: Add support for the CHIP Pro Makefile | 3 +- arch/arm/dts/Makefile | 1 +- arch/arm/dts/axp209.dtsi | 6 +- arch/arm/dts/ntc-gr8-chip-pro.dts | 266 +++++++- arch/arm/dts/ntc-gr8.dtsi | 1132 ++++++++++++++++++++++++++++++- board/sunxi/Kconfig | 8 +- board/sunxi/README.nand | 54 +- cmd/Kconfig | 19 +- cmd/mtdparts.c | 8 +- common/Kconfig | 65 ++- configs/CHIP_pro_defconfig | 32 +- drivers/mtd/nand/Kconfig | 19 +- drivers/mtd/nand/nand_ids.c | 3 +- drivers/mtd/nand/sunxi_nand_spl.c | 7 +- include/configs/sunxi-common.h | 44 +- include/environment.h | 2 +- lib/bch.c | 48 +- scripts/Makefile.spl | 15 +- tools/.gitignore | 1 +- tools/Makefile | 2 +- tools/sunxi-spl-image-builder.c | 484 +++++++++++++- 21 files changed, 2204 insertions(+), 15 deletions(-) create mode 100644 arch/arm/dts/ntc-gr8-chip-pro.dts create mode 100644 arch/arm/dts/ntc-gr8.dtsi create mode 100644 board/sunxi/README.nand create mode 100644 configs/CHIP_pro_defconfig create mode 100644 tools/sunxi-spl-image-builder.c base-commit: d8bdfc80da39211d95f10d24e79f2e867305f71b -- git-series 0.8.11

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[U-Boot] [PATCH][v3] armv8: fsl-layerscape: Add support of GPIO structure
by Prabhakar Kushwaha 06 Jan '17

06 Jan '17

Layerscape Gen2 SoC supports GPIO registers to control GPIO signals. Adding support of GPIO structure to access GPIO registers. Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava(a)nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> --- Changes for v2: Incorporated York's comments - Removed CONFIG_SYS_GPIO1_ADDR as bool - Renamed CONFIG_SYS_GPIO1_ADDR Changes for v3: - Corrected the GPIO address - updated patch description This structure is required while supporting ethernent in LS1012AFRDM. arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index d684a07..33f3e2e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -52,6 +52,11 @@ #define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000) #define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000) +#define GPIO1_BASE_ADDR (CONFIG_SYS_IMMR + 0x1300000) +#define GPIO2_BASE_ADDR (CONFIG_SYS_IMMR + 0x1310000) +#define GPIO3_BASE_ADDR (CONFIG_SYS_IMMR + 0x1320000) +#define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x1330000) + #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) @@ -588,6 +593,16 @@ struct ccsr_cci400 { u8 res_e004[0x10000 - 0xe004]; }; +struct ccsr_gpio { + u32 gpdir; + u32 gpodr; + u32 gpdat; + u32 gpier; + u32 gpimr; + u32 gpicr; + u32 gpibe; +}; + /* MMU 500 */ #define SMMU_SCR0 (SMMU_BASE + 0x0) #define SMMU_SCR1 (SMMU_BASE + 0x4) -- 2.7.4

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