November 2016 - U-Boot

[U-Boot] [PATCH RESEND v2 1/2] ARM: dts: dra7xx: Update spi-max-frequency for qspi slave node
by Vignesh R 05 Nov '16

05 Nov '16

Update the spi-max-frequency property of m25p80 flash slave to match that of TI QSPI controller node, so that QSPI operations happen at maximum supported frequency of 76.8MHz. Signed-off-by: Vignesh R <vigneshr(a)ti.com> Reviewed-by: Jagan Teki <jteki(a)openedev.com> --- v2: No changes arch/arm/dts/dra7-evm.dts | 2 +- arch/arm/dts/dra72-evm-common.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts index fe755c05841d..be36d456206d 100644 --- a/arch/arm/dts/dra7-evm.dts +++ b/arch/arm/dts/dra7-evm.dts @@ -505,7 +505,7 @@ spi-max-frequency = <76800000>; m25p80@0 { compatible = "s25fl256s1","spi-flash"; - spi-max-frequency = <64000000>; + spi-max-frequency = <76800000>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; diff --git a/arch/arm/dts/dra72-evm-common.dtsi b/arch/arm/dts/dra72-evm-common.dtsi index b0993e5bf7e0..1e1ca725577f 100644 --- a/arch/arm/dts/dra72-evm-common.dtsi +++ b/arch/arm/dts/dra72-evm-common.dtsi @@ -441,7 +441,7 @@ spi-max-frequency = <76800000>; m25p80@0 { compatible = "s25fl256s1", "spi-flash"; - spi-max-frequency = <64000000>; + spi-max-frequency = <76800000>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; -- 2.10.2

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[U-Boot] cubieboard sunxi u-boot help me
by 崔超 05 Nov '16

05 Nov '16

Hi , I' from China. I am studying u-boot on Cubieboard and I have a problem. https://github.com/OSer916/u-boot.git . My code is on the "cubieboard" branch. When I do "make sunny_defconfig && make CROSS_COMPILE=arm-linux-gnueabihf-", the trouble comes out last: arm-linux-gnueabihf-ld.bfd: BFD (GNU Binutils) 2.25.0 Linaro 2015_10 assertion fail /home/tcwg-buildslave/workspace/tcwg-make-release/label/tcwg-x86_64-ex40/target/arm-linux-gnueabihf/snapshots/binutils-gdb.git~linaro_binutils-2_25-branch/bfd/elf32-arm.c:7827 arm-linux-gnueabihf-ld.bfd: error: required section '.rel.plt' not found in the linker script arm-linux-gnueabihf-ld.bfd: final link failed: Invalid operation Makefile:1207: recipe for target 'u-boot' failed make: *** [u-boot] Error 1 I used the compiler version is "gcc-linaro-5.3-2016.02-x86_64_arm-linux-gnueabihf" Hi, thanks! My mean is that I am porting u-boot to the Cubieboard board from stratch for studying the internal construction of the u-boot. So I create a new defconfig named "sunny_defconfig". The "diff" of the branch "cubieboard" and the "master": https://github.com/OSer916/u-boot/commit/df3b61630806ab2fbcfdfb48aee048a076… When I do "make sunny_defconfig" and "make CROSS_COMPILE=arm-linux-gnueabihf-", I have the trouble that " arm-linux-gnueabihf-ld.bfd: error: required section '.rel.plt' not found in the linker script" Thanks! -- OSer

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[U-Boot] [PATCH v2 2/7] spi: cadence_qspi: Fix baud rate calculation
by Phil Edworthy 04 Nov '16

04 Nov '16

With the existing code, when the requested SPI clock rate is near to the lowest that can be achieved by the hardware (max divider of the ref clock is 32), the generated clock rate is wrong. For example, with a 50MHz ref clock, when asked for anything less than a 1.5MHz SPI clock, the code sets up the divider to generate 25MHz. This change fixes the calculation. Signed-off-by: Phil Edworthy <phil.edworthy(a)renesas.com> --- v2: - Use the DIV_ROUND_UP macro --- drivers/spi/cadence_qspi_apb.c | 23 +++++++---------------- 1 file changed, 7 insertions(+), 16 deletions(-) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 2403e71..b9e0df7 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -273,22 +273,13 @@ void cadence_qspi_apb_config_baudrate_div(void *reg_base, reg = readl(reg_base + CQSPI_REG_CONFIG); reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); - div = ref_clk_hz / sclk_hz; - - if (div > 32) - div = 32; - - /* Check if even number. */ - if ((div & 1)) { - div = (div / 2); - } else { - if (ref_clk_hz % sclk_hz) - /* ensure generated SCLK doesn't exceed user - specified sclk_hz */ - div = (div / 2); - else - div = (div / 2) - 1; - } + /* + * The baud_div field in the config reg is 4 bits, and the ref clock is + * divided by 2 * (baud_div + 1). Round up the divider to ensure the + * SPI clock rate is less than or equal to the requested clock rate. + */ + div = DIV_ROUND_UP(ref_clk_hz, sclk_hz); + div = DIV_ROUND_UP(div, 2) - 1; debug("%s: ref_clk %dHz sclk %dHz Div 0x%x\n", __func__, ref_clk_hz, sclk_hz, div); -- 2.5.0

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[U-Boot] [RFC] 0/4] Add Pl330 DMA support
by Dinh Nguyen 04 Nov '16

04 Nov '16

Hi, This patchset adds the PL330 DMA driver to U-Boot. The SoCFPGA platform makes use of the PL330 to transfer zereos to the SDRAM which enables the ECC bit. This is only an RFC because after rebasing to v2016.11-rc1, I had to revert the following patch "a78cd8613204 ARM: Rework and correct barrier definitions" in order for this patch set to work correctly. With the above patch applied, after the SDRAM scrubbing is complete, the SPL is failing to find the MMC device. I'm continue to debug this, but would like to solicit comments with this patchset. Thanks, Dinh Dinh Nguyen (4): drivers: dma: Add the ARM PL330 DMA driver dma: Kconfig: Add CONFIG_PL330_DMA entry dm: add DMA_SUPPORTS_DEV_TO_MEM type to DMA_UCLASS arm: socfpga: scrub the SDRAM to properly enable ECC support arch/arm/include/asm/pl330.h | 105 +++ arch/arm/mach-socfpga/include/mach/reset_manager.h | 21 + arch/arm/mach-socfpga/include/mach/sdram.h | 2 + arch/arm/mach-socfpga/spl.c | 8 + arch/arm/mach-socfpga/wrap_sdram_config.c | 28 + configs/socfpga_cyclone5_defconfig | 2 + drivers/dma/Kconfig | 4 + drivers/dma/Makefile | 1 + drivers/dma/dma-uclass.c | 3 +- drivers/dma/pl330.c | 942 +++++++++++++++++++++ 10 files changed, 1115 insertions(+), 1 deletion(-) create mode 100644 arch/arm/include/asm/pl330.h create mode 100644 drivers/dma/pl330.c -- 2.8.3

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Re: [U-Boot] [PATCHv2 1/3] igep00x0: disable CONFIG_DISPLAY_BOARDINFO
by Ladislav Michl 04 Nov '16

04 Nov '16

On Fri, Nov 04, 2016 at 12:42:57PM -0300, Javier Martinez Canillas wrote: > Hello Ladis, > > On 11/04/2016 08:55 AM, Ladislav Michl wrote: > > As a single U-Boot binary can now run on various board modifications, > > drop CONFIG_DISPLAY_BOARDINFO as it prints flash memory information > > too early to give us chance to easily detect it. Also saves few bytes > > as a bonus. > > > > Signed-off-by: Ladislav Michl <ladis(a)linux-mips.org> > > --- > > I tried to test your patches on latest u-boot master (sha-1 dd93a8e9e688) > but my IGEPv2 board fails to boot and prints in an infinite loop following: > > "ecc unrecoverable error" This comes from SPL, right? That would imply you boot from NAND... > This is not related to your patches though, since I've the same issue > without your patches applied. > > Did you see this issue? u-boot works with previous v2016.09 release so > this is a newly introduced regression. No, otherwise I would fix that. Care to send complete boot log if there is any? > Unfortunately I don't have time to dig deeper on this but I may give a > try next week. Thank you, ladis

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[U-Boot] U-Boot Support for SIL3531
by Rudolf J Streif 04 Nov '16

04 Nov '16

Does anyone know if u-boot supports the SIL3531 PCIE SATA controller? drivers/block/sata_sil.c explicitly lists SIL3131, SIL3132, and SIL3124. I am not that familiar with the history of the SIL SATA chips and maybe somebody knows if the SIL3531 is backwards compatible to those chips. Thank you, :rjs

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[U-Boot] cubieboard sunxi u-boot help me
by 崔超 04 Nov '16

04 Nov '16

Hi , I' from China. I am studying u-boot on Cubieboard and I have a problem. https://github.com/OSer916/u-boot.git . My code is on the "cubieboard" branch. When I do "make sunny_defconfig && make CROSS_COMPILE=arm-linux-gnueabihf-", the trouble comes out last: arm-linux-gnueabihf-ld.bfd: BFD (GNU Binutils) 2.25.0 Linaro 2015_10 assertion fail /home/tcwg-buildslave/workspace/tcwg-make-release/label/tcwg-x86_64-ex40/target/arm-linux-gnueabihf/snapshots/binutils-gdb.git~linaro_binutils-2_25-branch/bfd/elf32-arm.c:7827 arm-linux-gnueabihf-ld.bfd: error: required section '.rel.plt' not found in the linker script arm-linux-gnueabihf-ld.bfd: final link failed: Invalid operation Makefile:1207: recipe for target 'u-boot' failed make: *** [u-boot] Error 1 I used the compiler version is "gcc-linaro-5.3-2016.02-x86_64_arm-linux-gnueabihf" Thanks!

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[U-Boot] [PATCH v2 ] spi: cadence_qspi: Support specifying the sample edge used
by Phil Edworthy 04 Nov '16

04 Nov '16

Whilst at it, move the code to read the "sram-size" property into the other code that reads properties from the node, rather than the SF subnode. Also change the code to use a bool for the bypass arg. Signed-off-by: Phil Edworthy <phil.edworthy(a)renesas.com> --- v2: Change name of DT prop and provide details of what it does. Whilst at it, move the code to read the "sram-size" property into the other code that reads properties from the node, rather than the SF subnode. Also changed the code to use a bool for the bypass arg. Note: I didn't explicitly state that the prop is optional as all of the props listed in that section are optional. --- doc/device-tree-bindings/spi/spi-cadence.txt | 2 ++ drivers/spi/cadence_qspi.c | 13 +++++++++---- drivers/spi/cadence_qspi.h | 3 ++- drivers/spi/cadence_qspi_apb.c | 8 +++++++- 4 files changed, 20 insertions(+), 6 deletions(-) diff --git a/doc/device-tree-bindings/spi/spi-cadence.txt b/doc/device-tree-bindings/spi/spi-cadence.txt index c1e2233..94c800b 100644 --- a/doc/device-tree-bindings/spi/spi-cadence.txt +++ b/doc/device-tree-bindings/spi/spi-cadence.txt @@ -26,3 +26,5 @@ connected flash properties select (n_ss_out). - tslch-ns : Delay in master reference clocks between setting n_ss_out low and first bit transfer +- sample-edge-rising : Data outputs from flash memory will be sampled on the + rising edge. Default is falling edge. diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 1051afb..16fb18e 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -39,8 +39,10 @@ static int cadence_spi_write_speed(struct udevice *bus, uint hz) /* Calibration sequence to determine the read data capture delay register */ static int spi_calibration(struct udevice *bus, uint hz) { + struct cadence_spi_platdata *plat = bus->platdata; struct cadence_spi_priv *priv = dev_get_priv(bus); void *base = priv->regbase; + bool edge = plat->sample_edge_rising; u8 opcode_rdid = 0x9F; unsigned int idcode = 0, temp = 0; int err = 0, i, range_lo = -1, range_hi = -1; @@ -49,7 +51,7 @@ static int spi_calibration(struct udevice *bus, uint hz) cadence_spi_write_speed(bus, 1000000); /* configure the read data capture delay register to 0 */ - cadence_qspi_apb_readdata_capture(base, 1, 0); + cadence_qspi_apb_readdata_capture(base, true, edge, 0); /* Enable QSPI */ cadence_qspi_apb_controller_enable(base); @@ -69,7 +71,7 @@ static int spi_calibration(struct udevice *bus, uint hz) cadence_qspi_apb_controller_disable(base); /* reconfigure the read data capture delay register */ - cadence_qspi_apb_readdata_capture(base, 1, i); + cadence_qspi_apb_readdata_capture(base, true, edge, i); /* Enable back QSPI */ cadence_qspi_apb_controller_enable(base); @@ -105,7 +107,8 @@ static int spi_calibration(struct udevice *bus, uint hz) cadence_qspi_apb_controller_disable(base); /* configure the final value for read data capture delay register */ - cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2); + cadence_qspi_apb_readdata_capture(base, true, edge, + (range_hi + range_lo) / 2); debug("SF: Read data capture delay calibrated to %i (%i - %i)\n", (range_hi + range_lo) / 2, range_lo, range_hi); @@ -298,6 +301,7 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) plat->regbase = (void *)data[0]; plat->ahbbase = (void *)data[2]; + plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128); /* All other paramters are embedded in the child node */ subnode = fdt_first_subnode(blob, node); @@ -317,7 +321,8 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) plat->tsd2d_ns = fdtdec_get_int(blob, subnode, "tsd2d-ns", 255); plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20); plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20); - plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128); + plat->sample_edge_rising = fdtdec_get_bool(blob, subnode, + "sample-edge-rising"); debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", __func__, plat->regbase, plat->ahbbase, plat->max_hz, diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index a849f7b..ad1dbae 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -26,6 +26,7 @@ struct cadence_spi_platdata { u32 tchsh_ns; u32 tslch_ns; u32 sram_size; + bool sample_edge_rising; }; struct cadence_spi_priv { @@ -73,6 +74,6 @@ void cadence_qspi_apb_delay(void *reg_base, unsigned int tchsh_ns, unsigned int tslch_ns); void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy); void cadence_qspi_apb_readdata_capture(void *reg_base, - unsigned int bypass, unsigned int delay); + bool bypass, bool edge, unsigned int delay); #endif /* __CADENCE_QSPI_H__ */ diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 4a6b76e..7cc6411 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -98,6 +98,7 @@ #define CQSPI_REG_RD_DATA_CAPTURE_BYPASS BIT(0) #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB 1 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK 0xF +#define CQSPI_REG_RD_DATA_CAPTURE_EDGE BIT(5) #define CQSPI_REG_SIZE 0x14 #define CQSPI_REG_SIZE_ADDRESS_LSB 0 @@ -237,7 +238,7 @@ static unsigned int cadence_qspi_wait_idle(void *reg_base) } void cadence_qspi_apb_readdata_capture(void *reg_base, - unsigned int bypass, unsigned int delay) + bool bypass, bool edge, unsigned int delay) { unsigned int reg; cadence_qspi_apb_controller_disable(reg_base); @@ -249,6 +250,11 @@ void cadence_qspi_apb_readdata_capture(void *reg_base, else reg &= ~CQSPI_REG_RD_DATA_CAPTURE_BYPASS; + if (edge) + reg |= CQSPI_REG_RD_DATA_CAPTURE_EDGE; + else + reg &= ~CQSPI_REG_RD_DATA_CAPTURE_EDGE; + reg &= ~(CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB); -- 2.5.0

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[U-Boot] [PULL] u-boot-usb/master
by Marek Vasut 04 Nov '16

04 Nov '16

The following changes since commit d8bdfc80da39211d95f10d24e79f2e867305f71b: Prepare v2016.11-rc3 (2016-10-31 16:36:10 -0400) are available in the git repository at: git://git.denx.de/u-boot-usb.git master for you to fetch changes up to dd93a8e9e688f4c448092a275bf7db3e16d21c6f: dfu: align array in dfu_get_dev_type with enum dfu_device_type (2016-11-03 11:55:25 +0100) ---------------------------------------------------------------- Michal Simek (1): cmd: dfu: Add error handling for board_usb_init Patrick Delaunay (1): dfu: align array in dfu_get_dev_type with enum dfu_device_type common/dfu.c | 6 +++++- drivers/dfu/dfu.c | 2 +- 2 files changed, 6 insertions(+), 2 deletions(-)

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[U-Boot] Please pull u-boot-rockchip
by Simon Glass 04 Nov '16

04 Nov '16

Hi Tom, This includes various minor tweaks for rockchip. The following changes since commit 48d2fc47c9feac54fdc0e2e0462f13b1a8689ece: Merge branch 'sun9i-a80-spl' of http://git.denx.de/u-boot-sunxi (2016-10-30 08:12:00 -0400) are available in the git repository at: git://git.denx.de/u-boot-rockchip.git for you to fetch changes up to 4594ac07847f5c7fe7294ce6c71849fea0a431e0: rk3288: kconfig: remove duplicate definition of SPL_MMC_SUPPORT (2016-10-30 13:29:06 -0600) ---------------------------------------------------------------- Jacob Chen (3): clk: rk3399: fix rockchip_get_cru rockchip: use rockchip linux partitions layout rockchip: doc: add GPT partition layout Kever Yang (7): rk3399: disable the clock multiplier support when SoC init rk3288: fix reg address for GRF_SOC_CON2 evb-rk3399: config: set emmc as default boot dev rk3288: config change for enable dram capacity auto-detect. rk3288: sdram: auto-detect the capacity dts: rk3288: remove node in dmc which not need anymore rk3288: kconfig: remove duplicate definition of SPL_MMC_SUPPORT Sandy Patterson (1): rockchip: RK3288 needs fdt and initrd below 256M now Simon Glass (3): rockchip: rk3036: Move rockchip_get_cru() out of the driver rockchip: rk3399: Move rockchip_get_cru() out of the driver rockchip: rk3288: Move rockchip_get_cru() out of the driver arch/arm/dts/rk3288-evb.dts | 3 - arch/arm/dts/rk3288-fennec.dts | 3 - arch/arm/dts/rk3288-firefly.dts | 2 - arch/arm/dts/rk3288-miniarm.dts | 3 - arch/arm/dts/rk3288-popmetal.dts | 3 - arch/arm/dts/rk3288-rock2-square.dts | 2 - arch/arm/dts/rk3288-veyron.dtsi | 2 - arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 6 ++ arch/arm/include/asm/arch-rockchip/cru_rk3288.h | 7 +++ arch/arm/include/asm/arch-rockchip/cru_rk3399.h | 6 ++ arch/arm/include/asm/arch-rockchip/sdram.h | 15 +++++ arch/arm/mach-rockchip/rk3036/Makefile | 2 + arch/arm/mach-rockchip/rk3036/clk_rk3036.c | 33 +++++++++++ arch/arm/mach-rockchip/rk3288/Kconfig | 3 - arch/arm/mach-rockchip/rk3288/clk_rk3288.c | 16 ++++++ arch/arm/mach-rockchip/rk3288/rk3288.c | 2 +- arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 272 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------------- arch/arm/mach-rockchip/rk3399/Makefile | 1 + arch/arm/mach-rockchip/rk3399/clk_rk3399.c | 33 +++++++++++ arch/arm/mach-rockchip/rk3399/rk3399.c | 14 +++++ configs/evb-rk3288_defconfig | 1 + configs/fennec-rk3288_defconfig | 1 + configs/miniarm-rk3288_defconfig | 1 + configs/popmetal-rk3288_defconfig | 1 + doc/README.rockchip | 11 +++- drivers/clk/rockchip/clk_rk3036.c | 24 +------- drivers/clk/rockchip/clk_rk3288.c | 21 ------- drivers/clk/rockchip/clk_rk3399.c | 24 +------- include/configs/evb_rk3399.h | 2 +- include/configs/rk3036_common.h | 17 +----- include/configs/rk3288_common.h | 23 ++------ include/configs/rk3399_common.h | 16 +----- include/configs/rockchip-common.h | 35 ++++++++++++ 33 files changed, 422 insertions(+), 183 deletions(-) create mode 100644 arch/arm/mach-rockchip/rk3036/clk_rk3036.c create mode 100644 arch/arm/mach-rockchip/rk3399/clk_rk3399.c create mode 100644 include/configs/rockchip-common.h Regards, Simon

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