November 2016 - U-Boot

[U-Boot] [PATCH 2/2][v2] armv8: ls1046aqds: add lpuart support
by shh.xie＠gmail.com 23 Nov '16

23 Nov '16

From: Shaohui Xie <Shaohui.Xie(a)nxp.com> LPUART0 is used by default, and it's using platform clock. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)nxp.com> --- changes in v2: 1. dropped CONFIG_LPUART_CLK. 2. uses CONFIG_SYS_FSL_DDR4 in defconfig. arch/arm/dts/Makefile | 1 + arch/arm/dts/fsl-ls1046a-qds-lpuart.dts | 16 ++++++++++ arch/arm/dts/fsl-ls1046a-qds.dtsi | 4 +++ arch/arm/dts/fsl-ls1046a.dtsi | 54 +++++++++++++++++++++++++++++++++ board/freescale/ls1046aqds/ls1046aqds.c | 18 +++++++++++ configs/ls1046aqds_lpuart_defconfig | 30 ++++++++++++++++++ include/configs/ls1046aqds.h | 8 +++++ 7 files changed, 131 insertions(+) create mode 100644 arch/arm/dts/fsl-ls1046a-qds-lpuart.dts create mode 100644 configs/ls1046aqds_lpuart_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8dbaea0..afc68e1 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -148,6 +148,7 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1043a-qds-lpuart.dtb \ fsl-ls1043a-rdb.dtb \ fsl-ls1046a-qds-duart.dtb \ + fsl-ls1046a-qds-lpuart.dtb \ fsl-ls1046a-rdb.dtb \ fsl-ls1012a-qds.dtb \ fsl-ls1012a-rdb.dtb \ diff --git a/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts b/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts new file mode 100644 index 0000000..21243d0 --- /dev/null +++ b/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts @@ -0,0 +1,16 @@ +/* + * Device Tree file for Freescale Layerscape-1046A family SoC. + * + * Copyright (C) 2016, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "fsl-ls1046a-qds.dtsi" + +/ { + chosen { + stdout-path = &lpuart0; + }; +}; diff --git a/arch/arm/dts/fsl-ls1046a-qds.dtsi b/arch/arm/dts/fsl-ls1046a-qds.dtsi index c512293..a49ca08 100644 --- a/arch/arm/dts/fsl-ls1046a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1046a-qds.dtsi @@ -75,3 +75,7 @@ &duart1 { status = "okay"; }; + +&lpuart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index 87dd997..359a9d1 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -151,6 +151,60 @@ clocks = <&clockgen 4 0>; }; + lpuart0: serial@2950000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2950000 0x0 0x1000>; + interrupts = <0 48 0x4>; + clocks = <&clockgen 4 0>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart1: serial@2960000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2960000 0x0 0x1000>; + interrupts = <0 49 0x4>; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart2: serial@2970000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2970000 0x0 0x1000>; + interrupts = <0 50 0x4>; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart3: serial@2980000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2980000 0x0 0x1000>; + interrupts = <0 51 0x4>; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart4: serial@2990000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2990000 0x0 0x1000>; + interrupts = <0 52 0x4>; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart5: serial@29a0000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x29a0000 0x0 0x1000>; + interrupts = <0 53 0x4>; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + qspi: quadspi@1550000 { compatible = "fsl,vf610-qspi"; #address-cells = <1>; diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index 8c18538..552365b 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -120,6 +120,13 @@ unsigned long get_board_ddr_clk(void) return 66666666; } +#ifdef CONFIG_LPUART +u32 get_lpuart_clk(void) +{ + return gd->bus_clk; +} +#endif + int select_i2c_ch_pca9547(u8 ch) { int ret; @@ -157,6 +164,9 @@ int board_early_init_f(void) struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; u32 usb_pwrfault; #endif +#ifdef CONFIG_LPUART + u8 uart; +#endif #ifdef CONFIG_SYS_I2C_EARLY_INIT i2c_early_init_f(); @@ -175,6 +185,14 @@ int board_early_init_f(void) out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); #endif +#ifdef CONFIG_LPUART + /* We use lpuart0 as system console */ + uart = QIXIS_READ(brdcfg[14]); + uart &= ~CFG_UART_MUX_MASK; + uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT; + QIXIS_WRITE(brdcfg[14], uart); +#endif + return 0; } diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig new file mode 100644 index 0000000..25bb5f9 --- /dev/null +++ b/configs/ls1046aqds_lpuart_defconfig @@ -0,0 +1,30 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1046AQDS=y +CONFIG_SYS_FSL_DDR4=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-lpuart" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="LPUART" +CONFIG_BOOTDELAY=10 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_FSL_DSPI=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index c0f5bd3..29e0aa5 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -127,6 +127,14 @@ unsigned long get_board_ddr_clk(void); #endif #endif +/* LPUART */ +#ifdef CONFIG_LPUART +#define CONFIG_LPUART_32B_REG +#define CFG_UART_MUX_MASK 0x6 +#define CFG_UART_MUX_SHIFT 1 +#define CFG_LPUART_EN 0x2 +#endif + /* SATA */ #define CONFIG_LIBATA #define CONFIG_SCSI_AHCI -- 2.1.0.27.g96db324

2 1

[U-Boot] [PATCH 1/2][v2] lpuart: add a get_lpuart_clk function
by shh.xie＠gmail.com 23 Nov '16

23 Nov '16

From: Shaohui Xie <Shaohui.Xie(a)nxp.com> It's not always true that LPUART clock is CONFIG_SYS_CLK_FREQ, this patch provides a weak function get_lpuart_clk, so that the clock can be ovreride on a specific board which uses different clock for LPUART. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)nxp.com> --- changes in v2: none. drivers/serial/serial_lpuart.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index 042e9a2..beb4243 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -170,9 +170,14 @@ static int lpuart_serial_probe(struct udevice *dev) } #else +u32 __weak get_lpuart_clk(void) +{ + return CONFIG_SYS_CLK_FREQ; +} + static void _lpuart32_serial_setbrg(struct lpuart_fsl *base, int baudrate) { - u32 clk = CONFIG_SYS_CLK_FREQ; + u32 clk = get_lpuart_clk(); u32 sbr; sbr = (clk / (16 * baudrate)); -- 2.1.0.27.g96db324

2 1

[U-Boot] [PATCH V2] Add support of ls1021a-iot
by feng.li_2＠nxp.com 23 Nov '16

23 Nov '16

From: Feng Li <feng.li_2(a)nxp.com> The patch add support ls1021a-iot. It supports I2C, MMC, PCIe, eTSEC, SATA, EEPROM, CPLD, HDMI, Serial port, HXCI, DSPI, SD boot, QSPI boot, Broadcom wifi card, QCA wifi card. Signed-off-by: Feng Li <feng.li_2(a)nxp.com> Cc: York Sun <york.sun(a)nxp.com> Cc: Alison Wang <alison.wang(a)nxp.com> --- Changes for V2: - CPU_V7_HAS_NONSEC and CPU_V7_HAS_VIRT are moved to Kconfig to correctly select ARMV7_PSCI. - CONFIG_ARMV7_PSCI_1_0 and CONFIG_ARMV7_PSCI_GTE_1_0 are deleted. arch/arm/Kconfig | 15 + arch/arm/dts/Makefile | 3 +- arch/arm/dts/ls1021a-iot-duart.dts | 16 ++ arch/arm/dts/ls1021a-iot.dtsi | 103 +++++++ board/freescale/ls1021aiot/Kconfig | 15 + board/freescale/ls1021aiot/MAINTAINERS | 7 + board/freescale/ls1021aiot/Makefile | 9 + board/freescale/ls1021aiot/README | 58 ++++ board/freescale/ls1021aiot/dcu.c | 47 ++++ board/freescale/ls1021aiot/ls1021aiot.c | 259 +++++++++++++++++ board/freescale/ls1021aiot/ls102xa_pbi.cfg | 14 + board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg | 27 ++ board/freescale/ls1021aiot/psci.S | 28 ++ configs/ls1021aiot_qspi_defconfig | 15 + configs/ls1021aiot_sdcard_defconfig | 17 ++ include/configs/ls1021aiot.h | 367 +++++++++++++++++++++++++ 16 files changed, 999 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/ls1021a-iot-duart.dts create mode 100644 arch/arm/dts/ls1021a-iot.dtsi create mode 100644 board/freescale/ls1021aiot/Kconfig create mode 100644 board/freescale/ls1021aiot/MAINTAINERS create mode 100644 board/freescale/ls1021aiot/Makefile create mode 100644 board/freescale/ls1021aiot/README create mode 100644 board/freescale/ls1021aiot/dcu.c create mode 100644 board/freescale/ls1021aiot/ls1021aiot.c create mode 100644 board/freescale/ls1021aiot/ls102xa_pbi.cfg create mode 100644 board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg create mode 100644 board/freescale/ls1021aiot/psci.S create mode 100644 configs/ls1021aiot_qspi_defconfig create mode 100644 configs/ls1021aiot_sdcard_defconfig create mode 100644 include/configs/ls1021aiot.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d7a9b11..5a46ad4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -761,6 +761,20 @@ config TARGET_LS1021ATWR select ARCH_SUPPORT_PSCI select LS1_DEEP_SLEEP +config TARGET_LS1021AIOT + bool "Support ls1021aiot" + select CPU_V7 + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT + select SUPPORT_SPL + select ARCH_LS1021A + select ARCH_SUPPORT_PSCI + help + Support for Freescale LS1021AIOT platform. + The LS1021A Freescale board (IOT) is a high-performance + development platform that supports the QorIQ LS1021A + Layerscape Architecture processor. + config TARGET_LS1043AQDS bool "Support ls1043aqds" select ARCH_LS1043A @@ -962,6 +976,7 @@ source "board/freescale/ls2080ardb/Kconfig" source "board/freescale/ls1021aqds/Kconfig" source "board/freescale/ls1043aqds/Kconfig" source "board/freescale/ls1021atwr/Kconfig" +source "board/freescale/ls1021aiot/Kconfig" source "board/freescale/ls1046aqds/Kconfig" source "board/freescale/ls1043ardb/Kconfig" source "board/freescale/ls1046ardb/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 836a8c4..2ea27c7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -141,7 +141,8 @@ dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb dtb-$(CONFIG_LS102XA) += ls1021a-qds-duart.dtb \ ls1021a-qds-lpuart.dtb \ - ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb + ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \ + ls1021a-iot-duart.dtb dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls2080a-rdb.dtb dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ diff --git a/arch/arm/dts/ls1021a-iot-duart.dts b/arch/arm/dts/ls1021a-iot-duart.dts new file mode 100644 index 0000000..62e4c67 --- /dev/null +++ b/arch/arm/dts/ls1021a-iot-duart.dts @@ -0,0 +1,16 @@ +/* + * Freescale ls1021a IOT board device tree source + * + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "ls1021a-iot.dtsi" + +/ { + chosen { + stdout-path = &uart0; + }; +}; diff --git a/arch/arm/dts/ls1021a-iot.dtsi b/arch/arm/dts/ls1021a-iot.dtsi new file mode 100644 index 0000000..1817c62 --- /dev/null +++ b/arch/arm/dts/ls1021a-iot.dtsi @@ -0,0 +1,103 @@ +/* + * Freescale ls1021a IOT board device tree source + * + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#include "ls1021a.dtsi" + +/ { + model = "LS1021A IOT Board"; + + aliases { + enet2_rgmii_phy = &rgmii_phy1; + enet0_sgmii_phy = &sgmii_phy2; + enet1_sgmii_phy = &sgmii_phy0; + spi0 = &qspi; + spi1 = &dspi1; + }; +}; + +&qspi { + bus-num = <0>; + status = "okay"; + + qflash0: n25q128a13@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&dspi1 { + bus-num = <0>; + status = "okay"; + + dspiflash: at26df081a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <16000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&ifc { + #address-cells = <2>; + #size-cells = <1>; + /* NOR Flash on board */ + ranges = <0x0 0x0 0x60000000 0x08000000>; + status = "okay"; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x8000000>; + bank-width = <2>; + device-width = <1>; + }; +}; + +&lpuart0 { + status = "okay"; +}; + +&mdio0 { + sgmii_phy0: ethernet-phy@0 { + reg = <0x0>; + }; + rgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + sgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + tbi1: tbi-phy@1f { + reg = <0x1f>; + device_type = "tbi-phy"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; diff --git a/board/freescale/ls1021aiot/Kconfig b/board/freescale/ls1021aiot/Kconfig new file mode 100644 index 0000000..4a12c16 --- /dev/null +++ b/board/freescale/ls1021aiot/Kconfig @@ -0,0 +1,15 @@ +if TARGET_LS1021AIOT + +config SYS_BOARD + default "ls1021aiot" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "ls102xa" + +config SYS_CONFIG_NAME + default "ls1021aiot" + +endif diff --git a/board/freescale/ls1021aiot/MAINTAINERS b/board/freescale/ls1021aiot/MAINTAINERS new file mode 100644 index 0000000..2dab798 --- /dev/null +++ b/board/freescale/ls1021aiot/MAINTAINERS @@ -0,0 +1,7 @@ +LS1021AIOT BOARD +M: Feng Li <feng.li_2(a)nxp.com> +S: Maintained +F: board/freescale/ls1021aiot/ +F: include/configs/ls1021aiot.h +F: configs/ls1021aiot_sdcard_defconfig +F: configs/ls1021aiot_qspi_defconfig diff --git a/board/freescale/ls1021aiot/Makefile b/board/freescale/ls1021aiot/Makefile new file mode 100644 index 0000000..05709e6 --- /dev/null +++ b/board/freescale/ls1021aiot/Makefile @@ -0,0 +1,9 @@ +# +# Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1021aiot.o +obj-$(CONFIG_FSL_DCU_FB) += dcu.o +obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/freescale/ls1021aiot/README b/board/freescale/ls1021aiot/README new file mode 100644 index 0000000..08b0268 --- /dev/null +++ b/board/freescale/ls1021aiot/README @@ -0,0 +1,58 @@ +Overview +-------- +The LS1021A-IOT is a Freescale reference board that hosts +the LS1021A SoC. + +LS1021AIOT board Overview +------------------------- + - DDR Controller + - Supports 1GB un-buffered DDR3L SDRAM discrete + devices(32-bit bus) with 4 bit ECC + - DDR power supplies 1.35V to all devices with + automatic tracking of VTT + - Soldered DDR chip + - Supprot one fixed speed + - Ethernet + - Two on-board SGMII 10/100/1G ethernet ports + - One Gbit Etherent RGMII interface to 4-ports switch + with 4x 10/100/1000 RJ145 ports + - CPLD + - 8-bit registers in CPLD for system configuration + - connected to IFC_AD[0:7] + - Power Supplies + - 12V@5A DC + - SDHC + - SDHC port connects directly to a full 8-bit SD/MMC slot + - Support for SDIO devices + - USB + - Two on-board USB 3.0 + - One on-board USB k22 + - PCIe + - Two MiniPCIe Solts + - SATA + - Support SATA Connector + - AUDIO + - AUDIO in and out + - I/O Expansion + - Arduino Shield Connector + - Port0 - CAN/GPIO/Flextimer + - Port1 - GPIO/CPLD Expansion + - Port2 - SPI/I2C/UART + +Memory map +----------- +The addresses in brackets are physical addresses. + +Start Address End Address Description Size +0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB +0x00_4000_0000 0x00_43FF_FFFF QSPI(Chip select 0) 64MB +0x00_4400_0000 0x00_47FF_FFFF QSPI(Chip select 1) 64MB +0x00_6000_0000 0x00_6000_FFFF CPLD 64K +0x00_8000_0000 0x00_BFFF_FFFF DDR 1GB + +Boot description +----------------- +LS1021A-IOT support two ways of boot: +Qspi boot and SD boot +The board doesn't support boot from another +source without changing any switch/jumper. diff --git a/board/freescale/ls1021aiot/dcu.c b/board/freescale/ls1021aiot/dcu.c new file mode 100644 index 0000000..e27647f --- /dev/null +++ b/board/freescale/ls1021aiot/dcu.c @@ -0,0 +1,47 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * FSL DCU Framebuffer driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fsl_dcu_fb.h> +#include "div64.h" +#include "../common/dcu_sii9022a.h" + +DECLARE_GLOBAL_DATA_PTR; + +unsigned int dcu_set_pixel_clock(unsigned int pixclock) +{ + unsigned long long div; + + div = (unsigned long long)(gd->bus_clk / 1000); + div *= (unsigned long long)pixclock; + do_div(div, 1000000000); + + return div; +} + +int platform_dcu_init(unsigned int xres, unsigned int yres, + const char *port, + struct fb_videomode *dcu_fb_videomode) +{ + const char *name; + unsigned int pixel_format; + + if (strncmp(port, "twr_lcd", 4) == 0) { + name = "TWR_LCD_RGB card"; + } else { + name = "HDMI"; + dcu_set_dvi_encoder(dcu_fb_videomode); + } + + printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres); + + pixel_format = 32; + fsl_dcu_init(xres, yres, pixel_format); + + return 0; +} diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c new file mode 100644 index 0000000..3340e4d --- /dev/null +++ b/board/freescale/ls1021aiot/ls1021aiot.c @@ -0,0 +1,259 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/immap_ls102xa.h> +#include <asm/arch/clock.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/ls102xa_stream_id.h> + +#include <asm/arch/ls102xa_devdis.h> +#include <asm/arch/ls102xa_soc.h> +#include <asm/arch/ls102xa_sata.h> +#include <fsl_csu.h> +#include <fsl_esdhc.h> +#include <fsl_immap.h> +#include <netdev.h> +#include <fsl_mdio.h> +#include <tsec.h> +#include <spl.h> + +#include <fsl_validate.h> +#include "../common/sleep.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define DDR_SIZE 0x40000000 + + +int checkboard(void) +{ + puts("Board: LS1021AIOT\n"); + +#ifndef CONFIG_QSPI_BOOT + struct ccsr_gur *dcfg = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR; + u32 cpldrev; + + cpldrev = in_be32(&dcfg->gpporcr1); + + printf("CPLD: V%d.%d\n", ((cpldrev >> 28) & 0xf), ((cpldrev >> 24) & + 0xf)); +#endif + return 0; +} + +void ddrmc_init(void) +{ + struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; + u32 temp_sdram_cfg, tmp; + + out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); + + out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); + out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); + + out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); + out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); + out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); + out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); + out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); + out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); + + out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); + out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); + + out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); + out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2); + + out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL); + + out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL); + + out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2); + out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3); + + out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); + + out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL); + out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); + + out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2); + + /* DDR erratum A-009942 */ + tmp = in_be32(&ddr->debug[28]); + out_be32(&ddr->debug[28], tmp | 0x0070006f); + + udelay(500); + + temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI); + + out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg); +} + +int dram_init(void) +{ +#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) + ddrmc_init(); +#endif + + gd->ram_size = DDR_SIZE; + return 0; +} + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg[1] = { + {CONFIG_SYS_FSL_ESDHC_ADDR}, +}; + +int board_mmc_init(bd_t *bis) +{ + esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + + return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); +} + +#endif + +#ifdef CONFIG_TSEC_ENET +int board_eth_init(bd_t *bis) +{ + struct fsl_pq_mdio_info mdio_info; + struct tsec_info_struct tsec_info[4]; + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + if (is_serdes_configured(SGMII_TSEC1)) { + puts("eTSEC1 is in sgmii mode.\n"); + tsec_info[num].flags |= TSEC_SGMII; + } + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + if (is_serdes_configured(SGMII_TSEC2)) { + puts("eTSEC2 is in sgmii mode.\n"); + tsec_info[num].flags |= TSEC_SGMII; + } + num++; +#endif + if (!num) { + printf("No TSECs initialized\n"); + return 0; + } + + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + fsl_pq_mdio_init(bis, &mdio_info); + + tsec_eth_init(bis, tsec_info, num); + + return pci_eth_init(bis); +} +#endif + +int board_early_init_f(void) +{ + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + +#ifdef CONFIG_TSEC_ENET + /* clear BD & FR bits for BE BD's and frame data */ + clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); + out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); + +#endif + + arch_soc_init(); + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong dummy) +{ + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + + get_clocks(); + + preloader_console_init(); + + dram_init(); + + /* Allow OCRAM access permission as R/W */ + +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + + board_init_r(NULL, 0); +} +#endif + +int board_init(void) +{ +#ifndef CONFIG_SYS_FSL_NO_SERDES + fsl_serdes_init(); +#endif + + ls102xa_smmu_stream_id_init(); + +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_SCSI_AHCI_PLAT + ls1021a_sata_init(); +#endif + + return 0; +} +#endif + +#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{ +#ifdef CONFIG_FSL_DEVICE_DISABLE + device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); + +#endif + +#ifdef CONFIG_FSL_CAAM + return sec_init(); +#endif +} +#endif + +int ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif + + return 0; +} + +void flash_write16(u16 val, void *addr) +{ + u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); + + __raw_writew(shftval, addr); +} + +u16 flash_read16(void *addr) +{ + u16 val = __raw_readw(addr); + + return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); +} diff --git a/board/freescale/ls1021aiot/ls102xa_pbi.cfg b/board/freescale/ls1021aiot/ls102xa_pbi.cfg new file mode 100644 index 0000000..b5ac5e2 --- /dev/null +++ b/board/freescale/ls1021aiot/ls102xa_pbi.cfg @@ -0,0 +1,14 @@ +#PBI commands + +09570200 ffffffff +09570158 00000300 +8940007c 21f47300 + +#Configure Scratch register +09ee0200 10000000 +#Configure alternate space +09570158 00001000 +#Flush PBL data +096100c0 000FFFFF + +09ea085c 00502880 diff --git a/board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg b/board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg new file mode 100644 index 0000000..a1984c7 --- /dev/null +++ b/board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg @@ -0,0 +1,27 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# serdes protocol + +#Default with 2 x SGMII (no SATA) +0608000a 00000000 00000000 00000000 +20000000 08407900 60025a00 21046000 +00000000 00000000 00000000 20038000 +20024800 881b1340 00000000 00000000 + +#SATA set-up +#0608000a 00000000 00000000 00000000 +#70000000 08007900 60025a00 21046000 +#00000000 00000000 00000000 20038000 +#20024800 881b1340 00000000 00000000 + +#HDMI set-up +#0608000a 00000000 00000000 00000000 +#20000000 08407900 60025a00 21046000 +#00000000 00000000 00000000 20038000 +#00000000 881b1340 00000000 00000000 + +#QE testing +#0608000a 00000000 00000000 00000000 +#20000000 08407900 60025a00 21046000 +#00000000 00000000 00000000 00038000 +#20094800 881b1340 00000000 00000000 diff --git a/board/freescale/ls1021aiot/psci.S b/board/freescale/ls1021aiot/psci.S new file mode 100644 index 0000000..564145c --- /dev/null +++ b/board/freescale/ls1021aiot/psci.S @@ -0,0 +1,28 @@ +/* + * Copyright 2016 NXP Semiconductor. + * Author: Feng Li <feng.li_2(a)nxp.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <linux/linkage.h> + +#include <asm/armv7.h> +#include <asm/psci.h> + + .pushsection ._secure.text, "ax" + + .arch_extension sec + + .align 5 + +.globl psci_system_off +psci_system_off: +1: wfi + b 1b + +.globl psci_text_end +psci_text_end: + nop + .popsection diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig new file mode 100644 index 0000000..6c9140b --- /dev/null +++ b/configs/ls1021aiot_qspi_defconfig @@ -0,0 +1,15 @@ +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" +CONFIG_ARM=y +CONFIG_DM_SPI=y +CONFIG_DM=y +CONFIG_OF_CONTROL=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y +CONFIG_TARGET_LS1021AIOT=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart" diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig new file mode 100644 index 0000000..4b082ab --- /dev/null +++ b/configs/ls1021aiot_sdcard_defconfig @@ -0,0 +1,17 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1021AIOT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart" +CONFIG_DM_SPI=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI" +CONFIG_CMD_DM=y +CONFIG_DM=y +CONFIG_OF_CONTROL=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_SYS_NS16550=y diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h new file mode 100644 index 0000000..a82a828 --- /dev/null +++ b/include/configs/ls1021aiot.h @@ -0,0 +1,367 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_LS102XA + +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR + +#define CONFIG_SYS_FSL_CLK + +#define CONFIG_BOARD_EARLY_INIT_F + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) + +#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE + +/* XHCI Support - enabled by default */ +#define CONFIG_HAS_FSL_XHCI_USB + +#ifdef CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI_FSL +#define CONFIG_USB_XHCI_DWC3 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#endif + +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB) +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_EXT2 +#endif + +/* + * Generic Timer Definitions + */ +#define GENERIC_TIMER_CLK 12500000 + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 + +/* + * DDR: 800 MHz ( 1600 MT/s data rate ) + */ + +#define DDR_SDRAM_CFG 0x470c0008 +#define DDR_CS0_BNDS 0x008000bf +#define DDR_CS0_CONFIG 0x80014302 +#define DDR_TIMING_CFG_0 0x50550004 +#define DDR_TIMING_CFG_1 0xbcb38c56 +#define DDR_TIMING_CFG_2 0x0040d120 +#define DDR_TIMING_CFG_3 0x010e1000 +#define DDR_TIMING_CFG_4 0x00000001 +#define DDR_TIMING_CFG_5 0x03401400 +#define DDR_SDRAM_CFG_2 0x00401010 +#define DDR_SDRAM_MODE 0x00061c60 +#define DDR_SDRAM_MODE_2 0x00180000 +#define DDR_SDRAM_INTERVAL 0x18600618 +#define DDR_DDR_WRLVL_CNTL 0x8655f605 +#define DDR_DDR_WRLVL_CNTL_2 0x05060607 +#define DDR_DDR_WRLVL_CNTL_3 0x05050505 +#define DDR_DDR_CDR1 0x80040000 +#define DDR_DDR_CDR2 0x00000001 +#define DDR_SDRAM_CLK_CNTL 0x02000000 +#define DDR_DDR_ZQ_CNTL 0x89080600 +#define DDR_CS0_CONFIG_2 0 +#define DDR_SDRAM_CFG_MEM_EN 0x80000000 +#define SDRAM_CFG2_D_INIT 0x00000010 +#define DDR_CDR2_VREF_TRAIN_EN 0x00000080 +#define SDRAM_CFG2_FRC_SR 0x80000000 +#define SDRAM_CFG_BI 0x00000001 + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI \ + board/freescale/ls1021aiot/ls102xa_pbi.cfg +#endif + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 + +#define CONFIG_SPL_TEXT_BASE 0x10000000 +#define CONFIG_SPL_MAX_SIZE 0x1a000 +#define CONFIG_SPL_STACK 0x1001d000 +#define CONFIG_SPL_PAD_TO 0x1c000 +#define CONFIG_SYS_TEXT_BASE 0x82000000 + +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_MONITOR_LEN 0x80000 +#define CONFIG_SYS_NO_FLASH +#endif + +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_SYS_TEXT_BASE 0x40010000 +#endif + +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_SYS_NO_FLASH +#endif + +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_FSL_CAAM /* Enable CAAM */ + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#define CONFIG_BAUDRATE 115200 + +/* + * I2C + */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/* + * MMC + */ +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_GENERIC_MMC + +/* SATA */ +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_CMD_SCSI +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#ifndef PCI_DEVICE_ID_FREESCALE_AHCI +#define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440 +#endif +#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \ + PCI_DEVICE_ID_FREESCALE_AHCI} + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* SPI */ +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_SPI_FLASH_SPANSION + +/* QSPI */ +#define QSPI0_AMBA_BASE 0x40000000 +#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_NUM 2 +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SPI_FLASH_SPANSION +#endif + +/* DM SPI */ +#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) +#define CONFIG_CMD_SF +#define CONFIG_DM_SPI_FLASH +#endif + +/* + * eTSEC + */ +#define CONFIG_TSEC_ENET + +#ifdef CONFIG_TSEC_ENET +#define CONFIG_MII +#define CONFIG_MII_DEFAULT_TSEC 1 +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" + +#define TSEC1_PHY_ADDR 1 +#define TSEC2_PHY_ADDR 3 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC2" + +#define CONFIG_PHY_GIGE +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#endif + +/* PCIe */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ + +/* Use common FSL Layerscape PCIe code */ +#define CONFIG_PCIE_LAYERSCAPE +#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" + +#define CONFIG_SYS_PCI_64BIT + +#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 +#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ +#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 +#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ + +#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 +#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ + +#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 +#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 +#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ + +#ifdef CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_CMD_PCI +#endif + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII + +#define CONFIG_CMDLINE_TAG +#define CONFIG_CMDLINE_EDITING + +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT) +#undef CONFIG_CMD_IMLS +#endif + +#define CONFIG_PEN_ADDR_BIG_ENDIAN +#define CONFIG_LAYERSCAPE_NS_ACCESS +#define CONFIG_SMP_PEN_ADDR 0x01ee0200 +#define CONFIG_TIMER_CLK_FREQ 12500000 + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 256 + +#define CONFIG_FSL_DEVICE_DISABLE + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ +"initrd_high=0xffffffff\0" \ +"fdt_high=0xffffffff\0" + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_MEMINFO + +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +#define CONFIG_LS102XA_STREAM_ID + +/* + * Stack sizes + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (30 * 1024) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +/* start of monitor */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#endif + +#define CONFIG_SYS_QE_FW_ADDR 0x67f40000 + +/* + * Environment + */ + +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_SD_BOOT) +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#endif + +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS +#define CONFIG_CMD_BOOTZ + +#define CONFIG_MISC_INIT_R + +/* Hash command with SHA acceleration supported in hardware */ + +#ifdef CONFIG_FSL_CAAM + +#define CONFIG_CMD_HASH + +#define CONFIG_SHA_HW_ACCEL + +#endif + +#include <asm/fsl_secure_boot.h> + +#endif -- 1.7.10

3 3

[U-Boot] [PATCH] configs: ls2080ardb: Enable DSPI flash support
by Yuan Yao 23 Nov '16

23 Nov '16

From: Yuan Yao <yao.yuan(a)nxp.com> There is the stmicro DSPI flash on LS12080ARDB. Enable DSPI flash related configure options. Signed-off-by: Yuan Yao <yao.yuan(a)nxp.com> --- include/configs/ls2080ardb.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index b93e919..90e31d4 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -271,6 +271,7 @@ unsigned long get_board_sys_clk(void); #ifdef CONFIG_FSL_DSPI #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_BAR +#define CONFIG_SPI_FLASH_STMICRO #endif /* -- 2.1.0.27.g96db324

2 1

[U-Boot] [PATCH] armv8:ls1012a: Update bootargs for fast-boot
by Pratiyush Srivastava 23 Nov '16

23 Nov '16

Add optimization parameters like "quiet" in bootargs to reduce the system boot time Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava(a)nxp.com> Signed-off-by: Harninder Rai <harninder.rai(a)nxp.com> --- include/configs/ls1012a_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 5fb6c47..a0ef2cd 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -120,7 +120,7 @@ "console=ttyAMA0,38400n8\0" #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ - "earlycon=uart8250,mmio,0x21c0500" + "earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" #define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\ "$kernel_start $kernel_size && "\ "bootm $kernel_load" -- 2.7.4

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[U-Boot] U-Boot vulnerable to CVE-2014-4607 (LZO)?
by Thomas Deutschmann 22 Nov '16

22 Nov '16

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA512 Hi, could you please help me to determine if U-Boot was or still is vulnerable to CVE-2014-4607? The project uses LZO decompression in lib/lzo/lzo1x_decompress.c I found the following applied patch set http://lists.denx.de/pipermail/u-boot/2014-December/197547.html but I am not sure. Thanks for any help! - -- Regards, Thomas -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0 iQJ8BAEBCgBmBQJYNLCXXxSAAAAAAC4AKGlzc3Vlci1mcHJAbm90YXRpb25zLm9w ZW5wZ3AuZmlmdGhob3JzZW1hbi5uZXQzM0M1ODQ4MkM0MDIyOTJEMkUzQzVDMDY5 NzA5RjkwQzNDOTZGRkM4AAoJEJcJ+Qw8lv/IWjEP/0sl5PHukqI+aKhDtVripPU5 67QUsepFnzPTXWmaz4a4ZVYngnSaxSbrn7l12BBr5KA3h9ffkvMpP7OWy2C7+MVO +eTOzDzMjGk5G3XLkSu3O7nnK2qqwNaoM4S+jZGrttpNXWmEVfHu3/K9vonM7WvQ B/HDf/FpAl400HWQtbCw2uz84/J8ApHjLalhPgUxS0EF5ndhmYZGaeoioaYMXXcK 2KNbS2eydBneDuoyQJAjveDqwhRVNhqKNaBZFFq1cKVBpAVVWJy1yyQFSMwYp8st /mLzFJ+3zBULrMbgoLGbgk5A9GGWVEMt1Z+OPhjExJDAe/zFfzr0BcdP9z5895nN E9TfBicVTIDNlXm4T9LVa992dJKyKD599ziU8sMsL4c7SU7G0bJp+1I1IP/LaMGZ TZ6Jcvoq/bIdfMoiY6RYjLJy1R48zwUC3BfIOz7UjhJX3WRObMXaNX9LCyih5TP3 FJVy1UB3w0zDQ53LZTvsJghQlbkEwHUaLA9ePjlnugeS5oLrtnrDR+jQYsvifRCB QMYkFloNUjNBuOIe/gTrNzfZCwk8M2zGB4efYPhVBnWUdH/fiETGC8PdzwL54uQk lvXuBWGprQXHqdjwMUblDUm3CucAFsB38y31ax3D062UySB2KO5xfb48pxe0inZX /WuG9EAxfcK7PzQYcOVw =fgWw -----END PGP SIGNATURE-----

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[U-Boot] Pull request: u-boot-spi/master
by Jagan Teki 22 Nov '16

22 Nov '16

Hi Tom, Please pull this PR. thanks! Jagan. The following changes since commit c2cbd164ea5b5f564fcf03447c7bf9ec4a9f5699: Merge branch 'master' of http://git.denx.de/u-boot-mmc (2016-11-17 11:46:56 -0500) are available in the git repository at: git://git.denx.de/u-boot-spi.git master for you to fetch changes up to 84cdc6e27aede7d87322842d262f0414824bb126: sf: Fix s25fs512s id table (2016-11-18 13:04:55 +0530) ---------------------------------------------------------------- Chris Packham (1): spi: kirkwood_spi: implement mvebu_spi_set_mode() Jagan Teki (21): sf: Adopt flash table INFO macro from Linux sf: Simplify lock ops detection code sf: sandbox: Use JEDEC_MFR|ID in id exctract sf: Cleanup spi_flash_info{} sf: nr_sectors -> n_sectors sf: Add SPI_FLASH_MAX_ID_LEN sf: Increase max id length by 1 byte sf: Add INFO6 flash_info macro sf: params: Add S25FS256S_64K spi flash support sf: Remove spansion_s25fss_disable_4KB_erase sf: Remove non-meaningful comments sf: Rename sf_params.c to spi_flash_ids.c sf: ids: Use small letter's with flash name sf: ids: Use small letter in ext_jedec sf: Rename few local functions spi: Remove dual flash options/flags sf: dataflash: Remove unneeded spi data sf: dataflash: Move flash id detection into jedec_probe sf: dataflash: Fix add_dataflash return logic sf: dataflash: Minor cleanups sf: Fix s25fs512s id table arch/arm/include/asm/arch-mvebu/spi.h | 4 + doc/device-tree-bindings/mtd/spi/spi-flash.txt | 2 +- drivers/mtd/spi/Makefile | 2 +- drivers/mtd/spi/sandbox.c | 11 +- drivers/mtd/spi/sf.c | 4 - drivers/mtd/spi/sf_dataflash.c | 178 +++++++++---------- drivers/mtd/spi/sf_internal.h | 71 ++++---- drivers/mtd/spi/sf_params.c | 149 ---------------- drivers/mtd/spi/spi_flash.c | 228 ++++++++----------------- drivers/mtd/spi/spi_flash_ids.c | 180 +++++++++++++++++++ drivers/spi/kirkwood_spi.c | 15 ++ include/linux/err.h | 5 + include/spi.h | 6 - 13 files changed, 400 insertions(+), 455 deletions(-) delete mode 100644 drivers/mtd/spi/sf_params.c create mode 100644 drivers/mtd/spi/spi_flash_ids.c

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Re: [U-Boot] [PATCH] arm: exynos: Use the generic lowlevel_init instead of the specific one
by Alison Wang 22 Nov '16

22 Nov '16

2016년 11월 16일 (수) 19:44, Alison Wang <alison.wang(a)nxp.com<mailto:alison.wang@nxp.com>>님이 작성: Hi, Thomas, I didn't see your patch. Maybe it isn't CC'ing me. Could you send me and york the link? Minkyu Kang, Could you add review-by and assign this patch http://patchwork.ozlabs.org/patch/667948/ to York? So he can merge this patch and Thomas's patch together. It's OK. York means yorksun? [Alison Wang] Yes. Reviewed-by: Minkyu Kang <mk7.kang(a)samsung.com<mailto:mk7.kang@samsung.com>> Thanks, Minkyu Kang. Thanks. Best Regards, Alison Wang > > On Tue, Nov 15, 2016 at 1:03 PM, Alison Wang <alison.wang(a)nxp.com<mailto:alison.wang@nxp.com>> > > wrote: > > > Hi, Thomas, Alex and York, > > > > > > Before there are some discussions about this patch, could we make a > > solution now? Or else, the patches about [PATCH v8 0/3] armv8: > Support > > loading 32-bit OS in AArch32 execution state can't be merged, as the > > compiling will fail without this patch. > > > > > > Thomas, is ARMV8_MULTIENTRY enabled on Exynos7420 now? If not, is > > there a good way to enable ARMV8_MULTIENTRY on Exynos7420 now? > > > > It is not yet enabled. I will post the ARMV8_MULTIENTRY enable patch > > for Exynos7420 later today. Alternatively, you could include the > patch > > listed in the previous email in your series. > > > [Alison Wang] Thanks for your reply. I think it's better to send the > patch by you (the maintainer). Please send it later today. :) > > > > > > > Thanks. > > > > > > Best Regards, > > > Alison Wang > > > > > >> -----Original Message----- > > >> From: Thomas Abraham [mailto:ta.omasab@gmail.com<mailto:ta.omasab@gmail.com>] > > >> Sent: Tuesday, September 20, 2016 4:45 PM > > >> To: Alexander Graf <agraf(a)suse.de<mailto:agraf@suse.de>> > > >> Cc: Alison Wang <b18965(a)freescale.com<mailto:b18965@freescale.com>>; thomas.ab(a)samsung.com<mailto:thomas.ab@samsung.com>; > > Minkyu > > >> Kang <mk7.kang(a)samsung.com<mailto:mk7.kang@samsung.com>>; york sun <york.sun(a)nxp.com<mailto:york.sun@nxp.com>>; U-Boot > > >> Mailing List <u-boot(a)lists.denx.de<mailto:u-boot@lists.denx.de>>; Jason Jin <jason.jin(a)nxp.com<mailto:jason.jin@nxp.com>> > > >> Subject: Re: [U-Boot] [PATCH] arm: exynos: Use the generic > > >> lowlevel_init instead of the specific one > > >> > > >> On Tue, Sep 20, 2016 at 12:03 PM, Alexander Graf <agraf(a)suse.de<mailto:agraf@suse.de>> > > wrote: > > >> > > > >> > > > >> > On 20.09.16 08:25, Thomas Abraham wrote: > > >> >> On Tue, Sep 20, 2016 at 11:35 AM, Alexander Graf <agraf(a)suse.de<mailto:agraf@suse.de>> > > >> wrote: > > >> >>> > > >> >>> > > >> >>> Am 20.09.2016 um 07:51 schrieb Thomas Abraham > > <ta.omasab(a)gmail.com<mailto:ta.omasab@gmail.com>>: > > >> >>> > > >> >>> Hi Alison, > > >> >>> > > >> >>> > > >> >>> On Mon, Sep 19, 2016 at 7:38 PM, Alexander Graf <agraf(a)suse.de<mailto:agraf@suse.de>> > > >> wrote: > > >> >>> > > >> >>> > > >> >>> > > >> >>> On 09.09.16 10:48, Alison Wang wrote: > > >> >>> > > >> >>> This patch is to use the the generic lowlevel_init instead of > > the > > >> >>> > > >> >>> specific one. > > >> >>> > > >> >>> > > >> >>> Signed-off-by: Alison Wang <alison.wang(a)nxp.com<mailto:alison.wang@nxp.com>> > > >> >>> > > >> >>> > > >> >>> If I had to guess, I'd think they only had their own version > > >> because the > > >> >>> > > >> >>> old one required a GIC. > > >> >>> > > >> >>> > > >> >>> I apologize for the delay. > > >> >>> > > >> >>> The reason for using a custom version was to avoid enabling > > >> >>> ARMV8_MULTIENTRY config option since the Exynos7 code was > ready > > for > > >> >>> it. > > >> >>> > > >> >>> > > >> >>> Either way, since Samsung doesn't reply, I'm fine potentially > > >> breaking > > >> >>> > > >> >>> their boards if that means that we can make progress for > > actively > > >> >>> > > >> >>> maintained ones: > > >> >>> > > >> >>> > > >> >>> Reviewed-by: Alexander Graf <agraf(a)suse.de<mailto:agraf@suse.de>> > > >> >>> > > >> >>> > > >> >>> This patch without the ARMV8_MULTIENTRY and > ARMV8_SWITCH_TO_EL1 > > >> config > > >> >>> options does not switch the boot CPU from EL3 to EL1. So it > > would > > >> be > > >> >>> preferable to not merge this patch until ARMV8_MULTIENTRY is > > >> enabled > > >> >>> for Exynos7. > > >> >>> > > >> >>> > > >> >>> Why do you want to switch it to EL1 in the first place? Linux > > >> >>> is > > >> very happy > > >> >>> to live in EL2 - which is what we call it in by default. > > >> >> > > >> >> Okay, there is no particular requirement to be in EL1 for > Exynos7. > > >> EL2 > > >> >> would also be fine. But Exynos7 support in u-boot is not yet > > ready > > >> for > > >> >> enabling ARMV8_MULTIENTRY config option. Is there anything be > > >> blocked > > >> >> due to Exynos7 using a custom lowlevel_init function? > > >> > > > >> > Yes, we're changing the semantics of armv8_switch_to_el2 and > > >> > armv8_switch_to_el1: > > >> > > > >> > > > >> > http://lists.denx.de/pipermail/u-boot/2016-September/266217.html > > >> > > > >> > which is a prerequisite for AArch32 kernel boot on AArch64 > systems. > > >> > > >> Okay. > > >> > > >> > > > >> > How quickly do you think you could make Exynos7 work with > > MULTIENTRY? > > >> > > > >> > > >> Exynos7420 uses CPU 0 of Cluster 1 as boot CPU (master CPU). The > > macro > > >> 'branch_if_master' requires all affinity values to be zero for a > > >> CPU to be identified as a master CPU. And so the boot CPU is > > >> incorrectly detected as a slave CPU. I have tested with the > > >> following temporary workaround to enable ARMV8_MULTIENTRY on > > >> Exynos7420. If it looks > > fine, > > >> this can be merged along with Alison's patch. > > >> > > >> Thomas. > > >> > > >> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach- > > >> exynos/Kconfig index ce2a16f..45c5eeb 100644 > > >> --- a/arch/arm/mach-exynos/Kconfig > > >> +++ b/arch/arm/mach-exynos/Kconfig > > >> @@ -126,6 +126,8 @@ choice > > >> config TARGET_ESPRESSO7420 > > >> bool "ESPRESSO7420 board" > > >> select ARM64 > > >> + select ARMV8_MULTIENTRY > > >> + select ARMV8_SWITCH_TO_EL1 > > >> select SUPPORT_SPL > > >> select OF_CONTROL > > >> select SPL_DISABLE_OF_CONTROL diff --git > > >> a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c index > > >> f9c7468..6c3ebb0 100644 > > >> --- a/arch/arm/mach-exynos/soc.c > > >> +++ b/arch/arm/mach-exynos/soc.c > > >> @@ -9,6 +9,16 @@ > > >> #include <asm/io.h> > > >> #include <asm/system.h> > > >> > > >> +#ifdef CONFIG_TARGET_ESPRESSO7420 > > >> +/* > > >> + * Exynos7420 uses CPU0 of Cluster-1 as boot CPU. Due to this > > >> branch_if_master > > >> + * fails to identify as the master CPU. As temporary workaround, > > setup > > >> the > > >> + * slave CPU boot address as "_main". > > >> + */ > > >> +extern void _main(void); > > >> +void *secondary_boot_addr = (void *)_main; #endif /* > > >> +CONFIG_TARGET_ESPRESSO7420 */ > > >> + > > >> void reset_cpu(ulong addr) > > >> { > > >> #ifdef CONFIG_CPU_V7 > > >> diff --git a/include/configs/exynos7420-common.h > > >> b/include/configs/exynos7420-common.h > > >> index 9e03962..6f58aef 100644 > > >> --- a/include/configs/exynos7420-common.h > > >> +++ b/include/configs/exynos7420-common.h > > >> @@ -48,6 +48,7 @@ > > >> #define CONFIG_IRAM_BASE 0x02100000 > > >> #define CONFIG_IRAM_SIZE 0x58000 > > >> #define CONFIG_IRAM_END (CONFIG_IRAM_BASE > + > > >> CONFIG_IRAM_SIZE) > > >> +#define CPU_RELEASE_ADDR secondary_boot_addr > > >> > > >> /* Number of CPUs available */ > > >> #define CONFIG_CORE_COUNT 0x8 > > >> > > >> > > > >> > Alex _______________________________________________ U-Boot mailing list U-Boot(a)lists.denx.de<mailto:U-Boot@lists.denx.de> http://lists.denx.de/mailman/listinfo/u-boot

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[U-Boot] [PATCH 1/3] davinci: omapl138_lcdk: use correct AIS config
by Fabien Parent 22 Nov '16

22 Nov '16

The AIS image built for the OMAPL138-LCDK board is not booting because the AIS configuration is not correct. This commit adds a AIS configuration file that allow the SPL to boot correctly. Signed-off-by: Fabien Parent <fparent(a)baylibre.com> --- board/davinci/da8xxevm/omapl138_lcdk_ais.cfg | 4 ++++ include/configs/omapl138_lcdk.h | 3 +++ scripts/config_whitelist.txt | 1 + 3 files changed, 8 insertions(+) create mode 100644 board/davinci/da8xxevm/omapl138_lcdk_ais.cfg diff --git a/board/davinci/da8xxevm/omapl138_lcdk_ais.cfg b/board/davinci/da8xxevm/omapl138_lcdk_ais.cfg new file mode 100644 index 0000000..afce286 --- /dev/null +++ b/board/davinci/da8xxevm/omapl138_lcdk_ais.cfg @@ -0,0 +1,4 @@ +PLL0 180001 40b +DDR2 18010001 2 c5 134832 264a3209 3c14c722 492 0 +EMIFA_ASYNC 0 3ffffffd 0 0 2 +PSC 10d0003 diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 854fc47..91ddbb1 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -272,6 +272,9 @@ #define CONFIG_SPL_PAD_TO 32768 #endif +/* AIS Image */ +#define CONFIG_AIS_CONFIG_FILE "board/davinci/da8xxevm/omapl138_lcdk_ais.cfg" + /* additions for new relocation code, must added to all boards */ #define CONFIG_SYS_SDRAM_BASE 0xc0000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index d476367..c694f90 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -73,6 +73,7 @@ CONFIG_ADP_AG101P CONFIG_AEABI CONFIG_AEMIF_CNTRL_BASE CONFIG_AES +CONFIG_AIS_CONFIG_FILE CONFIG_ALTERA_SDRAM CONFIG_ALTERA_SPI_IDLE_VAL CONFIG_ALTIVEC -- 2.10.2

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[U-Boot] [u-boot-2013.01.y] [NEED HELP] spl_image.flags has a bad default value
by Shmuel Weiss 22 Nov '16

22 Nov '16

HI All, We have an issue with this variable which is not initialized in our am335x board, the default value there is 0XFF which is making the condition successful and cause SPL to fail after power cycle. common/spl/spl.c:81: if (spl_image.flags & SPL_COPY_PAYLOAD_ONLY) { Can anybody say what we are missing about this flag initialization ? Thanks.

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