October 2016 - U-Boot

[U-Boot] [PULL v3] efi patch queue 2016-10-19
by Alexander Graf 20 Oct '16

20 Oct '16

Hi Tom, This is my current patch queue for efi. Please pull. Alex The following changes since commit d5a815327d2c257fbba108ff46974b1c1d12fd2a: Prepare v2016.11-rc2 (2016-10-17 20:09:33 -0400) are available in the git repository at: git://github.com/agraf/u-boot.git tags/signed-efi-next for you to fetch changes up to 3fb97e267a5e136d8386a7cb1d5b4fe63af518eb: efi_loader: Revert device_handle to disk after net boot (2016-10-19 09:01:54 +0200) ---------------------------------------------------------------- Patch queue for efi - 2016-10-19 Highlights this time around: - Add run time service (power control) support for PSCI (fixed in v3) - Add efi gop pointer exposure - SMBIOS support for EFI (on ARM) - efi pool memory unmap support (needed for 4.8) - initial x86 efi payload support (fixed up in v2) - various bug fixes ---------------------------------------------------------------- Alexander Graf (19): efi_loader: Allow boards to implement get_time and reset_system arm: Disable HVC PSCI calls by default arm: Add PSCI shutdown function arm: Provide common PSCI based reset handler efi_loader: Add generic PSCI RTS efi_loader: Allow bouncing for network efi_loader: gop: Expose fb when 32bpp x86: Move table csum into separate file x86: Move smbios generation into arch independent directory efi_loader: Expose efi_install_configuration_table smbios: Allow compilation on 64bit systems cpu: Add DMTF id and family fields cpu: Add get_vendor callback smbios: Generate type 4 on non-x86 systems smbios: Expose in efi_loader as table efi_loader: Fix efi_install_configuration_table smbios: Provide serial number efi_loader: Rename EFI_RUNTIME_{TEXT, DATA} to __efi_runtime{, _data} efi_loader: Revert device_handle to disk after net boot Robin Randhawa (1): efi_loader: Fix crash on 32-bit systems Simon Glass (3): efi: Use asmlinkage for EFIAPI efi: Fix missing EFIAPI specifiers x86: efi: Add EFI loader support for x86 Stefan Brüns (7): efi_loader: Update description of internal efi_mem_carve_out efi_loader: Fix memory map size check to avoid out-of-bounds access efi_loader: Move efi_allocate_pool implementation to efi_memory.c efi_loader: Track size of pool allocations to allow freeing efi_loader: Readd freed pages to memory pool efi_loader: Keep memory mapping sorted when splitting an entry efi_loader: Do not leak memory when unlinking a mapping arch/arm/cpu/armv8/Kconfig | 18 +++++ arch/arm/cpu/armv8/fwcall.c | 59 +++++++++++++- arch/arm/include/asm/system.h | 12 +-- arch/arm/mach-meson/board.c | 2 +- arch/avr32/include/asm/linkage.h | 0 arch/m68k/include/asm/linkage.h | 0 arch/microblaze/include/asm/linkage.h | 0 arch/mips/include/asm/linkage.h | 0 arch/nios2/include/asm/linkage.h | 0 arch/openrisc/include/asm/linkage.h | 0 arch/sandbox/include/asm/linkage.h | 0 arch/sh/include/asm/linkage.h | 0 arch/sparc/include/asm/linkage.h | 0 arch/x86/Kconfig | 27 ------- arch/x86/cpu/baytrail/cpu.c | 1 + arch/x86/cpu/broadwell/cpu.c | 1 + arch/x86/cpu/cpu_x86.c | 18 +++++ arch/x86/cpu/ivybridge/model_206ax.c | 1 + arch/x86/cpu/u-boot.lds | 36 ++++++++- arch/x86/include/asm/cpu_x86.h | 13 +++ arch/x86/include/asm/tables.h | 2 + arch/x86/lib/Makefile | 2 +- arch/x86/lib/sections.c | 12 +++ arch/x86/lib/tables.c | 21 ++--- board/xilinx/zynqmp/zynqmp.c | 5 -- cmd/bootefi.c | 16 +++- drivers/cpu/cpu-uclass.c | 10 +++ include/cpu.h | 22 ++++++ include/efi.h | 3 +- include/efi_api.h | 4 + include/efi_loader.h | 39 +++++++-- {arch/x86/include/asm => include}/smbios.h | 8 +- include/tables_csum.h | 12 +++ lib/Kconfig | 33 ++++++++ lib/Makefile | 2 + lib/efi_loader/Makefile | 1 + lib/efi_loader/efi_boottime.c | 57 +++++++++----- lib/efi_loader/efi_disk.c | 13 +-- lib/efi_loader/efi_gop.c | 16 ++++ lib/efi_loader/efi_memory.c | 88 ++++++++++++++++++--- lib/efi_loader/efi_net.c | 11 ++- lib/efi_loader/efi_runtime.c | 122 ++++++++++++++++++++++++----- lib/efi_loader/efi_smbios.c | 32 ++++++++ {arch/x86/lib => lib}/smbios.c | 82 +++++++++++++------ lib/tables_csum.c | 20 +++++ 45 files changed, 667 insertions(+), 154 deletions(-) create mode 100644 arch/avr32/include/asm/linkage.h create mode 100644 arch/m68k/include/asm/linkage.h create mode 100644 arch/microblaze/include/asm/linkage.h create mode 100644 arch/mips/include/asm/linkage.h create mode 100644 arch/nios2/include/asm/linkage.h create mode 100644 arch/openrisc/include/asm/linkage.h create mode 100644 arch/sandbox/include/asm/linkage.h create mode 100644 arch/sh/include/asm/linkage.h create mode 100644 arch/sparc/include/asm/linkage.h create mode 100644 arch/x86/lib/sections.c rename {arch/x86/include/asm => include}/smbios.h (95%) create mode 100644 include/tables_csum.h create mode 100644 lib/efi_loader/efi_smbios.c rename {arch/x86/lib => lib}/smbios.c (78%) create mode 100644 lib/tables_csum.c

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[U-Boot] u-boot, powerpc and multilib and linker scripts
by Michael Walle 20 Oct '16

20 Oct '16

[CC Wolfgang because he's the ppc maintainer] Hi, I've build a powerpc64 cross compile toolchain with multilib support (using http://crosstool-ng.org/). Eg. the default one is 64bit and you can choose a 32 bit compile with "-m32". I can compile the bootloader but linking fails with "libgcc not found". The (correct) 32-bit libgcc.a is skipped because it is incompatible. I've debugged the issue and found, that the linker scripts are responsible for this. OUTPUT_ARCH is set to powerpc. But "powerpc" can either be the 32 bit BFD or the 64 bit BFD (see [1]). This depends on which cross compiler you've build. Eg. a "multilib powerpc" or a "multilib powerpc64". The default linker scripts all use the printable BFD name for the OUTPUT_ARCH, which has a fixed mapping. "powerpc:common" for 32 bit and "powerpc:common64" for 64 bit. Now if I set the OUTPUT_ARCH to "powerpc:common" everything works fine. But I want to make sure this change is correct and there are no objections before commiting a patch for all powerpc linker scripts. So please comment :) -michael [1] https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob;f=bfd/cpu-p…

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[U-Boot] [PATCH 1/3] armv8/ls1043a: fixup GIC offset according to SVR and GIC400_ADDR_ALIGN_64K[GIC_ADDR]
by Wenbin song 20 Oct '16

20 Oct '16

The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment and 64K alignment. The bit GIC400_ADDR_ALIGN_64K[GIC_ADDR] is used to choose which offset will be used. If GIC_ADDR bit is set, 4K alignment is used, or else 64K alignment is used. 64K alignment is the default setting. Signed-off-by: Wenbin Song <wenbin.song(a)nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 47 +++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 12 +++++- 2 files changed, 57 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 5d0b7a4..569d2c2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -14,6 +14,40 @@ #include <asm/arch/mp.h> #endif +#ifdef CONFIG_LS1043A + +/* fixup GIC offset */ +ENTRY(fix_gic_offset) + ldr x0, =GICD_BASE + ldr x1, =GICC_BASE + ldr x3, =DCFG_CCSR_SVR + ldr w3, [x3] + rev w3, w3 + ands w3, w3, #0xff + cmp w3, #REV1_0 + b.eq 1f + ldr x3, =SCFG_GIC400_ALIGN + ldr w3, [x3] + rev w3, w3 + tbnz w3, #GIC_ADDR_BIT, 1f + ret +1: + ldr x0, =GICD_BASE_4K + ldr x1, =GICC_BASE_4K + ret +ENDPROC(fix_gic_offset) + +ENTRY(smp_kick_all_cpus) + /* Kick secondary cpus up by SGI 0 interrupt */ + mov x29, lr /* Save LR */ + bl fix_gic_offset + bl gic_kick_secondary_cpus + mov lr, x29 /* Restore LR */ + ret +ENDPROC(smp_kick_all_cpus) + +#endif + ENTRY(lowlevel_init) mov x29, lr /* Save LR */ @@ -105,15 +139,23 @@ ENTRY(lowlevel_init) /* Initialize GIC Secure Bank Status */ #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) branch_if_slave x0, 1f +#ifdef CONFIG_LS1043A + bl fix_gic_offset +#else ldr x0, =GICD_BASE +#endif bl gic_init_secure 1: #ifdef CONFIG_GICV3 ldr x0, =GICR_BASE bl gic_init_secure_percpu #elif defined(CONFIG_GICV2) +#ifdef CONFIG_LS1043A + bl fix_gic_offset +#else ldr x0, =GICD_BASE ldr x1, =GICC_BASE +#endif bl gic_init_secure_percpu #endif #endif @@ -335,7 +377,12 @@ ENTRY(secondary_boot_func) #if defined(CONFIG_GICV3) gic_wait_for_interrupt_m x0 #elif defined(CONFIG_GICV2) +#ifdef CONFIG_LS1043A + bl fix_gic_offset + mov x0, x1 +#else ldr x0, =GICC_BASE +#endif gic_wait_for_interrupt_m x0, w1 #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 4201e0f..eb6e58d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -172,8 +172,16 @@ #define SMMU_BASE 0x09000000 /* Generic Interrupt Controller Definitions */ -#define GICD_BASE 0x01401000 -#define GICC_BASE 0x01402000 +#define GICD_BASE 0x01410000 +#define GICC_BASE 0x01420000 +#define GICD_BASE_4K 0x01401000 +#define GICC_BASE_4K 0x01402000 + +#define DCFG_CCSR_SVR 0x1ee00a4 +#define REV1_0 0x10 +#define REV1_1 0x11 +#define GIC_ADDR_BIT 31 +#define SCFG_GIC400_ALIGN 0x1570188 #define CONFIG_SYS_FSL_ERRATUM_A008850 #define CONFIG_SYS_FSL_ERRATUM_A009663 -- 2.1.0.27.g96db324

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[U-Boot] [RFC PATCH 0/1] 4-byte SPI flash addressing
by Chris Packham 20 Oct '16

20 Oct '16

I'm working on a board that uses a MX25L25735E spi-nor flash chip from Macronix. This is a 32MB chip that uses 4-bytes for addressing. Annoyingly this chip identifies the same as a MX25L25635F the only difference appears to be the size reported (I don't actually have a MX25L25635F so that statement is an educated guess based on the datasheets). What follows is a patch that gets the flash going on the board I'm working on. But I am wondering if instead of a config option I should follow more closely what Linux does and add and addr_width to struct spi_flash which gets set based on the size detected. Chris Packham (1): sf: support chips using 4-byte addressing drivers/mtd/spi/Kconfig | 7 +++++++ drivers/mtd/spi/sf_internal.h | 5 +++++ drivers/mtd/spi/spi_flash.c | 7 +++++++ 3 files changed, 19 insertions(+) -- 2.10.0.479.g7c56b16

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[U-Boot] [PATCH] libfdt: replace ARCH_FIXUP_FDT with ARCH_FIXUP_FDT_MEMORY
by Masahiro Yamada 20 Oct '16

20 Oct '16

Commit e2f88dfd2d96 ("libfdt: Introduce new ARCH_FIXUP_FDT option") allows us to skip memory setup of DTB, but a problem for ARM is that spin_table_update_dt() and psci_update_dt() are skipped as well if CONFIG_ARCH_FIXUP_FDT is disabled. This commit allows us to skip only fdt_fixup_memory_banks() instead of the whole of arch_fixup_fdt(). It will be useful when we want to use a memory node from a kernel DTB as is, but need some fixups for Spin-Table/PSCI. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- Kconfig | 5 ++--- arch/arm/lib/bootm-fdt.c | 2 -- arch/arm/lib/bootm.c | 2 -- arch/mips/lib/bootm.c | 2 -- common/fdt_support.c | 2 ++ common/image-fdt.c | 7 +++++-- include/fdt_support.h | 8 ++++++++ 7 files changed, 17 insertions(+), 11 deletions(-) diff --git a/Kconfig b/Kconfig index 1263d0b..b7cb142 100644 --- a/Kconfig +++ b/Kconfig @@ -324,9 +324,8 @@ config SYS_CLK_FREQ help TODO: Move CONFIG_SYS_CLK_FREQ for all the architecture -config ARCH_FIXUP_FDT - bool "Enable arch_fixup_fdt() call" - depends on ARM || MIPS +config ARCH_FIXUP_FDT_MEMORY + bool "Enable arch_fixup_memory_banks() call" default y help Enable FDT memory map syncup before OS boot. This feature can be diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c index a517550..4481f9e 100644 --- a/arch/arm/lib/bootm-fdt.c +++ b/arch/arm/lib/bootm-fdt.c @@ -25,7 +25,6 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_ARCH_FIXUP_FDT int arch_fixup_fdt(void *blob) { bd_t *bd = gd->bd; @@ -61,4 +60,3 @@ int arch_fixup_fdt(void *blob) return 0; } -#endif diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 53c3141..0e890ce 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -372,10 +372,8 @@ void boot_prep_vxworks(bootm_headers_t *images) if (images->ft_addr) { off = fdt_path_offset(images->ft_addr, "/memory"); if (off < 0) { -#ifdef CONFIG_ARCH_FIXUP_FDT if (arch_fixup_fdt(images->ft_addr)) puts("## WARNING: fixup memory failed!\n"); -#endif } } #endif diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c index 0c6a4ab..aa0475a 100644 --- a/arch/mips/lib/bootm.c +++ b/arch/mips/lib/bootm.c @@ -253,7 +253,6 @@ static int boot_reloc_fdt(bootm_headers_t *images) #endif } -#ifdef CONFIG_ARCH_FIXUP_FDT int arch_fixup_fdt(void *blob) { #if CONFIG_IS_ENABLED(MIPS_BOOT_FDT) && CONFIG_IS_ENABLED(OF_LIBFDT) @@ -265,7 +264,6 @@ int arch_fixup_fdt(void *blob) return 0; #endif } -#endif static int boot_setup_fdt(bootm_headers_t *images) { diff --git a/common/fdt_support.c b/common/fdt_support.c index 2020586..c87031f 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -381,6 +381,7 @@ void do_fixup_by_compat_u32(void *fdt, const char *compat, do_fixup_by_compat(fdt, compat, prop, &tmp, 4, create); } +#ifdef CONFIG_ARCH_FIXUP_FDT_MEMORY /* * fdt_pack_reg - pack address and size array into the "reg"-suitable stream */ @@ -459,6 +460,7 @@ int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks) } return 0; } +#endif int fdt_fixup_memory(void *blob, u64 start, u64 size) { diff --git a/common/image-fdt.c b/common/image-fdt.c index 3d23608..91970d4 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -458,6 +458,11 @@ __weak int ft_verify_fdt(void *fdt) return 1; } +__weak int arch_fixup_fdt(void *blob) +{ + return 0; +} + int image_setup_libfdt(bootm_headers_t *images, void *blob, int of_size, struct lmb *lmb) { @@ -474,12 +479,10 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob, printf("ERROR: /chosen node create failed\n"); goto err; } -#ifdef CONFIG_ARCH_FIXUP_FDT if (arch_fixup_fdt(blob) < 0) { printf("ERROR: arch-specific fdt fixup failed\n"); goto err; } -#endif if (IMAGE_OF_BOARD_SETUP) { fdt_ret = ft_board_setup(blob, gd->bd); if (fdt_ret) { diff --git a/include/fdt_support.h b/include/fdt_support.h index 8f40231..7110061 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -93,7 +93,15 @@ int fdt_fixup_memory(void *blob, u64 start, u64 size); * property will be left untouched. * @return 0 if ok, or -1 or -FDT_ERR_... on error */ +#ifdef CONFIG_ARCH_FIXUP_FDT_MEMORY int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks); +#else +static inline int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], + int banks) +{ + return 0; +} +#endif void fdt_fixup_ethernet(void *fdt); int fdt_find_and_setprop(void *fdt, const char *node, const char *prop, -- 1.9.1

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[U-Boot] Help with spl: zImage support in Falcon mode
by Diego Dorta 19 Oct '16

19 Oct '16

Hi all, According to commit log: commit 431889d6ad9a39846636716478d504aa7ff976fc Author: Ladislav Michl <ladis(a)linux-mips.org> Date: Tue Jul 12 20:28:14 2016 +0200 spl: zImage support in Falcon mode Other payload than uImage is currently considered to be raw U-Boot image. Check also for zImage in Falcon mode. Signed-off-by: Ladislav Michl <ladis(a)linux-mips.org> Reviewed-by: Heiko Schocher <hs(a)denx.de> Already include at U-Boot 2016.09.01. I was trying to apply Falcon mode on i.MX6 Sabre SD using zImage instead of uImage. After the steps below I got an error trying to "spl export": # dhcp ${fdt_addr} imx6q-sabresd.dtb # dhcp ${loadaddr} zImage # mmc write ${loadaddr} 0x1000 0x4000 # setenv bootargs 'console=ttymxc0,115200 root=/dev/mmcblk1p1 rootfstype=ext4 rootwait quiet rw' # spl export fdt ${loadaddr} - ${fdt_addr} i�{��]߬�o��;��]��o��k5�ك�2s�C�Ǎ��x��ɾ��6�}��]�0��֮��m�\�S��'��;}��ۗ�Ԭ2�[��w<��O����7ە}�v�c��-�ϥ��9��w`o��ߎ�ݭ�zoERROR: can't get kernel image! XIP Invalid Image ... OK ERROR: booting os 'Invalid OS' (0) is not supported ERROR: booting os 'Invalid OS' (0) is not supported ERROR: booting os 'Invalid OS' (0) is not supported ERROR prep subcommand failed! Subcommand failed I can't understand this error. Does anybody know how to fix it? Regards, Diego

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Re: [U-Boot] [PATCH v2 2/2] armv8: s32v234: Introduce basic support for s32v234evb
by El-Sharkawy, Mohamed A. 19 Oct '16

19 Oct '16

Hi Eddy: I am trying to use the S32V234 EVB for Vision SDK and a camera. Do you have any basic bootloader that could help me with that? Thanks Mohamed El-Sharkawy Professor Purdue School of Engineering and Technology 723 W Michigan Street, SL 160H Indianapolis, IN 46202 melshark(a)purdue.edu<mailto:melshark@purdue.edu> melshark(a)iupui.edu<mailto:melshark@iupui.edu> 317-274-4559 https://sites.google.com/site/elsharkawyiupui/

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[U-Boot] [PATCH v2 0/3] am335x-icev2: Ethernet support
by Roger Quadros 19 Oct '16

19 Oct '16

Hi, am335x-icev2 has 2 Ethernet ports that can be used either as CPSW ethernet (RMII mode) or PRUSS ethernet (MII mode) using jumpers placed next to the port on the board. As a different PHY clock is required for RMII mode vs MII mode, we detect the jumper setting and set the PHY clock frequency accordingly. Tested with CPSW in RMII mode. cheers,m -roger Changelog: v2: - removed unnecessary patch 1. Mugunthan V N (1): driver: net: cpsw: add support for RGMII id mode support and RMII clock source selection Roger Quadros (2): board: am335x-icev2: add ethernet phy mode detection logic board: am335x: Always set eth/eth1addr environment variable board/ti/am335x/board.c | 154 +++++++++++++++++++++++++++++++++++++---------- drivers/net/cpsw.c | 157 +++++++++++++++++++++++++++++++++++++++++++----- include/cpsw.h | 1 + 3 files changed, 265 insertions(+), 47 deletions(-) -- 2.7.4

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[U-Boot] [PATCH 1/2] armv8: add hooks for all cache-wide operations
by Stephen Warren 19 Oct '16

19 Oct '16

From: Stephen Warren <swarren(a)nvidia.com> SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. These dummy implementations are moved into C code, since there's no need to implement them in assembly. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- arch/arm/cpu/armv8/cache.S | 6 ------ arch/arm/cpu/armv8/cache_v8.c | 23 ++++++++++++++++++++--- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 4 ++-- arch/arm/include/asm/system.h | 5 ++++- arch/arm/mach-tegra/tegra186/cache.c | 2 +- 5 files changed, 27 insertions(+), 13 deletions(-) diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S index 46f25e63f01d..23fa914dc556 100644 --- a/arch/arm/cpu/armv8/cache.S +++ b/arch/arm/cpu/armv8/cache.S @@ -150,12 +150,6 @@ ENTRY(__asm_invalidate_icache_all) ret ENDPROC(__asm_invalidate_icache_all) -ENTRY(__asm_flush_l3_cache) - mov x0, #0 /* return status as success */ - ret -ENDPROC(__asm_flush_l3_cache) - .weak __asm_flush_l3_cache - /* * void __asm_switch_ttbr(ulong new_ttbr) * diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index cd3f6c10ae12..d2965e9878a0 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -415,25 +415,36 @@ __weak void mmu_setup(void) set_sctlr(get_sctlr() | CR_M); } +__weak int invalidate_dcache_all_l3(void) +{ + return 0; +} + /* * Performs a invalidation of the entire data cache at all levels */ void invalidate_dcache_all(void) { __asm_invalidate_dcache_all(); + invalidate_dcache_all_l3(); +} + +__weak int flush_dcache_all_l3(void) +{ + return 0; } /* * Performs a clean & invalidation of the entire data cache at all levels. * This function needs to be inline to avoid using stack. - * __asm_flush_l3_cache return status of timeout + * flush_dcache_all_l3 return status of timeout */ inline void flush_dcache_all(void) { int ret; __asm_flush_dcache_all(); - ret = __asm_flush_l3_cache(); + ret = flush_dcache_all_l3(); if (ret) debug("flushing dcache returns 0x%x\n", ret); else @@ -623,7 +634,7 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, void icache_enable(void) { - __asm_invalidate_icache_all(); + invalidate_icache_all(); set_sctlr(get_sctlr() | CR_I); } @@ -637,9 +648,15 @@ int icache_status(void) return (get_sctlr() & CR_I) != 0; } +__weak int invalidate_icache_all_l3(void) +{ + return 0; +} + void invalidate_icache_all(void) { __asm_invalidate_icache_all(); + invalidate_icache_all_l3(); } #else /* CONFIG_SYS_ICACHE_OFF */ diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 5d0b7a45c354..4e4ef8b7a6df 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -245,7 +245,7 @@ hnf_set_pstate: ret -ENTRY(__asm_flush_l3_cache) +ENTRY(flush_dcache_all_l3) /* * Return status in x0 * success 0 @@ -275,7 +275,7 @@ ENTRY(__asm_flush_l3_cache) mov x0, x8 mov lr, x29 ret -ENDPROC(__asm_flush_l3_cache) +ENDPROC(flush_dcache_all_l3) #endif #ifdef CONFIG_MP diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index c18e1e3a10ee..095f3742ce60 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -93,9 +93,12 @@ void __asm_invalidate_dcache_all(void); void __asm_flush_dcache_range(u64 start, u64 end); void __asm_invalidate_tlb_all(void); void __asm_invalidate_icache_all(void); -int __asm_flush_l3_cache(void); void __asm_switch_ttbr(u64 new_ttbr); +int invalidate_dcache_all_l3(void); +int flush_dcache_all_l3(void); +int invalidate_icache_all_l3(void); + void armv8_switch_to_el2(void); void armv8_switch_to_el1(void); void gic_init(void); diff --git a/arch/arm/mach-tegra/tegra186/cache.c b/arch/arm/mach-tegra/tegra186/cache.c index adaed8968eb9..fb0b1142e49b 100644 --- a/arch/arm/mach-tegra/tegra186/cache.c +++ b/arch/arm/mach-tegra/tegra186/cache.c @@ -10,7 +10,7 @@ #define SMC_SIP_INVOKE_MCE 0x82FFFF00 #define MCE_SMC_ROC_FLUSH_CACHE 11 -int __asm_flush_l3_cache(void) +int flush_dcache_all_l3(void) { struct pt_regs regs = {0}; -- 2.10.1

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[U-Boot] Some issues with the python tests
by Stefan Bruens 19 Oct '16

19 Oct '16

Hi, I have started diving into the u-boot python tests. Now I have come accross two problems: 1. I would like to access the config, specifically the paths to e.g. build_dir, result_dir, ... 2. I would like to run and log system commands Now while I can do this via the u_boot_console fixture, I would like to issue some of my fixture setup on the session/module level. Unfortunately, the u_boot_console fixture has "function" scope, and thus my fixtures are limited to function scope as well. Although for the u_boot_console (i.e. the sandbox instance or the SoC terminal) function scope is likely correct, the runner/logger and the config should be accessible independent of u_boot_console. Any ideas how to solve this issue? Kind regards, Stefan -- Stefan Brüns / Bergstraße 21 / 52062 Aachen home: +49 241 53809034 mobile: +49 151 50412019 work: +49 2405 49936-424

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