October 2016 - U-Boot

[U-Boot] [PATCH] tools: mkimage: Check if file is regular file
by Michal Simek 21 Oct '16

21 Oct '16

Current Makefile.spl passes -R parameter which is not empty and pointing to ./ folder. "./tools/mkimage -T zynqmpimage -R ./"" -d spl/u-boot-spl.bin spl/boot.bin" That's why mkimage is trying to parse ./ file and generate register init which is wrong. Check that passed filename is regular file. If not do not work with it. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- tools/zynqmpimage.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/tools/zynqmpimage.c b/tools/zynqmpimage.c index d08144c2bdfd..202faea07295 100644 --- a/tools/zynqmpimage.c +++ b/tools/zynqmpimage.c @@ -237,12 +237,18 @@ static int zynqmpimage_check_image_types(uint8_t type) static void zynqmpimage_parse_initparams(struct zynqmp_header *zynqhdr, const char *filename) { - /* Expect a table of register-value pairs, e.g. "0x12345678 0x4321" */ - FILE *fp = fopen(filename, "r"); + FILE *fp; struct zynqmp_reginit reginit; unsigned int reg_count = 0; int r; + struct stat path_stat; + + stat(filename, &path_stat); + if (!S_ISREG(path_stat.st_mode)) + return; + /* Expect a table of register-value pairs, e.g. "0x12345678 0x4321" */ + fp = fopen(filename, "r"); if (!fp) { fprintf(stderr, "Cannot open initparams file: %s\n", filename); exit(1); -- 1.9.1

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[U-Boot] [PATCH] mmc: refactor two core functions
by Masahiro Yamada 21 Oct '16

21 Oct '16

Drop unneeded variables and assignments. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- drivers/mmc/mmc-uclass.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c index 425abb1..4e955da 100644 --- a/drivers/mmc/mmc-uclass.c +++ b/drivers/mmc/mmc-uclass.c @@ -116,13 +116,7 @@ int get_mmc_num(void) int mmc_get_next_devnum(void) { - int ret; - - ret = blk_find_max_devnum(IF_TYPE_MMC); - if (ret < 0) - return ret; - - return ret; + return blk_find_max_devnum(IF_TYPE_MMC); } struct blk_desc *mmc_get_blk_desc(struct mmc *mmc) @@ -243,7 +237,6 @@ static int mmc_select_hwpart(struct udevice *bdev, int hwpart) struct udevice *mmc_dev = dev_get_parent(bdev); struct mmc *mmc = mmc_get_mmc_dev(mmc_dev); struct blk_desc *desc = dev_get_uclass_platdata(bdev); - int ret; if (desc->hwpart == hwpart) return 0; @@ -251,11 +244,7 @@ static int mmc_select_hwpart(struct udevice *bdev, int hwpart) if (mmc->part_config == MMCPART_NOAVAILABLE) return -EMEDIUMTYPE; - ret = mmc_switch_part(mmc, hwpart); - if (ret) - return ret; - - return 0; + return mmc_switch_part(mmc, hwpart); } static const struct blk_ops mmc_blk_ops = { -- 1.9.1

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[U-Boot] [PATCH] mmc: sdhci: fix the "misaligned operation at range" for cache
by Jaehoon Chung 21 Oct '16

21 Oct '16

This pathc is fixed the below thing. If misaligned the cache range, Just flush to CACHLINE_SIZE. "CACHE: Misaligned operation at range [7ae55b00, 7ae55b08]" Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> --- drivers/mmc/sdhci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 837c538..10ff57e 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -242,6 +242,7 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT); #ifdef CONFIG_MMC_SDMA + trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE); flush_cache(start_addr, trans_bytes); #endif sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND); -- 1.9.1

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[U-Boot] [PATCH V2] mmc: introduce mmc_power_init
by Peng Fan 21 Oct '16

21 Oct '16

In device tree, there is vmmc-supply property for SD/MMC. Introduce mmc_power_init function to handle vmmc-supply. mmc_power_init will first invoke board_mmc_power_init to avoid break boards which already implement board_mmc_power_init. If DM_MMC and DM_REGULATOR is defined, the regulator will be enabled to power up the device. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> --- V2: Change function prototype to static. Use puts to replace debug, when no vmmc-supply. V1: Use a generic way to handle vmmc supply, but not let vendor driver to handle it. The RFC patset thread: http://lists.denx.de/pipermail/u-boot/2016-April/251019.html drivers/mmc/mmc.c | 30 +++++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 0312da9..320413a 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -15,6 +15,7 @@ #include <errno.h> #include <mmc.h> #include <part.h> +#include <power/regulator.h> #include <malloc.h> #include <memalign.h> #include <linux/list.h> @@ -1582,6 +1583,31 @@ __weak void board_mmc_power_init(void) { } +static int mmc_power_init(struct mmc *mmc) +{ + board_mmc_power_init(); + +#if defined(CONFIG_DM_MMC) && defined(CONFIG_DM_REGULATOR) && \ + !defined(CONFIG_SPL_BUILD) + struct udevice *vmmc_supply; + int ret; + + ret = device_get_supply_regulator(mmc->dev, "vmmc-supply", + &vmmc_supply); + if (ret) { + puts("No vmmc supply\n"); + return 0; + } + + ret = regulator_set_enable(vmmc_supply, true); + if (ret) { + puts("Error enabling VMMC supply\n"); + return ret; + } +#endif + return 0; +} + int mmc_start_init(struct mmc *mmc) { bool no_card; @@ -1606,7 +1632,9 @@ int mmc_start_init(struct mmc *mmc) #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT mmc_adapter_card_type_ident(); #endif - board_mmc_power_init(); + err = mmc_power_init(mmc); + if (err) + return err; #ifdef CONFIG_DM_MMC_OPS /* The device has already been probed ready for use */ -- 2.6.2

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[U-Boot] [ANN] U-Boot v2016.11-rc2 released
by Tom Rini 21 Oct '16

21 Oct '16

Hey all, It's release day and v2016.11-rc2 is out. I've tried to clean up my queue a bit, but I think there's still a few things I have outstanding. And I know I need to get some changes from Alexander for EFI stuff that I've already promised can come in. But we should also be moving towards release. So I will be picking up some Kconfig related changes and making sure we have no (unexplained) binary size changes. A perhaps less obvious change between -rc1 and -rc2 is that I've added test.py running for qemu-ppce500, qemu-x86, vexpress_ca15_tc2, vexpres_ca9x5 and integratorap_cm926ejs along with qemu-mips*. I plan on doing -rc3 on the 31st. Thanks all! -- Tom

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[U-Boot] [RFC PATCH v1 0/6] pxa3xx_nand updates
by Chris Packham 21 Oct '16

21 Oct '16

I'm looking into the NAND support for the db-88f6820-amc board. There are a number of changes in the pxa3xx_nand driver in Linux that are relevant (not specifically to this boards but to Armada boards in general). Some of these changes are cleanups and some are actual bug fixes. I'd really appreciate some testing on this. It doesn't make my board magically work but I feel like I'm making forward progress. Where applicable I'll Cc the author of the equivalent Linux patch. Perhaps I should put them in the From: line or not they deserve all the credit, I just want to see these changes in u-boot. Chris Packham (6): mtd: nand: pxa3xx_nand: Increase initial buffer size mtd: nand: pxa3xx_nand: use nand_to_mtd() mtd: nand: pxa3xx_nand: sync pxa3xx_nand_set_sdr_timing() mtd: nand: pxa3xx_nand: fix early spurious interrupt mtd: nand: pxa3xx-nand: fix random command timeouts mtd: nand: pxa3xx_nand: add support for partial chunks drivers/mtd/nand/pxa3xx_nand.c | 203 ++++++++++++++++++++++++++--------------- 1 file changed, 127 insertions(+), 76 deletions(-) -- 2.10.0.479.g7c56b16

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[U-Boot] [PATCH v2 1/3] armv8/ls1043a: fixup GIC offset according to SVR and GIC400_ADDR_ALIGN_64K[GIC_ADDR]
by Wenbin song 20 Oct '16

20 Oct '16

The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment and 64K alignment. The bit GIC400_ADDR_ALIGN_64K[GIC_ADDR] is used to choose which offset will be used. If GIC_ADDR bit is set, 4K alignment is used, or else 64K alignment is used. 64K alignment is the default setting. Signed-off-by: Wenbin Song <wenbin.song(a)nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu(a)nxp.com> --- v2: None --- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 47 +++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 12 +++++- 2 files changed, 57 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 5d0b7a4..569d2c2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -14,6 +14,40 @@ #include <asm/arch/mp.h> #endif +#ifdef CONFIG_LS1043A + +/* fixup GIC offset */ +ENTRY(fix_gic_offset) + ldr x0, =GICD_BASE + ldr x1, =GICC_BASE + ldr x3, =DCFG_CCSR_SVR + ldr w3, [x3] + rev w3, w3 + ands w3, w3, #0xff + cmp w3, #REV1_0 + b.eq 1f + ldr x3, =SCFG_GIC400_ALIGN + ldr w3, [x3] + rev w3, w3 + tbnz w3, #GIC_ADDR_BIT, 1f + ret +1: + ldr x0, =GICD_BASE_4K + ldr x1, =GICC_BASE_4K + ret +ENDPROC(fix_gic_offset) + +ENTRY(smp_kick_all_cpus) + /* Kick secondary cpus up by SGI 0 interrupt */ + mov x29, lr /* Save LR */ + bl fix_gic_offset + bl gic_kick_secondary_cpus + mov lr, x29 /* Restore LR */ + ret +ENDPROC(smp_kick_all_cpus) + +#endif + ENTRY(lowlevel_init) mov x29, lr /* Save LR */ @@ -105,15 +139,23 @@ ENTRY(lowlevel_init) /* Initialize GIC Secure Bank Status */ #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) branch_if_slave x0, 1f +#ifdef CONFIG_LS1043A + bl fix_gic_offset +#else ldr x0, =GICD_BASE +#endif bl gic_init_secure 1: #ifdef CONFIG_GICV3 ldr x0, =GICR_BASE bl gic_init_secure_percpu #elif defined(CONFIG_GICV2) +#ifdef CONFIG_LS1043A + bl fix_gic_offset +#else ldr x0, =GICD_BASE ldr x1, =GICC_BASE +#endif bl gic_init_secure_percpu #endif #endif @@ -335,7 +377,12 @@ ENTRY(secondary_boot_func) #if defined(CONFIG_GICV3) gic_wait_for_interrupt_m x0 #elif defined(CONFIG_GICV2) +#ifdef CONFIG_LS1043A + bl fix_gic_offset + mov x0, x1 +#else ldr x0, =GICC_BASE +#endif gic_wait_for_interrupt_m x0, w1 #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 4201e0f..eb6e58d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -172,8 +172,16 @@ #define SMMU_BASE 0x09000000 /* Generic Interrupt Controller Definitions */ -#define GICD_BASE 0x01401000 -#define GICC_BASE 0x01402000 +#define GICD_BASE 0x01410000 +#define GICC_BASE 0x01420000 +#define GICD_BASE_4K 0x01401000 +#define GICC_BASE_4K 0x01402000 + +#define DCFG_CCSR_SVR 0x1ee00a4 +#define REV1_0 0x10 +#define REV1_1 0x11 +#define GIC_ADDR_BIT 31 +#define SCFG_GIC400_ALIGN 0x1570188 #define CONFIG_SYS_FSL_ERRATUM_A008850 #define CONFIG_SYS_FSL_ERRATUM_A009663 -- 2.1.0.27.g96db324

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[U-Boot] Altera CycloneV socfpga development kit QSPI flash access from u-boot
by Marcel Gielen [Celestia-STS] 20 Oct '16

20 Oct '16

I am trying to use the QSPI flash from uboot on the development kit. The flash content starts at offset 0 with 0xdeadbeaf * Reading in linux from the MTD partition => data ok * Using u-boot from the SDK GSRD image (u-boot 2013.01.01) => data ok * Using u-boot socfpga 2016-05 from Altera git => data incorrect * Using u-boot socfpga 2016-09 from Altera git => data incorrect * Using u-boot 2016-09 from git.denx => resets at "Trying to boot from MMC1" I assume the SPL expects u-boot somewhere else ? All last three u-boot versions were stock version with default confuration for the SOC development kit. Any clue why it doesn't work ? I would expect timing issue, but the read errors are consistent. Read command used: => sf probe => sf read ${loadaddr} 0 128 device 0 offset 0x0, size 0x128 SF: 296 bytes @ 0x0 Read: OK => md ${loadaddr} Data as read with GSRD u-boot 00008090: deadbeaf deadbeaf deadbeaf deadbeaf ................ 000080a0: deadbeaf deadbeaf deadbeaf deadbeaf ................ 000080b0: deadbeaf deadbeaf deadbeaf deadbeaf ................ 000080c0: deadbeaf deadbeaf deadbeaf deadbeaf ................ 000080d0: deadbeaf deadbeaf deadbeaf deadbeaf ................ ... Data as read with newer u-boot 01000000: beafdeff beafdead beafdead beafdead ................ 01000010: beafdead beafdead beafdead beafdead ................ 01000020: beafdead beafdead ffffdead ffffffff ................ 01000030: ffffffff ffffffff ffffffff ffffffff ................ 01000040: ffffffff ffffffff ffffffff ffffffff ................ 01000050: ffffffff ffffffff ffffffff ffffffff ................ ...

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[U-Boot] [PATCH] i2c: designware: Avoid overwriting the cmd_data register
by Marek Vasut 20 Oct '16

20 Oct '16

Make sure the driver writes the cmd_data register only once per read transfer instead of doing so potentially repeatedly. In case the read transfer didn't finish quickly enough, the loop in the driver code would spin fast enough to write the same value into the cmd_data register again before re-checking whether the transfer completed, which would cause another spurious read transfer on the bus. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> Cc: Alexey Brodkin <abrodkin(a)synopsys.com> Cc: Heiko Schocher <hs(a)denx.de> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Chin Liang See <clsee(a)altera.com> --- drivers/i2c/designware_i2c.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index e60fd0a..c68ff64 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -249,6 +249,7 @@ static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr, int alen, u8 *buffer, int len) { unsigned long start_time_rx; + unsigned int active = 0; #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW /* @@ -274,18 +275,28 @@ static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr, start_time_rx = get_timer(0); while (len) { - if (len == 1) - writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data); - else - writel(IC_CMD, &i2c_base->ic_cmd_data); + if (!active) { + /* + * Avoid writing to ic_cmd_data multiple times + * in case this loop spins too quickly and the + * ic_status RFNE bit isn't set after the first + * write. Subsequent writes to ic_cmd_data can + * trigger spurious i2c transfer. + */ + if (len == 1) + writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data); + else + writel(IC_CMD, &i2c_base->ic_cmd_data); + active = 1; + } if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) { *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data); len--; start_time_rx = get_timer(0); - + active = 0; } else if (get_timer(start_time_rx) > I2C_BYTE_TO) { - return 1; + return 1; } } -- 2.9.3

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[U-Boot] [PATCH] spi: cadence_qspi_apb: Improve indirect write transaction
by Vignesh R 20 Oct '16

20 Oct '16

If the write transaction size(write_bytes) is not a multiple of word length, then issue word length writes till the we reach the dangling bytes. On the final write, issue byte by byte write to complete the transaction. This marginally improves write throughput when performing random sized writes to the flash. Signed-off-by: Vignesh R <vigneshr(a)ti.com> --- Tested on K2G GP EVM. drivers/spi/cadence_qspi_apb.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index e285d3c1e761..4b891f227243 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -752,10 +752,16 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, while (remaining > 0) { write_bytes = remaining > page_size ? page_size : remaining; /* Handle non-4-byte aligned access to avoid data abort. */ - if (((uintptr_t)txbuf % 4) || (write_bytes % 4)) + if ((uintptr_t)txbuf % 4) { writesb(plat->ahbbase, txbuf, write_bytes); - else + } else { writesl(plat->ahbbase, txbuf, write_bytes >> 2); + if (write_bytes % 4) { + writesb(plat->ahbbase, + txbuf + rounddown(write_bytes, 4), + write_bytes % 4); + } + } ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL, CQSPI_REG_SDRAMLEVEL_WR_MASK << -- 2.7.4

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