January 2016 - U-Boot

[U-Boot] [PATCH] drivers/net/phy: introduce phy_set_supported()
by Alexey Brodkin 11 Jan '16

11 Jan '16

This new function will allow MAC drivers to override supported capabilities of the phy. It is required when MAC cannot handle all speeds supported by phy. For example phy supports up-to 1Gb connections while MAC may only work in modes up to 100 or even 10 Mbit/sec. Signed-off-by: Alexey Brodkin <abrodkin(a)synopsys.com> Cc: Joe Hershberger <joe.hershberger(a)ni.com> --- drivers/net/phy/phy.c | 24 ++++++++++++++++++++++++ include/phy.h | 1 + 2 files changed, 25 insertions(+) diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index ec9be6b..4ad4e78 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -526,6 +526,30 @@ int phy_register(struct phy_driver *drv) return 0; } +int phy_set_supported(struct phy_device *phydev, u32 max_speed) +{ + /* The default values for phydev->supported are provided by the PHY + * driver "features" member, we want to reset to sane defaults first + * before supporting higher speeds. + */ + phydev->supported &= PHY_DEFAULT_FEATURES; + + switch (max_speed) { + default: + return -ENOTSUPP; + case SPEED_1000: + phydev->supported |= PHY_1000BT_FEATURES; + /* fall through */ + case SPEED_100: + phydev->supported |= PHY_100BT_FEATURES; + /* fall through */ + case SPEED_10: + phydev->supported |= PHY_10BT_FEATURES; + } + + return 0; +} + static int phy_probe(struct phy_device *phydev) { int err = 0; diff --git a/include/phy.h b/include/phy.h index b793e90..e030c9f 100644 --- a/include/phy.h +++ b/include/phy.h @@ -234,6 +234,7 @@ int phy_startup(struct phy_device *phydev); int phy_config(struct phy_device *phydev); int phy_shutdown(struct phy_device *phydev); int phy_register(struct phy_driver *drv); +int phy_set_supported(struct phy_device *phydev, u32 max_speed); int genphy_config_aneg(struct phy_device *phydev); int genphy_restart_aneg(struct phy_device *phydev); int genphy_update_link(struct phy_device *phydev); -- 2.4.3

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[U-Boot] [PATCH v3 0/4] Change DM_SEQ_ALIAS to be configurable for SPL
by Nathan Rossi 11 Jan '16

11 Jan '16

Add a config option for SPL_DM_SEQ_ALIAS and enable it for the Zynq targets which require it for SPI flash support in SPL. Changes in v2: * Add patches to enable the config for mvebu and socfpga targets. Changes in v3: * Removed de0nano and mcvevk boards from socfpga config patch Nathan Rossi (4): spl: dm: Add SPL_DM_SEQ_ALIAS config option arm: zynq: Enable SPL_DM_SEQ_ALIAS for all Zynq configs arm: mvebu: Select SPL_DM_SEQ_ALIAS arm: socfpga: Enable SPL_DM_SEQ_ALIAS for all SOCFPGA configs arch/arm/Kconfig | 1 + configs/socfpga_arria5_defconfig | 1 + configs/socfpga_cyclone5_defconfig | 1 + configs/socfpga_sockit_defconfig | 1 + configs/socfpga_socrates_defconfig | 1 + configs/socfpga_sr1500_defconfig | 1 + configs/zynq_microzed_defconfig | 1 + configs/zynq_picozed_defconfig | 1 + configs/zynq_zc702_defconfig | 1 + configs/zynq_zc706_defconfig | 1 + configs/zynq_zc770_xm010_defconfig | 1 + configs/zynq_zc770_xm011_defconfig | 1 + configs/zynq_zc770_xm012_defconfig | 1 + configs/zynq_zc770_xm013_defconfig | 1 + configs/zynq_zed_defconfig | 1 + configs/zynq_zybo_defconfig | 1 + drivers/core/Kconfig | 9 +++++++++ drivers/core/device.c | 2 +- include/config_uncmd_spl.h | 1 - include/configs/socfpga_common.h | 1 - 20 files changed, 26 insertions(+), 3 deletions(-) -- 2.6.4

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[U-Boot] [PATCHv2 0/3] spl: Lightweight UBI and UBI fastmap support
by Ladislav Michl 11 Jan '16

11 Jan '16

This is an update of Thomas's patchset: https://patchwork.ozlabs.org/patch/367305/ https://patchwork.ozlabs.org/patch/367306/ Changes from previous version: - fixes ubi_calc_fm_size to include also sizeof(struct ubi_fm_sb) - dropped private copy of ubi-media.h - ubi-wrapper.h now contains only needed definitions from ubi.h and ubi-user.h - used return values from errno.h - added example implementation for igep00x0.

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[U-Boot] [Patch V4 3/4] spi: fsl_qspi: Fix qspi_op_rdsr memcpy issue
by Gong Qianyu 11 Jan '16

11 Jan '16

From: Gong Qianyu <Qianyu.Gong(a)freescale.com> In current driver, we always copy 4 bytes to the dest memory. Actually the dest memory may be shorter than 4 bytes. Add an argument to indicate the dest memory length. Avoid writing memory outside of the bounds. Signed-off-by: Gong Qianyu <Qianyu.Gong(a)freescale.com> --- V3-V4: - No change. V2: - New patch. drivers/spi/fsl_qspi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 4d58211..ab17c4e 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -642,7 +642,7 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len) qspi_write32(priv->flags, &regs->mcr, mcr_reg); } -static void qspi_op_rdsr(struct fsl_qspi_priv *priv, u32 *rxbuf) +static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len) { struct fsl_qspi_regs *regs = priv->regs; u32 mcr_reg, reg, data; @@ -665,7 +665,7 @@ static void qspi_op_rdsr(struct fsl_qspi_priv *priv, u32 *rxbuf) if (reg & QSPI_RBSR_RDBFL_MASK) { data = qspi_read32(priv->flags, &regs->rbdr[0]); data = qspi_endian_xchg(data); - memcpy(rxbuf, &data, 4); + memcpy(rxbuf, &data, len); qspi_write32(priv->flags, &regs->mcr, qspi_read32(priv->flags, &regs->mcr) | QSPI_MCR_CLR_RXF_MASK); @@ -754,7 +754,7 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen, } else if (priv->cur_seqid == QSPI_CMD_RDID) qspi_op_rdid(priv, din, bytes); else if (priv->cur_seqid == QSPI_CMD_RDSR) - qspi_op_rdsr(priv, din); + qspi_op_rdsr(priv, din, bytes); #ifdef CONFIG_SPI_FLASH_BAR else if ((priv->cur_seqid == QSPI_CMD_BRRD) || (priv->cur_seqid == QSPI_CMD_RDEAR)) { -- 2.1.0.27.g96db324

1 0

[U-Boot] [Patch V3 4/4] dm: env_sf: fix saveenv() to use driver model
by Gong Qianyu 11 Jan '16

11 Jan '16

From: Gong Qianyu <Qianyu.Gong(a)freescale.com> It might be missed when converting spi_flash_probe() in cmd_sf.c. This commit refers to fbb099183e3a53f77a975964cdf2e73d11e565af. Signed-off-by: Gong Qianyu <Qianyu.Gong(a)freescale.com> --- V3: - Remove redundant operations for saveenv() V2: - New patch. common/env_sf.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/common/env_sf.c b/common/env_sf.c index 9409831..fd0c82a 100644 --- a/common/env_sf.c +++ b/common/env_sf.c @@ -16,6 +16,7 @@ #include <spi_flash.h> #include <search.h> #include <errno.h> +#include <dm/device-internal.h> #ifndef CONFIG_ENV_SPI_BUS # define CONFIG_ENV_SPI_BUS 0 @@ -51,6 +52,22 @@ int saveenv(void) char *saved_buffer = NULL, flag = OBSOLETE_FLAG; u32 saved_size, saved_offset, sector = 1; int ret; +#ifdef CONFIG_DM_SPI_FLASH + struct udevice *new; + unsigned int bus = CONFIG_SF_DEFAULT_BUS; + unsigned int cs = CONFIG_SF_DEFAULT_CS; + unsigned int speed = CONFIG_SF_DEFAULT_SPEED; + unsigned int mode = CONFIG_SF_DEFAULT_MODE; + + ret = spi_flash_probe_bus_cs(bus, cs, speed, mode, &new); + if (ret) { + printf("Failed to initialize SPI flash at %u:%u (error %d)\n", + bus, cs, ret); + return 1; + } + + env_flash = dev_get_uclass_priv(new); +#else if (!env_flash) { env_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, @@ -61,6 +78,7 @@ int saveenv(void) return 1; } } +#endif ret = env_export(&env_new); if (ret) @@ -227,6 +245,22 @@ int saveenv(void) char *saved_buffer = NULL; int ret = 1; env_t env_new; +#ifdef CONFIG_DM_SPI_FLASH + struct udevice *new; + unsigned int bus = CONFIG_SF_DEFAULT_BUS; + unsigned int cs = CONFIG_SF_DEFAULT_CS; + unsigned int speed = CONFIG_SF_DEFAULT_SPEED; + unsigned int mode = CONFIG_SF_DEFAULT_MODE; + + ret = spi_flash_probe_bus_cs(bus, cs, speed, mode, &new); + if (ret) { + printf("Failed to initialize SPI flash at %u:%u (error %d)\n", + bus, cs, ret); + return 1; + } + + env_flash = dev_get_uclass_priv(new); +#else if (!env_flash) { env_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, @@ -237,6 +271,7 @@ int saveenv(void) return 1; } } +#endif /* Is the sector larger than the env (i.e. embedded) */ if (CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE) { -- 2.1.0.27.g96db324

3 2

[U-Boot] [PATCH 0/6] arm: socfpga: arria10: more a10 enablement
by dinguyen＠opensource.altera.com 10 Jan '16

10 Jan '16

From: Dinh Nguyen <dinguyen(a)opensource.altera.com> Hi, This is another round of patches for the Arria10 device. There are still some build failures that related to the clocking, FPGA manager, and bridge support. Thanks, Dinh Nguyen (6): arm: socfpga: wrap system manager functions for A5/C5 devices arm: socfpga: add reset manager defines for Arria10 arm: socfpga: arria10: update dwmac reset function to support Arria10 arm: socfpga: arria10: don't build GEN5 sdram for arria10 arm: socfpga: arria10 fpga does not have bridges mapped arm: socfpga: arria10: remove board_init and s_init .../arm/mach-socfpga/include/mach/system_manager.h | 1 + arch/arm/mach-socfpga/misc.c | 20 ++++ arch/arm/mach-socfpga/system_manager.c | 2 + board/altera/arria10-socdk/socfpga.c | 17 ---- drivers/Kconfig | 2 + drivers/ddr/Kconfig | 1 + drivers/ddr/altera/Kconfig | 6 ++ drivers/fpga/socfpga.c | 2 + include/configs/socfpga_common.h | 5 - include/dt-bindings/reset/altr,rst-mgr-a10.h | 103 +++++++++++++++++++++ 10 files changed, 137 insertions(+), 22 deletions(-) create mode 100644 drivers/ddr/Kconfig create mode 100644 drivers/ddr/altera/Kconfig create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h -- 2.6.2

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[U-Boot] [PULL] Please pull u-boot-imx
by Stefano Babic 10 Jan '16

10 Jan '16

Hi Tom, just a few fixes for release. Pleas epull from u-boot-imx, thanks ! The following changes since commit 3861d784b1a470570a0098ac5c25d79e3073c0d9: Merge git://git.denx.de/u-boot-mpc85xx (2016-01-07 11:24:27 -0500) are available in the git repository at: git://www.denx.de/git/u-boot-imx.git master for you to fetch changes up to 587c3f8ebe356b558f1876414885c1b4a31294ab: imx_watchdog: always set minimal timeout in reset_cpu (2016-01-07 17:54:53 +0100) ---------------------------------------------------------------- Andrey Skvortsov (1): imx_watchdog: always set minimal timeout in reset_cpu Fabio Estevam (3): phy: atheros: Use ar8035_config for AR8031 mx6sabresd: Simplify the Ethernet PHY configuration wandboard: Simplify the Ethernet PHY configuration Måns Rullgård (1): gpio: mxs: add name_to_gpio() function Peng Fan (2): imx: mx6ul: disable VIDEO for SPL imx: mx7: fix the temperature checking for Rev1.1 Ye.Li (1): pfuze: Fix unsigned variable for less-than-zero comparison board/freescale/common/pfuze.c | 3 ++- board/freescale/mx6sabresd/mx6sabresd.c | 36 ++---------------------------------- board/wandboard/wandboard.c | 36 ++---------------------------------- drivers/gpio/mxs_gpio.c | 15 +++++++++++++++ drivers/net/phy/atheros.c | 2 +- drivers/thermal/imx_thermal.c | 23 +++++++++++++++-------- drivers/watchdog/imx_watchdog.c | 2 +- include/configs/mx6ul_14x14_evk.h | 2 ++ include/fsl_wdog.h | 1 + 9 files changed, 41 insertions(+), 79 deletions(-) -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic(a)denx.de =====================================================================

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[U-Boot] [PATCH] common: cli_simple: use strncpy instead of strcpy
by Peng Fan 10 Jan '16

10 Jan '16

Report Coverity log: Destination buffer too small (STRING_OVERFLOW) string_overflow: You might overrun the 1024 byte destination string lastcommand by writing 1025 bytes from console_buffer Signed-off-by: Peng Fan <van.freenix(a)gmail.com> Cc: Heiko Schocher <hs(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> Cc: Tom Rini <trini(a)konsulko.com> --- common/cli_simple.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/common/cli_simple.c b/common/cli_simple.c index 9c3d073..c51f963 100644 --- a/common/cli_simple.c +++ b/common/cli_simple.c @@ -276,7 +276,8 @@ void cli_simple_loop(void) flag = 0; /* assume no special flags for now */ if (len > 0) - strcpy(lastcommand, console_buffer); + strncpy(lastcommand, console_buffer, + CONFIG_SYS_CBSIZE + 1); else if (len == 0) flag |= CMD_FLAG_REPEAT; #ifdef CONFIG_BOOT_RETRY_TIME -- 2.6.2

2 2

[U-Boot] [PATCH v2 06/13] MIPS: Add support for Microchip PIC32MZ[DA] family.
by Purna Chandra Mandal 09 Jan '16

09 Jan '16

Signed-off-by: Purna Chandra Mandal <purna.mandal(a)microchip.com> --- Changes in v2: - drop unnecessary board_early_init_f() - use LEAF(), END() macros for lowlevel_init - move initialization of board_init_f() argument to common start.S - move initdram() from board/microchip/ to mach-pic32/cpu.c - remove MIPS virtual address in favor of physical address in dts file arch/mips/cpu/start.S | 2 + arch/mips/dts/pic32mzda.dtsi | 64 +++++++++++++ arch/mips/mach-pic32/Kconfig | 16 +++- arch/mips/mach-pic32/Makefile | 2 +- arch/mips/mach-pic32/cpu.c | 146 ++++++++++++++++++++++++++++++ arch/mips/mach-pic32/include/mach/pic32.h | 3 + arch/mips/mach-pic32/lowlevel_init.S | 27 ++++++ arch/mips/mach-pic32/reset.c | 36 ++++++++ 8 files changed, 294 insertions(+), 2 deletions(-) create mode 100644 arch/mips/dts/pic32mzda.dtsi create mode 100644 arch/mips/mach-pic32/lowlevel_init.S create mode 100644 arch/mips/mach-pic32/reset.c diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index e95cdca..a7e6722 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -185,6 +185,8 @@ reset: PTR_ADDU t0, k0, GD_MALLOC_BASE # gd->malloc_base offset sw sp, 0(t0) #endif + /* Initialize args to zero. */ + li a0, 0x0 PTR_LA t9, board_init_f jr t9 diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi new file mode 100644 index 0000000..f518ba8 --- /dev/null +++ b/arch/mips/dts/pic32mzda.dtsi @@ -0,0 +1,64 @@ +/* + * Copyright 2015 Microchip Technology, Inc. + * Purna Chandra Mandal, <purna.mandal(a)microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/clock/microchip,clock.h> +#include "skeleton.dtsi" + +/ { + compatible = "microchip,pic32mzda", "microchip,pic32mz"; + + cpus { + cpu@0 { + compatible = "mips,mips14kc"; + }; + }; + + clock: clk@1f801200 { + compatible = "microchip,pic32mzda_clk"; + reg = <0x1f801200 0x1000>; + clock-cells = <1>; + }; + + uart1: serial@1f822000 { + compatible = "microchip,pic32mzda-uart"; + reg = <0x1f822000 0x50>; + interrupts = <112 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + clocks = <&clock PB2CLK>; + }; + + uart2: serial@1f822200 { + compatible = "microchip,pic32mzda-uart"; + reg = <0x1f822200 0x50>; + interrupts = <145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock PB2CLK>; + status = "disabled"; + }; + + uart6: serial@1f822a00 { + compatible = "microchip,pic32mzda-uart"; + reg = <0x1f822a00 0x50>; + interrupts = <188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock PB2CLK>; + status = "disabled"; + }; + + evic: interrupt-controller@1f810000 { + compatible = "microchip,pic32mzda-evic"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1f810000 0x1000>; + }; + + pinctrl: pinctrl@1f801400 { + compatible = "microchip,pic32mzda-pinctrl"; + reg = <0x1f801400 0x100>, /* in */ + <0x1f801500 0x200>; /* out */ + status = "disabled"; + }; +}; diff --git a/arch/mips/mach-pic32/Kconfig b/arch/mips/mach-pic32/Kconfig index 98b0b88..a394791 100644 --- a/arch/mips/mach-pic32/Kconfig +++ b/arch/mips/mach-pic32/Kconfig @@ -2,11 +2,25 @@ menu "Microchip PIC32 platforms" depends on MACH_PIC32 config SYS_SOC - default "none" + default "pic32mzda" if SOC_PIC32MZDA choice prompt "PIC32 SoC select" +config SOC_PIC32MZDA + bool "Microchip PIC32MZ[DA] family" + select SUPPORTS_LITTLE_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select SYS_MIPS_CACHE_INIT_RAM_LOAD + select MIPS_BOOT_CMDLINE_LEGACY + select MIPS_BOOT_FDT + select DM_SERIAL + select PIC32_SERIAL + select PIC32_PINCTRL + help + This supports Microchip PIC32MZ[DA] family of microcontrollers. + endchoice choice diff --git a/arch/mips/mach-pic32/Makefile b/arch/mips/mach-pic32/Makefile index cb42607..e321e65 100644 --- a/arch/mips/mach-pic32/Makefile +++ b/arch/mips/mach-pic32/Makefile @@ -4,4 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y = cpu.o +obj-y = cpu.o lowlevel_init.o reset.o \ No newline at end of file diff --git a/arch/mips/mach-pic32/cpu.c b/arch/mips/mach-pic32/cpu.c index 58fd3ab..7bd0f07 100644 --- a/arch/mips/mach-pic32/cpu.c +++ b/arch/mips/mach-pic32/cpu.c @@ -6,8 +6,154 @@ * */ #include <common.h> +#include <dm.h> +#include <clk.h> +#include <debug_uart.h> +#include <linux/compiler.h> +#include <asm/io.h> +#include <asm/mipsregs.h> +#include <mach/pic32.h> +#include <mach/ddr.h> +#include <dt-bindings/clock/microchip,clock.h> +/* Flash prefetch */ +#define PRECON 0x00 +#define PRECONCLR (PRECON + _CLR_OFFSET) +#define PRECONSET (PRECON + _SET_OFFSET) + +/* Flash ECCCON */ +#define ECC_MASK 0x03 +#define ECC_SHIFT 4 + +DECLARE_GLOBAL_DATA_PTR; + +static ulong clk_get_cpu_rate(void) +{ + int ret; + struct udevice *dev; + + ret = uclass_get_device(UCLASS_CLK, 0, &dev); + if (ret) { + panic("uclass-clk: device not found\n"); + return 0; + } + + return clk_get_rate(dev); +} + +/* initialize prefetch module related to cpu_clk */ +static void init_prefetch(void) +{ +#define _MHZ(x) ((x) * 1000000) + void __iomem *base; + int v, nr_waits; + ulong rate; + + rate = clk_get_cpu_rate(); + + /* get flash ECC type */ + base = pic32_ioremap(PIC32_CFG_BASE); + v = (readl(base + CFGCON) >> ECC_SHIFT) & ECC_MASK; + if (v < 2) { + if (rate < _MHZ(66)) + nr_waits = 0; + else if (rate < _MHZ(133)) + nr_waits = 1; + else + nr_waits = 2; + } else { + if (rate <= _MHZ(83)) + nr_waits = 0; + else if (rate <= _MHZ(166)) + nr_waits = 1; + else + nr_waits = 2; + } + + base = pic32_ioremap(PREFETCH_BASE); + writel(nr_waits, base + PRECON); + + /* Enable prefetch for all */ + writel(0x30, base + PRECONSET); +#undef _MHZ +} + +/* arch specific CPU init after DM */ +int arch_cpu_init_dm(void) +{ + /* flash prefetch */ + init_prefetch(); + return 0; +} + +/* Un-gate DDR2 modules (gated by default) */ +static void ddr2_pmd_ungate(void) +{ + void __iomem *regs; + + regs = pic32_ioremap(PIC32_CFG_BASE); + writel(0, regs + PMD7); +} + +/* initialize the DDR2 Controller and DDR2 PHY */ phys_size_t initdram(int board_type) { + ddr2_pmd_ungate(); + ddr2_phy_init(); + ddr2_ctrl_init(); + return ddr2_calculate_size(); +} + +int misc_init_r(void) +{ + set_io_port_base(0); + return 0; +} + +#ifdef CONFIG_DISPLAY_BOARDINFO +const char *get_core_name(void) +{ + u32 proc_id; + const char *str; + + proc_id = read_c0_prid(); + switch (proc_id) { + case 0x19e28: + str = "PIC32MZ[DA]"; + break; + default: + str = "UNKNOWN"; + } + + return str; +} +#endif + +#ifdef CONFIG_CMD_CLK +int soc_clk_dump(void) +{ +#define F_MHZ(x) ((x) / 1000000) + int i, ret; + struct udevice *dev; + + ret = uclass_get_device(UCLASS_CLK, 0, &dev); + if (ret) { + printf("clk-uclass not found\n"); + return ret; + } + + printf("PLL Speed: %lu MHz\n", F_MHZ(clk_get_periph_rate(dev, PLLCLK))); + printf("CPU Speed: %lu MHz\n", F_MHZ(clk_get_rate(dev))); + printf("MPLL Speed: %lu MHz\n", F_MHZ(clk_get_periph_rate(dev, MPLL))); + + for (i = PB1CLK; i <= PB7CLK; i++) + printf("PB%d Clock Speed: %lu MHz\n", + i - PB1CLK + 1, F_MHZ(clk_get_periph_rate(dev, i))); + + for (i = REF1CLK; i <= REF5CLK; i++) + printf("REFO%d Clock Speed: %lu MHz\n", i - REF1CLK + 1, + F_MHZ(clk_get_periph_rate(dev, i))); +#undef F_MHZ return 0; } +#endif diff --git a/arch/mips/mach-pic32/include/mach/pic32.h b/arch/mips/mach-pic32/include/mach/pic32.h index f618697..8d4b275 100644 --- a/arch/mips/mach-pic32/include/mach/pic32.h +++ b/arch/mips/mach-pic32/include/mach/pic32.h @@ -76,4 +76,7 @@ static inline void __iomem *pic32_ioremap(phys_addr_t addr) return (void __iomem *)CKSEG1ADDR(addr); } +/* Core */ +const char *get_core_name(void); + #endif /* __PIC32_REGS_H__ */ diff --git a/arch/mips/mach-pic32/lowlevel_init.S b/arch/mips/mach-pic32/lowlevel_init.S new file mode 100644 index 0000000..bff5553 --- /dev/null +++ b/arch/mips/mach-pic32/lowlevel_init.S @@ -0,0 +1,27 @@ +/* + * (c) 2015 Purna Chandra Mandal <purna.mandal(a)microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * +*/ + +#include <config.h> +#include <asm/regdef.h> +#include <asm/mipsregs.h> +#include <asm/asm.h> + +LEAF(lowlevel_init) + /* + * Establish Cause + * (set IV bit) + */ + li t1, 0x00800000 + mtc0 t1, CP0_CAUSE + + /* Establish Wired (and Random) */ + mtc0 zero, CP0_WIRED + nop + + jr ra + nop + END(lowlevel_init) diff --git a/arch/mips/mach-pic32/reset.c b/arch/mips/mach-pic32/reset.c new file mode 100644 index 0000000..70467cb --- /dev/null +++ b/arch/mips/mach-pic32/reset.c @@ -0,0 +1,36 @@ +/* + * (c) 2015 Purna Chandra Mandal <purna.mandal(a)microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include <common.h> +#include <asm/io.h> +#include <mach/pic32.h> + +#define SYSKEY 0x0030 +#define UNLOCK_KEY1 0xaa996655 +#define UNLOCK_KEY2 0x556699aa +#define LOCK_KEY 0 + +#define RSWRST 0x1250 + +void _machine_restart(void) +{ + void __iomem *base; + + base = pic32_ioremap(PIC32_CFG_BASE); + + /* unlock sequence */ + writel(LOCK_KEY, base + SYSKEY); + writel(UNLOCK_KEY1, base + SYSKEY); + writel(UNLOCK_KEY2, base + SYSKEY); + + /* soft reset */ + writel(0x1, base + RSWRST); + (void) readl(base + RSWRST); + + while (1) + ; +} -- 1.8.3.1

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[U-Boot] [PATCH v6 08/10] mips: ath79: add spi driver
by Wills Wang 09 Jan '16

09 Jan '16

Signed-off-by: Wills Wang <wills.wang(a)live.com> --- Changes in v6: - Add rrw_delay in ath79_spi_priv for more accurate timing - Remove ath79_spi_delay - Calculate delay in ath79_spi_set_speed Changes in v5: - remove ar933x_spi_platdata - Import document "spi-ath79.txt" from kernel - Add delay for bitbang operation Changes in v4: - Use get_bus_freq instead of hardcode in SPI driver Changes in v3: - Convert spi driver to driver model - Same code style convertion Changes in v2: - Add a compatible spi driver doc/device-tree-bindings/spi/spi-ath79.txt | 19 +++ drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/ath79_spi.c | 230 +++++++++++++++++++++++++++++ 4 files changed, 258 insertions(+) create mode 100644 doc/device-tree-bindings/spi/spi-ath79.txt create mode 100644 drivers/spi/ath79_spi.c diff --git a/doc/device-tree-bindings/spi/spi-ath79.txt b/doc/device-tree-bindings/spi/spi-ath79.txt new file mode 100644 index 0000000..3fd9d67 --- /dev/null +++ b/doc/device-tree-bindings/spi/spi-ath79.txt @@ -0,0 +1,19 @@ +Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller + +Required properties: +- compatible: has to be "qca,<soc-type>-spi", "qca,ar7100-spi" as fallback. +- reg: Base address and size of the controllers memory area +- #address-cells: <1>, as required by generic SPI binding. +- #size-cells: <0>, also as required by generic SPI binding. + +Child nodes as per the generic SPI binding. + +Example: + + spi@1f000000 { + compatible = "qca,ar9132-spi", "qca,ar7100-spi"; + reg = <0x1f000000 0x10>; + + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 2cdb110..0ab2741 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -23,6 +23,14 @@ config ALTERA_SPI IP core. Please find details on the "Embedded Peripherals IP User Guide" of Altera. +config ATH79_SPI + bool "Atheros SPI driver" + help + Enable the Atheros ar7xxx/ar9xxx SoC SPI driver, it was used + to access SPI NOR flash and other SPI peripherals. This driver + uses driver model and requires a device tree binding to operate. + please refer to doc/device-tree-bindings/spi/spi-ath79.txt. + config CADENCE_QSPI bool "Cadence QSPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 3eca745..7fb2926 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -17,6 +17,7 @@ endif obj-$(CONFIG_ALTERA_SPI) += altera_spi.o obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o +obj-$(CONFIG_ATH79_SPI) += ath79_spi.o obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o obj-$(CONFIG_BFIN_SPI) += bfin_spi.o diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c new file mode 100644 index 0000000..3912332 --- /dev/null +++ b/drivers/spi/ath79_spi.c @@ -0,0 +1,230 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spi.h> +#include <dm.h> +#include <div64.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <mach/ar71xx_regs.h> + +/* CLOCK_DIVIDER = 3 (SPI clock = 200 / 8 ~ 25 MHz) */ +#define ATH79_SPI_CLK_DIV(x) (((x) >> 1) - 1) +#define ATH79_SPI_RRW_DELAY_FACTOR 12000 +#define MHZ (1000 * 1000) + +struct ath79_spi_priv { + void __iomem *regs; + u32 rrw_delay; +}; + +static inline u32 ath79_spi_read(struct udevice *bus, u32 offset) +{ + struct ath79_spi_priv *priv = dev_get_priv(bus); + return readl(priv->regs + offset); +} + +static inline void ath79_spi_write(struct udevice *bus, + u32 val, u32 offset) +{ + struct ath79_spi_priv *priv = dev_get_priv(bus); + writel(val, priv->regs + offset); +} + +static int ath79_spi_claim_bus(struct udevice *dev) +{ + return 0; +} + +static int ath79_spi_release_bus(struct udevice *dev) +{ + return 0; +} + +static int ath79_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct ath79_spi_priv *priv = dev_get_priv(bus); + struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev); + u8 *rx = din; + const u8 *tx = dout; + u8 curbyte, curbitlen, restbits; + u32 bytes = bitlen / 8; + u32 out, in; + u64 tick; + + + if (flags & SPI_XFER_BEGIN) { + ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS); + ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL, AR71XX_SPI_REG_IOC); + } + + restbits = (bitlen % 8); + if (restbits) + bytes++; + + out = AR71XX_SPI_IOC_CS_ALL & ~(AR71XX_SPI_IOC_CS(slave->cs)); + while (bytes > 0) { + bytes--; + curbyte = 0; + if (tx) + curbyte = *tx++; + + if (restbits && !bytes) { + curbitlen = restbits; + curbyte <<= 8 - restbits; + } else { + curbitlen = 8; + } + + for (curbyte <<= (8 - curbitlen); curbitlen; curbitlen--) { + if (curbyte & 0x80) + out |= AR71XX_SPI_IOC_DO; + else + out &= ~(AR71XX_SPI_IOC_DO); + + ath79_spi_write(bus, out, AR71XX_SPI_REG_IOC); + + /* delay for low level */ + if (priv->rrw_delay) { + tick = get_ticks() + priv->rrw_delay; + while (get_ticks() < tick) + /*NOP*/; + } + + ath79_spi_write(bus, out | AR71XX_SPI_IOC_CLK, + AR71XX_SPI_REG_IOC); + + /* delay for high level */ + if (priv->rrw_delay) { + tick = get_ticks() + priv->rrw_delay; + while (get_ticks() < tick) + /*NOP*/; + } + + curbyte <<= 1; + } + + if (!bytes) + ath79_spi_write(bus, out, AR71XX_SPI_REG_IOC); + + in = ath79_spi_read(bus, AR71XX_SPI_REG_RDS); + if (rx) { + if (restbits && !bytes) + *rx++ = (in << (8 - restbits)); + else + *rx++ = in; + } + } + + if (flags & SPI_XFER_END) { + ath79_spi_write(bus, AR71XX_SPI_IOC_CS(slave->cs), + AR71XX_SPI_REG_IOC); + ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL, AR71XX_SPI_REG_IOC); + ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS); + } + + return 0; +} + + +static int ath79_spi_set_speed(struct udevice *bus, uint speed) +{ + struct ath79_spi_priv *priv = dev_get_priv(bus); + u32 val, div = 0; + u64 time; + + if (speed) + div = get_bus_freq(0) / speed; + + if (div > 63) + div = 63; + + if (div < 5) + div = 5; + + /* calculate delay */ + time = get_tbclk(); + do_div(time, speed / 2); + val = ATH79_SPI_RRW_DELAY_FACTOR / (get_bus_freq(0) / MHZ); + if (time > val) + priv->rrw_delay = time - val + 1; + else + priv->rrw_delay = 0; + + ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS); + val = ath79_spi_read(bus, AR71XX_SPI_REG_CTRL); + val &= ~AR71XX_SPI_CTRL_DIV_MASK; + val |= ATH79_SPI_CLK_DIV(div); + ath79_spi_write(bus, val, AR71XX_SPI_REG_CTRL); + ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS); + return 0; +} + +static int ath79_spi_set_mode(struct udevice *bus, uint mode) +{ + return 0; +} + +static int ath79_spi_probe(struct udevice *bus) +{ + struct ath79_spi_priv *priv = dev_get_priv(bus); + fdt_addr_t addr; + + addr = dev_get_addr(bus); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->regs = map_physmem(addr, + AR71XX_SPI_SIZE, + MAP_NOCACHE); + + /* Init SPI Hardware, disable remap, set clock */ + ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS); + ath79_spi_write(bus, AR71XX_SPI_CTRL_RD | ATH79_SPI_CLK_DIV(8), + AR71XX_SPI_REG_CTRL); + ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS); + + return 0; +} + +static int ath79_cs_info(struct udevice *bus, uint cs, + struct spi_cs_info *info) +{ + /* Always allow activity on CS 0/1/2 */ + if (cs >= 3) + return -ENODEV; + + return 0; +} + +static const struct dm_spi_ops ath79_spi_ops = { + .claim_bus = ath79_spi_claim_bus, + .release_bus = ath79_spi_release_bus, + .xfer = ath79_spi_xfer, + .set_speed = ath79_spi_set_speed, + .set_mode = ath79_spi_set_mode, + .cs_info = ath79_cs_info, +}; + +static const struct udevice_id ath79_spi_ids[] = { + { .compatible = "qca,ar7100-spi" }, + {} +}; + +U_BOOT_DRIVER(ath79_spi) = { + .name = "ath79_spi", + .id = UCLASS_SPI, + .of_match = ath79_spi_ids, + .ops = &ath79_spi_ops, + .priv_auto_alloc_size = sizeof(struct ath79_spi_priv), + .probe = ath79_spi_probe, +}; -- 1.9.1

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