January 2016 - U-Boot

[U-Boot] [PATCH] igep00x0: enable CONFIG_CMD_SETEXPR
by Ladislav Michl 21 Jan '16

21 Jan '16

Enable CONFIG_CMD_SETEXPR, useful when passing initramfs end address: $ fatload mmc 0:1 $rdaddr root.cpio.gz $ setexpr rdendaddr $rdaddr + $filesize $ fdt chosen $rdaddr $rdendaddr $ bootz $loadaddr - $fdtaddr Signed-off-by: Ladislav Michl <ladis(a)linux-mips.org> --- configs/igep0020_defconfig | 2 +- configs/igep0020_nand_defconfig | 2 +- configs/igep0030_defconfig | 2 +- configs/igep0030_nand_defconfig | 2 +- configs/igep0032_defconfig | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/configs/igep0020_defconfig b/configs/igep0020_defconfig index a96c130..d4b5746 100644 --- a/configs/igep0020_defconfig +++ b/configs/igep0020_defconfig @@ -6,6 +6,6 @@ CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y -# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_SETEXPR=y CONFIG_SYS_NS16550=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/igep0020_nand_defconfig b/configs/igep0020_nand_defconfig index cf3ee79..57a3e78 100644 --- a/configs/igep0020_nand_defconfig +++ b/configs/igep0020_nand_defconfig @@ -6,6 +6,6 @@ CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y -# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_SETEXPR=y CONFIG_SYS_NS16550=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/igep0030_defconfig b/configs/igep0030_defconfig index 63ce633..1a1f548 100644 --- a/configs/igep0030_defconfig +++ b/configs/igep0030_defconfig @@ -6,5 +6,5 @@ CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y -# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_SETEXPR=y CONFIG_SYS_NS16550=y diff --git a/configs/igep0030_nand_defconfig b/configs/igep0030_nand_defconfig index dce7e06..c59b988 100644 --- a/configs/igep0030_nand_defconfig +++ b/configs/igep0030_nand_defconfig @@ -6,5 +6,5 @@ CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y -# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_SETEXPR=y CONFIG_SYS_NS16550=y diff --git a/configs/igep0032_defconfig b/configs/igep0032_defconfig index b7f1d61..27a763f 100644 --- a/configs/igep0032_defconfig +++ b/configs/igep0032_defconfig @@ -6,6 +6,6 @@ CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y -# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_SETEXPR=y CONFIG_SYS_NS16550=y CONFIG_NET_RANDOM_ETHADDR=y -- 2.1.4

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[U-Boot] [PATCH 1/2] armv8/ls1043a: fsl_qman: Implement device tree fixup for QBMan
by Gong Qianyu 21 Jan '16

21 Jan '16

From: Roy Pledge <Roy.Pledge(a)freescale.com> Add support for device tree fixup for the QBMan nodes in ARM platforms Signed-off-by: Roy Pledge <Roy.Pledge(a)freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 87 ++++++++++++++++++++++ .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 3 + .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 + include/configs/ls1043a_common.h | 2 + 4 files changed, 94 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index eafdd71..2a3e621 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -8,6 +8,8 @@ #include <libfdt.h> #include <fdt_support.h> #include <phy.h> +#include <asm/io.h> +#include <asm/arch/speed.h> #ifdef CONFIG_FSL_LSCH3 #include <asm/arch/fdt.h> #endif @@ -179,8 +181,86 @@ static void fdt_fixup_smmu(void *blob) } #endif +#ifdef CONFIG_SYS_DPAA_QBMAN +#define BMAN_IP_REV_1 0xBF8 +#define BMAN_IP_REV_2 0xBFC +void fdt_fixup_bportals(void *blob) +{ + int off, err; + unsigned int maj, min; + unsigned int ip_cfg; + + u32 rev_1 = in_be32(CONFIG_SYS_FSL_BMAN_ADDR + BMAN_IP_REV_1); + u32 rev_2 = in_be32(CONFIG_SYS_FSL_BMAN_ADDR + BMAN_IP_REV_2); + char compat[64]; + int compat_len; + + maj = (rev_1 >> 8) & 0xff; + min = rev_1 & 0xff; + + ip_cfg = rev_2 & 0xff; + + compat_len = sprintf(compat, "fsl,bman-portal-%u.%u.%u", + maj, min, ip_cfg) + 1; + compat_len += sprintf(compat + compat_len, "fsl,bman-portal") + 1; + + off = fdt_node_offset_by_compatible(blob, -1, "fsl,bman-portal"); + while (off != -FDT_ERR_NOTFOUND) { + err = fdt_setprop(blob, off, "compatible", compat, compat_len); + if (err < 0) { + printf("ERROR: unable to create props for %s: %s\n", + fdt_get_name(blob, off, NULL), + fdt_strerror(err)); + return; + } + + off = fdt_node_offset_by_compatible(blob, off, + "fsl,bman-portal"); + } +} + +#define QMAN_IP_REV_1 0xBF8 +#define QMAN_IP_REV_2 0xBFC +void fdt_fixup_qportals(void *blob) +{ + int off, err; + unsigned int maj, min; + unsigned int ip_cfg; + u32 rev_1 = in_be32(CONFIG_SYS_FSL_QMAN_ADDR + QMAN_IP_REV_1); + u32 rev_2 = in_be32(CONFIG_SYS_FSL_QMAN_ADDR + QMAN_IP_REV_2); + char compat[64]; + int compat_len; + + maj = (rev_1 >> 8) & 0xff; + min = rev_1 & 0xff; + ip_cfg = rev_2 & 0xff; + + compat_len = sprintf(compat, "fsl,qman-portal-%u.%u.%u", + maj, min, ip_cfg) + 1; + compat_len += sprintf(compat + compat_len, "fsl,qman-portal") + 1; + + off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal"); + while (off != -FDT_ERR_NOTFOUND) { + err = fdt_setprop(blob, off, "compatible", compat, compat_len); + if (err < 0) { + printf("ERROR: unable to create props for %s: %s\n", + fdt_get_name(blob, off, NULL), + fdt_strerror(err)); + return; + } + + off = fdt_node_offset_by_compatible(blob, off, + "fsl,qman-portal"); + } +} +#endif + void ft_cpu_setup(void *blob, bd_t *bd) { + struct sys_info sysinfo; + + get_sys_info(&sysinfo); + #ifdef CONFIG_MP ft_fixup_cpu(blob); #endif @@ -201,4 +281,11 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_FSL_LSCH3 fdt_fixup_smmu(blob); #endif + +#ifdef CONFIG_SYS_DPAA_QBMAN + fdt_fixup_bportals(blob); + fdt_fixup_qportals(blob); + do_fixup_by_compat_u32(blob, "fsl,qman", + "clock-frequency", sysinfo.freq_qman, 1); +#endif } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 6f6a588..99a9c36 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -117,6 +117,9 @@ void get_sys_info(struct sys_info *sys_info) sys_info->freq_localbus = sys_info->freq_systembus / ccr; #endif +#ifdef CONFIG_SYS_DPAA_QBMAN + sys_info->freq_qman = sys_info->freq_systembus / 2; +#endif } int get_clocks(void) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 21b803f..e3ca7cb 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -24,6 +24,8 @@ #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0) #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) #define CONFIG_SYS_FSL_FMAN_ADDR (CONFIG_SYS_IMMR + 0x00a00000) +#define CONFIG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000) +#define CONFIG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000) #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) #define CONFIG_SYS_FSL_DCFG_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) #define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 677d281..8220f6b 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -209,6 +209,8 @@ #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ + /* Miscellaneous configurable options */ #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) #define CONFIG_ARCH_EARLY_INIT_R -- 2.1.0.27.g96db324

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[U-Boot] [PATCH v3 0/5] Add wait_for_bit()
by Mateusz Kulikowski 21 Jan '16

21 Jan '16

Changes in V3: - wait_for_bit code is moved to header and converted to static inline function. Previous version added ~7byte of rodata to all boards (even not using wait_for_bit). Changes in V2: - wait_bit.o is always compiled in - Removed CONFIG_LIB_WAIT_BIT from configs/Kconfigs - Constified arguments to wait_bit - Removed check for CONFIG_... in drivers - Added tested-by to ohci-lp32xx @Sylvain Lemieux: I didn't changed driver logic with v2, so allowed myself to add your tested-by directly. Tested on: - USB driver on Dragonboard (not yet in mainline) - Infinite sleep (if timeout/interruption works) Build tested on single board for each driver/commit: - hikey - zynq_microzed - platinum (Old) notes from V1: This series add generic function to poll register waiting for one or more bits to change. Very similar function was used in several drivers: - dwc2 - ohci-lp32xx - ehci-mx6 - zynq_gem First patch adds function, following patches update drivers and board config files / defconfigs. This series was compile-tested with buildman for ~50 boards (most or even all boards affected by change) Code was also run-tested on ehci-msm driver (not yet in mainline) There is single difference in behavior: ohci-lp32xx driver will not print "Timeout..." message with debug disabled. I think it's not a big issue as this driver seems unused, but if it's an issue - please drop that patch. Mateusz Kulikowski (5): lib: Add wait_for_bit usb: dwc2: Use shared wait_for_bit usb: ohci-lpc32xx: Use shared wait_for_bit usb: ehci-mx6: Use shared wait_for_bit net: zynq_gem: Use shared wait_for_bit drivers/net/zynq_gem.c | 35 ++------------------ drivers/usb/host/dwc2.c | 41 ++++++++---------------- drivers/usb/host/ehci-mx6.c | 32 +++---------------- drivers/usb/host/ohci-lpc32xx.c | 34 ++++---------------- include/wait_bit.h | 71 +++++++++++++++++++++++++++++++++++++++++ 5 files changed, 97 insertions(+), 116 deletions(-) create mode 100644 include/wait_bit.h -- 2.5.0

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[U-Boot] [PATCH 0/4] sunxi: PSCI support for H3
by Chen-Yu Tsai 21 Jan '16

21 Jan '16

Hi everyone, This series enables PSCI support for the H3. Like other Allwinner SoCs, the implementation only supports PSCI 0.1, specifically only secondary CPU boot/hotplug. Patch 1 supports the SMTA (previously called TZPC) TrustZone hardware on H3. This controls non-secure access to some important hardware blocks. Patch 2 supports the security switch in H3's CCU. This is H3 only. No other SoCs have this feature. Patch 3 supports H3 using sun6i PSCI implementation. H3 uses the same power sequence as sun6i, including the power clamps. This is shown in Allwinner's SDK, and confirmed / tested by Siarhei. Patch 4 enables PSCI support for the H3 in Kconfig. I've only tested booting HYP/SMP on my Orange Pi PC. Hotplugging was not tested, but should work. Regards ChenYu Chen-Yu Tsai (4): sunxi: Support Secure Memory Touch Arbiter (SMTA) in sun8i H3 sunxi: Support H3 CCU security switches sunxi: Support PSCI ops on Allwinner H3 sunxi: Enable booting non-secure and virtualization for H3 arch/arm/cpu/armv7/sunxi/Makefile | 1 + arch/arm/cpu/armv7/sunxi/clock.c | 5 +++++ arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 13 +++++++++++++ arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 4 ++-- arch/arm/cpu/armv7/sunxi/tzpc.c | 11 ++++++++++- arch/arm/include/asm/arch-sunxi/clock.h | 1 + arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 7 +++++++ arch/arm/include/asm/arch-sunxi/tzpc.h | 13 ++++++++++++- board/sunxi/Kconfig | 3 +++ 9 files changed, 54 insertions(+), 4 deletions(-) -- 2.6.4

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[U-Boot] [PATCH] MIPS: start.S: fix and optimize instructions
by Daniel Schwierzeck 21 Jan '16

21 Jan '16

Fix 32 vs 64 bit load/store instructions. Access CP0_WATCHHI as 32 Bit register. Use 64 Bit register access for clearing gd_data and copying U-Boot. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> --- arch/mips/cpu/start.S | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index 2aa2dcb..d2c31ae 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -115,7 +115,7 @@ reset: /* Clear watch registers */ MTC0 zero, CP0_WATCHLO - MTC0 zero, CP0_WATCHHI + mtc0 zero, CP0_WATCHHI /* WP(Watch Pending), SW0/1 should be cleared */ mtc0 zero, CP0_CAUSE @@ -161,14 +161,14 @@ reset: #endif /* Set up temporary stack */ - PTR_LI t0, -16 + li t0, -16 PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR and sp, t1, t0 # force 16 byte alignment PTR_SUB sp, sp, GD_SIZE # reserve space for gd and sp, sp, t0 # force 16 byte alignment move k0, sp # save gd pointer #ifdef CONFIG_SYS_MALLOC_F_LEN - PTR_LI t2, CONFIG_SYS_MALLOC_F_LEN + li t2, CONFIG_SYS_MALLOC_F_LEN PTR_SUB sp, sp, t2 # reserve space for early malloc and sp, sp, t0 # force 16 byte alignment #endif @@ -177,14 +177,14 @@ reset: /* Clear gd */ move t0, k0 1: - sw zero, 0(t0) + PTR_S zero, 0(t0) blt t0, t1, 1b - PTR_ADDI t0, 4 + PTR_ADDI t0, PTRSIZE #ifdef CONFIG_SYS_MALLOC_F_LEN - PTR_ADDU t0, k0, GD_MALLOC_BASE # gd->malloc_base offset - sw sp, 0(t0) + PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset #endif + move a0, zero # a0 <-- boot_flags = 0 PTR_LA t9, board_init_f jr t9 @@ -224,11 +224,11 @@ ENTRY(relocate_code) * t2 = source end address */ 1: - lw t3, 0(t0) - sw t3, 0(t1) - PTR_ADDU t0, 4 + PTR_L t3, 0(t0) + PTR_S t3, 0(t1) + PTR_ADDU t0, PTRSIZE blt t0, t2, 1b - PTR_ADDU t1, 4 + PTR_ADDU t1, PTRSIZE /* If caches were enabled, we would have to flush them here. */ PTR_SUB a1, t1, s2 # a1 <-- size -- 2.5.0

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[U-Boot] Uboot send pull request
by uboot＠andestech.com 21 Jan '16

21 Jan '16

Hi Tom, Please pull the following patch from u-boot-nds32 into your tree. Thanks! The following changes since commit 077678eb0c226e52a1f90edabd3369ab26065b32: Merge git://git.denx.de/u-boot-dm (2016-01-12 18:12:42 -0500) are available in the git repository at: git://git.denx.de/u-boot-nds32.git master for you to fetch changes up to b19cc6bf2160e09607e141fe0fc571701070d1d6: nds32: Fix compile error. (2016-01-21 10:41:43 +0800) ---------------------------------------------------------------- rick (1): nds32: Fix compile error. arch/nds32/cpu/n1213/start.S | 2 +- arch/nds32/include/asm/macro.h | 22 +++++++++++----------- arch/nds32/include/asm/posix_types.h | 4 ++++ 3 files changed, 16 insertions(+), 12 deletions(-)

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[U-Boot] Please pull from u-boot-i2c
by Heiko Schocher 21 Jan '16

21 Jan '16

Hello Tom, please pull from u-boot-i2c.git The following changes since commit 57e5ecaf755d5301cd33683788e4b8432938bbbe: iocon / bamboo: Drop CONFIG_SYS_LONGHELP (2016-01-20 15:25:00 -0500) are available in the git repository at: git://git.denx.de/u-boot-i2c.git master for you to fetch changes up to 9d0826879e13e8139a7b169c2365225e848ff57e: sunxi: Add support for the I2C controller which is part of the PRCM (2016-01-21 07:30:01 +0100) ---------------------------------------------------------------- Hans de Goede (1): i2c: mvtwsi: Fix mvtwsi not working on sun6i and newer sunxi SoCs Jelle van der Waa (1): sunxi: Add support for the I2C controller which is part of the PRCM arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 10 ++++++++++ arch/arm/cpu/armv7/sunxi/prcm.c | 12 ++++++++++++ arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 1 + arch/arm/include/asm/arch-sunxi/gpio.h | 2 ++ arch/arm/include/asm/arch-sunxi/i2c.h | 3 +++ arch/arm/include/asm/arch-sunxi/prcm.h | 2 ++ board/sunxi/Kconfig | 6 ++++++ board/sunxi/board.c | 6 ++++++ configs/orangepi_pc_defconfig | 1 + drivers/i2c/mvtwsi.c | 31 +++++++++++++++++++++++++++---- include/configs/sunxi-common.h | 2 +- 11 files changed, 71 insertions(+), 5 deletions(-) bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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[U-Boot] [RFC PATCH 0/6] clk: some fixes, device tree support, new features
by Masahiro Yamada 21 Jan '16

21 Jan '16

Masahiro Yamada (6): clk: fix comments in include/clk.h clk: add needed include and declaration to include/clk.h clk: add function to get peripheral ID clk: add device tree support for clock framework clk: add enable() callback clk: add fixed rate clock driver drivers/clk/Makefile | 3 +- drivers/clk/clk-fdt.c | 37 +++++++++++++++++++ drivers/clk/clk-fixed-rate.c | 58 +++++++++++++++++++++++++++++ drivers/clk/clk-uclass.c | 10 +++++ include/clk.h | 87 +++++++++++++++++++++++++++++++++++++++----- 5 files changed, 184 insertions(+), 11 deletions(-) create mode 100644 drivers/clk/clk-fdt.c create mode 100644 drivers/clk/clk-fixed-rate.c -- 1.9.1

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[U-Boot] [PATCH v2] board/t4240rdb: VID support
by ying.zhang＠freescale.com 21 Jan '16

21 Jan '16

From: Ying Zhang <b40530(a)freescale.com> The fuse status register provides the values from on-chip voltage ID efuses programmed at the factory. These values define the voltage requirements for the chip. u-boot reads FUSESR and translates the values into the appropriate commands to set the voltage output value of an external voltage regulator. Signed-off-by: Ying Zhang <b40530(a)freescale.com> --- Changed from v1: - Not support IR chip is used in AMD mode --- board/freescale/common/vid.c | 19 +++++++++++++++++-- board/freescale/common/vid.h | 4 ++++ board/freescale/t4rdb/t4240rdb.c | 7 +++++++ include/configs/T4240RDB.h | 10 ++++++++++ 4 files changed, 38 insertions(+), 2 deletions(-) diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index f1bed51..1bd65a8 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -42,7 +42,7 @@ int __weak board_vdd_drop_compensation(void) * The IR chip can show up under the following addresses: * 0x08 (Verified on T1040RDB-PA,T4240RDB-PB,X-T4240RDB-16GPA) * 0x09 (Verified on T1040RDB-PA) - * 0x38 (Verified on T2080QDS, T2081QDS) + * 0x38 (Verified on T2080QDS, T2081QDS, T4240RDB) */ static int find_ir_chip_on_i2c(void) { @@ -292,7 +292,7 @@ int adjust_vdd(ulong vdd_override) (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif u32 fusesr; - u8 vid; + u8 vid, buf; int vdd_target, vdd_current, vdd_last; int ret, i2caddress; unsigned long vdd_string_override; @@ -346,6 +346,21 @@ int adjust_vdd(ulong vdd_override) debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress); } + /* check IR chip work on Intel mode*/ + ret = i2c_read(i2caddress, + IR36021_INTEL_MODE_OOFSET, + 1, (void *)&buf, 1); + if (ret) { + printf("VID: failed to read IR chip mode.\n"); + ret = -1; + goto exit; + } + if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) { + printf("VID: IR Chip is not used in Intel mode.\n"); + ret = -1; + goto exit; + } + /* get the voltage ID from fuse status register */ fusesr = in_be32(&gur->dcfg_fusesr); /* diff --git a/board/freescale/common/vid.h b/board/freescale/common/vid.h index a9c7bb4..9182c20 100644 --- a/board/freescale/common/vid.h +++ b/board/freescale/common/vid.h @@ -11,6 +11,10 @@ #define IR36021_LOOP1_VOUT_OFFSET 0x9A #define IR36021_MFR_ID_OFFSET 0x92 #define IR36021_MFR_ID 0x43 +#define IR36021_INTEL_MODE_OOFSET 0x14 +#define IR36021_MODE_MASK 0x20 +#define IR36021_INTEL_MODE 0x00 +#define IR36021_AMD_MODE 0x20 /* step the IR regulator in 5mV increments */ #define IR_VDD_STEP_DOWN 5 diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c index fac442b..99a8730 100644 --- a/board/freescale/t4rdb/t4240rdb.c +++ b/board/freescale/t4rdb/t4240rdb.c @@ -21,6 +21,7 @@ #include "t4rdb.h" #include "cpld.h" +#include "../common/vid.h" DECLARE_GLOBAL_DATA_PTR; @@ -79,6 +80,12 @@ int board_early_init_r(void) #ifdef CONFIG_SYS_DPAA_QBMAN setup_portals(); #endif + /* + * Adjust core voltage according to voltage ID + * This function changes I2C mux to channel 2. + */ + if (adjust_vdd(0)) + printf("Warning: Adjusting core voltage failed.\n"); return 0; } diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 73279c8..4a17f41 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -606,6 +606,16 @@ unsigned long get_board_ddr_clk(void); #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 +#define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_VID +#endif +#define CONFIG_VOL_MONITOR_IR36021_SET +#define CONFIG_VOL_MONITOR_IR36021_READ +/* The lowest and highest voltage allowed for T4240RDB */ +#define VDD_MV_MIN 819 +#define VDD_MV_MAX 1212 + /* * eSPI - Enhanced SPI */ -- 1.8.4.1

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[U-Boot] [PATCH] ARMv8:ls2-2080a: Implement core ERRATA 829520, 833471
by Ashish Kumar 21 Jan '16

21 Jan '16

* 829520: Code bounded by indirect conditional branch might corrupt instruction stream, Workaround: Set CPUACTLR_EL1[4] = 1'b1 to disable the Indirect Predictor * 833471: VMSR FPSCR functional failure or deadlock Workaround: Set CPUACTLR[38] to 1, which forces FPSCR write flush Signed-off-by: Ashish Kumar <Ashish.Kumar(a)freescale.com> --- arch/arm/cpu/armv8/start.S | 20 ++++++++++++++++++++ include/configs/ls2080a_common.h | 2 ++ 2 files changed, 22 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index da45d98..dd583c9 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -132,6 +132,26 @@ apply_a57_core_errata: msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ #endif +#ifdef CONFIG_ARM_ERRATA_833471 + mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ + /* FPSCR write flush. + * Note that in some cases where a flush is unnecessary this + could impact performance. */ + orr x0, x0, #1 << 38 + msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ +#endif + +#ifdef CONFIG_ARM_ERRATA_829520 + mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ + /* Disable Indirect Predictor bit will prevent this erratum + from occurring + * Note that in some cases where a flush is unnecessary this + could impact performance. */ + orr x0, x0, #1 << 4 + msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ +#endif + + #ifdef CONFIG_ARM_ERRATA_833069 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ /* Disable Enable Invalidates of BTB bit */ diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index a503934..9ab5d97 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -18,6 +18,8 @@ /* Errata fixes */ #define CONFIG_ARM_ERRATA_828024 #define CONFIG_ARM_ERRATA_826974 +#define CONFIG_ARM_ERRATA_833471 +#define CONFIG_ARM_ERRATA_829520 #include <asm/arch/ls2080a_stream_id.h> #include <asm/arch/config.h> -- 1.7.6.GIT

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