January 2016 - U-Boot

[U-Boot] [Patch V5 1/4] spi: fsl_qspi: fix compile warning for 64-bit platform
by Gong Qianyu 26 Jan '16

26 Jan '16

From: Gong Qianyu <Qianyu.Gong(a)freescale.com> This patch fixes the following compile warning: drivers/spi/fsl_qspi.c: In function 'fsl_qspi_probe': drivers/spi/fsl_qspi.c:937:15: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] priv->regs = (struct fsl_qspi_regs *)plat->reg_base; ^ Just make the cast explicit. Signed-off-by: Gong Qianyu <Qianyu.Gong(a)freescale.com> --- V5: - Use uintptr_t instead of unsigned long. V4: - Revise the commit message. V2-V3: - No change. drivers/spi/fsl_qspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 542b6cf..38e5900 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -936,7 +936,7 @@ static int fsl_qspi_probe(struct udevice *bus) dm_spi_bus->max_hz = plat->speed_hz; - priv->regs = (struct fsl_qspi_regs *)plat->reg_base; + priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base; priv->flags = plat->flags; priv->speed_hz = plat->speed_hz; -- 2.1.0.27.g96db324

5 14

[U-Boot] [PATCH] video: add CONFIG_I2C_EDID and disable CONFIG_DISPLAY by default
by Anatolij Gustschin 26 Jan '16

26 Jan '16

Enabling CONFIG_DISPLAY breaks building for some architectures (microblaze-generic), so we disable CONFIG_DISPLAY in Kconfig by default and enable this option in defconfigs. CONFIG_DISPLAY depends on CONFIG_I2C_EDID, so add and enable it in defconfigs, too. Signed-off-by: Anatolij Gustschin <agust(a)denx.de> Reported-by: Bin Meng <bmeng.cn(a)gmail.com> Cc: Simon Glass <sjg(a)chromium.org> --- configs/chromebook_jerry_defconfig | 2 ++ configs/firefly-rk3288_defconfig | 2 ++ configs/nyan-big_defconfig | 1 + configs/rock2_defconfig | 2 ++ drivers/video/Kconfig | 10 +++++++++- include/configs/chromebook_jerry.h | 1 - include/configs/firefly-rk3288.h | 1 - include/configs/nyan-big.h | 2 -- include/configs/rock2.h | 1 - 9 files changed, 16 insertions(+), 6 deletions(-) diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 27e53c1..bd8b964 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -55,6 +55,8 @@ CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_ROCKCHIP_SPI=y CONFIG_DM_VIDEO=y +CONFIG_I2C_EDID=y +CONFIG_DISPLAY=y CONFIG_VIDEO_ROTATION=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 15eb4d8..3b29158 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -47,6 +47,8 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_DM_VIDEO=y +CONFIG_I2C_EDID=y +CONFIG_DISPLAY=y CONFIG_VIDEO_ROTATION=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig index 03348a6..ca0f9e0 100644 --- a/configs/nyan-big_defconfig +++ b/configs/nyan-big_defconfig @@ -26,6 +26,7 @@ CONFIG_TPM_TIS_INFINEON=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_DISPLAY=y +CONFIG_I2C_EDID=y CONFIG_VIDEO_TEGRA124=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_TPM=y diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index 2563775..68e3b36 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -45,6 +45,8 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_DM_VIDEO=y +CONFIG_I2C_EDID=y +CONFIG_DISPLAY=y CONFIG_VIDEO_ROTATION=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 912e397..3fd781b 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -293,10 +293,18 @@ config VIDEO_LCD_SPI_MISO option takes a string in the format understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H. +config I2C_EDID + bool "Enable EDID library" + depends on DM_I2C + default n + help + This enables library for accessing EDID data from an LCD panel. + config DISPLAY bool "Enable Display support" depends on DM - default y + default n + select I2C_EDID help This supports drivers that provide a display, such as eDP (Embedded DisplayPort) and HDMI (High Definition Multimedia Interface). diff --git a/include/configs/chromebook_jerry.h b/include/configs/chromebook_jerry.h index 150e876..67f45c0 100644 --- a/include/configs/chromebook_jerry.h +++ b/include/configs/chromebook_jerry.h @@ -30,7 +30,6 @@ #define CONFIG_SPL_POWER_SUPPORT #define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_I2C_EDID #define CONFIG_SYS_WHITE_ON_BLACK #define CONFIG_CONSOLE_SCROLL_LINES 10 diff --git a/include/configs/firefly-rk3288.h b/include/configs/firefly-rk3288.h index d6423e7..a29f557 100644 --- a/include/configs/firefly-rk3288.h +++ b/include/configs/firefly-rk3288.h @@ -24,7 +24,6 @@ */ #define CONFIG_ENV_OFFSET (96 * 1024) -#define CONFIG_I2C_EDID #define CONFIG_SYS_WHITE_ON_BLACK #define CONFIG_CONSOLE_SCROLL_LINES 10 diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h index 9464153..176f6e9 100644 --- a/include/configs/nyan-big.h +++ b/include/configs/nyan-big.h @@ -37,8 +37,6 @@ #define CONFIG_SYS_MMC_ENV_PART 2 #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) -#define CONFIG_I2C_EDID - /* LCD support */ #define CONFIG_LCD #define CONFIG_PWM_TEGRA diff --git a/include/configs/rock2.h b/include/configs/rock2.h index d6423e7..a29f557 100644 --- a/include/configs/rock2.h +++ b/include/configs/rock2.h @@ -24,7 +24,6 @@ */ #define CONFIG_ENV_OFFSET (96 * 1024) -#define CONFIG_I2C_EDID #define CONFIG_SYS_WHITE_ON_BLACK #define CONFIG_CONSOLE_SCROLL_LINES 10 -- 1.9.1

4 4

[U-Boot] [PATCH v3 0/4] add support for loading ACPI tables from QEMU
by Miao Yan 26 Jan '16

26 Jan '16

Currently, if CONFIG_GENERATE_ACPI_TABLE is defined, U-Boot will generate ACPI tables itlself, this patchset adds the ability to load the ACPI tables generated by QEMU. Changes in v3: - fix a build error in patch 3/4 - re-order patch 3/4 and patch 4/4 in v2 Changes in v2: - Drop [PATCH 4/4] x86: qemu: loading ACPI table from QEMU, add a config option CONFIG_QEMU_ACPI_TABLE - various cleanups Miao Yan (4): x86: qemu: re-structure qemu_fwcfg_list_firmware() x86: qemu: setup PM IO base for ACPI in southbridge x86: qemu: add the ability to load and link ACPI tables from QEMU x86: config option for loading ACPI table from QEMU arch/x86/Kconfig | 9 + arch/x86/cpu/qemu/Kconfig | 7 + arch/x86/cpu/qemu/Makefile | 2 + arch/x86/cpu/qemu/fw_cfg.c | 316 ++++++++++++++++++++++++++++++-- arch/x86/cpu/qemu/qemu.c | 29 +++ arch/x86/include/asm/arch-qemu/device.h | 2 + arch/x86/include/asm/arch-qemu/qemu.h | 5 + arch/x86/include/asm/fw_cfg.h | 70 ++++++- arch/x86/lib/Makefile | 2 + arch/x86/lib/acpi_table.c | 4 + 10 files changed, 429 insertions(+), 17 deletions(-) -- 1.9.1

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[U-Boot] [PATCH 1/2 v2] misc: Add simple driver to enable the legacy UART on Winbond Super IO chips
by Stefan Roese 26 Jan '16

26 Jan '16

On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8) are provided by a superio chip connected to the LPC bus. We must program the superio chip so that serial ports are available for us. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Bin Meng <bmeng.cn(a)gmail.com> Cc: Simon Glass <sjg(a)chromium.org> --- v2: - Address Bin's comments: - Make description more generic, so that other functions of this Winbond super IO chip may be integrated - Lowercase hex value - Minor changes to the comments drivers/misc/Kconfig | 8 ++++++++ drivers/misc/Makefile | 1 + drivers/misc/winbond_w83627.c | 41 +++++++++++++++++++++++++++++++++++++++++ include/winbond_w83627.h | 35 +++++++++++++++++++++++++++++++++++ 4 files changed, 85 insertions(+) create mode 100644 drivers/misc/winbond_w83627.c create mode 100644 include/winbond_w83627.h diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index b92da4e..dfd804f 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -112,4 +112,12 @@ config RESET effect a reset. The uclass will try all available drivers when reset_walk() is called. +config WINBOND_W83627 + bool "Enable Winbond Super I/O driver" + help + If you say Y here, you will get support for the Winbond + W83627 Super I/O driver. This can be used to enable the + legacy UART or other devices in the Winbond Super IO chips + on X86 platforms. + endmenu diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index aa137f5..15505bf 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -38,3 +38,4 @@ obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o obj-$(CONFIG_PCA9551_LED) += pca9551_led.o obj-$(CONFIG_RESET) += reset-uclass.o obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o +obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o diff --git a/drivers/misc/winbond_w83627.c b/drivers/misc/winbond_w83627.c new file mode 100644 index 0000000..59db7d9 --- /dev/null +++ b/drivers/misc/winbond_w83627.c @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2016 Stefan Roese <sr(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/pnp_def.h> + +#define WINBOND_ENTRY_KEY 0x87 +#define WINBOND_EXIT_KEY 0xaa + +/* Enable configuration: pass entry key '0x87' into index port dev twice */ +static void pnp_enter_conf_state(u16 dev) +{ + u16 port = dev >> 8; + + outb(WINBOND_ENTRY_KEY, port); + outb(WINBOND_ENTRY_KEY, port); +} + +/* Disable configuration: pass exit key '0xAA' into index port dev */ +static void pnp_exit_conf_state(u16 dev) +{ + u16 port = dev >> 8; + + outb(WINBOND_EXIT_KEY, port); +} + +/* Bring up early serial debugging output before the RAM is initialized */ +void winbond_enable_serial(uint dev, uint iobase, uint irq) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_irq(dev, PNP_IDX_IRQ0, irq); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/include/winbond_w83627.h b/include/winbond_w83627.h new file mode 100644 index 0000000..ac3bec6 --- /dev/null +++ b/include/winbond_w83627.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2016 Stefan Roese <sr(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _WINBOND_W83627_H_ +#define _WINBOND_W83627_H_ + +/* I/O address of Winbond Super IO chip */ +#define WINBOND_IO_PORT 0x2e + +/* Logical device number */ +#define W83627DHG_FDC 0 /* Floppy */ +#define W83627DHG_PP 1 /* Parallel port */ +#define W83627DHG_SP1 2 /* Com1 */ +#define W83627DHG_SP2 3 /* Com2 */ +#define W83627DHG_KBC 5 /* PS/2 keyboard & mouse */ +#define W83627DHG_SPI 6 /* Serial peripheral interface */ +#define W83627DHG_WDTO_PLED 8 /* WDTO#, PLED */ +#define W83627DHG_ACPI 10 /* ACPI */ +#define W83627DHG_HWM 11 /* Hardware monitor */ +#define W83627DHG_PECI_SST 12 /* PECI, SST */ + +/** + * Configure the base I/O port of the specified serial device and enable the + * serial device. + * + * @dev: high 8 bits = super I/O port, low 8 bits = logical device number + * @iobase: processor I/O port address to assign to this serial device + * @irq: processor IRQ number to assign to this serial device + */ +void winbond_enable_serial(uint dev, uint iobase, uint irq); + +#endif /* _WINBOND_W83627_H_ */ -- 2.6.5

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[U-Boot] [PATCH] x86: baytrail: Add documentation for FSP memory-down values
by Stefan Roese 26 Jan '16

26 Jan '16

This patch adds the documentation for the memory-down parameters of the Intel FSP. To configure a board without SPD DDR DIMM but with onboard DDR chips. The values are taken from the coreboot header: src/soc/intel/fsp_baytrail/chip.h (git ID da1a70ea from 2016-01-16 as reference). Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Andrew Bradford <andrew.bradford(a)kodakalaris.com> Cc: Bin Meng <bmeng.cn(a)gmail.com> Cc: Simon Glass <sjg(a)chromium.org> --- .../misc/intel,baytrail-fsp.txt | 31 +++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt b/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt index b44b5b5..07fa46e 100644 --- a/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt +++ b/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt @@ -74,12 +74,41 @@ discovered by the FSP and used to setup main memory. # Integer properties: - - fsp,dram-speed + - fsp,dram-speed: + 0x0: "800 MHz" + 0x1: "1066 MHz" + 0x2: "1333 MHz" + 0x3: "1600 MHz" + - fsp,dram-type + 0x0: "DDR3" + 0x1: "DDR3L" + 0x2: "DDR3U" + 0x4: "LPDDR2" + 0x5: "LPDDR3" + 0x6: "DDR4" + - fsp,dimm-width + 0x0: "x8" + 0x1: "x16" + 0x2: "x32" + - fsp,dimm-density + 0x0: "1 Gbit" + 0x1: "2 Gbit" + 0x2: "4 Gbit" + 0x3: "8 Gbit" + - fsp,dimm-bus-width + 0x0: "8 bits" + 0x1: "16 bits" + 0x2: "32 bits" + 0x3: "64 bits" + - fsp,dimm-sides + 0x0: "1 rank" + 0x1: "2 ranks" + - fsp,dimm-tcl - fsp,dimm-trpt-rcd - fsp,dimm-twr -- 2.6.5

2 2

[U-Boot] [PATCH v7 0/7] add support for atheros ath79 based SOCs
by Wills Wang 26 Jan '16

26 Jan '16

These series of patch add support for atheros ath79 based SOCs in u-boot, at the present moment it's just available for ar933x and qca953x chip. This patch serises is based on mips_io_v4 branch on u-boot-mips repository [1] and tested on ar933x and qca953x board. [1] http://git.denx.de/?p=u-boot/u-boot-mips.git;a=shortlog;h=refs/heads/mips_i… Changes in v7: - Use setbits_32 - Fix include path for SoC specific headers - Use CKSEGxADDR instead of KSEGxADDR for ar933x - Use CKSEGxADDR instead of KSEGxADDR for qca953x - remove map_physmem for debug port - Define spi_cs_activate/spi_cs_deactivate - Rename MHZ to ATH79_SPI_MHZ - Use clrsetbits_32 - Use KSEG1 address for debug port in ap121 - Use KSEG1 address for debug port in ap143 Changes in v6: - Move ar933x as separate patch - Add get_bootstrap in reset.c - Use map_physmem instead of KSEG1ADDR - Add arch_cpu_init for detect SOC type for early - Remove board.c - Define magic value in ddr.c - Remove wait loop in putc and getc - Use map_physmem instead of KSEG1ADDR - Add rrw_delay in ath79_spi_priv for more accurate timing - Remove ath79_spi_delay - Calculate delay in ath79_spi_set_speed - Convert SZ_XXX into hex in ap121.h - Remove useless CONFIG_SYS_INIT_SP_OFFSET in ap121.h - Add board_early_init_f for DDR and pin initialization - Select UART and SPI in ap121_defconfig Changes in v5: - Add independent Kconfig - Use SRAM for initial stack - Move DDR initialization into board_early_init_f - Convert DDR tap tunning code to C - Save SOC's version into arch_global_data - remove ar933x_serial_platdata - Import document "qca,ar9330-uart.txt" from kernel - Add support for debug UART - remove ar933x_spi_platdata - Import document "spi-ath79.txt" from kernel - Add delay for bitbang operation - Move CONFIG_SYS_TEXT_BASE into ap121.h, and remove config.mk - Remove useless README file - Remove useless checkboard function Changes in v4: - Use global_data to save CPU/DDR/AHB clock - Use arch_global_data to save SOC's type, revison and id - Auto calculate baudrate for serial driver - Move pinctrl code in serial driver into arch/mips/mach-ath79 - Use get_serial_clock to serial clock source - Use get_bus_freq instead of hardcode in SPI driver Changes in v3: - Move SoC specific header files into arch/mips/mach-ath79/include/mach - Optimize assembly code - Same code style convertion - Convert serial driver to driver model - Convert spi driver to driver model - Add support for device tree Changes in v2: - Move all SoC specific header files into arch/mips/include/asm/arch-ath79 - Check SOC type and extract common code into arch/mips/mach-ath79 - Move serial driver code into drivers/serial - Add a compatible spi driver - Add a reference board implemention Wills Wang (7): mips: add base support for QCA/Atheros ath79 SOCs mips: ath79: add support for AR933x SOCs mips: ath79: add support for QCA953x SOCs mips: ath79: add serial driver for ar933x SOC mips: ath79: add spi driver mips: ath79: add AP121 reference board mips: ath79: add AP143 reference board arch/mips/Kconfig | 6 + arch/mips/Makefile | 1 + arch/mips/dts/Makefile | 3 +- arch/mips/dts/ap121.dts | 43 + arch/mips/dts/ap143.dts | 43 + arch/mips/dts/ar933x.dtsi | 70 ++ arch/mips/dts/qca953x.dtsi | 72 ++ arch/mips/include/asm/global_data.h | 6 + arch/mips/mach-ath79/Kconfig | 46 + arch/mips/mach-ath79/Makefile | 10 + arch/mips/mach-ath79/ar933x/Makefile | 7 + arch/mips/mach-ath79/ar933x/clk.c | 89 ++ arch/mips/mach-ath79/ar933x/ddr.c | 316 ++++++ arch/mips/mach-ath79/ar933x/lowlevel_init.S | 279 +++++ arch/mips/mach-ath79/cpu.c | 203 ++++ arch/mips/mach-ath79/dram.c | 16 + arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 1187 ++++++++++++++++++++ arch/mips/mach-ath79/include/mach/ath79.h | 143 +++ arch/mips/mach-ath79/include/mach/ddr.h | 13 + arch/mips/mach-ath79/include/mach/reset.h | 14 + arch/mips/mach-ath79/qca953x/Makefile | 7 + arch/mips/mach-ath79/qca953x/clk.c | 111 ++ arch/mips/mach-ath79/qca953x/ddr.c | 462 ++++++++ arch/mips/mach-ath79/qca953x/lowlevel_init.S | 185 +++ arch/mips/mach-ath79/reset.c | 71 ++ board/ath79/ap121/Kconfig | 9 + board/ath79/ap121/MAINTAINERS | 6 + board/ath79/ap121/Makefile | 5 + board/ath79/ap121/ap121.c | 47 + board/ath79/ap143/Kconfig | 9 + board/ath79/ap143/MAINTAINERS | 6 + board/ath79/ap143/Makefile | 5 + board/ath79/ap143/ap143.c | 63 ++ configs/ap121_defconfig | 42 + configs/ap143_defconfig | 43 + .../serial/qca,ar9330-uart.txt | 24 + doc/device-tree-bindings/spi/spi-ath79.txt | 19 + drivers/serial/Kconfig | 17 + drivers/serial/Makefile | 1 + drivers/serial/serial_ar933x.c | 254 +++++ drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/ath79_spi.c | 237 ++++ include/configs/ap121.h | 87 ++ include/configs/ap143.h | 91 ++ 45 files changed, 4376 insertions(+), 1 deletion(-) create mode 100644 arch/mips/dts/ap121.dts create mode 100644 arch/mips/dts/ap143.dts create mode 100644 arch/mips/dts/ar933x.dtsi create mode 100644 arch/mips/dts/qca953x.dtsi create mode 100644 arch/mips/mach-ath79/Kconfig create mode 100644 arch/mips/mach-ath79/Makefile create mode 100644 arch/mips/mach-ath79/ar933x/Makefile create mode 100644 arch/mips/mach-ath79/ar933x/clk.c create mode 100644 arch/mips/mach-ath79/ar933x/ddr.c create mode 100644 arch/mips/mach-ath79/ar933x/lowlevel_init.S create mode 100644 arch/mips/mach-ath79/cpu.c create mode 100644 arch/mips/mach-ath79/dram.c create mode 100644 arch/mips/mach-ath79/include/mach/ar71xx_regs.h create mode 100644 arch/mips/mach-ath79/include/mach/ath79.h create mode 100644 arch/mips/mach-ath79/include/mach/ddr.h create mode 100644 arch/mips/mach-ath79/include/mach/reset.h create mode 100644 arch/mips/mach-ath79/qca953x/Makefile create mode 100644 arch/mips/mach-ath79/qca953x/clk.c create mode 100644 arch/mips/mach-ath79/qca953x/ddr.c create mode 100644 arch/mips/mach-ath79/qca953x/lowlevel_init.S create mode 100644 arch/mips/mach-ath79/reset.c create mode 100644 board/ath79/ap121/Kconfig create mode 100644 board/ath79/ap121/MAINTAINERS create mode 100644 board/ath79/ap121/Makefile create mode 100644 board/ath79/ap121/ap121.c create mode 100644 board/ath79/ap143/Kconfig create mode 100644 board/ath79/ap143/MAINTAINERS create mode 100644 board/ath79/ap143/Makefile create mode 100644 board/ath79/ap143/ap143.c create mode 100644 configs/ap121_defconfig create mode 100644 configs/ap143_defconfig create mode 100644 doc/device-tree-bindings/serial/qca,ar9330-uart.txt create mode 100644 doc/device-tree-bindings/spi/spi-ath79.txt create mode 100644 drivers/serial/serial_ar933x.c create mode 100644 drivers/spi/ath79_spi.c create mode 100644 include/configs/ap121.h create mode 100644 include/configs/ap143.h -- 1.9.1

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[U-Boot] [PATCH v2 1/3] QE: mask the codes not used for micro QE
by Zhao Qiang 26 Jan '16

26 Jan '16

use "#ifdef CONFIG_QE" to mask the codes not used for micro QE Signed-off-by: Zhao Qiang <qiang.zhao(a)nxp.com> --- Changes for v2: - this patch is new added to this patchset drivers/qe/qe.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 08620b2..2a9e61b 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -20,7 +20,9 @@ #define MPC85xx_DEVDISR_QE_DISABLE 0x1 qe_map_t *qe_immr = NULL; +#ifdef CONFIG_QE static qe_snum_t snums[QE_NUM_OF_SNUM]; +#endif DECLARE_GLOBAL_DATA_PTR; @@ -81,6 +83,7 @@ void *qe_muram_addr(uint offset) return (void *)&qe_immr->muram[offset]; } +#ifdef CONFIG_QE static void qe_sdma_init(void) { volatile sdma_t *p; @@ -184,6 +187,7 @@ void qe_init(uint qe_base) qe_sdma_init(); qe_snums_init(); } +#endif #ifdef CONFIG_U_QE void u_qe_init(void) @@ -214,6 +218,7 @@ void qe_reset(void) (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0); } +#ifdef CONFIG_QE void qe_assign_page(uint snum, uint para_ram_base) { u32 cecr; @@ -229,6 +234,7 @@ void qe_assign_page(uint snum, uint para_ram_base) return; } +#endif /* * brg: 0~15 as BRG1~BRG16 -- 2.1.0.27.g96db324

3 4

[U-Boot] unable to enumerate USB device on port 2
by Felix Zheng 26 Jan '16

26 Jan '16

Hi guys, I was using a combination of Gumstix overo and TOBI board. A USB HUB with external power was connected to the TOBI, so I can use mouse and keyboard at the same time. After I updated the uboot (MLO and u-boot.img) recently, the USB port stopped working. During the boot, I captured some information like this : Waiting for root device /dev/mmcblk0p2... hub 2-0:1.0: unable to enumerate USB device on port 2 After the boot process, I can use SSH from another machine to log in. The following is the dmesg results. $ dmesg |grep hub usbcore: registered new interface driver hub hub 1-0:1.0: usb_probe_interface hub 1-0:1.0: usb_probe_interface - got id hub 1-0:1.0: USB hub found hub 1-0:1.0: 1 port detected hub 1-0:1.0: standalone hub hub 1-0:1.0: individual port power switching hub 1-0:1.0: no over-current protection hub 1-0:1.0: Single TT hub 1-0:1.0: TT requires at most 8 FS bit times (666 ns) hub 1-0:1.0: power on to power good time: 10ms hub 1-0:1.0: 100mA bus power budget for each child hub 1-0:1.0: local power source is good hub 1-0:1.0: enabling power on all ports hub 1-0:1.0: state 7 ports 1 chg 0000 evt 0000 hub 2-0:1.0: usb_probe_interface hub 2-0:1.0: usb_probe_interface - got id hub 2-0:1.0: USB hub found hub 2-0:1.0: 3 ports detected hub 2-0:1.0: standalone hub hub 2-0:1.0: individual port power switching hub 2-0:1.0: individual port over-current protection hub 2-0:1.0: power on to power good time: 20ms hub 2-0:1.0: local power source is good hub 2-0:1.0: enabling power on all ports hub 2-0:1.0: port 2: status 0501 change 0001 hub 2-0:1.0: state 7 ports 3 chg 0004 evt 0000 hub 2-0:1.0: port 2, status 0501, change 0000, 480 Mb/s hub 2-0:1.0: port 2 not reset yet, waiting 50ms hub 2-0:1.0: unable to enumerate USB device on port 2 hub 2-0:1.0: state 7 ports 3 chg 0000 evt 0004 It is obvious that this is not a hardware problem, because all I changed are just from old MLO, u-boot.bin to new MLO and u-boot.img. The same type of 16GB SD cards were used here. I have already changed the mmcrootfstype type back to ext3 so it can boot. I have checked several previous posts, but they were just facing hardware problems or bugs between different linux kernels. So does anybody know, is there any other setting I need to fix when I update the two uboot files? Thanks for your help, Felix

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[U-Boot] [PATCH] pci: restore initialization for DM_PCI
by Stephen Warren 26 Jan '16

26 Jan '16

From: Stephen Warren <swarren(a)nvidia.com> PCI controllers should be enumerated at startup so that PCI devices such as Ethernet controllers are available at startup. Fix board_init_r() not to skip calling pci_init() when CONFIG_DM_PCI is defined, and provide an implementation of pci_init() for the DM case. Fixes: 96350f729c42 ("dm: tegra: net: Convert tegra boards to driver model for Ethernet") Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- I'm not sure if relying on the side-effects of calling uclass_{first,ext}_device is the correct approach; is there a more explicit way to probe all PCI controllers? Arguably, perhaps we should introduce a "pci start" command instead of this change to be consistent with e.g. USB. However, that would be a regression relative to earlier versions of U-Boot. --- common/board_r.c | 2 -- drivers/pci/pci-uclass.c | 15 +++++++++++++++ 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/common/board_r.c b/common/board_r.c index 75ee43e2d76e..e5029aff1e96 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -249,9 +249,7 @@ static int initr_unlock_ram_in_cache(void) #ifdef CONFIG_PCI static int initr_pci(void) { -#ifndef CONFIG_DM_PCI pci_init(); -#endif return 0; } diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 685df9d274e4..f51f08289d66 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -1247,3 +1247,18 @@ U_BOOT_DRIVER(pci_generic_drv) = { .id = UCLASS_PCI_GENERIC, .of_match = pci_generic_ids, }; + +void pci_init(void) +{ + struct udevice *bus; + + /* + * Enumerate all known controller devices. Enumeration has the side- + * effect of probing them, so PCIe devices will be enumerated too. + */ + for (uclass_first_device(UCLASS_PCI, &bus); + bus; + uclass_next_device(&bus)) { + ; + } +} -- 2.7.0

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[U-Boot] [PATCH REPOST] checkpatch: ignore request to use ether_addr_copy()
by Stephen Warren 25 Jan '16

25 Jan '16

From: Stephen Warren <swarren(a)nvidia.com> The Linux kernel, from which checkpatch originates, contains function ether_addr_copy() to copy Ethernet MAC addresses, and checkpatch warns that it should be used in preference to memcpy() where appropriate. U-Boot doesn't contain ether_addr_copy(), so tell checkpatch not to issue this warning. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> Reviewed-by: Marek Vasut <marex(a)denx.de> Acked-by: Joe Hershberger <joe.hershberger(a)ni.com> --- .checkpatch.conf | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/.checkpatch.conf b/.checkpatch.conf index 35167e12015b..d1d32fac9db5 100644 --- a/.checkpatch.conf +++ b/.checkpatch.conf @@ -21,3 +21,7 @@ # Ignore networking block comment style --ignore NETWORKING_BLOCK_COMMENT_STYLE + +# Ignore "WARNING: Prefer ether_addr_copy() over memcpy() if the Ethernet +# addresses are __aligned(2)". +--ignore PREFER_ETHER_ADDR_COPY -- 2.7.0

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