January 2016 - U-Boot

[U-Boot] [PATCH][v2] armv8: fsl-layerscape: fixes lsch2 serdes registers define
by shh.xie＠gmail.com 27 Jan '16

27 Jan '16

From: Shaohui Xie <Shaohui.Xie(a)freescale.com> Fixes lsch2 SerDes registers define according to LS1043A RM Rev D. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- changes in v2: 1. fixes indent. .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 67 +++++++++++++++------- 1 file changed, 47 insertions(+), 20 deletions(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 83caa91..b794982 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -450,7 +450,8 @@ struct ccsr_serdes { u32 res_0c; /* 0x00c */ u32 pllcr3; u32 pllcr4; - u8 res_18[0x20-0x18]; + u32 pllcr5; /* 0x018 SerDes PLL1 Control 5 */ + u8 res_1c[0x20-0x1c]; } bank[2]; u8 res_40[0x90-0x40]; u32 srdstcalcr; /* 0x90 TX Calibration Control */ @@ -458,25 +459,25 @@ struct ccsr_serdes { u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ u8 res_a4[0xb0-0xa4]; u32 srdsgr0; /* 0xb0 General Register 0 */ - u8 res_b4[0xe0-0xb4]; - u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */ - u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */ - u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */ - u32 srdspccr3; /* 0xec Protocol Converter Config 3 */ - u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */ - u8 res_f4[0x100-0xf4]; + u8 res_b4[0x100-0xb4]; struct { - u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */ + u32 lnpssr0; /* 0x100, 0x120, 0x140, 0x160 */ u8 res_104[0x120-0x104]; - } srdslnpssr[4]; - u8 res_180[0x300-0x180]; - u32 srdspexeqcr; - u32 srdspexeqpcr[11]; - u8 res_330[0x400-0x330]; - u32 srdspexapcr; - u8 res_404[0x440-0x404]; - u32 srdspexbpcr; - u8 res_444[0x800-0x444]; + } lnpssr[4]; /* Lane A, B, C, D */ + u8 res_180[0x200-0x180]; + u32 srdspccr0; /* 0x200 Protocol Configuration 0 */ + u32 srdspccr1; /* 0x204 Protocol Configuration 1 */ + u32 srdspccr2; /* 0x208 Protocol Configuration 2 */ + u32 srdspccr3; /* 0x20c Protocol Configuration 3 */ + u32 srdspccr4; /* 0x210 Protocol Configuration 4 */ + u32 srdspccr5; /* 0x214 Protocol Configuration 5 */ + u32 srdspccr6; /* 0x218 Protocol Configuration 6 */ + u32 srdspccr7; /* 0x21c Protocol Configuration 7 */ + u32 srdspccr8; /* 0x220 Protocol Configuration 8 */ + u32 srdspccr9; /* 0x224 Protocol Configuration 9 */ + u32 srdspccra; /* 0x228 Protocol Configuration A */ + u32 srdspccrb; /* 0x22c Protocol Configuration B */ + u8 res_230[0x800-0x230]; struct { u32 gcr0; /* 0x800 General Control Register 0 */ u32 gcr1; /* 0x804 General Control Register 1 */ @@ -489,8 +490,34 @@ struct ccsr_serdes { u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ u8 res_824[0x83c-0x824]; u32 tcsr3; - } lane[4]; /* Lane A, B, C, D, E, F, G, H */ - u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */ + } lane[4]; /* Lane A, B, C, D */ + u8 res_900[0x1000-0x900]; /* from 0x900 to 0xfff */ + struct { + u32 srdspexcr0; /* 0x1000, 0x1040, 0x1080 */ + u8 res_1004[0x1040-0x1004]; + } pcie[3]; + u8 res_10c0[0x1800-0x10c0]; + struct { + u8 res_1800[0x1804-0x1800]; + u32 srdssgmiicr1; /* 0x1804 SGMII Protocol Control 1 */ + u8 res_1808[0x180c-0x1808]; + u32 srdssgmiicr3; /* 0x180c SGMII Protocol Control 3 */ + } sgmii[4]; /* Lane A, B, C, D */ + u8 res_1840[0x1880-0x1840]; + struct { + u8 res_1880[0x1884-0x1880]; + u32 srdsqsgmiicr1; /* 0x1884 QSGMII Protocol Control 1 */ + u8 res_1888[0x188c-0x1888]; + u32 srdsqsgmiicr3; /* 0x188c QSGMII Protocol Control 3 */ + } qsgmii[2]; /* Lane A, B */ + u8 res_18a0[0x1980-0x18a0]; + struct { + u8 res_1980[0x1984-0x1980]; + u32 srdsxficr1; /* 0x1984 XFI Protocol Control 1 */ + u8 res_1988[0x198c-0x1988]; + u32 srdsxficr3; /* 0x198c XFI Protocol Control 3 */ + } xfi[2]; /* Lane A, B */ + u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */ }; #define CCI400_CTRLORD_TERM_BARRIER 0x00000008 -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] arm: ls1021a: Adjust sata register default values
by Yuantian.Tang＠freescale.com 27 Jan '16

27 Jan '16

From: Tang Yuantian <Yuantian.Tang(a)freescale.com> Updated the default sata register values to enhance the performance and stability. Signed-off-by: Tang Yuantian <Yuantian.Tang(a)freescale.com> --- arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c index deeb674..144f2c3 100644 --- a/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c @@ -11,11 +11,11 @@ /* port register default value */ #define AHCI_PORT_PHY_1_CFG 0xa003fffe -#define AHCI_PORT_PHY_2_CFG 0x28183411 -#define AHCI_PORT_PHY_3_CFG 0x0e081004 -#define AHCI_PORT_PHY_4_CFG 0x00480811 -#define AHCI_PORT_PHY_5_CFG 0x192c96a4 -#define AHCI_PORT_TRANS_CFG 0x08000025 +#define AHCI_PORT_PHY_2_CFG 0x28183414 +#define AHCI_PORT_PHY_3_CFG 0x0e080e06 +#define AHCI_PORT_PHY_4_CFG 0x064a080b +#define AHCI_PORT_PHY_5_CFG 0x2aa86470 +#define AHCI_PORT_TRANS_CFG 0x08000029 #define SATA_ECC_REG_ADDR 0x20220520 #define SATA_ECC_DISABLE 0x00020000 -- 2.1.0.27.g96db324

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[U-Boot] [PATCH v2] driver/ddr/fsl: Add workaround for A009663
by Shengzhou Liu 27 Jan '16

27 Jan '16

Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0 before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE] to the desired value after DDR initialization has completed. When DDR controller is configured to operate in auto-precharge mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> --- v2: add more comments. arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 +++ arch/arm/include/asm/arch-ls102xa/config.h | 1 + arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++ arch/powerpc/include/asm/config_mpc85xx.h | 2 ++ drivers/ddr/fsl/fsl_ddr_gen4.c | 10 ++++++++++ include/fsl_ddr_sdram.h | 1 + 6 files changed, 20 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 6e5224e..fac82ff 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -118,6 +118,8 @@ #define CONFIG_SYS_FSL_ERRATUM_A008585 #define CONFIG_SYS_FSL_ERRATUM_A008751 #define CONFIG_SYS_FSL_ERRATUM_A009635 +#define CONFIG_SYS_FSL_ERRATUM_A009663 + #elif defined(CONFIG_LS1043A) #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_CACHELINE_SIZE 64 @@ -165,6 +167,7 @@ /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 +#define CONFIG_SYS_FSL_ERRATUM_A009663 #else #error SoC not defined diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index f066480..424fe87 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -131,6 +131,7 @@ #define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_ERRATUM_A008378 +#define CONFIG_SYS_FSL_ERRATUM_A009663 #else #error SoC not defined #endif diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index a493556..3b06ae4 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -326,6 +326,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_SYS_FSL_B4860QDS_XFI_ERR) && defined(CONFIG_B4860QDS) puts("Work-around for Erratum XFI on B4860QDS enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A009663 + puts("Work-around for Erratum A009663 enabled\n"); +#endif return 0; } diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 674fac8..eccc146 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -808,6 +808,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define QE_NUM_OF_SNUM 28 #define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_ERRATUM_A008378 +#define CONFIG_SYS_FSL_ERRATUM_A009663 #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) @@ -856,6 +857,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define QE_NUM_OF_SNUM 28 #define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_ERRATUM_A008378 +#define CONFIG_SYS_FSL_ERRATUM_A009663 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #define CONFIG_E6500 diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 3fca5c2..6bd447d 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -151,7 +151,12 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15); ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16); ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); +#ifdef CONFIG_SYS_FSL_ERRATUM_A009663 + ddr_out32(&ddr->sdram_interval, + regs->ddr_sdram_interval & ~SDRAM_INTERVAL_BSTOPRE); +#else ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); +#endif ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init); ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); #ifndef CONFIG_SYS_FSL_DDR_EMU @@ -379,6 +384,11 @@ step2: if (timeout <= 0) printf("Waiting for D_INIT timeout. Memory may not work.\n"); + +#ifdef CONFIG_SYS_FSL_ERRATUM_A009663 + ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); +#endif + #ifdef CONFIG_DEEP_SLEEP if (is_warm_boot()) { /* exit self-refresh */ diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 4b022d4..504903d 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -131,6 +131,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define SDRAM_CFG2_ODT_ONLY_READ 2 #define SDRAM_CFG2_ODT_ALWAYS 3 +#define SDRAM_INTERVAL_BSTOPRE 0x3FFF #define TIMING_CFG_2_CPO_MASK 0x0F800000 #if defined(CONFIG_SYS_FSL_DDR_VER) && \ -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] armv8: fsl-lsch3: fixup SYSCLK frequency in device tree
by Prabhakar Kushwaha 27 Jan '16

27 Jan '16

SYSCLK frequency is dependent on on-board switch settings. It may vary as per requirement. boot-loader is aware of board switch configurations. So Fixup Linux device tree from boot-loader. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> CC: Mingkai Hu <Mingkai.Hu(a)freescale.com> --- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index eafdd71..4e4861d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -190,6 +190,9 @@ void ft_cpu_setup(void *blob, bd_t *bd) "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); #endif + do_fixup_by_compat_u32(blob, "fixed-clock", + "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); + #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif -- 1.9.1

2 1

[U-Boot] [Patch V2 0/3] QIXIS related patches
by Gong Qianyu 27 Jan '16

27 Jan '16

Hi all, The version 2 patchset fixed to: - use qixis_write_i2c() instead of QIXIS_WRITE once QSPI is enabled. [Patch V2 1/3] freescale/qixis: Add support for booting from SD/QSPI [Patch V2 2/3] armv8/ls1043aqds: fix qixis_reset command issue [Patch V2 3/3] armv8/ls1043aqds: enable qixis_reset command to boot Regards, Qianyu

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[U-Boot] [PATCH] armv8/ls1043aqds: Add support for >2GB memory
by shh.xie＠gmail.com 27 Jan '16

27 Jan '16

From: Shaohui Xie <Shaohui.Xie(a)freescale.com> This patch also exposes the complete DDR region(s) to Linux. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- board/freescale/ls1043aqds/ddr.c | 19 ++++++++++++++++--- board/freescale/ls1043aqds/ls1043aqds.c | 10 ++++++++++ include/configs/ls1043aqds.h | 2 +- 3 files changed, 27 insertions(+), 4 deletions(-) diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c index 42d9068..3d3c533 100644 --- a/board/freescale/ls1043aqds/ddr.c +++ b/board/freescale/ls1043aqds/ddr.c @@ -132,9 +132,22 @@ void dram_init_banksize(void) * The address needs to add the offset of its bank. */ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { + gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; + gd->bd->bi_dram[1].size = gd->ram_size - + CONFIG_SYS_DDR_BLOCK1_SIZE; #ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; - gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->secure_ram = gd->bd->bi_dram[1].start + + gd->secure_ram - + CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; #endif + } else { + gd->bd->bi_dram[0].size = gd->ram_size; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif + } } diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index d6696ca..576fa46 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -303,6 +303,16 @@ int board_init(void) #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + + /* fixup DT for the two DDR banks */ + base[0] = gd->bd->bi_dram[0].start; + size[0] = gd->bd->bi_dram[0].size; + base[1] = gd->bd->bi_dram[1].start; + size[1] = gd->bd->bi_dram[1].size; + + fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 398f1c3..02247b3 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -33,7 +33,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DIMM_SLOTS_PER_CTLR 1 /* Physical Memory Map */ #define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_NR_DRAM_BANKS 2 #define CONFIG_DDR_SPD #define SPD_EEPROM_ADDRESS 0x51 -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] fsl/ddr: Add workaround for ERRATUM_A009942
by Shengzhou Liu 27 Jan '16

27 Jan '16

During the receive data training, the DDRC may complete on a non-optimal setting that could lead to data corruption or initialization failure. Workaround: before setting MEM_EN, set DEBUG_29 register with specific value for different data rates. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> --- arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 + drivers/ddr/fsl/fsl_ddr_gen4.c | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 49b113d..83a207c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -118,6 +118,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A008585 #define CONFIG_SYS_FSL_ERRATUM_A008751 #define CONFIG_SYS_FSL_ERRATUM_A009635 +#define CONFIG_SYS_FSL_ERRATUM_A009942 #elif defined(CONFIG_LS1043A) #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_CACHELINE_SIZE 64 diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 3fca5c2..0d9dd0b 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -55,6 +55,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, u32 vref_seq2[3] = {0xc0, 0xf0, 0x70}; /* for range 2 */ u32 *vref_seq = vref_seq1; #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 + ulong ddr_freq; + u32 tmp; +#endif #ifdef CONFIG_FSL_DDR_BIST u32 mtcr, err_detect, err_sbe; u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config; @@ -227,6 +231,20 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->debug[25], 0x9000); } #endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 + ddr_freq = get_ddr_freq(ctrl_num) / 1000000; + tmp = ddr_in32(&ddr->debug[28]); + if (ddr_freq <= 1333) + ddr_out32(&ddr->debug[28], tmp | 0x0080006a); + else if (ddr_freq <= 1600) + ddr_out32(&ddr->debug[28], tmp | 0x0070006f); + else if (ddr_freq <= 1867) + ddr_out32(&ddr->debug[28], tmp | 0x00700076); + else if (ddr_freq <= 2133) + ddr_out32(&ddr->debug[28], tmp | 0x0060007b); +#endif + /* * For RDIMMs, JEDEC spec requires clocks to be stable before reset is * deasserted. Clocks start when any chip select is enabled and clock -- 2.1.0.27.g96db324

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[U-Boot] [PATCH v3 0/5] ARM: at91: improve peripheral and system clock handle functions
by Wenyou Yang 27 Jan '16

27 Jan '16

To reduce the duplicated code, rework the peripheral's and system's clock handle functions, use these functions to replace the clock handle code. Changes in v3: - fix incorrectly used the indicator '&' to achieve the variable pointer of pmc->pcer and pmc->pcdr. Changes in v2: - fix checkpatch warning. Wenyou Yang (5): ARM: at91: asm/at91_pmc.h: fix trival register offset ARM: at91: clock: add a new file to handle clock ARM: cpu: at91: clean up peripheral clock code board: atmel: clean up peripheral clock code drivers: at91: clean up peripheral clock code arch/arm/mach-at91/Makefile | 1 + arch/arm/mach-at91/arm920t/at91rm9200_devices.c | 13 +--- arch/arm/mach-at91/arm920t/timer.c | 4 +- arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c | 36 +++------- arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c | 28 ++------ arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c | 37 +++------- .../mach-at91/arm926ejs/at91sam9m10g45_devices.c | 33 +++------ arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c | 40 +++-------- arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c | 28 ++------ arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c | 38 +++-------- arch/arm/mach-at91/arm926ejs/clock.c | 7 -- arch/arm/mach-at91/arm926ejs/cpu.c | 1 - arch/arm/mach-at91/arm926ejs/timer.c | 5 +- arch/arm/mach-at91/armv7/clock.c | 26 ------- arch/arm/mach-at91/armv7/cpu.c | 1 - arch/arm/mach-at91/armv7/timer.c | 1 - arch/arm/mach-at91/clock.c | 72 ++++++++++++++++++++ arch/arm/mach-at91/include/mach/at91_pmc.h | 8 +-- arch/arm/mach-at91/include/mach/clk.h | 2 + arch/arm/mach-at91/phy.c | 1 - arch/arm/mach-at91/sdram.c | 1 - board/atmel/at91rm9200ek/at91rm9200ek.c | 1 - board/atmel/at91rm9200ek/led.c | 5 +- board/atmel/at91sam9260ek/at91sam9260ek.c | 15 ++-- board/atmel/at91sam9261ek/at91sam9261ek.c | 8 +-- board/atmel/at91sam9261ek/led.c | 6 +- board/atmel/at91sam9263ek/at91sam9263ek.c | 23 ++----- board/atmel/at91sam9263ek/led.c | 9 +-- board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 20 ++---- board/atmel/at91sam9m10g45ek/led.c | 7 +- board/atmel/at91sam9n12ek/at91sam9n12ek.c | 6 +- board/atmel/at91sam9rlek/at91sam9rlek.c | 18 ++--- board/atmel/at91sam9rlek/led.c | 7 +- board/atmel/at91sam9x5ek/at91sam9x5ek.c | 10 +-- board/atmel/sama5d2_xplained/sama5d2_xplained.c | 1 - board/atmel/sama5d3_xplained/sama5d3_xplained.c | 5 +- board/atmel/sama5d3xek/sama5d3xek.c | 5 +- board/atmel/sama5d4_xplained/sama5d4_xplained.c | 5 +- board/atmel/sama5d4ek/sama5d4ek.c | 5 +- board/bluewater/snapper9260/snapper9260.c | 15 ++-- board/calao/usb_a9263/usb_a9263.c | 11 ++- board/egnite/ethernut5/ethernut5.c | 20 +++--- board/esd/meesc/meesc.c | 15 ++-- board/mini-box/picosam9g45/led.c | 7 +- board/mini-box/picosam9g45/picosam9g45.c | 17 ++--- board/ronetix/pm9261/led.c | 7 +- board/ronetix/pm9261/pm9261.c | 22 ++---- board/ronetix/pm9263/led.c | 7 +- board/ronetix/pm9263/pm9263.c | 19 ++---- board/ronetix/pm9g45/pm9g45.c | 20 ++---- board/siemens/corvus/board.c | 6 +- board/siemens/smartweb/smartweb.c | 3 +- board/siemens/taurus/taurus.c | 3 +- drivers/net/at91_emac.c | 9 ++- drivers/usb/host/ehci-atmel.c | 8 --- drivers/usb/host/ohci-at91.c | 20 ++---- 56 files changed, 252 insertions(+), 496 deletions(-) create mode 100644 arch/arm/mach-at91/clock.c -- 1.7.9.5

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[U-Boot] [PATCH 2/2] net: phy: implements probe for Cortina phy
by shh.xie＠gmail.com 27 Jan '16

27 Jan '16

From: Shaohui Xie <Shaohui.Xie(a)nxp.com> Cortine phy cannot support soft reset, this commit implements probe for Cortina PHY to tell phylib to skip phy soft reset by setting PHY_BROKEN_RESET in flags. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)nxp.com> --- drivers/net/phy/cortina.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c index 3a2b3bb..2d04f62 100644 --- a/drivers/net/phy/cortina.c +++ b/drivers/net/phy/cortina.c @@ -256,6 +256,12 @@ int cs4340_config(struct phy_device *phydev) return 0; } +int cs4340_probe(struct phy_device *phydev) +{ + phydev->flags = PHY_BROKEN_RESET; + return 0; +} + int cs4340_startup(struct phy_device *phydev) { phydev->link = 1; @@ -275,6 +281,7 @@ struct phy_driver cs4340_driver = { MDIO_DEVS_PHYXS | MDIO_DEVS_AN | MDIO_DEVS_VEND1 | MDIO_DEVS_VEND2), .config = &cs4340_config, + .probe = &cs4340_probe, .startup = &cs4340_startup, .shutdown = &gen10g_shutdown, }; -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] ARM: zynq: Add function to get reboot status register value.
by Moritz Fischer 27 Jan '16

27 Jan '16

Signed-off-by: Moritz Fischer <moritz.fischer(a)ettus.com> --- Hi Michal, I was planning to use this in future to boot into recovery mode. The change is small enough I feel that we could directly take it. If you want to hold off until there's a user that's fine for me, too. Cheers, Moritz --- arch/arm/mach-zynq/slcr.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c index 05f4099..709711a 100644 --- a/arch/arm/mach-zynq/slcr.c +++ b/arch/arm/mach-zynq/slcr.c @@ -166,6 +166,11 @@ u32 zynq_slcr_get_boot_mode(void) return readl(&slcr_base->boot_mode); } +u32 zynq_slcr_get_reboot_status(void) +{ + return readl(&slcr_base->reboot_status); +} + u32 zynq_slcr_get_idcode(void) { return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >> -- 2.7.0

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