January 2016 - U-Boot

[U-Boot] [PATCH] tools: mxsboot: Use more portable cpu_to_le32()
by Bin Meng 02 Feb '16

02 Feb '16

Currently when building mxsboot on certain machines it reports: HOSTCC tools/mxsboot tools/mxsboot.c: In function 'mx28_create_sd_image': tools/mxsboot.c:560: warning: implicit declaration of function 'htole32' /tmp/cchLIV6q.o: In function 'main': mxsboot.c:(.text+0x6d8): undefined reference to 'htole32' mxsboot.c:(.text+0x6e7): undefined reference to 'htole32' mxsboot.c:(.text+0x6f6): undefined reference to 'htole32' mxsboot.c:(.text+0x705): undefined reference to 'htole32' mxsboot.c:(.text+0x711): undefined reference to 'htole32' /tmp/cchLIV6q.o:mxsboot.c:(.text+0x71d): more undefined references to 'htole32' follow collect2: ld returned 1 exit status make[1]: *** [tools/mxsboot] Error 1 make: *** [tools] Error 2 The solution is to use cpu_to_le32() instead which is more portable, just like other U-Boot tools [1] do. [1] http://lists.denx.de/pipermail/u-boot/2014-October/192919.html Suggested-by: Marek Vasut <marex(a)denx.de> Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- tools/mxsboot.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/tools/mxsboot.c b/tools/mxsboot.c index 3434c81..457f435 100644 --- a/tools/mxsboot.c +++ b/tools/mxsboot.c @@ -557,15 +557,15 @@ static int mx28_create_sd_image(int infd, int outfd) cb = (struct mx28_sd_config_block *)buf; - cb->signature = htole32(0x00112233); - cb->primary_boot_tag = htole32(0x1); - cb->secondary_boot_tag = htole32(0x1); - cb->num_copies = htole32(1); - cb->drv_info[0].chip_num = htole32(0x0); - cb->drv_info[0].drive_type = htole32(0x0); - cb->drv_info[0].tag = htole32(0x1); - cb->drv_info[0].first_sector_number = htole32(sd_sector + 4); - cb->drv_info[0].sector_count = htole32((size - 4) / 512); + cb->signature = cpu_to_le32(0x00112233); + cb->primary_boot_tag = cpu_to_le32(0x1); + cb->secondary_boot_tag = cpu_to_le32(0x1); + cb->num_copies = cpu_to_le32(1); + cb->drv_info[0].chip_num = cpu_to_le32(0x0); + cb->drv_info[0].drive_type = cpu_to_le32(0x0); + cb->drv_info[0].tag = cpu_to_le32(0x1); + cb->drv_info[0].first_sector_number = cpu_to_le32(sd_sector + 4); + cb->drv_info[0].sector_count = cpu_to_le32((size - 4) / 512); wr_size = write(outfd, buf, size); if (wr_size != size) { -- 1.8.2.1

3 2

[U-Boot] [PATCH] test/py: make each unit test a pytest
by Stephen Warren 02 Feb '16

02 Feb '16

From: Stephen Warren <swarren(a)nvidia.com> A custom fixture named ut_subtest is implemented which is parametrized with the names of all unit tests that the U-Boot binary supports. This causes each U-Boot unit test to be exposes as a separate pytest. In turn, this allows more fine-grained pass/fail counts and test selection, e.g.: test.py --bd sandbox -k ut_dm_usb ... will run about 8 tests at present. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- This depends on at least my recently sent "test/py: run C-based unit tests". test/py/conftest.py | 105 ++++++++++++++++++++++++++++++++++++----------- test/py/tests/test_ut.py | 14 +++---- 2 files changed, 86 insertions(+), 33 deletions(-) diff --git a/test/py/conftest.py b/test/py/conftest.py index 3e162cafcc4a..05491a2453c0 100644 --- a/test/py/conftest.py +++ b/test/py/conftest.py @@ -21,7 +21,9 @@ import pexpect import pytest from _pytest.runner import runtestprotocol import ConfigParser +import re import StringIO +import subprocess import sys # Globals: The HTML log file, and the connection to the U-Boot console. @@ -189,8 +191,43 @@ def pytest_configure(config): import u_boot_console_exec_attach console = u_boot_console_exec_attach.ConsoleExecAttach(log, ubconfig) -def pytest_generate_tests(metafunc): - """pytest hook: parameterize test functions based on custom rules. +re_ut_test_list = re.compile(r'_u_boot_list_2_(dm|env)_test_2_\1_test_(.*)\s*$') +def generate_ut_subtest(metafunc, fixture_name): + """Provide parametrization for a ut_subtest fixture. + + Determines the set of unit tests built into a U-Boot binary by parsing the + list of symbols present in the U-Boot binary. Provides this information to + test functions by parameterizing their ut_subtest fixture parameter. + + Args: + metafunc: The pytest test function. + fixture_name: The fixture name to test. + + Returns: + Nothing. + """ + + # This does rely on an objdump binary, but that's quite likely to be + # present. This approach trivially takes care of any source or Makefile- + # level conditional compilation which may occur, and matches the test + # execution order of a plain "ut dm" command. A source-scanning approach + # would not do neither. This approach also doesn't require access to the + # U-Boot source tree when running tests. + + cmd = 'objdump -t "%s" | sort' % (console.config.build_dir + '/u-boot') + out = subprocess.check_output(cmd, shell=True) + vals = [] + for l in out.splitlines(): + m = re_ut_test_list.search(l) + if not m: + continue + vals.append(m.group(1) + ' ' + m.group(2)) + + ids = ['ut_' + s.replace(' ', '_') for s in vals] + metafunc.parametrize(fixture_name, vals, ids=ids) + +def generate_config(metafunc, fixture_name): + """Provide parametrization for {env,brd}__ fixtures. If a test function takes parameter(s) (fixture names) of the form brd__xxx or env__xxx, the brd and env configuration dictionaries are consulted to @@ -199,6 +236,7 @@ def pytest_generate_tests(metafunc): Args: metafunc: The pytest test function. + fixture_name: The fixture name to test. Returns: Nothing. @@ -208,30 +246,49 @@ def pytest_generate_tests(metafunc): 'brd': console.config.brd, 'env': console.config.env, } + parts = fixture_name.split('__') + if len(parts) < 2: + return + if parts[0] not in subconfigs: + return + subconfig = subconfigs[parts[0]] + vals = [] + val = subconfig.get(fixture_name, []) + # If that exact name is a key in the data source: + if val: + # ... use the dict value as a single parameter value. + vals = (val, ) + else: + # ... otherwise, see if there's a key that contains a list of + # values to use instead. + vals = subconfig.get(fixture_name+ 's', []) + def fixture_id(index, val): + try: + return val['fixture_id'] + except: + return fixture_name + str(index) + ids = [fixture_id(index, val) for (index, val) in enumerate(vals)] + metafunc.parametrize(fixture_name, vals, ids=ids) + +def pytest_generate_tests(metafunc): + """pytest hook: parameterize test functions based on custom rules. + + Check each test function parameter (fixture name) to see if it is one of + our custom names, and if so, provide the correct parametrization for that + parameter. + + Args: + metafunc: The pytest test function. + + Returns: + Nothing. + """ + for fn in metafunc.fixturenames: - parts = fn.split('__') - if len(parts) < 2: + if fn == 'ut_subtest': + generate_ut_subtest(metafunc, fn) continue - if parts[0] not in subconfigs: - continue - subconfig = subconfigs[parts[0]] - vals = [] - val = subconfig.get(fn, []) - # If that exact name is a key in the data source: - if val: - # ... use the dict value as a single parameter value. - vals = (val, ) - else: - # ... otherwise, see if there's a key that contains a list of - # values to use instead. - vals = subconfig.get(fn + 's', []) - def fixture_id(index, val): - try: - return val["fixture_id"] - except: - return fn + str(index) - ids = [fixture_id(index, val) for (index, val) in enumerate(vals)] - metafunc.parametrize(fn, vals, ids=ids) + generate_config(metafunc, fn) @pytest.fixture(scope='function') def u_boot_console(request): diff --git a/test/py/tests/test_ut.py b/test/py/tests/test_ut.py index b033ca54d756..cd85b3ddc0ce 100644 --- a/test/py/tests/test_ut.py +++ b/test/py/tests/test_ut.py @@ -6,8 +6,8 @@ import os.path import pytest @pytest.mark.buildconfigspec('ut_dm') -def test_ut_dm(u_boot_console): - """Execute the "ut dm" command.""" +def test_ut_dm_init(u_boot_console): + """Initialize data for ut dm tests.""" fn = u_boot_console.config.source_dir + '/testflash.bin' if not os.path.exists(fn): @@ -16,14 +16,10 @@ def test_ut_dm(u_boot_console): with open(fn, 'wb') as fh: fh.write(data) - output = u_boot_console.run_command('ut dm') - assert output.endswith('Failures: 0') - -(a)pytest.mark.buildconfigspec('ut_env') -def test_ut_env(u_boot_console): - """Execute the "ut env" command.""" +def test_ut(u_boot_console, ut_subtest): + """Execute a "ut" subtest.""" - output = u_boot_console.run_command('ut env') + output = u_boot_console.run_command('ut ' + ut_subtest) assert output.endswith('Failures: 0') @pytest.mark.buildconfigspec('ut_time') -- 2.7.0

2 6

[U-Boot] [PATCH] fsl_qspi: fix address mask issue
by Ye Li 02 Feb '16

02 Feb '16

The OFFSET_BITS_MASK should mask bit from 0-23. By using GENMASK(24, 0), when using the fast read common (0xb), a invalid sf_addr 0x1000000 is produced by swab32(txbuf) & OFFSET_BITS_MASK. Signed-off-by: Ye Li <ye.li(a)nxp.com> --- drivers/spi/fsl_qspi.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index feec3e8..542b6cf 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR; #define TX_BUFFER_SIZE 0x40 #endif -#define OFFSET_BITS_MASK GENMASK(24, 0) +#define OFFSET_BITS_MASK GENMASK(23, 0) #define FLASH_STATUS_WEL 0x02 -- 1.7.4.1

3 2

[U-Boot] [PATCHv2 0/8] Migrate NXP/Freescale Vybrid based boards to support pure DT
by Bhuvanchandra DV 02 Feb '16

02 Feb '16

Changes since V1: - Update the license string in device tree's. - Update all lpuart's uart nodes in device tree. - Dropped *_dtb_defconfig and updated the default defconfig's with DT support. - Reordered defconfig's using defconfig via savedefconfig. - Use one patch to update all Vybrid based board defconfig's. - Dropped vybrid_gpio driver legacy code. Thanks! Stefan for pointing this. - Dropped the legacy way of enabling GPIO, UART and SPI on NXP/Freescale Vybrid based board's. - Compile checked for vf610twr and pcm052 since I don't have access to such hardware at my end. Reviewer's and tester's welcome! Bhuvanchandra DV (8): arm: vybrid: Enable lpuart support arm: colibri-vf: Enable serial support dm: lpuart: Drop the legacy code dm: vybrid_gpio: Drop legacy code arm: vybrid: Drop enabling gpio, uart and spi in legacy mode arm: vf610-twr: Add device tree files arm: pcm052: Add device tree files arm: vybrid: Update defconfig's arch/arm/dts/Makefile | 4 +- arch/arm/dts/pcm052.dts | 22 +++++++++ arch/arm/dts/vf-colibri.dtsi | 9 ++++ arch/arm/dts/vf.dtsi | 47 ++++++++++++++++-- arch/arm/dts/vf500-colibri.dts | 5 -- arch/arm/dts/vf610-colibri.dts | 5 -- arch/arm/dts/vf610-twr.dts | 22 +++++++++ configs/colibri_vf_defconfig | 8 ++++ configs/colibri_vf_dtb_defconfig | 14 ------ configs/pcm052_defconfig | 7 +++ configs/vf610twr_defconfig | 7 +++ configs/vf610twr_nand_defconfig | 7 +++ drivers/gpio/vybrid_gpio.c | 18 ------- drivers/serial/serial_lpuart.c | 101 +-------------------------------------- include/configs/colibri_vf.h | 13 ----- include/configs/pcm052.h | 3 -- include/configs/vf610twr.h | 3 -- 17 files changed, 129 insertions(+), 166 deletions(-) create mode 100644 arch/arm/dts/pcm052.dts create mode 100644 arch/arm/dts/vf610-twr.dts delete mode 100644 configs/colibri_vf_dtb_defconfig -- 2.7.0

3 12

[U-Boot] [PATCH v7 5/7] mips: ath79: add spi driver
by Wills Wang 02 Feb '16

02 Feb '16

Reviewed-by: Thomas Chou <thomas(a)wytron.com.tw> Signed-off-by: Wills Wang <wills.wang(a)live.com> --- Changes in v7: - Define spi_cs_activate/spi_cs_deactivate - Rename MHZ to ATH79_SPI_MHZ - Use clrsetbits_32 Changes in v6: - Add rrw_delay in ath79_spi_priv for more accurate timing - Remove ath79_spi_delay - Calculate delay in ath79_spi_set_speed Changes in v5: - remove ar933x_spi_platdata - Import document "spi-ath79.txt" from kernel - Add delay for bitbang operation Changes in v4: - Use get_bus_freq instead of hardcode in SPI driver Changes in v3: - Convert spi driver to driver model Changes in v2: - Add a compatible spi driver doc/device-tree-bindings/spi/spi-ath79.txt | 19 +++ drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/ath79_spi.c | 237 +++++++++++++++++++++++++++++ 4 files changed, 265 insertions(+) create mode 100644 doc/device-tree-bindings/spi/spi-ath79.txt create mode 100644 drivers/spi/ath79_spi.c diff --git a/doc/device-tree-bindings/spi/spi-ath79.txt b/doc/device-tree-bindings/spi/spi-ath79.txt new file mode 100644 index 0000000..3fd9d67 --- /dev/null +++ b/doc/device-tree-bindings/spi/spi-ath79.txt @@ -0,0 +1,19 @@ +Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller + +Required properties: +- compatible: has to be "qca,<soc-type>-spi", "qca,ar7100-spi" as fallback. +- reg: Base address and size of the controllers memory area +- #address-cells: <1>, as required by generic SPI binding. +- #size-cells: <0>, also as required by generic SPI binding. + +Child nodes as per the generic SPI binding. + +Example: + + spi@1f000000 { + compatible = "qca,ar9132-spi", "qca,ar7100-spi"; + reg = <0x1f000000 0x10>; + + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 2cdb110..0ab2741 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -23,6 +23,14 @@ config ALTERA_SPI IP core. Please find details on the "Embedded Peripherals IP User Guide" of Altera. +config ATH79_SPI + bool "Atheros SPI driver" + help + Enable the Atheros ar7xxx/ar9xxx SoC SPI driver, it was used + to access SPI NOR flash and other SPI peripherals. This driver + uses driver model and requires a device tree binding to operate. + please refer to doc/device-tree-bindings/spi/spi-ath79.txt. + config CADENCE_QSPI bool "Cadence QSPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 3eca745..7fb2926 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -17,6 +17,7 @@ endif obj-$(CONFIG_ALTERA_SPI) += altera_spi.o obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o +obj-$(CONFIG_ATH79_SPI) += ath79_spi.o obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o obj-$(CONFIG_BFIN_SPI) += bfin_spi.o diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c new file mode 100644 index 0000000..568548f --- /dev/null +++ b/drivers/spi/ath79_spi.c @@ -0,0 +1,237 @@ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spi.h> +#include <dm.h> +#include <div64.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <mach/ar71xx_regs.h> + +/* CLOCK_DIVIDER = 3 (SPI clock = 200 / 8 ~ 25 MHz) */ +#define ATH79_SPI_CLK_DIV(x) (((x) >> 1) - 1) +#define ATH79_SPI_RRW_DELAY_FACTOR 12000 +#define ATH79_SPI_MHZ (1000 * 1000) + +struct ath79_spi_priv { + void __iomem *regs; + u32 rrw_delay; +}; + +static inline u32 ath79_spi_read(struct udevice *bus, u32 offset) +{ + struct ath79_spi_priv *priv = dev_get_priv(bus); + return readl(priv->regs + offset); +} + +static inline void ath79_spi_write(struct udevice *bus, + u32 val, u32 offset) +{ + struct ath79_spi_priv *priv = dev_get_priv(bus); + writel(val, priv->regs + offset); +} + +static void spi_cs_activate(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + + ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS); + ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL, AR71XX_SPI_REG_IOC); +} + +static void spi_cs_deactivate(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + + ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL, AR71XX_SPI_REG_IOC); + ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS); +} + +static int ath79_spi_claim_bus(struct udevice *dev) +{ + return 0; +} + +static int ath79_spi_release_bus(struct udevice *dev) +{ + return 0; +} + +static int ath79_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct ath79_spi_priv *priv = dev_get_priv(bus); + struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev); + u8 *rx = din; + const u8 *tx = dout; + u8 curbyte, curbitlen, restbits; + u32 bytes = bitlen / 8; + u32 out, in; + u64 tick; + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(dev); + + restbits = (bitlen % 8); + if (restbits) + bytes++; + + out = AR71XX_SPI_IOC_CS_ALL & ~(AR71XX_SPI_IOC_CS(slave->cs)); + while (bytes > 0) { + bytes--; + curbyte = 0; + if (tx) + curbyte = *tx++; + + if (restbits && !bytes) { + curbitlen = restbits; + curbyte <<= 8 - restbits; + } else { + curbitlen = 8; + } + + for (curbyte <<= (8 - curbitlen); curbitlen; curbitlen--) { + if (curbyte & 0x80) + out |= AR71XX_SPI_IOC_DO; + else + out &= ~(AR71XX_SPI_IOC_DO); + + ath79_spi_write(bus, out, AR71XX_SPI_REG_IOC); + + /* delay for low level */ + if (priv->rrw_delay) { + tick = get_ticks() + priv->rrw_delay; + while (get_ticks() < tick) + /*NOP*/; + } + + ath79_spi_write(bus, out | AR71XX_SPI_IOC_CLK, + AR71XX_SPI_REG_IOC); + + /* delay for high level */ + if (priv->rrw_delay) { + tick = get_ticks() + priv->rrw_delay; + while (get_ticks() < tick) + /*NOP*/; + } + + curbyte <<= 1; + } + + if (!bytes) + ath79_spi_write(bus, out, AR71XX_SPI_REG_IOC); + + in = ath79_spi_read(bus, AR71XX_SPI_REG_RDS); + if (rx) { + if (restbits && !bytes) + *rx++ = (in << (8 - restbits)); + else + *rx++ = in; + } + } + + if (flags & SPI_XFER_END) + spi_cs_deactivate(dev); + + return 0; +} + + +static int ath79_spi_set_speed(struct udevice *bus, uint speed) +{ + struct ath79_spi_priv *priv = dev_get_priv(bus); + u32 val, div = 0; + u64 time; + + if (speed) + div = get_bus_freq(0) / speed; + + if (div > 63) + div = 63; + + if (div < 5) + div = 5; + + /* calculate delay */ + time = get_tbclk(); + do_div(time, speed / 2); + val = get_bus_freq(0) / ATH79_SPI_MHZ; + val = ATH79_SPI_RRW_DELAY_FACTOR / val; + if (time > val) + priv->rrw_delay = time - val + 1; + else + priv->rrw_delay = 0; + + ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS); + clrsetbits_32(priv->regs + AR71XX_SPI_REG_CTRL, + AR71XX_SPI_CTRL_DIV_MASK, ATH79_SPI_CLK_DIV(div)); + ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS); + return 0; +} + +static int ath79_spi_set_mode(struct udevice *bus, uint mode) +{ + return 0; +} + +static int ath79_spi_probe(struct udevice *bus) +{ + struct ath79_spi_priv *priv = dev_get_priv(bus); + fdt_addr_t addr; + + addr = dev_get_addr(bus); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->regs = map_physmem(addr, + AR71XX_SPI_SIZE, + MAP_NOCACHE); + + /* Init SPI Hardware, disable remap, set clock */ + ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS); + ath79_spi_write(bus, AR71XX_SPI_CTRL_RD | ATH79_SPI_CLK_DIV(8), + AR71XX_SPI_REG_CTRL); + ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS); + + return 0; +} + +static int ath79_cs_info(struct udevice *bus, uint cs, + struct spi_cs_info *info) +{ + /* Always allow activity on CS 0/1/2 */ + if (cs >= 3) + return -ENODEV; + + return 0; +} + +static const struct dm_spi_ops ath79_spi_ops = { + .claim_bus = ath79_spi_claim_bus, + .release_bus = ath79_spi_release_bus, + .xfer = ath79_spi_xfer, + .set_speed = ath79_spi_set_speed, + .set_mode = ath79_spi_set_mode, + .cs_info = ath79_cs_info, +}; + +static const struct udevice_id ath79_spi_ids[] = { + { .compatible = "qca,ar7100-spi" }, + {} +}; + +U_BOOT_DRIVER(ath79_spi) = { + .name = "ath79_spi", + .id = UCLASS_SPI, + .of_match = ath79_spi_ids, + .ops = &ath79_spi_ops, + .priv_auto_alloc_size = sizeof(struct ath79_spi_priv), + .probe = ath79_spi_probe, +}; -- 1.9.1

3 5

[U-Boot] [PATCH 1/2] net: phy: micrel: add documentation for Micrel KSZ90x1 binding
by dinguyen＠opensource.altera.com 02 Feb '16

02 Feb '16

From: Dinh Nguyen <dinguyen(a)opensource.altera.com> Add the DTS documentation for the Micrel KSZ90x1 binding. The original document was from: [commit 4b405efbe12de28b26289282b431323d73992381 from the Linux kernel] This takes the original document and adds a clarification on how the skew values are represented in the code. References: Micrel ksz9021rl/rn Data Sheet, Revision 1.2. Dated 2/13/2014. http://www.micrel.com/_PDF/Ethernet/datasheets/ksz9021rl-rn_ds.pdf Micrel ksz9031rnx Data Sheet, Revision 2.1. Dated 11/20/2014. http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf Signed-off-by: Dinh Nguyen <dinguyen(a)opensource.altera.com> --- doc/device-tree-bindings/net/micrel-ksz90x1.txt | 165 ++++++++++++++++++++++++ 1 file changed, 165 insertions(+) create mode 100644 doc/device-tree-bindings/net/micrel-ksz90x1.txt diff --git a/doc/device-tree-bindings/net/micrel-ksz90x1.txt b/doc/device-tree-bindings/net/micrel-ksz90x1.txt new file mode 100644 index 0000000..307f53f --- /dev/null +++ b/doc/device-tree-bindings/net/micrel-ksz90x1.txt @@ -0,0 +1,165 @@ +Micrel KSZ9021/KSZ9031 Gigabit Ethernet PHY + +Some boards require special tuning values, particularly when it comes to +clock delays. You can specify clock delay values by adding +micrel-specific properties to an Ethernet OF device node. + +Note that these settings are applied after any phy-specific fixup from +phy_fixup_list (see phy_init_hw() from drivers/net/phy/phy_device.c), +and therefore may overwrite them. + +KSZ9021: + + All skew control options are specified in picoseconds. The minimum + value is 0, the maximum value is 1800, and it is incremented by 120ps + steps. + + Optional properties: + + - rxc-skew-ps : Skew control of RXC pad + - rxdv-skew-ps : Skew control of RX CTL pad + - txc-skew-ps : Skew control of TXC pad + - txen-skew-ps : Skew control of TX CTL pad + - rxd0-skew-ps : Skew control of RX data 0 pad + - rxd1-skew-ps : Skew control of RX data 1 pad + - rxd2-skew-ps : Skew control of RX data 2 pad + - rxd3-skew-ps : Skew control of RX data 3 pad + - txd0-skew-ps : Skew control of TX data 0 pad + - txd1-skew-ps : Skew control of TX data 1 pad + - txd2-skew-ps : Skew control of TX data 2 pad + - txd3-skew-ps : Skew control of TX data 3 pad + +KSZ9031: + + All skew control options are specified in picoseconds. The minimum + value is 0, and the maximum is property-dependent. The increment + step is 60ps. + + The KSZ9031 hardware supports a range of skew values from negative to + positive, where the specific range is property dependent. All values + specified in the devicetree are offset by the minimum value so they + can be represented as positive integers in the devicetree since it's + difficult to represent a negative number in the devictree. + + The following 5-bit values table apply to rxc-skew-ps and txc-skew-ps. + + Pad Skew Value Delay (ps) Devicetree Value + ------------------------------------------------------ + 0_0000 -900ps 0 + 0_0001 -840ps 60 + 0_0010 -780ps 120 + 0_0011 -720ps 180 + 0_0100 -660ps 240 + 0_0101 -600ps 300 + 0_0110 -540ps 360 + 0_0111 -480ps 420 + 0_1000 -420ps 480 + 0_1001 -360ps 540 + 0_1010 -300ps 600 + 0_1011 -240ps 660 + 0_1100 -180ps 720 + 0_1101 -120ps 780 + 0_1110 -60ps 840 + 0_1111 0ps 900 + 1_0000 60ps 960 + 1_0001 120ps 1020 + 1_0010 180ps 1080 + 1_0011 240ps 1140 + 1_0100 300ps 1200 + 1_0101 360ps 1260 + 1_0110 420ps 1320 + 1_0111 480ps 1380 + 1_1000 540ps 1440 + 1_1001 600ps 1500 + 1_1010 660ps 1560 + 1_1011 720ps 1620 + 1_1100 780ps 1680 + 1_1101 840ps 1740 + 1_1110 900ps 1800 + 1_1111 960ps 1860 + + The following 4-bit values table apply to the txdX-skew-ps, rxdX-skew-ps + data pads, and the rxdv-skew-ps, txen-skew-ps control pads. + + Pad Skew Value Delay (ps) Devicetree Value + ------------------------------------------------------ + 0000 -420ps 0 + 0001 -360ps 60 + 0010 -300ps 120 + 0011 -240ps 180 + 0100 -180ps 240 + 0101 -120ps 300 + 0110 -60ps 360 + 0111 0ps 420 + 1000 60ps 480 + 1001 120ps 540 + 1010 180ps 600 + 1011 240ps 660 + 1100 300ps 720 + 1101 360ps 780 + 1110 420ps 840 + 1111 480ps 900 + + Optional properties: + + Maximum value of 1860: + + - rxc-skew-ps : Skew control of RX clock pad + - txc-skew-ps : Skew control of TX clock pad + + Maximum value of 900: + + - rxdv-skew-ps : Skew control of RX CTL pad + - txen-skew-ps : Skew control of TX CTL pad + - rxd0-skew-ps : Skew control of RX data 0 pad + - rxd1-skew-ps : Skew control of RX data 1 pad + - rxd2-skew-ps : Skew control of RX data 2 pad + - rxd3-skew-ps : Skew control of RX data 3 pad + - txd0-skew-ps : Skew control of TX data 0 pad + - txd1-skew-ps : Skew control of TX data 1 pad + - txd2-skew-ps : Skew control of TX data 2 pad + - txd3-skew-ps : Skew control of TX data 3 pad + +Examples: + + /* Attach to an Ethernet device with autodetected PHY */ + &enet { + rxc-skew-ps = <1800>; + rxdv-skew-ps = <0>; + txc-skew-ps = <1800>; + txen-skew-ps = <0>; + status = "okay"; + }; + + /* Attach to an explicitly-specified PHY */ + mdio { + phy0: ethernet-phy@0 { + rxc-skew-ps = <1800>; + rxdv-skew-ps = <0>; + txc-skew-ps = <1800>; + txen-skew-ps = <0>; + reg = <0>; + }; + }; + ethernet@70000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + +References + + Micrel ksz9021rl/rn Data Sheet, Revision 1.2. Dated 2/13/2014. + http://www.micrel.com/_PDF/Ethernet/datasheets/ksz9021rl-rn_ds.pdf + + Micrel ksz9031rnx Data Sheet, Revision 2.1. Dated 11/20/2014. + http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf + +Notes: + + Note that a previous version of the Micrel ksz9021rl/rn Data Sheet + was missing extended register 106 (transmit data pad skews), and + incorrectly specified the ps per step as 200ps/step instead of + 120ps/step. The latest update to this document reflects the latest + revision of the Micrel specification even though usage in the kernel + still reflects that incorrect document. -- 2.6.2

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[U-Boot] [PATCH 0/2] atmel_nand: add sama5d2 chip support, which support up to 32bit pmecc
by Josh Wu 02 Feb '16

02 Feb '16

This patch set will enable sama5d2 chip pmecc support, it includes: 1. update the pmecc registers and pmecc error location registers map. 2. add 32bit ecc support. Josh Wu (2): atmel_nand_ecc: update pmecc registers according to sama5d2 chip atmel_nand: Add 32 bit ecc support for sama5d2 chip drivers/mtd/nand/atmel_nand.c | 10 +++++++++- drivers/mtd/nand/atmel_nand_ecc.h | 36 ++++++++++++++++++++++++++++++++---- 2 files changed, 41 insertions(+), 5 deletions(-) -- 1.9.1

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[U-Boot] [PATCH] patman: fix series-notes handling for buildman
by Albert ARIBAUD 02 Feb '16

02 Feb '16

A patman series with a 'Series-notes' section causes buildman to crash with: self.series.notes += self.section TypeError: cannot concatenate 'str' and 'list' objects Fix by initializing series.notes as a one-element array rathen than a scalar. Signed-off-by: Albert ARIBAUD <albert.u.boot(a)aribaud.net> --- tools/patman/series.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/patman/series.py b/tools/patman/series.py index 3399f2c..e8aad59 100644 --- a/tools/patman/series.py +++ b/tools/patman/series.py @@ -69,7 +69,7 @@ class Series(dict): # Otherwise just set the value elif name in valid_series: - self[name] = value + self[name] = [value] else: raise ValueError("In %s: line '%s': Unknown 'Series-%s': valid " "options are %s" % (commit.hash, line, name, -- 2.5.0

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[U-Boot] [PATCH] fdt: __of_translate_address(): check parent's 'ranges' before translate
by Przemyslaw Marczak 02 Feb '16

02 Feb '16

The present implementation of __of_translate_address() taken from the Linux, is designed for translate bus/child address mappings by using 'ranges' property - and it doesn't allow for checking an address for a device's node with zero size-cells. The 'size-cells > 0' is required for bus/child address mapping, but is not required for non-memory mapped address, e.g.: I2C chip. Then when we need only raw 'reg' property's value. Since the I2C device address goes to a single-cell reg property, support for that case is welcome, but currently calling dev_get_addr() for I2C device will return 'FDT_ADDR_T_NONE', and print the warning: warning: __of_translate_address: Bad cell count for 'some-dev' The fix: The proper result by this commit, is achieved by skipping the condition check: 'size-cells > 0', when the parent doesn't provide the 'ranges' property and allows to return 1:1 address translation, if caller want's just the reg property's value. No additional argument is needed, the 'ranges' property existence decides, what type of translation is done when calling dev_get_addr(). And this should be, what the compatible driver expects. Now, by this commit the function __of_translate_address() can be used for the both reg property use-cases: Case 1: (ranges) ---------------- some-bus { address-cells = <1>; size-cells = <1>; ranges = <0x0 0x10000000 0x1000>; reg = <0x10000000 0x1000>; child1 { reg = <0xa00 0x100>; }; child2 { reg = <0xb00 0x100>; }; }; Return values (CONFIG_OF_TRANSLATE=y): - dev_get_addr(some-bus) - retrurns: 0x10000000 - correct - dev_get_addr(child1) - retrurns: 0x10000a00 - correct - dev_get_addr(child2) - retrurns: 0x10000b00 - correct This works as previous - this commit have no impact on this case. Case 2: (no ranges - e.g. I2C bus childs) - fixed ------------------------------------------------- I2C-bus { address-cells = <1>; size-cells = <0>; reg = <0x10000000>; chip1 { reg = <0xa00>; }; chip2 { reg = <0xb00>; }; }; Return values (CONFIG_OF_TRANSLATE=y): - dev_get_addr(I2C-bus) - retrurns: 0x10000000 - correct - dev_get_addr(chip1) - retrurns: 0xa00 - correct - dev_get_addr(chip2) - retrurns: 0xb00 - correct This is fixed, since the previously returned value for chip1 and chip2 was: 0xffffffff, which means: 'FDT_ADDR_T_NONE'. Signed-off-by: Przemyslaw Marczak <p.marczak(a)samsung.com> Cc: Stefan Roese <sr(a)denx.de> Cc: Tom Rini <trini(a)konsulko.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Stephen Warren <swarren(a)nvidia.com> Cc: Stephen Warren <swarren(a)wwwdotorg.org> --- common/fdt_support.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/common/fdt_support.c b/common/fdt_support.c index 66464db..1f472ca 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -952,8 +952,9 @@ void fdt_del_node_and_alias(void *blob, const char *alias) /* Max address size we deal with */ #define OF_MAX_ADDR_CELLS 4 #define OF_BAD_ADDR FDT_ADDR_T_NONE -#define OF_CHECK_COUNTS(na, ns) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS && \ - (ns) > 0) +#define OF_CHECK_COUNTS(na, ns, skip_ns) \ + ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS && \ + (skip_ns || (ns) > 0)) /* Debug utility */ #ifdef DEBUG @@ -1104,11 +1105,12 @@ static int of_translate_one(void * blob, int parent, struct of_bus *bus, static u64 __of_translate_address(void *blob, int node_offset, const fdt32_t *in_addr, const char *rprop) { - int parent; - struct of_bus *bus, *pbus; + const fdt32_t *pranges; fdt32_t addr[OF_MAX_ADDR_CELLS]; - int na, ns, pna, pns; + int na, ns, pna, pns, parent; + struct of_bus *bus, *pbus; u64 result = OF_BAD_ADDR; + bool skip_ns_check; debug("OF: ** translation for device %s **\n", fdt_get_name(blob, node_offset, NULL)); @@ -1119,9 +1121,16 @@ static u64 __of_translate_address(void *blob, int node_offset, const fdt32_t *in goto bail; bus = &of_busses[0]; - /* Cound address cells & copy address locally */ + /* Chek 'ns' only if parent provides 'ranges' property */ + pranges = fdt_getprop(blob, parent, rprop, NULL); + if (pranges) + skip_ns_check = false; + else + skip_ns_check = true; + + /* Count address cells & copy address locally */ bus->count_cells(blob, parent, &na, &ns); - if (!OF_CHECK_COUNTS(na, ns)) { + if (!OF_CHECK_COUNTS(na, ns, skip_ns_check)) { printf("%s: Bad cell count for %s\n", __FUNCTION__, fdt_get_name(blob, node_offset, NULL)); goto bail; @@ -1148,7 +1157,7 @@ static u64 __of_translate_address(void *blob, int node_offset, const fdt32_t *in /* Get new parent bus and counts */ pbus = &of_busses[0]; pbus->count_cells(blob, parent, &pna, &pns); - if (!OF_CHECK_COUNTS(pna, pns)) { + if (!OF_CHECK_COUNTS(pna, pns, skip_ns_check)) { printf("%s: Bad cell count for %s\n", __FUNCTION__, fdt_get_name(blob, node_offset, NULL)); break; -- 1.9.1

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[U-Boot] [PATCH v1 0/2] Add back P2020DS
by York Sun 02 Feb '16

02 Feb '16

Recently Freescale (now NXP) received order to make more P2020DS. It's better have to U-Boot support than digging out old releases. Changes in v1: Add back P2020DS, using generic board structure. Initial patch to adjust DDR speed tables. York Sun (2): Revert "powerpc: mpc85xx: remove P2020DS board support" powerpc: p2020ds: Update DDR speed tables arch/powerpc/cpu/mpc85xx/Kconfig | 4 + board/freescale/p2020ds/Kconfig | 12 + board/freescale/p2020ds/MAINTAINERS | 10 + board/freescale/p2020ds/Makefile | 12 + board/freescale/p2020ds/ddr.c | 151 +++++++ board/freescale/p2020ds/law.c | 20 + board/freescale/p2020ds/p2020ds.c | 261 ++++++++++++ board/freescale/p2020ds/tlb.c | 91 +++++ configs/P2020DS_36BIT_defconfig | 9 + configs/P2020DS_DDR2_defconfig | 9 + configs/P2020DS_SDCARD_defconfig | 9 + configs/P2020DS_SPIFLASH_defconfig | 9 + configs/P2020DS_defconfig | 8 + doc/README.scrapyard | 1 - include/configs/P2020DS.h | 755 +++++++++++++++++++++++++++++++++++ 15 files changed, 1360 insertions(+), 1 deletion(-) create mode 100644 board/freescale/p2020ds/Kconfig create mode 100644 board/freescale/p2020ds/MAINTAINERS create mode 100644 board/freescale/p2020ds/Makefile create mode 100644 board/freescale/p2020ds/ddr.c create mode 100644 board/freescale/p2020ds/law.c create mode 100644 board/freescale/p2020ds/p2020ds.c create mode 100644 board/freescale/p2020ds/tlb.c create mode 100644 configs/P2020DS_36BIT_defconfig create mode 100644 configs/P2020DS_DDR2_defconfig create mode 100644 configs/P2020DS_SDCARD_defconfig create mode 100644 configs/P2020DS_SPIFLASH_defconfig create mode 100644 configs/P2020DS_defconfig create mode 100644 include/configs/P2020DS.h -- 1.7.9.5

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