August 2015 - U-Boot

[U-Boot] [PATCH 0/6] Introduce new board cm-t43
by Nikita Kiryanov 13 Aug '15

13 Aug '15

This series adds initial support for CM-T43, an AM437x based SoM. This support includes: serial, MMC/eMMC, NAND, USB, ETH, I2C, GPIO, DRAM detection. Cc: Igor Grinberg <grinberg(a)compulab.co.il> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> Cc: Pantelis Antoniou <panto(a)antoniou-consulting.com> Cc: Jagan Teki <jteki(a)openedev.com> Cc: Tom Rini <trini(a)konsulko.com> Nikita Kiryanov (6): spi: omap3_spi: add am43xx support to omap3_spi arm: am43xx: enable spi clock mmc: omap_hsmmc: enable proper CMD(DAT) lines reset procedure for am43xx mmc: omap_hsmmc: enable 8bit interface for eMMC for AM43xx gpio: am43xx: expand gpio support arm: am437x: Introduce new board cm-t43 arch/arm/Kconfig | 6 + arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 1 + arch/arm/include/asm/arch-am33xx/gpio.h | 4 + board/compulab/cm_t43/Kconfig | 15 ++ board/compulab/cm_t43/MAINTAINERS | 6 + board/compulab/cm_t43/Makefile | 9 + board/compulab/cm_t43/board.c | 272 +++++++++++++++++++++++++++++++ board/compulab/cm_t43/board.h | 12 ++ board/compulab/cm_t43/mux.c | 143 ++++++++++++++++ configs/cm_t43_defconfig | 10 ++ drivers/mmc/omap_hsmmc.c | 6 +- drivers/spi/omap3_spi.h | 2 +- include/configs/cm_t43.h | 182 +++++++++++++++++++++ 13 files changed, 664 insertions(+), 4 deletions(-) create mode 100644 board/compulab/cm_t43/Kconfig create mode 100644 board/compulab/cm_t43/MAINTAINERS create mode 100644 board/compulab/cm_t43/Makefile create mode 100644 board/compulab/cm_t43/board.c create mode 100644 board/compulab/cm_t43/board.h create mode 100644 board/compulab/cm_t43/mux.c create mode 100644 configs/cm_t43_defconfig create mode 100644 include/configs/cm_t43.h -- 1.9.1

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[U-Boot] [PATCH 1/2] spl: Fix compile warning for arm64
by Gong Qianyu 13 Aug '15

13 Aug '15

Make the cast explicit for "warning: cast to pointer from integer of different size". Signed-off-by: Gong Qianyu <Qianyu.Gong(a)freescale.com> diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index 494f683..ce58c58 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -44,7 +44,7 @@ static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector) /* Read the header too to avoid extra memcpy */ count = mmc->block_dev.block_read(0, sector, image_size_sectors, - (void *)spl_image.load_addr); + (void *)(ulong)spl_image.load_addr); debug("read %x sectors to %x\n", image_size_sectors, spl_image.load_addr); -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 2/2] common/cmd_source.c: Fix the source command failure under 64-bit platform
by Gong Qianyu 13 Aug '15

13 Aug '15

Modify the data pointer type from ulong* to u32*. For arm64 type "ulong" could be 64-bit. Then in line 89 of common/cmd_source.c: "while (*data++);" data will point to the next 64 bits each time. As the uImage file generated by mkimage tool keeps the same data format in either 32-bit or 64-bit platform, the difference would cause failure in 64-bit platform. Signed-off-by: Gong Qianyu <Qianyu.Gong(a)freescale.com> diff --git a/common/cmd_source.c b/common/cmd_source.c index d2a881d..db7ab7e 100644 --- a/common/cmd_source.c +++ b/common/cmd_source.c @@ -33,7 +33,7 @@ source (ulong addr, const char *fit_uname) #if defined(CONFIG_IMAGE_FORMAT_LEGACY) const image_header_t *hdr; #endif - ulong *data; + u32 *data; int verify; void *buf; #if defined(CONFIG_FIT) @@ -74,7 +74,7 @@ source (ulong addr, const char *fit_uname) } /* get length of script */ - data = (ulong *)image_get_data (hdr); + data = (u32 *)image_get_data (hdr); if ((len = uimage_to_cpu (*data)) == 0) { puts ("Empty Script\n"); @@ -128,7 +128,7 @@ source (ulong addr, const char *fit_uname) return 1; } - data = (ulong *)fit_data; + data = (u32 *)fit_data; len = (ulong)fit_len; break; #endif -- 2.1.0.27.g96db324

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[U-Boot] [PATCH v2 0/8] ARM: keystone2: Clocks and PLLs cleanup
by Lokesh Vutla 13 Aug '15

13 Aug '15

This seires does a several bunch of cleanups for clock and PLL related definitions. This helps a lot in adding data for new Keystone2 SoCs. And also adds support for CPU detection. This is based on Nishanth's config cleanup series: https://www.mail-archive.com/u-boot%40lists.denx.de/msg177822.html Tested on K2HK-evm: http://pastebin.ubuntu.com/11952380/ Changes since v1: - Added support for detecting SR - Corrected CPU detection. - Corrected DEV speeds for Edison - Added proper delays for PLL init code. Lokesh Vutla (8): ARM: keystone2: Cleanup SoC detection ARM: keystone2: Enable CONFIG_DISPLAY_CPUINFO ARM: keystone2: Cleanup PLL init code ARM: keystone2: Fix dev and arm speed detection ARM: keystone2: Use common structure for PLLs ARM: keystone2: Cleanup init_pll definition ARM: keystone2: Remove unsed external clocks ARM: keystone2: Use common definition for clk_get_rate arch/arm/mach-keystone/Makefile | 3 - arch/arm/mach-keystone/clock-k2e.c | 117 ----- arch/arm/mach-keystone/clock-k2hk.c | 145 ------ arch/arm/mach-keystone/clock-k2l.c | 138 ------ arch/arm/mach-keystone/clock.c | 513 +++++++++++++-------- arch/arm/mach-keystone/cmd_clock.c | 7 +- arch/arm/mach-keystone/include/mach/clock-k2e.h | 58 +-- arch/arm/mach-keystone/include/mach/clock-k2hk.h | 64 +-- arch/arm/mach-keystone/include/mach/clock-k2l.h | 59 +-- arch/arm/mach-keystone/include/mach/clock.h | 67 ++- arch/arm/mach-keystone/include/mach/clock_defs.h | 98 ++-- .../arm/mach-keystone/include/mach/hardware-k2hk.h | 4 - arch/arm/mach-keystone/include/mach/hardware.h | 51 +- arch/arm/mach-keystone/init.c | 32 ++ board/ti/ks2_evm/board.c | 1 - board/ti/ks2_evm/board_k2e.c | 76 ++- board/ti/ks2_evm/board_k2hk.c | 69 +-- board/ti/ks2_evm/board_k2l.c | 68 +-- include/configs/ti_armv7_keystone2.h | 1 + 19 files changed, 663 insertions(+), 908 deletions(-) delete mode 100644 arch/arm/mach-keystone/clock-k2e.c delete mode 100644 arch/arm/mach-keystone/clock-k2hk.c delete mode 100644 arch/arm/mach-keystone/clock-k2l.c -- 2.1.4

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[U-Boot] [PATCH V2 0/3] ARM: DRA74x: Provide support for ARM erratum 801819
by Nishanth Menon 13 Aug '15

13 Aug '15

Provide support ARM erratum 801819 with capability to disable write streaming. Obvioulsy on SMP systems such as DRA74x/OMAP5, this will benefit only CPU0. CPU1 when made online in HLOS such as linux kernel will need similar workaround as well. Ignoring v1 of the patch completely here. Nishanth Menon (3): ARM: Introduce erratum workaround for 801819 ARM: DRA7/ OMAP5: implement Auxiliary Control Register configuration ARM: DRA72: disable workaround for 801819 README | 1 + arch/arm/cpu/armv7/omap5/hwinit.c | 17 +++++++++++++++++ arch/arm/cpu/armv7/start.S | 21 +++++++++++++++++++++ arch/arm/include/asm/arch-omap5/sys_proto.h | 1 + 4 files changed, 40 insertions(+) -- 2.1.4

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[U-Boot] [PATCH 7/7] net: lpc32xx: eth buffers base config
by slemieux.tyco＠gmail.com 13 Aug '15

13 Aug '15

From: Sylvain Lemieux <slemieux(a)tycoint.com> Add support to specify the Ethernet buffer base address; if none are supply by the board, the default value is use (from existing code). Signed-off-by: Sylvain Lemieux <slemieux(a)tycoint.com> --- drivers/net/lpc32xx_eth.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/net/lpc32xx_eth.c b/drivers/net/lpc32xx_eth.c index f3ab0f4..e76e9bc 100644 --- a/drivers/net/lpc32xx_eth.c +++ b/drivers/net/lpc32xx_eth.c @@ -353,15 +353,17 @@ int lpc32xx_eth_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr, #endif /* + * Provide default Ethernet buffers base address if target did not. * Locate buffers in SRAM at 0x00001000 to avoid cache issues and * maximize throughput. */ - -#define LPC32XX_ETH_BUFS 0x00001000 +#if !defined(CONFIG_LPC32XX_ETH_BUFS_BASE) +#define CONFIG_LPC32XX_ETH_BUFS_BASE 0x00001000 +#endif static struct lpc32xx_eth_device lpc32xx_eth = { .regs = (struct lpc32xx_eth_registers *)LPC32XX_ETH_BASE, - .bufs = (struct lpc32xx_eth_buffers *)LPC32XX_ETH_BUFS, + .bufs = (struct lpc32xx_eth_buffers *)CONFIG_LPC32XX_ETH_BUFS_BASE, #if defined(CONFIG_RMII) .phy_rmii = true, #endif -- 1.8.3.1

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[U-Boot] [PATCH 6/7] i2c: lpc32xx: fix write timeout
by slemieux.tyco＠gmail.com 13 Aug '15

13 Aug '15

From: Sylvain Lemieux <slemieux(a)tycoint.com> Fix a condition that generate watchdog timeout inside "lpc32xx_i2c_write" when parameters alen = 0 and len = 0. Signed-off-by: Sylvain Lemieux <slemieux(a)tycoint.com> --- drivers/i2c/lpc32xx_i2c.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c index 4c66769..7f4eccd 100644 --- a/drivers/i2c/lpc32xx_i2c.c +++ b/drivers/i2c/lpc32xx_i2c.c @@ -200,6 +200,8 @@ static int lpc32xx_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, if (alen | length) /* Address slave in write mode */ writel((dev<<1) | LPC32XX_I2C_TX_START, &i2c->tx); + else + return 0; /* write address bytes */ while (alen) { /* wait for transmit fifo not full */ -- 1.8.3.1

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[U-Boot] [PATCH 5/7] i2c: lpc32xx: fix read timeout
by slemieux.tyco＠gmail.com 13 Aug '15

13 Aug '15

From: Sylvain Lemieux <slemieux(a)tycoint.com> Fix a condition that generate watchdog timeout inside "lpc32xx_i2c_read" when parameters alen != 0 and len = 0. Signed-off-by: Sylvain Lemieux <slemieux(a)tycoint.com> --- drivers/i2c/lpc32xx_i2c.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c index 98106fa..4c66769 100644 --- a/drivers/i2c/lpc32xx_i2c.c +++ b/drivers/i2c/lpc32xx_i2c.c @@ -172,12 +172,12 @@ static int lpc32xx_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, *(data++) = readl(&i2c->rx); } } + /* wait for end of transation */ + while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI)) + ; + /* clear end-of-transaction flag */ + writel(1, &i2c->stat); } - /* wait for end of transation */ - while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI)) - ; - /* clear end-of-transaction flag */ - writel(1, &i2c->stat); /* success */ return 0; } -- 1.8.3.1

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[U-Boot] [PATCH 4/7] i2c: lpc32xx: use api to get hclk instead of fix value
by slemieux.tyco＠gmail.com 13 Aug '15

13 Aug '15

From: Sylvain Lemieux <slemieux(a)tycoint.com> The HCLK is not constant and can take different value; use the api function to get the value of the HCLK for the I2C clock high and low computation. Signed-off-by: Sylvain Lemieux <slemieux(a)tycoint.com> --- drivers/i2c/lpc32xx_i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c index 78d26e4..98106fa 100644 --- a/drivers/i2c/lpc32xx_i2c.c +++ b/drivers/i2c/lpc32xx_i2c.c @@ -72,7 +72,7 @@ static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap, if (speed == 0) return -EINVAL; - half_period = (105000000 / speed) / 2; + half_period = (get_hclk_clk_rate() / speed) / 2; if ((half_period > 255) || (half_period < 0)) return -EINVAL; -- 1.8.3.1

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[U-Boot] [PATCH 3/7] arm: lpc32xx: gpio macro for pin mapping
by slemieux.tyco＠gmail.com 13 Aug '15

13 Aug '15

From: Sylvain Lemieux <slemieux(a)tycoint.com> Add LPC32xx GPIO interface macro for pin mapping. Signed-off-by: Sylvain Lemieux <slemieux(a)tycoint.com> --- arch/arm/include/asm/arch-lpc32xx/gpio_grp.h | 40 ++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 arch/arm/include/asm/arch-lpc32xx/gpio_grp.h diff --git a/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h b/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h new file mode 100644 index 0000000..c9cf9df --- /dev/null +++ b/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h @@ -0,0 +1,40 @@ +/* + * LPC32xx GPIO interface macro for pin mapping. + * + * (C) Copyright 2015 DENX Software Engineering GmbH + * Written-by: Sylvain Lemieux <slemieux@@tycoint.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _LPC32XX_GPIO_GRP_H +#define _LPC32XX_GPIO_GRP_H + +/* + * Macro to map the pin for the lpc32xx_gpio driver. + * Note: - GPIOS are considered here as homogeneous and linear, from 0 to 127; + * mapping is done per register, as group of 32. + * (see drivers/gpio/lpc32xx_gpio.c for details). + * - macros can be use with the following pins: + * P0.0 - P0.7 + * P1.0 - P1.23 + * P2.0 - P2.12 + * P3 GPI_0 - GPI_9 / GPI_15 - GPI_23 / GPI_25 / GPI_27 - GPI_28 + * P3 GPO_0 - GPO_23 + * P3 GPIO_0 - GPIO_5 (output register only) + */ +#define LPC32XX_GPIO_P0_GRP 0 +#define LPC32XX_GPIO_P1_GRP 32 +#define LPC32XX_GPIO_P2_GRP 64 +#define LPC32XX_GPI_P3_GRP 96 +#define LPC32XX_GPO_P3_GRP 96 +#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPO_P3_GRP + 25) + +/* + * A specific GPIO can be selected with this macro + * ie, GPIO P0.1 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P0_GRP, 1) + * See the LPC32x0 User's guide for GPIO group numbers + */ +#define LPC32XX_GPIO(x, y) ((x) + (y)) + +#endif /* _LPC32XX_GPIO_GRP_H */ -- 1.8.3.1

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