August 2015 - U-Boot

[U-Boot] [PATCH] ARM: fix the misset of global data pointer
by Masahiro Yamada 17 Aug '15

17 Aug '15

I found some of my boards would not boot since commit 2afddae07523 ("Align global_data to a 16-byte boundary"). Probably, many ARM boards using Generic Board framework are broken, including ARM64 ones. That commit aligned the global data pointer, i.e. inserted some spaces between the gd and the bd. The assembly code in arch/arm/lib/crt0(_64).S must be adjusted because the new gd is no longer just below the bd. Otherwise, r9 (x18) holds a wrong pointer to the global data. This commit uses GD_NEW_GD to directly reference the offset to the new_gd. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- Tom, I guess many ARM boards are broken. This issue should be fixed asap. I confirmed this commit fixes the problem on my boards. Since I have no ARM64 board, I hope somebody could test it for ARM64. arch/arm/lib/crt0.S | 3 +-- arch/arm/lib/crt0_64.S | 3 +-- lib/asm-offsets.c | 2 ++ 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index afd4f10..c7bdfbf 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -119,8 +119,7 @@ clr_gd: #else bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ #endif - ldr r9, [r9, #GD_BD] /* r9 = gd->bd */ - sub r9, r9, #GD_SIZE /* new GD is below bd */ + ldr r9, [r9, #GD_NEW_GD] /* r9 = gd->new_gd */ adr lr, here ldr r0, [r9, #GD_RELOC_OFF] /* r0 = gd->reloc_off */ diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index 98a906e..13960d0 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -90,8 +90,7 @@ zero_gd: */ ldr x0, [x18, #GD_START_ADDR_SP] /* x0 <- gd->start_addr_sp */ bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */ - ldr x18, [x18, #GD_BD] /* x18 <- gd->bd */ - sub x18, x18, #GD_SIZE /* new GD is below bd */ + ldr x18, [x18, #GD_NEW_GD] /* x18 <- gd->new_gd */ adr lr, relocation_return ldr x9, [x18, #GD_RELOC_OFF] /* x9 <- gd->reloc_off */ diff --git a/lib/asm-offsets.c b/lib/asm-offsets.c index 221ebbf..88afedf 100644 --- a/lib/asm-offsets.c +++ b/lib/asm-offsets.c @@ -36,6 +36,8 @@ int main(void) DEFINE(GD_RELOC_OFF, offsetof(struct global_data, reloc_off)); + DEFINE(GD_NEW_GD, offsetof(struct global_data, new_gd)); + DEFINE(GD_START_ADDR_SP, offsetof(struct global_data, start_addr_sp)); return 0; -- 1.9.1

2 1

[U-Boot] Please pull u-boot-x86.git
by Simon Glass 17 Aug '15

17 Aug '15

Hi Tom, This includes various fixes including moving x86 over to use board_init_f_mem() and proper interrupt support on minnowmax. The revert of fdtdec_get_addr_size() is here also. Stephen confirmed it will not affect 64-bit Tegra. Due to problems with Stephen's latest patch (actually more likely problems in the callers!) I need to do more investigation before applying that. The following changes since commit bbc1b99e8b8a1b87c2d0d959a1fcd1990abe82dd: ARM: tegra: represent RAM in 1 or 2 banks (2015-08-13 13:06:04 -0700) are available in the git repository at: git://git.denx.de/u-boot-x86.git for you to fetch changes up to 236efe36be6d1c544f9477f10fdf38a17cd7a869: Revert "fdt: Fix fdtdec_get_addr_size() for 64-bit" (2015-08-14 10:00:52 -0600) ---------------------------------------------------------------- Andrew Bradford (1): x86: baytrail: Configure FSP UPD from device tree Bin Meng (5): common: Display >=4GiB memory bank size x86: baytrail: Add all IDE/SATA PCI device IDs x86: fsp: Do not assert VPD_IMAGE_REV when DEBUG video: vesa: Correct a typo in the Kconfig VESA mode string x86: Set APs' req_seq to the reg number from device tree Simon Glass (22): dm: pci: Provide friendly config access functions dm: pci: Add a way to iterate through all PCI devices x86: Re-order efi-x86_defconfig x86: Tidy up the PIRQ routing code a little x86: Split out fsp_init_phase_pci() code into a new function x86: Allow pirq_init() to return an error x86: baytrail: Tidy up interrupt and FSP init x86: baytrail: Support running as an EFI payload x86: Remove init_gd() function Align global_data to a 16-byte boundary Allow arch-specific setting of global_data in board_init_f_mem() x86: Move the GDT into global_data x86: Switch to using generic global_data setup Revert "dm: pci: Allow scan bridge child devices before relocation" x86: Convert minnowmax to use CONFIG_DM_USB x86: Convert minnowmax to use CONFIG_DM_NET x86: Show the un-relocated IP address in exceptions x86: Drop FSP error defines and use EFI instead x86: Return -1 when reading a PCI config register fails x86: minnowmax: Define and enable interrupt setup x86: Add a simple interrupt script to the README Revert "fdt: Fix fdtdec_get_addr_size() for 64-bit" Stoppa, Igor (1): x86: Add clarifications to the x86 README arch/x86/cpu/baytrail/fsp_configs.c | 162 +++++++++++++++++++++++++++++++++++++++++++---------- arch/x86/cpu/baytrail/valleyview.c | 11 +++- arch/x86/cpu/cpu.c | 11 ++-- arch/x86/cpu/interrupts.c | 2 + arch/x86/cpu/irq.c | 58 ++++++++----------- arch/x86/cpu/mp_init.c | 7 +++ arch/x86/cpu/pci.c | 9 ++- arch/x86/cpu/qemu/qemu.c | 4 +- arch/x86/cpu/quark/quark.c | 4 +- arch/x86/cpu/queensbay/tnc.c | 4 +- arch/x86/cpu/start.S | 95 +++++-------------------------- arch/x86/dts/bayleybay.dts | 38 +++++++++++++ arch/x86/dts/minnowmax.dts | 125 ++++++++++++++++++++++++++++++++++++++++- arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h | 1 - arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h | 1 - arch/x86/include/asm/fsp/fsp_support.h | 7 +++ arch/x86/include/asm/fsp/fsp_types.h | 11 ---- arch/x86/include/asm/global_data.h | 4 +- arch/x86/include/asm/irq.h | 4 +- arch/x86/include/asm/u-boot-x86.h | 1 - arch/x86/lib/fsp/fsp_common.c | 13 +++-- arch/x86/lib/fsp/fsp_support.c | 3 +- board/intel/minnowmax/minnowmax.c | 6 -- common/board_f.c | 20 +++++-- configs/efi-x86_defconfig | 10 ++-- configs/minnowmax_defconfig | 13 +++-- doc/README.x86 | 47 ++++++++++++---- doc/device-tree-bindings/misc/intel,baytrail-fsp.txt | 158 +++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/pci/pci-uclass.c | 140 +++++++++++++++++++++++++++++++++++++++++++++ drivers/video/Kconfig | 2 +- include/asm-generic/global_data.h | 3 +- include/asm-generic/u-boot.h | 4 +- include/common.h | 43 ++++++++++++++ include/configs/bayleybay.h | 3 +- include/configs/minnowmax.h | 7 ++- include/fdtdec.h | 2 + include/pci.h | 43 ++++++++++++++ include/pci_ids.h | 5 +- lib/fdtdec.c | 58 ++++++++----------- 39 files changed, 875 insertions(+), 264 deletions(-) create mode 100644 doc/device-tree-bindings/misc/intel,baytrail-fsp.txt Regards, Simon

2 1

[U-Boot] [PATCH v3] x86: baytrail: Configure FSP UPD from device tree
by Andrew Bradford 17 Aug '15

17 Aug '15

From: Andrew Bradford <andrew.bradford(a)kodakalaris.com> Allow for configuration of FSP UPD from the device tree which will override any settings which the FSP was built with itself. Modify the MinnowMax and BayleyBay boards to transfer sensible UPD settings from the Intel FSPv4 Gold release to the respective dts files, with the condition that the memory-down parameters for MinnowMax are also used. Signed-off-by: Andrew Bradford <andrew.bradford(a)kodakalaris.com> --- Changes from v2: - Switch to using booleans in dts, where appropriate. - Add Bayley Bay dts modifications. - Clarify docs to show bool versus int properties. - Include enable-igt property from FSPv4. Changes from v1: - Use "-" rather than "_" in dt property names. - Use "Bay Trail" for the formal name of the Intel product family. - Use an "fsp," prefix for dt property names for clarity. - Fix minor code indentation issues. - Create a dt subnode for the memory-down-params. - Clarify documentation that dt overrides the FSP's config, so we don't use booleans. arch/x86/cpu/baytrail/fsp_configs.c | 167 +++++++++++++++++---- arch/x86/dts/bayleybay.dts | 40 +++++ arch/x86/dts/minnowmax.dts | 58 +++++++ .../misc/intel,baytrail-fsp.txt | 158 +++++++++++++++++++ include/fdtdec.h | 2 + lib/fdtdec.c | 2 + 6 files changed, 397 insertions(+), 30 deletions(-) create mode 100644 doc/device-tree-bindings/misc/intel,baytrail-fsp.txt diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c index 86b6926..1e5656f 100644 --- a/arch/x86/cpu/baytrail/fsp_configs.c +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -1,14 +1,18 @@ /* * Copyright (C) 2013, Intel Corporation * Copyright (C) 2014, Bin Meng <bmeng.cn(a)gmail.com> + * Copyright (C) 2015, Kodak Alaris, Inc * * SPDX-License-Identifier: Intel */ #include <common.h> +#include <fdtdec.h> #include <asm/arch/fsp/azalia.h> #include <asm/fsp/fsp_support.h> +DECLARE_GLOBAL_DATA_PTR; + /* ALC262 Verb Table - 10EC0262 */ static const uint32_t verb_table_data13[] = { /* Pin Complex (NID 0x11) */ @@ -116,41 +120,144 @@ const struct pch_azalia_config azalia_config = { .reset_wait_timer_us = 300 }; +/** + * Override the FSP's UPD. + * If the device tree does not specify a integer setting, use the default + * provided in Intel's Baytrail_FSP_Gold4.tgz release FSP/BayleyBayFsp.bsf file. + */ void update_fsp_upd(struct upd_region *fsp_upd) { struct memory_down_data *mem; + const void *blob = gd->fdt_blob; + int node; - /* - * Configure everything here to avoid the poor hard-pressed user - * needing to run Intel's binary configuration tool. It may also allow - * us to support the 1GB single core variant easily. - * - * TODO(sjg(a)chromium.org): Move to device tree - */ - fsp_upd->mrc_init_tseg_size = 8; - fsp_upd->mrc_init_mmio_size = 0x800; - fsp_upd->emmc_boot_mode = 0xff; - fsp_upd->enable_sdio = 1; - fsp_upd->enable_sdcard = 1; - fsp_upd->enable_hsuart0 = 1; fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config; - fsp_upd->enable_i2_c0 = 0; - fsp_upd->enable_i2_c2 = 0; - fsp_upd->enable_i2_c3 = 0; - fsp_upd->enable_i2_c4 = 0; - fsp_upd->enable_xhci = 0; - fsp_upd->igd_render_standby = 1; + + node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BAYTRAIL_FSP); + if (node < 0) { + debug("%s: Cannot find FSP node\n", __func__); + return; + } + + fsp_upd->mrc_init_tseg_size = fdtdec_get_int(blob, node, + "fsp,mrc-init-tseg-size", + 0); + fsp_upd->mrc_init_mmio_size = fdtdec_get_int(blob, node, + "fsp,mrc-init-mmio-size", + 0x800); + fsp_upd->mrc_init_spd_addr1 = fdtdec_get_int(blob, node, + "fsp,mrc-init-spd-addr1", + 0xA0); + fsp_upd->mrc_init_spd_addr2 = fdtdec_get_int(blob, node, + "fsp,mrc-init-spd-addr2", + 0xA2); + fsp_upd->emmc_boot_mode = fdtdec_get_int(blob, node, + "fsp,emmc-boot-mode", 2); + fsp_upd->enable_sdio = fdtdec_get_bool(blob, node, "fsp,enable-sdio"); + fsp_upd->enable_sdcard = fdtdec_get_bool(blob, node, + "fsp,enable-sdcard"); + fsp_upd->enable_hsuart0 = fdtdec_get_bool(blob, node, + "fsp,enable-hsuart0"); + fsp_upd->enable_hsuart1 = fdtdec_get_bool(blob, node, + "fsp,enable-hsuart1"); + fsp_upd->enable_spi = fdtdec_get_bool(blob, node, "fsp,enable-spi"); + fsp_upd->enable_sata = fdtdec_get_bool(blob, node, "fsp,enable-sata"); + fsp_upd->sata_mode = fdtdec_get_int(blob, node, "fsp,sata-mode", 1); + fsp_upd->enable_azalia = fdtdec_get_bool(blob, node, + "fsp,enable-azalia"); + fsp_upd->enable_xhci = fdtdec_get_bool(blob, node, "fsp,enable-xhci"); + fsp_upd->enable_lpe = fdtdec_get_bool(blob, node, "fsp,enable-lpe"); + fsp_upd->lpss_sio_enable_pci_mode = fdtdec_get_bool(blob, node, + "fsp,lpss-sio-enable-pci-mode"); + fsp_upd->enable_dma0 = fdtdec_get_bool(blob, node, "fsp,enable-dma0"); + fsp_upd->enable_dma1 = fdtdec_get_bool(blob, node, "fsp,enable-dma1"); + fsp_upd->enable_i2_c0 = fdtdec_get_bool(blob, node, "fsp,enable-i2c0"); + fsp_upd->enable_i2_c1 = fdtdec_get_bool(blob, node, "fsp,enable-i2c1"); + fsp_upd->enable_i2_c2 = fdtdec_get_bool(blob, node, "fsp,enable-i2c2"); + fsp_upd->enable_i2_c3 = fdtdec_get_bool(blob, node, "fsp,enable-i2c3"); + fsp_upd->enable_i2_c4 = fdtdec_get_bool(blob, node, "fsp,enable-i2c4"); + fsp_upd->enable_i2_c5 = fdtdec_get_bool(blob, node, "fsp,enable-i2c5"); + fsp_upd->enable_i2_c6 = fdtdec_get_bool(blob, node, "fsp,enable-i2c6"); + fsp_upd->enable_pwm0 = fdtdec_get_bool(blob, node, "fsp,enable-pwm0"); + fsp_upd->enable_pwm1 = fdtdec_get_bool(blob, node, "fsp,enable-pwm1"); + fsp_upd->enable_hsi = fdtdec_get_bool(blob, node, "fsp,enable-hsi"); + fsp_upd->igd_dvmt50_pre_alloc = fdtdec_get_int(blob, node, + "fsp,igd-dvmt50-pre-alloc", + 2); + fsp_upd->aperture_size = fdtdec_get_int(blob, node, "fsp,aperture-size", + 2); + fsp_upd->gtt_size = fdtdec_get_int(blob, node, "fsp,gtt-size", 2); + fsp_upd->serial_debug_port_address = fdtdec_get_int(blob, node, + "fsp,serial-debug-port-address", + 0x3F8); + fsp_upd->serial_debug_port_type = fdtdec_get_int(blob, node, + "fsp,serial-debug-port-type", + 1); + fsp_upd->mrc_debug_msg = fdtdec_get_bool(blob, node, + "fsp,mrc-debug-msg"); + fsp_upd->isp_enable = fdtdec_get_bool(blob, node, "fsp,isp-enable"); + fsp_upd->scc_enable_pci_mode = fdtdec_get_bool(blob, node, + "fsp,scc-enable-pci-mode"); + fsp_upd->igd_render_standby = fdtdec_get_bool(blob, node, + "fsp,igd-render-standby"); + fsp_upd->txe_uma_enable = fdtdec_get_bool(blob, node, + "fsp,txe-uma-enable"); + fsp_upd->os_selection = fdtdec_get_int(blob, node, "fsp,os-selection", 4); + fsp_upd->emmc45_ddr50_enabled = fdtdec_get_bool(blob, node, + "fsp,emmc45-ddr50-enabled"); + fsp_upd->emmc45_hs200_enabled = fdtdec_get_bool(blob, node, + "fsp,emmc45-hs200-enabled"); + fsp_upd->emmc45_retune_timer_value = fdtdec_get_int(blob, node, + "fsp,emmc45-retune-timer-value", + 8); + fsp_upd->enable_igd = fdtdec_get_bool(blob, node, "fsp,enable-igd"); mem = &fsp_upd->memory_params; - mem->enable_memory_down = 1; - mem->dram_speed = 1; - mem->dimm_width = 1; - mem->dimm_density = 2; - mem->dimm_tcl = 0xb; - mem->dimm_trpt_rcd = 0xb; - mem->dimm_twr = 0xc; - mem->dimm_twtr = 6; - mem->dimm_trrd = 6; - mem->dimm_trtp = 6; - mem->dimm_tfaw = 0x14; + mem->enable_memory_down = fdtdec_get_bool(blob, node, + "fsp,enable-memory-down"); + if (mem->enable_memory_down) { + node = fdtdec_next_compatible(blob, node, + COMPAT_INTEL_BAYTRAIL_FSP_MDP); + if (node < 0) { + debug("%s: Cannot find FSP memory-down-params node\n", + __func__); + } else { + mem->dram_speed = fdtdec_get_int(blob, node, + "fsp,dram-speed", + 0x02); + mem->dram_type = fdtdec_get_int(blob, node, + "fsp,dram-type", 0x01); + mem->dimm_0_enable = fdtdec_get_bool(blob, node, + "fsp,dimm-0-enable"); + mem->dimm_1_enable = fdtdec_get_bool(blob, node, + "fsp,dimm-1-enable"); + mem->dimm_width = fdtdec_get_int(blob, node, + "fsp,dimm-width", + 0x00); + mem->dimm_density = fdtdec_get_int(blob, node, + "fsp,dimm-density", + 0x01); + mem->dimm_bus_width = fdtdec_get_int(blob, node, + "fsp,dimm-bus-width", + 0x03); + mem->dimm_sides = fdtdec_get_int(blob, node, + "fsp,dimm-sides", + 0x00); + mem->dimm_tcl = fdtdec_get_int(blob, node, + "fsp,dimm-tcl", 0x09); + mem->dimm_trpt_rcd = fdtdec_get_int(blob, node, + "fsp,dimm-trpt-rcd", + 0x09); + mem->dimm_twr = fdtdec_get_int(blob, node, + "fsp,dimm-twr", 0x0A); + mem->dimm_twtr = fdtdec_get_int(blob, node, + "fsp,dimm-twtr", 0x05); + mem->dimm_trrd = fdtdec_get_int(blob, node, + "fsp,dimm-trrd", 0x04); + mem->dimm_trtp = fdtdec_get_int(blob, node, + "fsp,dimm-trtp", 0x05); + mem->dimm_tfaw = fdtdec_get_int(blob, node, + "fsp,dimm-tfaw", 0x14); + } + } } diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index 9f8fa70..0ca7c3e 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -188,6 +188,46 @@ }; }; + fsp { + compatible = "intel,baytrail-fsp"; + fsp,mrc-init-tseg-size = <0>; + fsp,mrc-init-mmio-size = <0x800>; + fsp,mrc-init-spd-addr1 = <0xa0>; + fsp,mrc-init-spd-addr2 = <0xa2>; + fsp,emmc-boot-mode = <2>; + fsp,enable-sdio; + fsp,enable-sdcard; + fsp,enable-hsuart1; + fsp,enable-spi; + fsp,enable-sata; + fsp,sata-mode = <1>; + fsp,enable-xhci; + fsp,enable-lpe; + fsp,lpss-sio-enable-pci-mode; + fsp,enable-dma0; + fsp,enable-dma1; + fsp,enable-i2c0; + fsp,enable-i2c1; + fsp,enable-i2c2; + fsp,enable-i2c3; + fsp,enable-i2c4; + fsp,enable-i2c5; + fsp,enable-i2c6; + fsp,enable-pwm0; + fsp,enable-pwm1; + fsp,igd-dvmt50-pre-alloc = <2>; + fsp,aperture-size = <2>; + fsp,gtt-size = <2>; + fsp,serial-debug-port-address = <0x3f8>; + fsp,serial-debug-port-type = <1>; + fsp,mrc-debug-msg; + fsp,scc-enable-pci-mode; + fsp,os-selection = <4>; + fsp,emmc45-ddr50-enabled; + fsp,emmc45-retune-timer-value = <8>; + fsp,enable-igd; + }; + microcode { update@0 { #include "microcode/m0230671117.dtsi" diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 9527233..4c9e265 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -122,6 +122,64 @@ 0x01000000 0x0 0x2000 0x2000 0 0xe000>; }; + fsp { + compatible = "intel,baytrail-fsp"; + fsp,mrc-init-tseg-size = <0>; + fsp,mrc-init-mmio-size = <0x800>; + fsp,mrc-init-spd-addr1 = <0xa0>; + fsp,mrc-init-spd-addr2 = <0xa2>; + fsp,emmc-boot-mode = <2>; + fsp,enable-sdio; + fsp,enable-sdcard; + fsp,enable-hsuart1; + fsp,enable-spi; + fsp,enable-sata; + fsp,sata-mode = <1>; + fsp,enable-xhci; + fsp,enable-lpe; + fsp,lpss-sio-enable-pci-mode; + fsp,enable-dma0; + fsp,enable-dma1; + fsp,enable-i2c0; + fsp,enable-i2c1; + fsp,enable-i2c2; + fsp,enable-i2c3; + fsp,enable-i2c4; + fsp,enable-i2c5; + fsp,enable-i2c6; + fsp,enable-pwm0; + fsp,enable-pwm1; + fsp,igd-dvmt50-pre-alloc = <2>; + fsp,aperture-size = <2>; + fsp,gtt-size = <2>; + fsp,serial-debug-port-address = <0x3f8>; + fsp,serial-debug-port-type = <1>; + fsp,mrc-debug-msg; + fsp,scc-enable-pci-mode; + fsp,os-selection = <4>; + fsp,emmc45-ddr50-enabled; + fsp,emmc45-retune-timer-value = <8>; + fsp,enable-igd; + fsp,enable-memory-down; + fsp,memory-down-params { + compatible = "intel,baytrail-fsp-mdp"; + fsp,dram-speed = <1>; + fsp,dram-type = <1>; + fsp,dimm-0-enable; + fsp,dimm-width = <1>; + fsp,dimm-density = <2>; + fsp,dimm-bus-width = <3>; + fsp,dimm-sides = <0>; + fsp,dimm-tcl = <0xb>; + fsp,dimm-trpt-rcd = <0xb>; + fsp,dimm-twr = <0xc>; + fsp,dimm-twtr = <6>; + fsp,dimm-trrd = <6>; + fsp,dimm-trtp = <6>; + fsp,dimm-tfaw = <0x14>; + }; + }; + spi { #address-cells = <1>; #size-cells = <0>; diff --git a/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt b/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt new file mode 100644 index 0000000..cb9dd04 --- /dev/null +++ b/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt @@ -0,0 +1,158 @@ +Intel Bay Trail FSP UPD Binding +============================== + +The device tree node which describes the overriding of the Intel Bay Trail FSP +UPD data for configuring the SoC. + +All properties can be found within the `upd-region` struct in +arch/x86/include/asm/arch-baytrail/fsp/fsp-vpd.h, under the same names, and in +Intel's FSP Binary Configuration Tool for Bay Trail. This list of properties is +matched up to Intel's E3800 FSPv4 release. + +# Boolean properties: + +- fsp,enable-sdio +- fsp,enable-sdcard +- fsp,enable-hsuart0 +- fsp,enable-hsuart1 +- fsp,enable-spi +- fsp,enable-sata +- fsp,enable-azalia +- fsp,enable-xhci +- fsp,enable-lpe +- fsp,lpss-sio-enable-pci-mode +- fsp,enable-dma0 +- fsp,enable-dma1 +- fsp,enable-i2-c0 +- fsp,enable-i2-c1 +- fsp,enable-i2-c2 +- fsp,enable-i2-c3 +- fsp,enable-i2-c4 +- fsp,enable-i2-c5 +- fsp,enable-i2-c6 +- fsp,enable-pwm0 +- fsp,enable-pwm1 +- fsp,enable-hsi +- fsp,mrc-debug-msg +- fsp,isp-enable +- fsp,scc-enable-pci-mode +- fsp,igd-render-standby +- fsp,txe-uma-enable +- fsp,emmc45-ddr50-enabled +- fsp,emmc45-hs200-enabled +- fsp,enable-igd +- fsp,enable-memory-down + +If you set "fsp,enable-memory-down" you are strongly encouraged to provide an +"fsp,memory-down-params{};" to specify how your memory is configured. If you do +not set "fsp,enable-memory-down", then the DIMM SPD information will be +discovered by the FSP and used to setup main memory. + + +# Integer properties: + +- fsp,mrc-init-tseg-size +- fsp,mrc-init-mmio-size +- fsp,mrc-init-spd-addr1 +- fsp,mrc-init-spd-addr2 +- fsp,emmc-boot-mode +- fsp,sata-mode +- fsp,igd-dvmt50-pre-alloc +- fsp,aperture-size +- fsp,gtt-size +- fsp,serial-debug-port-address +- fsp,serial-debug-port-type +- fsp,os-selection +- fsp,emmc45-retune-timer-value + +- fsp,memory-down-params { + + # Boolean properties: + + - fsp,dimm-0-enable + - fsp,dimm-1-enable + + # Integer properties: + + - fsp,dram-speed + - fsp,dram-type + - fsp,dimm-width + - fsp,dimm-density + - fsp,dimm-bus-width + - fsp,dimm-sides + - fsp,dimm-tcl + - fsp,dimm-trpt-rcd + - fsp,dimm-twr + - fsp,dimm-twtr + - fsp,dimm-trrd + - fsp,dimm-trtp + - fsp,dimm-tfaw +}; + + +Example (from MinnowMax Dual Core): +----------------------------------- + +/ { + ... + + fsp { + compatible = "intel,baytrail-fsp"; + fsp,mrc-init-tseg-size = <0>; + fsp,mrc-init-mmio-size = <0x800>; + fsp,mrc-init-spd-addr1 = <0xa0>; + fsp,mrc-init-spd-addr2 = <0xa2>; + fsp,emmc-boot-mode = <2>; + fsp,enable-sdio; + fsp,enable-sdcard; + fsp,enable-hsuart1; + fsp,enable-spi; + fsp,enable-sata; + fsp,sata-mode = <1>; + fsp,enable-xhci; + fsp,enable-lpe; + fsp,lpss-sio-enable-pci-mode; + fsp,enable-dma0; + fsp,enable-dma1; + fsp,enable-i2c0; + fsp,enable-i2c1; + fsp,enable-i2c2; + fsp,enable-i2c3; + fsp,enable-i2c4; + fsp,enable-i2c5; + fsp,enable-i2c6; + fsp,enable-pwm0; + fsp,enable-pwm1; + fsp,igd-dvmt50-pre-alloc = <2>; + fsp,aperture-size = <2>; + fsp,gtt-size = <2>; + fsp,serial-debug-port-address = <0x3f8>; + fsp,serial-debug-port-type = <1>; + fsp,mrc-debug-msg; + fsp,scc-enable-pci-mode; + fsp,os-selection = <4>; + fsp,emmc45-ddr50-enabled; + fsp,emmc45-retune-timer-value = <8>; + fsp,enable-igd; + fsp,enable-memory-down; + fsp,memory-down-params { + compatible = "intel,baytrail-fsp-mdp"; + fsp,dram-speed = <1>; + fsp,dram-type = <1>; + fsp,dimm-0-enable; + fsp,dimm-width = <1>; + fsp,dimm-density = <2>; + fsp,dimm-bus-width = <3>; + fsp,dimm-sides = <0>; + fsp,dimm-tcl = <0xb>; + fsp,dimm-trpt-rcd = <0xb>; + fsp,dimm-twr = <0xc>; + fsp,dimm-twtr = <6>; + fsp,dimm-trrd = <6>; + fsp,dimm-trtp = <6>; + fsp,dimm-tfaw = <0x14>; + }; + }; + + ... +}; diff --git a/include/fdtdec.h b/include/fdtdec.h index 4b3f8d1..987d51a 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -186,6 +186,8 @@ enum fdt_compat_id { COMPAT_SOCIONEXT_XHCI, /* Socionext UniPhier xHCI */ COMPAT_INTEL_PCH, /* Intel PCH */ COMPAT_INTEL_IRQ_ROUTER, /* Intel Interrupt Router */ + COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */ + COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel Bay Trail FSP memory-down params */ COMPAT_COUNT, }; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 48667ef..42e8a8b 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -78,6 +78,8 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(SOCIONEXT_XHCI, "socionext,uniphier-xhci"), COMPAT(COMPAT_INTEL_PCH, "intel,bd82x6x"), COMPAT(COMPAT_INTEL_IRQ_ROUTER, "intel,irq-router"), + COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"), + COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"), }; const char *fdtdec_get_compatible(enum fdt_compat_id id) -- 1.9.1

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[U-Boot] [PATCH 1/7] arm: lpc32xx: mux: add missing registers
by slemieux.tyco＠gmail.com 17 Aug '15

17 Aug '15

From: Sylvain Lemieux <slemieux(a)tycoint.com> Add missing registers in struct definition. Update GPIO MUX base register to match GPIO base (refer to "LPC32x0 User manual" Rev. 3 - 22 July 2011). Signed-off-by: Sylvain Lemieux <slemieux(a)tycoint.com> --- arch/arm/include/asm/arch-lpc32xx/cpu.h | 2 +- arch/arm/include/asm/arch-lpc32xx/mux.h | 17 +++++++++++++++++ 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-lpc32xx/cpu.h b/arch/arm/include/asm/arch-lpc32xx/cpu.h index 0b5dca1..0de894b 100644 --- a/arch/arm/include/asm/arch-lpc32xx/cpu.h +++ b/arch/arm/include/asm/arch-lpc32xx/cpu.h @@ -27,7 +27,7 @@ #define HS_UART7_BASE 0x4001C000 /* High speed UART 7 registers base */ #define RTC_BASE 0x40024000 /* RTC registers base */ #define GPIO_BASE 0x40028000 /* GPIO registers base */ -#define MUX_BASE 0x40028100 /* MUX registers base */ +#define MUX_BASE 0x40028000 /* MUX registers base */ #define WDT_BASE 0x4003C000 /* Watchdog timer registers base */ #define TIMER0_BASE 0x40044000 /* Timer0 registers base */ #define TIMER1_BASE 0x4004C000 /* Timer1 registers base */ diff --git a/arch/arm/include/asm/arch-lpc32xx/mux.h b/arch/arm/include/asm/arch-lpc32xx/mux.h index dc1b5bc..665ea3f 100644 --- a/arch/arm/include/asm/arch-lpc32xx/mux.h +++ b/arch/arm/include/asm/arch-lpc32xx/mux.h @@ -12,7 +12,24 @@ */ struct mux_regs { + u32 reserved1[10]; + u32 p2_mux_set; + u32 p2_mux_clr; + u32 p2_mux_state; + u32 reserved2[51]; u32 p_mux_set; u32 p_mux_clr; u32 p_mux_state; + u32 reserved3; + u32 p3_mux_set; + u32 p3_mux_clr; + u32 p3_mux_state; + u32 reserved4; + u32 p0_mux_set; + u32 p0_mux_clr; + u32 p0_mux_state; + u32 reserved5; + u32 p1_mux_set; + u32 p1_mux_clr; + u32 p1_mux_state; }; -- 1.8.3.1

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[U-Boot] [PATCH 0/6] sf: BAR/wait_ready logic updates
by Jagan Teki 17 Aug '15

17 Aug '15

BAR and spi_flash_cmd_wait_ready are updated to make more module to add new status checks. Jagan Teki (6): spi: zynq_spi: Remove unneeded headers sf: Return proper bank_sel, if flash->bank_curr == bank_sel sf: Make BAR discovery, as spi_flash_read_bar sf: Optimize BAR write code sf: Make flash->flags use for generic usage sf: Update spi_flash_cmd_wait_ready drivers/mtd/spi/sf_internal.h | 5 ++ drivers/mtd/spi/sf_ops.c | 153 +++++++++++++++++++++--------------------- drivers/mtd/spi/sf_probe.c | 64 +++++++++++------- drivers/spi/zynq_spi.c | 6 +- include/spi_flash.h | 6 +- 5 files changed, 121 insertions(+), 113 deletions(-) -- 1.9.1

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[U-Boot] git fetch fails, and patchwork not updating
by Bin Meng 17 Aug '15

17 Aug '15

Hi, I noticed that this morning when I do git fetch it always fails with "Connection reset by peer" message. $ git fetch x86 fatal: read error: Connection reset by peer Also patchwork is not updating any new patches. I guess the denx.ge server is running into some problems again. Regards, Bin

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[U-Boot] [PATCH] Remove odroid_xu3.h.rej
by Masahiro Yamada 17 Aug '15

17 Aug '15

This file was accidentally added by commit 181bd9dc61d2 ("kconfig: add config option for shell prompt"). Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- include/configs/odroid_xu3.h.rej | 10 ---------- 1 file changed, 10 deletions(-) delete mode 100644 include/configs/odroid_xu3.h.rej diff --git a/include/configs/odroid_xu3.h.rej b/include/configs/odroid_xu3.h.rej deleted file mode 100644 index a1c2964..0000000 --- a/include/configs/odroid_xu3.h.rej +++ /dev/null @@ -1,10 +0,0 @@ ---- include/configs/odroid_xu3.h -+++ include/configs/odroid_xu3.h -@@ -10,7 +10,6 @@ - - #include "exynos5420-common.h" - --#define CONFIG_SYS_PROMPT "ODROID-XU3 # " - #define CONFIG_IDENT_STRING " for ODROID-XU3" - - #define CONFIG_BOARD_COMMON -- 1.9.1

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[U-Boot] ARM: sunxi: Experiences NAND flash
by Olliver Schinagl 17 Aug '15

17 Aug '15

Hello everybody, We are working with Boris and Roy's patch series on getting the NAND flash chip working on Olimex OLinuXino Lime2 boards. Initially, everything looks fine, but we noticed that occasionally (after power/cycle or power cut) ubi fails to mount the partition. It is not something easily enough to reproduce, but it has failed on 5 boards out of 30 we have. U-boot reports the following: UBI: default fastmap pool size: 100 UBI: default fastmap WL pool size: 25 UBI: attaching mtd1 to ubi0 UBI: scanning is finished UBI init error 22 Error reading superblock on volume 'ubi:boot' errno=-19! ubifsmount - mount UBIFS volume whereas the linux kernel booted from sd card gives: ubiattach /dev/ubi_ctrl -m 0 [ 100.560704] ubi0: default fastmap pool size: 8 [ 100.565186] ubi0: default fastmap WL pool size: 4 [ 100.570100] ubi0: attaching mtd0 [ 100.590469] ubi0: scanning is finished [ 100.594732] ubi0 error: ubi_read_volume_table: the layout volume was not found [ 100.602675] ubi0 error: ubi_attach_mtd_dev: failed to attach mtd0, error -22 ubiattach: error!: cannot attach mtd0 error 22 (Invalid argument) The u-boot version we are using is a few months out of date U-Boot 2015.07-rc2-g2540c39 (Aug 04 2015 - 16:09:02 +0200) Allwinner Technology arm-none-eabi-gcc (4.8.4-1+11-1) 4.8.4 20141219 (release) GNU ld (2.25-5+5+b1) 2.25 but the kernel is fairly up to date: 4.2.0-rc4-opinicus-g8ec3671 Now I know that the mtd stuff is all very new and all very untested, what I am curious about is a) have other people actually tried the mtd stuff on Allwinner hardware, and b) has anybody encountered this issue as well? It's not something very easily reproducible (toggling a machine on/off repeatedly did not trigger it yet) but it does happen. Olliver

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[U-Boot] [PATCH 1/3] sunxi: musb: Drop no longer accurate comment in Kconfig help text
by Hans de Goede 17 Aug '15

17 Aug '15

Drop the no longer accurate part of the USB_MUSB_SUNXI Kconfig help text, since the musb-host code now supports the device-model, ehci and musb in host mode can both be enabled at the same time without issues. Signed-off-by: Hans de Goede <hdegoede(a)redhat.com> --- drivers/usb/musb-new/Kconfig | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig index 0082ff8..6a6cb93 100644 --- a/drivers/usb/musb-new/Kconfig +++ b/drivers/usb/musb-new/Kconfig @@ -21,8 +21,6 @@ config USB_MUSB_SUNXI default y ---help--- Say y here to enable support for the sunxi OTG / DRC USB controller - used on almost all sunxi boards. Note currently u-boot can only have - one usb host controller enabled at a time, so enabling this on boards - which also use the ehci host controller will result in build errors. + used on almost all sunxi boards. endif -- 2.4.3

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[U-Boot] [PATCH 0/9] imx: mx6: support LPDDR2 and add mx6slevk spl
by Peng Fan 17 Aug '15

17 Aug '15

This patch set is to support SPL for mx6slevk board. But mx6slevk features one LPDDR2 chip. Then we need to first add LPDDR2 SPL support. Also introduce one ddr_type entry to differentiate DDR3 and LPDDR2. This patch set also correct tRFC and tXS for DDR3 4Gb chip. The LPDDR2 part is implemented referencing MX6SL LPDDR2 Script Aid V0.04.xlsx and JESD209-2E. I am not DDR expert, can not guarantee that this can achieve production quality. Please review. Patchset tested boot on mx6sxsabresd revb and mx6slevk board. Peng Fan (9): imx: mx6: ddr add more register entry for mmdc_p_regs imx: mx6: ddr no support MMDC1 for i.MX6SL imx: mx6: ddr correct tRFC and tXS imx: mx6: ddr add dram io configuration and header file for i.MX6SL imx: mx6: ddr add mpzqlp2ctl entry imx: mx6: ddr add an entry ddr_type for mx6_ddr_sysinfo imx: mx6: ddr init MMDC according to ddr_type imx: mx6: ddr: add LPDDR2 support imx: mx6slevk: add SPL support arch/arm/cpu/armv7/mx6/Kconfig | 1 + arch/arm/cpu/armv7/mx6/ddr.c | 379 +++++++++++++++++++++- arch/arm/include/asm/arch-mx6/mx6-ddr.h | 135 +++++++- arch/arm/include/asm/arch-mx6/mx6sl-ddr.h | 45 +++ board/barco/platinum/spl_picon.c | 1 + board/barco/platinum/spl_titanium.c | 1 + board/freescale/mx6sabresd/mx6sabresd.c | 1 + board/freescale/mx6slevk/mx6slevk.c | 164 ++++++++++ board/freescale/mx6sxsabresd/mx6sxsabresd.c | 1 + board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 1 + board/gateworks/gw_ventana/gw_ventana_spl.c | 1 + board/solidrun/mx6cuboxi/mx6cuboxi.c | 1 + configs/mx6slevk_spl_defconfig | 8 + include/configs/imx6_spl.h | 2 +- include/configs/mx6slevk.h | 7 + 15 files changed, 728 insertions(+), 20 deletions(-) create mode 100644 arch/arm/include/asm/arch-mx6/mx6sl-ddr.h create mode 100644 configs/mx6slevk_spl_defconfig -- 1.8.4

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