August 2015 - U-Boot

[U-Boot] [PATCH 5/5] x86: crownbay: Enable on-board SMSC superio keyboard controller
by Bin Meng 18 Aug '15

18 Aug '15

So far we only enabled one legacy serial port on the SMSC LPC47m superio chipset on Intel Crown Bay board. As the board also has dual PS/2 ports routed out, enable the keyboard controller which is i8042 compatible so that we can use PS/2 keyboard and mouse. In order to make PS/2 keyboard work with the VGA console, remove CONFIG_VGA_AS_SINGLE_DEVICE. To boot Linux kernel with PIC mode using PIRQ routing table, adjust the mask in the device tree to reserve irq12 which is used by PS/2 mouse. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/dts/crownbay.dts | 2 +- board/intel/crownbay/crownbay.c | 7 ++++--- include/configs/crownbay.h | 3 --- 3 files changed, 5 insertions(+), 7 deletions(-) diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts index 841f47e..6eb55d9 100644 --- a/arch/x86/dts/crownbay.dts +++ b/arch/x86/dts/crownbay.dts @@ -168,7 +168,7 @@ compatible = "intel,irq-router"; intel,pirq-config = "pci"; intel,pirq-link = <0x60 8>; - intel,pirq-mask = <0xdee0>; + intel,pirq-mask = <0xcee0>; intel,pirq-routing = < /* TunnelCreek PCI devices */ PCI_BDF(0, 2, 0) INTA PIRQE diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c index ad2d5b6..d6de9fa 100644 --- a/board/intel/crownbay/crownbay.c +++ b/board/intel/crownbay/crownbay.c @@ -10,11 +10,12 @@ #include <netdev.h> #include <smsc_lpc47m.h> -#define SERIAL_DEV PNP_DEV(0x2e, 4) - int board_early_init_f(void) { - lpc47m_enable_serial(SERIAL_DEV, UART0_BASE, UART0_IRQ); + lpc47m_enable_serial(PNP_DEV(LPC47M_IO_PORT, LPC47M_SP1), + UART0_BASE, UART0_IRQ); + lpc47m_enable_kbc(PNP_DEV(LPC47M_IO_PORT, LPC47M_KBC), + KBD_IRQ, MSE_IRQ); return 0; } diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index e87bd54..32b6006 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -54,9 +54,6 @@ #define CONFIG_PCH_GBE #define CONFIG_PHYLIB -/* TunnelCreek IGD support */ -#define CONFIG_VGA_AS_SINGLE_DEVICE - /* Environment configuration */ #define CONFIG_ENV_SECT_SIZE 0x1000 #define CONFIG_ENV_OFFSET 0 -- 1.8.2.1

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[U-Boot] [PATCH 2/5] x86: i8042: Correctly initialize the controller
by Bin Meng 18 Aug '15

18 Aug '15

The existing i8042 keyboard controller driver has some issues. First of all, it does not issue a self-test command (0xaa) to the controller at the very beginning. Without this, the controller does not respond any command at all. Secondly, it initializes the configuration byte reigster to turn on keyboard's interrupt, which is not allowed as U-Boot we don't normally enable interrupt. Finally, at the end of the initialization routine, it wrongly sets the controller to disable all interfaces including both keyboard and mouse. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- drivers/input/i8042.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/drivers/input/i8042.c b/drivers/input/i8042.c index 1769c5e..3799580 100644 --- a/drivers/input/i8042.c +++ b/drivers/input/i8042.c @@ -664,6 +664,18 @@ static int wait_until_kbd_output_full(void) static int kbd_reset(void) { + /* controller self test */ + if (kbd_input_empty() == 0) + return -1; + + out8(I8042_COMMAND_REG, 0xaa); + + if (wait_until_kbd_output_full() == 0) + return -1; + + if (in8(I8042_DATA_REG) != 0x55) /* success */ + return -1; + /* KB Reset */ if (kbd_input_empty() == 0) return -1; @@ -691,7 +703,7 @@ static int kbd_reset(void) if (kbd_input_empty() == 0) return -1; - out8(I8042_DATA_REG, 0x45); + out8(I8042_DATA_REG, 0x44); if (kbd_input_empty() == 0) return -1; @@ -701,13 +713,5 @@ static int kbd_reset(void) if (kbd_input_empty() == 0) return -1; - out8(I8042_COMMAND_REG, 0x60); - if (kbd_input_empty() == 0) - return -1; - - out8(I8042_DATA_REG, 0xf4); - if (kbd_input_empty() == 0) - return -1; - return 0; } -- 1.8.2.1

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[U-Boot] [PATCH v3 00/16] spi: zynq qspi support
by Jagan Teki 18 Aug '15

18 Aug '15

These are the last two version patches links. https://patchwork.ozlabs.org/patch/302945/ https://patchwork.ozlabs.org/patch/264440/ This series adds zynq qspi controller driver in driver model and enabled support on relevent zynq boards and tested the same. Branch to verify: $ git clone git://git.denx.de/u-boot-spi.git $ cd u-boot-spi $ git checkout -b spi-nor spi-nor Changes for v3: - Added driver-model to zynq-qspi driver - devicetree support on zynq-qspi - Enabled qspi nodes on relevent board dts files - Enabled qspi driver on relevent board config files Changes for v3: - Fixes with macro's addition Jagan Teki (16): spi: Add zynq qspi controller driver dts: zynq: Add zynq qspi controller nodes doc: device-tree-bindings: spi: Add zynq qspi info dts: microzed: Enable zynq qspi controller node dts: zc702: Enable zynq qspi controller node dts: zc706: Enable zynq qspi controller node dts: zc770-xm010: Enable zynq qspi controller node dts: zed: Enable zynq qspi controller node configs: Enable legacy SPI flash interface support zynq-common: Enable zynq qspi controller support zynq-common: Enable Bank/Extended address register support configs: zynq: Enable zynq qspi controller spi: Kconfig: Add Zynq QSPI controller entry spi: zynq_spi: Add config reg shift named macros spi: zynq_spi: Rename baudrate divisor mask name spi: zynq_spi: Store cs value into private data arch/arm/dts/zynq-7000.dtsi | 12 + arch/arm/dts/zynq-microzed.dts | 5 + arch/arm/dts/zynq-zc702.dts | 5 + arch/arm/dts/zynq-zc706.dts | 5 + arch/arm/dts/zynq-zc770-xm010.dts | 5 + arch/arm/dts/zynq-zed.dts | 5 + configs/zynq_microzed_defconfig | 2 + configs/zynq_zc702_defconfig | 2 + configs/zynq_zc706_defconfig | 2 + configs/zynq_zc70x_defconfig | 2 + configs/zynq_zc770_xm010_defconfig | 1 + configs/zynq_zed_defconfig | 2 + doc/device-tree-bindings/spi/spi-zynq-qspi.txt | 26 ++ drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/zynq_qspi.c | 622 +++++++++++++++++++++++++ drivers/spi/zynq_spi.c | 20 +- include/configs/zynq-common.h | 10 + 18 files changed, 729 insertions(+), 7 deletions(-) create mode 100644 doc/device-tree-bindings/spi/spi-zynq-qspi.txt create mode 100644 drivers/spi/zynq_qspi.c -- 1.9.1

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[U-Boot] Please pull u-boot-marvell master
by Luka Perkov 18 Aug '15

18 Aug '15

Hi Tom, pull containes patches from Stefan and Anton that have been posted on the mailing list a while back. The newest feature is PCI support on mvebu. The following changes since commit 58243001a9419d9d1671e32611b7d15f6ed64b3a: i2c: lpc32xx: fix write timeout (2015-08-17 08:11:50 -0400) are available in the git repository at: git://git.denx.de/u-boot-marvell.git for you to fetch changes up to ce2cb1d3ed92e91b24db516802be3688f7c28e26: arm: mvebu: db-88f6820-gp: Enable PCI support (2015-08-17 18:49:52 +0200) ---------------------------------------------------------------- Anton Schubert (2): arm: mvebu: add multiple usb-hostcontroller support for AXP pci: mvebu: Add PCIe driver Stefan Roese (16): arm: mvebu/armada100: dram.c: Remove CONFIG_SYS_BOARD_DRAM_INIT arm: mvebu: sdram: Enable ECC support on Armada XP arm: mvebu: db-mv784mp-gp.h: Fix image creation - use correct offset arm: mvebu: Change MBUS base addresses and sizes arm: mvebu: Setup the MBUS bridge registers arm: mvebu: Flush caches and disable MMU only on A38x arm: mvebu: Disable MBUS error propagation arm: mvebu: Enable NAND controller on MVEBU SoC's arm: mvebu: Enable USB EHCI support on Armada XP arm: mvebu: db-mv785mp-gp: Add USB/EHCI support arm: mvebu: Display ECC enabled / disabled upon bootup arm: mvebu: Move CONFIG_SYS_TEXT_BASE to an address < 16 MiB arm: mvebu: dram.c: Rework dram_init() and dram_init_banksize() arm: mvebu: Add complete SDRAM ECC scrubbing arm: mvebu: db-mv784mp-gp: Enable PCI support arm: mvebu: db-88f6820-gp: Enable PCI support arch/arm/cpu/arm926ejs/armada100/dram.c | 2 - arch/arm/mach-mvebu/Makefile | 4 + arch/arm/mach-mvebu/cpu.c | 103 +++++-- arch/arm/mach-mvebu/dram.c | 180 +++++++++++- arch/arm/mach-mvebu/include/mach/cpu.h | 13 +- arch/arm/mach-mvebu/include/mach/soc.h | 29 ++ arch/arm/mach-mvebu/mbus.c | 57 +++- board/Marvell/db-88f6820-gp/db-88f6820-gp.c | 9 +- board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c | 9 +- drivers/ddr/marvell/axp/ddr3_axp_config.h | 2 +- drivers/ddr/marvell/axp/xor.c | 3 +- drivers/ddr/marvell/axp/xor.h | 1 + drivers/net/mvneta.c | 1 - drivers/pci/Makefile | 1 + drivers/pci/pci_mvebu.c | 423 ++++++++++++++++++++++++++++ drivers/usb/host/ehci-marvell.c | 28 +- include/configs/db-88f6820-gp.h | 15 +- include/configs/db-mv784mp-gp.h | 24 +- include/configs/maxbcm.h | 7 +- 19 files changed, 855 insertions(+), 56 deletions(-) create mode 100644 drivers/pci/pci_mvebu.c Regards, Luka

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[U-Boot] [PATCH v5 3/6] net: e1000: Convert to driver model
by Simon Glass 18 Aug '15

18 Aug '15

Update this driver to support driver model. Signed-off-by: Simon Glass <sjg(a)chromium.org> Acked-by: Joe Hershberger <joe.hershberger(a)ni.com> Tested-by: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> Tested-on: Apalis T30 2GB on Apalis Evaluation Board --- Changes in v5: - Correct compatible string Changes in v4: None Changes in v3: - Add a comment as to why netdev.h cannot be included - Fix 'nove' typo and nCONFIG_DM_ETH #ifdef style Changes in v2: None drivers/net/e1000.c | 139 +++++++++++++++++++++++++++++++++++++++++++++++++++- drivers/net/e1000.h | 5 ++ 2 files changed, 143 insertions(+), 1 deletion(-) diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index e9a064d..3b4177a 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -1,4 +1,4 @@ -/************************************************************************** +B/************************************************************************** Intel Pro 1000 for ppcboot/das-u-boot Drivers are port from Intel's Linux driver e1000-4.3.15 and from Etherboot pro 1000 driver by mrakes at vivato dot net @@ -30,6 +30,7 @@ tested on both gig copper and gig fiber boards */ #include <common.h> +#include <dm.h> #include <errno.h> #include <pci.h> #include "e1000.h" @@ -47,12 +48,21 @@ tested on both gig copper and gig fiber boards /* Intel i210 needs the DMA descriptor rings aligned to 128b */ #define E1000_BUFFER_ALIGN 128 +/* + * TODO(sjg(a)chromium.org): Even with driver model we share these buffers. + * Concurrent receiving on multiple active Ethernet devices will not work. + * Normally U-Boot does not support this anyway. To fix it in this driver, + * move these buffers and the tx/rx pointers to struct e1000_hw. + */ DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN); DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN); DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN); static int tx_tail; static int rx_tail, rx_last; +#ifdef CONFIG_DM_ETH +static int num_cards; /* Number of E1000 devices seen so far */ +#endif static struct pci_device_id e1000_supported[] = { { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542) }, @@ -5295,8 +5305,10 @@ void e1000_get_bus_type(struct e1000_hw *hw) } } +#ifndef CONFIG_DM_ETH /* A list of all registered e1000 devices */ static LIST_HEAD(e1000_hw_list); +#endif static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno, unsigned char enetaddr[6]) @@ -5383,6 +5395,7 @@ static void e1000_name(char *str, int cardnum) sprintf(str, "e1000#%u", cardnum); } +#ifndef CONFIG_DM_ETH /************************************************************************** TRANSMIT - Transmit a frame ***************************************************************************/ @@ -5495,13 +5508,22 @@ struct e1000_hw *e1000_find_card(unsigned int cardnum) return NULL; } +#endif /* !CONFIG_DM_ETH */ #ifdef CONFIG_CMD_E1000 static int do_e1000(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { unsigned char *mac = NULL; +#ifdef CONFIG_DM_ETH + struct eth_pdata *plat; + struct udevice *dev; + char name[30]; + int ret; +#else struct e1000_hw *hw; +#endif + int cardnum; if (argc < 3) { cmd_usage(cmdtp); @@ -5510,9 +5532,18 @@ static int do_e1000(cmd_tbl_t *cmdtp, int flag, /* Make sure we can find the requested e1000 card */ cardnum = simple_strtoul(argv[1], NULL, 10); +#ifdef CONFIG_DM_ETH + e1000_name(name, cardnum); + ret = uclass_get_device_by_name(UCLASS_ETH, name, &dev); + if (!ret) { + plat = dev_get_platdata(dev); + mac = plat->enetaddr; + } +#else hw = e1000_find_card(cardnum); if (hw) mac = hw->nic->enetaddr; +#endif if (!mac) { printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]); return 1; @@ -5547,3 +5578,109 @@ U_BOOT_CMD( " - Manage the Intel E1000 PCI device" ); #endif /* not CONFIG_CMD_E1000 */ + +#ifdef CONFIG_DM_ETH +static int e1000_eth_start(struct udevice *dev) +{ + struct eth_pdata *plat = dev_get_platdata(dev); + struct e1000_hw *hw = dev_get_priv(dev); + + return _e1000_init(hw, plat->enetaddr); +} + +static void e1000_eth_stop(struct udevice *dev) +{ + struct e1000_hw *hw = dev_get_priv(dev); + + _e1000_disable(hw); +} + +static int e1000_eth_send(struct udevice *dev, void *packet, int length) +{ + struct e1000_hw *hw = dev_get_priv(dev); + int ret; + + ret = _e1000_transmit(hw, packet, length); + + return ret ? 0 : -ETIMEDOUT; +} + +static int e1000_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct e1000_hw *hw = dev_get_priv(dev); + int len; + + len = _e1000_poll(hw); + if (len) + *packetp = packet; + + return len ? len : -EAGAIN; +} + +static int e1000_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct e1000_hw *hw = dev_get_priv(dev); + + fill_rx(hw); + + return 0; +} + +static int e1000_eth_probe(struct udevice *dev) +{ + struct eth_pdata *plat = dev_get_platdata(dev); + struct e1000_hw *hw = dev_get_priv(dev); + int ret; + + hw->name = dev->name; + ret = e1000_init_one(hw, trailing_strtol(dev->name), pci_get_bdf(dev), + plat->enetaddr); + if (ret < 0) { + printf(pr_fmt("failed to initialize card: %d\n"), ret); + return ret; + } + + return 0; +} + +static int e1000_eth_bind(struct udevice *dev) +{ + char name[20]; + + /* + * A simple way to number the devices. When device tree is used this + * is unnecessary, but when the device is just discovered on the PCI + * bus we need a name. We could instead have the uclass figure out + * which devices are different and number them. + */ + e1000_name(name, num_cards++); + + return device_set_name(dev, name); +} + +static const struct eth_ops e1000_eth_ops = { + .start = e1000_eth_start, + .send = e1000_eth_send, + .recv = e1000_eth_recv, + .stop = e1000_eth_stop, + .free_pkt = e1000_free_pkt, +}; + +static const struct udevice_id e1000_eth_ids[] = { + { .compatible = "intel,e1000" }, + { } +}; + +U_BOOT_DRIVER(eth_e1000) = { + .name = "eth_e1000", + .id = UCLASS_ETH, + .of_match = e1000_eth_ids, + .bind = e1000_eth_bind, + .probe = e1000_eth_probe, + .ops = &e1000_eth_ops, + .priv_auto_alloc_size = sizeof(struct e1000_hw), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; + +U_BOOT_PCI_DEVICE(eth_e1000, e1000_supported); +#endif diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index da04cab..c851922 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -22,7 +22,10 @@ #include <linux/list.h> #include <malloc.h> #include <net.h> +/* Avoids a compile error since struct eth_device is not defined */ +#ifndef CONFIG_DM_ETH #include <netdev.h> +#endif #include <asm/io.h> #include <pci.h> @@ -1073,7 +1076,9 @@ typedef enum { struct e1000_hw { const char *name; struct list_head list_node; +#ifndef CONFIG_DM_ETH struct eth_device *nic; +#endif #ifdef CONFIG_E1000_SPI struct spi_slave spi; #endif -- 2.5.0.276.gf5e568e

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[U-Boot] [PATCH 00/11] x86: Improve U-Boot as the coreboot payload support
by Bin Meng 18 Aug '15

18 Aug '15

This series adds some improvment to the existing coreboot support, like >=4GiB memory support, correct E820 table report, don't bother configure system tables in Kconfig and support booting Linux kernel with a working graphics console. Tested on Intel Bayley Bay, U-Boot loaded by coreboot as a payload. Bin Meng (11): x86: doc: Update coreboot payload entry point address x86: coreboot: Increase memrange entry number to 32 x86: coreboot: Correctly report E820 types x86: Remove calculate_relocation_address() x86: coreboot: Allow >=4GiB memory bank size x86: kconfig: Hide "System tables" for EFI x86: kconfig: Hide "System tables" for coreboot x86: Only include cbfs command for coreboot x86: Enable CONFIG_PCI_CONFIG_HOST_BRIDGE for all boards video: coreboot: Save VESA mode for future use x86: Set up video framebuffer for coreboot before loading kernel arch/x86/Kconfig | 4 +-- arch/x86/cpu/coreboot/sdram.c | 33 ++++++++++-------- arch/x86/include/asm/arch-coreboot/sysinfo.h | 9 ++--- arch/x86/include/asm/init_helpers.h | 2 -- arch/x86/lib/init_helpers.c | 51 +--------------------------- doc/README.x86 | 6 ++-- drivers/pci/pci_rom.c | 4 +-- drivers/video/coreboot_fb.c | 24 +++++++++++++ include/configs/bayleybay.h | 1 - include/configs/crownbay.h | 1 - include/configs/minnowmax.h | 1 - include/configs/qemu-x86.h | 1 - include/configs/x86-common.h | 3 ++ include/vbe.h | 2 ++ 14 files changed, 56 insertions(+), 86 deletions(-) -- 1.8.2.1

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[U-Boot] [PATCH v2] efi: Update README.efi to clarify build and test instructions
by Bin Meng 18 Aug '15

18 Aug '15

The doc has a misleading 'make menuconfig' when building the EFI application and payload. Clarify this and also update information on test with QEMU. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- Changes in v2: - incorporate comments from Igor, clarify boolean options doc/README.efi | 32 +++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-) diff --git a/doc/README.efi b/doc/README.efi index 7c95579..38b9ab1 100644 --- a/doc/README.efi +++ b/doc/README.efi @@ -47,20 +47,25 @@ machine. You can use devices, boot a kernel, etc. Build Instructions ------------------ First choose a board that has EFI support and obtain an EFI implementation -for that board. It will be either 32-bit or 64-bit. +for that board. It will be either 32-bit or 64-bit. Alternatively, you can +opt for using QEMU [1] and the OVMF [2], as detailed below. -To build U-Boot as an EFI application (32-bit EFI required), enable -CONFIG_EFI and CONFIG_EFI_APP. The efi-x86 config is set up for this. +To build U-Boot as an EFI application (32-bit EFI required), enable CONFIG_EFI +and CONFIG_EFI_APP. The efi-x86 config (efi-x86_defconfig) is set up for this. -To build U-Boot as an EFI payload (32-bit or 64-bit EFI can be used), adjust -an existing config to enable CONFIG_EFI, CONFIG_EFI_STUB and either -CONFIG_EFI_STUB_32BIT or CONFIG_EFI_STUB_64BIT. +To build U-Boot as an EFI payload (32-bit or 64-bit EFI can be used), adjust an +existing config (like qemu-x86_defconfig) to enable CONFIG_EFI, CONFIG_EFI_STUB +and either CONFIG_EFI_STUB_32BIT or CONFIG_EFI_STUB_64BIT. All of these are +boolean Kconfig options. Then build U-Boot as normal, e.g. +For building an EFI application, run: + make efi-x86_defconfig + make + +For building an EFI payload, run: make qemu-x86_defconfig - make menuconfig (or make xconfig if you prefer) - # change the settings as above make You will end up with one of these files: @@ -71,8 +76,9 @@ You will end up with one of these files: Trying it out ------------- -Qemu is an emulator and it can emulate an x86 machine. You can run the -payload with something like this: +QEMU is an emulator and it can emulate an x86 machine. Please make sure your +QEMU version is 2.3.0 or above to test this. You can run the payload with +something like this: mkdir /tmp/efi cp /path/to/u-boot*.efi /tmp/efi @@ -80,7 +86,8 @@ payload with something like this: Add -nographic if you want to use the terminal for output. Once it starts type 'fs0:u-boot-payload.efi' to run the payload or 'fs0:u-boot-app.efi' to -run the application. 'bios.bin' is the EFI 'BIOS'. +run the application. 'bios.bin' is the EFI 'BIOS'. Check [2] to obtain a +prebuilt EFI BIOS for QEMU or you can build one from source as well. To try it on real hardware, put u-boot-app.efi on a suitable boot medium, such as a USB stick. Then you can type something like this to start it: @@ -235,3 +242,6 @@ common/cmd_efi.c Ben Stoltz, Simon Glass Google, Inc July 2015 + +[1] http://www.qemu.org +[2] http://www.tianocore.org/ovmf/ -- 1.8.2.1

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[U-Boot] [U-Boot RESEND v2 00/10] Enable edma support for ti-qspi
by Vignesh R 17 Aug '15

17 Aug '15

This patch series enables DMA for QSPI on dra7xx and am43xx. Resending this series after rebasing on current origin/master. v2: https://www.mail-archive.com/u-boot@lists.denx.de/msg179404.html changes in v2: * Move edma related code to edma driver instead of handling it in ti-qspi driver. v1: https://www.mail-archive.com/u-boot@lists.denx.de/msg176479.html Kishon Vijay Abraham I (2): ARM: AM43xx: Add support for disabling clocks in uboot ARM: OMAP5: Add support for disabling clocks in uboot Ravi Babu (2): sf: allocate cache aligned buffers to copy from flash env: use cache line aligned memory for flash read Tom Rini (1): sf: ops: Add spi_flash_copy_mmap function Vignesh R (5): ARM: OMAP5: Add functions to enable and disable EDMA3 clocks ARM: AM43XX: Add functions to enable and disable EDMA3 clocks dma: ti-edma3: Add helper function to support edma3 transfer spi: ti_qspi: Use DMA to read from qspi flash ARM: dra7xx_evm: Enable EDMA3 in SPL to support DMA on qspi arch/arm/cpu/armv7/am33xx/clock.c | 52 +++++++++++++++++ arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 36 ++++++++++++ arch/arm/cpu/armv7/omap-common/clocks-common.c | 53 +++++++++++++++++ arch/arm/cpu/armv7/omap5/hw_data.c | 41 ++++++++++++++ arch/arm/cpu/armv7/omap5/prcm-regs.c | 4 ++ arch/arm/include/asm/arch-am33xx/clock.h | 1 + arch/arm/include/asm/arch-omap5/hardware.h | 5 ++ arch/arm/include/asm/omap_common.h | 11 ++++ arch/arm/include/asm/ti-common/ti-edma3.h | 2 + common/cmd_sf.c | 6 +- common/env_sf.c | 11 ++-- drivers/dma/ti-edma3.c | 78 ++++++++++++++++++++++++++ drivers/mtd/spi/sf_ops.c | 8 ++- drivers/spi/ti_qspi.c | 23 ++++++++ include/configs/dra7xx_evm.h | 2 + include/spi.h | 3 + 16 files changed, 327 insertions(+), 9 deletions(-) -- 2.5.0

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[U-Boot] spi-nor: Choices of choosing bank or 4-byte addressing
by Jagan Teki 17 Aug '15

17 Aug '15

For accessing SPI-NOR flash's with > 16MiB we have two choices like Bank/Extended and 4-byte addressing register support. Status in u-boot: 1) BAR (Bank/Extended) - Added support in u-boot already, tested 2) 4-byte addressing - No support yet - Hou Zhiqiang sent patches, those are review. Ideally we may support any one of them, but there is some situation where (q)spi controller can only support 3-byte addressing (not supporting 4-byte addressing) but the connected flash could be > 16MiB, example: Xilinx Zynq QSPI In this case as controller not supporting 4-byte commands we must use BAR for accessing > 16MiB flash's. Siva, suggested like from controller driver (spi_slave {} ) we need to inform the flash about addressing width, so-that flash can configure accordingly. I indeed agree with this, and if we have both supported then the flash will configure accordingly with controller check. Pls- share for any other thoughts. thanks! -- Jagan | openedev.

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[U-Boot] [PATCH V2] ti: qspi: set flash quad bit based on quad support flag
by Vishal Mahaveer 17 Aug '15

17 Aug '15

Update op_mode_rx flag based on CONFIG_QSPI_QUAD_SUPPORT flag, instead of platform. Signed-off-by: Vishal Mahaveer <vishalm(a)ti.com> Reviewed-by: Jagan Teki <jteki(a)openedev.com> --- Re-sending, because missed copying Tom Rini http://marc.info/?l=u-boot&m=143948953129327&w=2 drivers/spi/ti_qspi.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 3356c0f..af40ec8 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -106,7 +106,6 @@ static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave) slave->memory_map = (void *)MMAP_START_ADDR_DRA; #else slave->memory_map = (void *)MMAP_START_ADDR_AM43x; - slave->op_mode_rx = 8; #endif #ifdef CONFIG_QSPI_QUAD_SUPPORT @@ -114,6 +113,7 @@ static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave) QSPI_SETUP0_NUM_D_BYTES_8_BITS | QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS); + slave->op_mode_rx = SPI_OPM_RX_QOF; #else memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES | QSPI_SETUP0_NUM_D_BYTES_NO_BITS | -- 1.7.4.1

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