August 2015 - U-Boot

[U-Boot] [RFC PATCH 0/1] sunxi board-specific options
by Bernhard Nortmann 24 Aug '15

24 Aug '15

I'm looking for ideas/comments on how to best integrate configuration tweaks for specific sunxi boards into the U-Boot (build) ecosystem. An example would be adding U-Boot support for GPIO-driven LEDs (and the "led" command), which I'm demonstrating here for the Banana Pi. My current line of thought is: Have sunxi-common.h include a separate sunxi-boards.h, to prevent pollution of the "master" include (in case the file later grows to accomodate multiple configurations). sunxi-boards.h in turn could tweak configuration settings as needed, or pull in further includes, depending on board-specific definitions. The latter would probably originate from the boards' *_defconfig files. Regards, B. Nortmann Bernhard Nortmann (1): sunxi: support board-specific configuration options configs/Bananapi_defconfig | 2 +- include/configs/bananapi.h | 23 +++++++++++++++++++++++ include/configs/sunxi-boards.h | 5 +++++ include/configs/sunxi-common.h | 1 + 4 files changed, 30 insertions(+), 1 deletion(-) create mode 100644 include/configs/bananapi.h create mode 100644 include/configs/sunxi-boards.h -- 2.4.6

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[U-Boot] [PATCH 1/3][v2] Pointers in ESBC header made 32 bit
by Aneesh Bansal 24 Aug '15

24 Aug '15

For the Chain of Trust, the esbc_validate command supports 32 bit fields for location of the image. In the header structure definition, these were declared as pointers which made them 64 bit on a 64 bit core. Signed-off-by: Aneesh Bansal <aneesh.bansal(a)freescale.com> --- Changes in v2: Compile time warning removed when printing Header Address. board/freescale/common/fsl_validate.c | 20 ++++++++++---------- include/fsl_validate.h | 14 +++++++------- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 5283648..465676f 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -63,12 +63,12 @@ static u32 check_ie(struct fsl_secboot_img_priv *img) * address */ #if defined(CONFIG_MPC85xx) -int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr) +int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]); u32 csf_flash_offset = csf_hdr_addr & ~(CONFIG_SYS_PBI_FLASH_BASE); - ulong flash_addr, addr; + u32 flash_addr, addr; int found = 0; int i = 0; @@ -76,7 +76,7 @@ int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr) flash_addr = flash_info[i].start[0]; addr = flash_info[i].start[0] + csf_flash_offset; if (memcmp((u8 *)addr, barker_code, ESBC_BARKER_LEN) == 0) { - debug("Barker found on addr %lx\n", addr); + debug("Barker found on addr %x\n", addr); found = 1; break; } @@ -94,7 +94,7 @@ int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr) /* For platforms like LS1020, correct flash address is present in * the header. So the function reqturns flash base address as 0 */ -int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr) +int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]); @@ -108,11 +108,11 @@ int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr) } #endif -static int get_ie_info_addr(ulong *ie_addr) +static int get_ie_info_addr(u32 *ie_addr) { struct fsl_secboot_img_hdr *hdr; struct fsl_secboot_sg_table *sg_tbl; - ulong flash_base_addr, csf_addr; + u32 flash_base_addr, csf_addr; if (get_csf_base_addr(&csf_addr, &flash_base_addr)) return -1; @@ -127,11 +127,11 @@ static int get_ie_info_addr(ulong *ie_addr) */ #if defined(CONFIG_FSL_TRUST_ARCH_v1) && defined(CONFIG_FSL_CORENET) sg_tbl = (struct fsl_secboot_sg_table *) - (((ulong)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) + + (((u32)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) + flash_base_addr); #else sg_tbl = (struct fsl_secboot_sg_table *)(csf_addr + - (ulong)hdr->psgtable); + (u32)hdr->psgtable); #endif /* IE Key Table is the first entry in the SG Table */ @@ -142,7 +142,7 @@ static int get_ie_info_addr(ulong *ie_addr) *ie_addr = sg_tbl->src_addr; #endif - debug("IE Table address is %lx\n", *ie_addr); + debug("IE Table address is %x\n", *ie_addr); return 0; } @@ -549,7 +549,7 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) if (memcmp(hdr->barker, barker_code, ESBC_BARKER_LEN)) return ERROR_ESBC_CLIENT_HEADER_BARKER; - sprintf(buf, "%p", hdr->pimg); + sprintf(buf, "%x", hdr->pimg); setenv("img_addr", buf); if (!hdr->img_size) diff --git a/include/fsl_validate.h b/include/fsl_validate.h index c460534..92dd98b 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -82,14 +82,14 @@ struct fsl_secboot_img_hdr { u32 psign; /* signature offset */ u32 sign_len; /* length of the signature in bytes */ union { - struct fsl_secboot_sg_table *psgtable; /* ptr to SG table */ - u8 *pimg; /* ptr to ESBC client image */ + u32 psgtable; /* ptr to SG table */ + u32 pimg; /* ptr to ESBC client image */ }; union { u32 sg_entries; /* no of entries in SG table */ u32 img_size; /* ESBC client image size in bytes */ }; - ulong img_start; /* ESBC client entry point */ + u32 img_start; /* ESBC client entry point */ u32 sg_flag; /* Scatter gather flag */ u32 uid_flag; u32 fsl_uid_0; @@ -133,7 +133,7 @@ struct srk_table { */ struct fsl_secboot_sg_table { u32 len; /* length of the segment in bytes */ - ulong src_addr; /* ptr to the data segment */ + u32 src_addr; /* ptr to the data segment */ }; #else /* @@ -146,8 +146,8 @@ struct fsl_secboot_sg_table { struct fsl_secboot_sg_table { u32 len; u32 trgt_id; - ulong src_addr; - ulong dst_addr; + u32 src_addr; + u32 dst_addr; }; #endif @@ -162,7 +162,7 @@ struct fsl_secboot_sg_table { */ struct fsl_secboot_img_priv { uint32_t hdr_location; - ulong ie_addr; + u32 ie_addr; u32 key_len; struct fsl_secboot_img_hdr hdr; -- 1.8.1.4

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[U-Boot] [PATCH 1/3][v2] Pointers in ESBC header made 32 bit
by Aneesh Bansal 24 Aug '15

24 Aug '15

For the Chain of Trust, the esbc_validate command supports 32 bit fields for location of the image. In the header structure definition, these were declared as pointers which made them 64 bit on a 64 bit core. Signed-off-by: Aneesh Bansal <aneesh.bansal(a)freescale.com> --- Changes in v2: Compile time warning removed when printing Header Address. board/freescale/common/fsl_validate.c | 20 ++++++++++---------- include/fsl_validate.h | 14 +++++++------- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 5283648..465676f 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -63,12 +63,12 @@ static u32 check_ie(struct fsl_secboot_img_priv *img) * address */ #if defined(CONFIG_MPC85xx) -int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr) +int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]); u32 csf_flash_offset = csf_hdr_addr & ~(CONFIG_SYS_PBI_FLASH_BASE); - ulong flash_addr, addr; + u32 flash_addr, addr; int found = 0; int i = 0; @@ -76,7 +76,7 @@ int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr) flash_addr = flash_info[i].start[0]; addr = flash_info[i].start[0] + csf_flash_offset; if (memcmp((u8 *)addr, barker_code, ESBC_BARKER_LEN) == 0) { - debug("Barker found on addr %lx\n", addr); + debug("Barker found on addr %x\n", addr); found = 1; break; } @@ -94,7 +94,7 @@ int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr) /* For platforms like LS1020, correct flash address is present in * the header. So the function reqturns flash base address as 0 */ -int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr) +int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]); @@ -108,11 +108,11 @@ int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr) } #endif -static int get_ie_info_addr(ulong *ie_addr) +static int get_ie_info_addr(u32 *ie_addr) { struct fsl_secboot_img_hdr *hdr; struct fsl_secboot_sg_table *sg_tbl; - ulong flash_base_addr, csf_addr; + u32 flash_base_addr, csf_addr; if (get_csf_base_addr(&csf_addr, &flash_base_addr)) return -1; @@ -127,11 +127,11 @@ static int get_ie_info_addr(ulong *ie_addr) */ #if defined(CONFIG_FSL_TRUST_ARCH_v1) && defined(CONFIG_FSL_CORENET) sg_tbl = (struct fsl_secboot_sg_table *) - (((ulong)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) + + (((u32)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) + flash_base_addr); #else sg_tbl = (struct fsl_secboot_sg_table *)(csf_addr + - (ulong)hdr->psgtable); + (u32)hdr->psgtable); #endif /* IE Key Table is the first entry in the SG Table */ @@ -142,7 +142,7 @@ static int get_ie_info_addr(ulong *ie_addr) *ie_addr = sg_tbl->src_addr; #endif - debug("IE Table address is %lx\n", *ie_addr); + debug("IE Table address is %x\n", *ie_addr); return 0; } @@ -549,7 +549,7 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) if (memcmp(hdr->barker, barker_code, ESBC_BARKER_LEN)) return ERROR_ESBC_CLIENT_HEADER_BARKER; - sprintf(buf, "%p", hdr->pimg); + sprintf(buf, "%x", hdr->pimg); setenv("img_addr", buf); if (!hdr->img_size) diff --git a/include/fsl_validate.h b/include/fsl_validate.h index c460534..92dd98b 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -82,14 +82,14 @@ struct fsl_secboot_img_hdr { u32 psign; /* signature offset */ u32 sign_len; /* length of the signature in bytes */ union { - struct fsl_secboot_sg_table *psgtable; /* ptr to SG table */ - u8 *pimg; /* ptr to ESBC client image */ + u32 psgtable; /* ptr to SG table */ + u32 pimg; /* ptr to ESBC client image */ }; union { u32 sg_entries; /* no of entries in SG table */ u32 img_size; /* ESBC client image size in bytes */ }; - ulong img_start; /* ESBC client entry point */ + u32 img_start; /* ESBC client entry point */ u32 sg_flag; /* Scatter gather flag */ u32 uid_flag; u32 fsl_uid_0; @@ -133,7 +133,7 @@ struct srk_table { */ struct fsl_secboot_sg_table { u32 len; /* length of the segment in bytes */ - ulong src_addr; /* ptr to the data segment */ + u32 src_addr; /* ptr to the data segment */ }; #else /* @@ -146,8 +146,8 @@ struct fsl_secboot_sg_table { struct fsl_secboot_sg_table { u32 len; u32 trgt_id; - ulong src_addr; - ulong dst_addr; + u32 src_addr; + u32 dst_addr; }; #endif @@ -162,7 +162,7 @@ struct fsl_secboot_sg_table { */ struct fsl_secboot_img_priv { uint32_t hdr_location; - ulong ie_addr; + u32 ie_addr; u32 key_len; struct fsl_secboot_img_hdr hdr; -- 1.8.1.4

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[U-Boot] [PATCH 0/3] arm, imx6: aristainetos board updates
by Heiko Schocher 24 Aug '15

24 Aug '15

This patchserie updates the aristainetos board: - some small fixes for the aristainetos and aristainetos2 board - there is a new hardware version for the aristaineos2 board, called 2b, add it - as the display driver is on the 2b version on another spi chipselect, make this configurable in the display driver. Heiko Schocher (3): arm, imx6: aristainetos board updates arm, imx6: add aristainetos 2b board version video, lg4573: make spi bus and cs configurable arch/arm/Kconfig | 4 +++ board/aristainetos/Kconfig | 13 ++++++++ board/aristainetos/aristainetos-v2.c | 57 ++++++++++++++++++++++++++++---- board/aristainetos/aristainetos.c | 19 +++++------ drivers/video/lg4573.c | 3 +- include/configs/aristainetos-common.h | 4 --- include/configs/aristainetos.h | 6 +++- include/configs/aristainetos2.h | 8 ++++- include/configs/aristainetos2b.h | 62 +++++++++++++++++++++++++++++++++++ 9 files changed, 151 insertions(+), 25 deletions(-) create mode 100644 include/configs/aristainetos2b.h -- 2.1.0

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[U-Boot] [PATCH 0/8] dm: rockchip: Enable booting from MMC
by Sjoerd Simons 24 Aug '15

24 Aug '15

This patchset allows u-boot on RK3288 device to load and boot kernels from MMC using the standard distro boot commands. Patchset is on top of the rockchip-working branch of u-boot dm There are some small oddities with the support: - Linux crashes when try to use the FDT if it's re-allocated to memory locations above 512MB. So fdt_high is set to ensure it stays below that. - This SoC seems sensitive to the order in which the caches are disabled, when disabling the i-cache before the d-cache starting linux fails (unsure if it fails before or after jumping to linux though) To fix the latter ``arm: Turn of d-cache before i-cache'' changes the ordering in the general v7 code. However i have not tested this yet on other device, so it may well need to be handled in rockchip specific code. Tested on a Radxa Rock 2 with square baseboard, booting from SD card. I haven't tested eMMC yet however i suspect the SPL will need modifications there to load u-boot from eMMC rather then SD (which has index 0) ideally by detecting where the SPL itself got loaded from. Sjoerd Simons (8): doc: Fix reference to Rock pro when Rock 2 is meant mmc: Probe DM based mmc devices in u-boot rockchip: Disable sdio mmc slot on rk3288-firefly rockchip: Turn off CONFIG_SPL_LED_SUPPORT for firefly rockchip: Add config_distro_bootcmd support arm: Turn of d-cache before i-cache rockchip: Drop first 32kb of zeros from the rksd image type rockchip: Update todo in README.rockchip arch/arm/cpu/armv7/cpu.c | 15 +++++++++------ arch/arm/dts/rk3288-firefly.dtsi | 2 +- doc/README.rockchip | 9 ++++----- drivers/mmc/mmc.c | 32 ++++++++++++++++++++++++++++---- include/configs/firefly-rk3288.h | 1 - include/configs/rk3288_common.h | 21 +++++++++++++++++++++ tools/rksd.c | 9 ++------- 7 files changed, 65 insertions(+), 24 deletions(-) -- 2.5.0

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[U-Boot] Question on fitupd
by Brian_Brelsford＠Dell.com 24 Aug '15

24 Aug '15

Dell Customer Communication PURPOSE: This email is with respect to the "fitupd" command. In looking at the source in the current u-boot tree, fitupd supports a NOR flash only. OUR GOAL: We would like to expand fitupd to be able to flash a SPI NOR, and MMC block devices. This would require support for, file writes (ex. ext4write), raw block writes (ex. mmc write), etc. Our design also supports a master boot record with two bootable partitions. QUESTIONS: Is expanding fitupd support for block devices a desirable feature to contribute back? Is this something that the u-boot projects would want? Would you want this in the ../common path for everyone to have access to? Or, prefer that this support be added to ../board/<mystuff>/ for our unique support only? I am leaving out all the details for now, we are first trying to understand the general direction we should go. Thank you for any advice in this area. Brian Brelsford

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[U-Boot] [PATCH] imx: mx6sxsabresd: enable CONFIG_SPL_FAT_SUPPORT
by Peng Fan 24 Aug '15

24 Aug '15

Enable CONFIG_SPL_FAT_SUPPORT to load u-boot.img from FAT partition. Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> --- include/configs/mx6sxsabresd.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 848bdcd..74d04a0 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -15,6 +15,7 @@ #ifdef CONFIG_SPL #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT #include "imx6_spl.h" #endif -- 1.8.4

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[U-Boot] [PATCH] x86: panther: Add PCI and video configuration
by Simon Glass 24 Aug '15

24 Aug '15

Add a PCI node to the device tree. This allows SPI flash and SATA to work correctly. Also configure the video to come up correectly even though there is no keyboard. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- arch/x86/dts/chromebox_panther.dts | 10 ++++++++++ include/configs/chromebox_panther.h | 2 ++ 2 files changed, 12 insertions(+) diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts index 84eae3a..f6a35b7 100644 --- a/arch/x86/dts/chromebox_panther.dts +++ b/arch/x86/dts/chromebox_panther.dts @@ -42,6 +42,16 @@ stdout-path = "/serial"; }; + pci { + compatible = "pci-x86"; + #address-cells = <3>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000 + 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 + 0x01000000 0x0 0x1000 0x1000 0 0xefff>; + }; + spi { #address-cells = <1>; #size-cells = <0>; diff --git a/include/configs/chromebox_panther.h b/include/configs/chromebox_panther.h index 00fe26d..dc732b8 100644 --- a/include/configs/chromebox_panther.h +++ b/include/configs/chromebox_panther.h @@ -14,4 +14,6 @@ /* Avoid a warning in the Realtek Ethernet driver */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define CONFIG_VGA_AS_SINGLE_DEVICE + #endif /* __CONFIG_H */ -- 2.5.0.457.gab17608

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[U-Boot] [PATCH v3 0/4] dm: pci: Support pci devices in the device tree with driver model
by Bin Meng 24 Aug '15

24 Aug '15

This is the 3rd attempt to support pci uart devices in the device tree with driver model. The v2 patch series is at [1]. With this series, pci uart now works on Intel Crown Bay with driver model. "dm tree" output below: => dm tree Class Probed Name ---------------------------------------- root [ + ] root_driver serial [ ] |-- serial rtc [ ] |-- rtc gpio [ ] |-- gpioa gpio [ ] |-- gpiob spi [ + ] |-- spi spi_flash [ ] | `-- spi-flash@0 pci [ + ] |-- pci pci [ + ] | |-- pcie@17,0 pci [ + ] | | `-- topcliff@0,0 serial [ ] | | |-- uart@a,1 serial [ ] | | |-- uart@a,2 serial [ + ] | | |-- uart@a,3 serial [ ] | | |-- uart@a,4 pci_generic [ ] | | |-- pci_2:0.0 pci_generic [ ] | | |-- pci_2:0.1 pci_generic [ ] | | |-- pci_2:0.2 pci_generic [ ] | | |-- pci_2:2.0 pci_generic [ ] | | |-- pci_2:2.1 pci_generic [ ] | | |-- pci_2:2.2 pci_generic [ ] | | |-- pci_2:2.3 pci_generic [ ] | | |-- pci_2:6.0 pci_generic [ ] | | |-- pci_2:8.0 pci_generic [ ] | | |-- pci_2:8.1 pci_generic [ ] | | |-- pci_2:8.2 pci_generic [ ] | | |-- pci_2:8.3 pci_generic [ ] | | |-- pci_2:a.0 pci_generic [ ] | | |-- pci_2:c.0 pci_generic [ ] | | |-- pci_2:c.2 pci_generic [ ] | | `-- pci_2:c.3 pci_generic [ ] | |-- pci_0:0.0 pci_generic [ ] | |-- pci_0:2.0 pci [ + ] | |-- pci_0:18.0 pci [ + ] | |-- pci_0:19.0 pci [ + ] | |-- pci_0:1a.0 pci_generic [ ] | |-- pci_0:1b.0 pci_generic [ ] | `-- pci_0:1f.0 simple_bus [ + ] `-- cpus cpu [ + ] |-- cpu@0 cpu [ + ] `-- cpu@1 [1] http://lists.denx.de/pipermail/u-boot/2015-August/224603.html Changes in v3: - Rebase on u-boot-x86/master - Drop v2 patches which were already applied Bin Meng (4): dm: pci: Optimize pci_uclass_post_bind() dm: core: Test dev->flags after device_probe() in device_probe_child() x86: crownbay: Support Topcliff integrated pci uart devices with driver model dm: pci: Document binding of pci device drivers arch/x86/dts/crownbay.dts | 15 ++++++--- doc/driver-model/pci-info.txt | 71 +++++++++++++++++++++++++++++++++++++++++-- drivers/core/device.c | 8 +++++ drivers/pci/pci-uclass.c | 7 +++++ 4 files changed, 93 insertions(+), 8 deletions(-) -- 1.8.2.1

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[U-Boot] [RESPIN PATCH v3 1/4] dm: pci: Optimize pci_uclass_post_bind()
by Bin Meng 24 Aug '15

24 Aug '15

If there is no pci device listed in the device tree, don't bother scanning the device tree. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- Simon, I see the following v2 patches were applied, but don't see you replied the patch thread to mention it's been applied. - x86: fsp: Call fsp_init_phase_pci() in pci_uclass_post_probe() - fdtdec: Fix possible infinite loop in fdtdec_get_pci_vendev() - dm: pci: Save devfn without bus number in pci_uclass_child_post_bind() I assume these patches look good, so I don't include those patches in the v3 series. Let me know if there is any issue. Changes in v3 respin: - Fix typo of 'tree' Changes in v3: - Rebase on u-boot-x86/master - Drop v2 patches which were already applied drivers/pci/pci-uclass.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 2d12344..b25298f 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -632,6 +632,13 @@ error: static int pci_uclass_post_bind(struct udevice *bus) { /* + * If there is no pci device listed in the device tree, + * don't bother scanning the device tree. + */ + if (bus->of_offset == -1) + return 0; + + /* * Scan the device tree for devices. This does not probe the PCI bus, * as this is not permitted while binding. It just finds devices * mentioned in the device tree. -- 1.8.2.1

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