July 2015 - U-Boot

[U-Boot] [PATCH v2 10/11] x86: crownbay: Enable graphics support
by Bin Meng 08 Jul '15

08 Jul '15

Enable graphics support on Intel Crown Bay board With the help of vgabios for Intel TunnelCreek IGD. Tested with an external LVDS panel connected to X4 connector and SDVO adapter connected to X9 connector on the board. Signed-off-by: Jian Luo <jian.luo4(a)boschrexroth.de> Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> Acked-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: None configs/crownbay_defconfig | 3 +++ doc/README.x86 | 20 +++++++++++++------- include/configs/crownbay.h | 14 +++++++------- 3 files changed, 23 insertions(+), 14 deletions(-) diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index e4edad0..de24bb6 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -4,10 +4,13 @@ CONFIG_DEFAULT_DEVICE_TREE="crownbay" CONFIG_TARGET_CROWNBAY=y CONFIG_SMP=y CONFIG_MAX_CPUS=2 +CONFIG_HAVE_VGA_BIOS=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_CMD_CPU=y CONFIG_CMD_NET=y CONFIG_OF_CONTROL=y CONFIG_CPU=y +CONFIG_VIDEO_VESA=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_DM_RTC=y diff --git a/doc/README.x86 b/doc/README.x86 index 7f3914f..646eff1 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -113,6 +113,10 @@ binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP binary, change the following five bytes values from orginally E8 42 FF FF FF to B8 00 80 0B 00. +As for the video ROM, you need manually extract it from the Intel provided +BIOS for Crown Bay here [6], using the AMI MMTool [7]. Check PCI option ROM +ID 8086:4108, extract and save it as vga.bin in the board directory. + Now you can build U-Boot and obtain u-boot.rom $ make crownbay_defconfig @@ -254,7 +258,7 @@ If you want to check both consoles, use '-serial stdio'. CPU Microcode ------------- -Modern CPUs usually require a special bit stream called microcode [6] to be +Modern CPUs usually require a special bit stream called microcode [8] to be loaded on the processor after power up in order to function properly. U-Boot has already integrated these as hex dumps in the source tree. @@ -265,9 +269,9 @@ Additional application processors (AP) can be brought up by U-Boot. In order to have an SMP kernel to discover all of the available processors, U-Boot needs to prepare configuration tables which contain the multi-CPUs information before loading the OS kernel. Currently U-Boot supports generating two types of tables -for SMP, called Simple Firmware Interface (SFI) [7] and Multi-Processor (MP) [8] -tables. The writing of these two tables are controlled by two Kconfig options -GENERATE_SFI_TABLE and GENERATE_MP_TABLE. +for SMP, called Simple Firmware Interface (SFI) [9] and Multi-Processor (MP) +[10] tables. The writing of these two tables are controlled by two Kconfig +options GENERATE_SFI_TABLE and GENERATE_MP_TABLE. Driver Model ------------ @@ -372,6 +376,8 @@ References [3] http://www.coreboot.org/~stepan/pci8086,0166.rom [4] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-pla… [5] http://www.intel.com/fsp -[6] http://en.wikipedia.org/wiki/Microcode -[7] http://simplefirmware.org -[8] http://www.intel.com/design/archives/processors/pro/docs/242016.htm +[6] http://www.intel.com/content/www/us/en/secure/intelligent-systems/privilege… +[7] http://www.ami.com/products/bios-uefi-tools-and-utilities/bios-uefi-utiliti… +[8] http://en.wikipedia.org/wiki/Microcode +[9] http://simplefirmware.org +[10] http://www.intel.com/design/archives/processors/pro/docs/242016.htm diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index 0e1f046..6cf53a3 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -32,15 +32,16 @@ #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS #define CONFIG_PCI_IO_SIZE 0xe000 +#define CONFIG_PCI_CONFIG_HOST_BRIDGE #define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP #define CONFIG_E1000 -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga,usbkbd\0" \ + "stdout=serial,vga\0" \ + "stderr=serial,vga\0" -#define CONFIG_SCSI_DEV_LIST \ +#define CONFIG_SCSI_DEV_LIST \ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA} #define CONFIG_SPI_FLASH_SST @@ -55,9 +56,8 @@ #define CONFIG_PCH_GBE #define CONFIG_PHYLIB -/* Video is not supported */ -#undef CONFIG_VIDEO -#undef CONFIG_CFB_CONSOLE +/* TunnelCreek IGD support */ +#define CONFIG_VGA_AS_SINGLE_DEVICE /* Environment configuration */ #define CONFIG_ENV_SECT_SIZE 0x1000 -- 1.8.2.1

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[U-Boot] [PATCH v2 09/11] x86: Remove MARK_GRAPHICS_MEM_WRCOMB
by Bin Meng 08 Jul '15

08 Jul '15

MARK_GRAPHICS_MEM_WRCOMB is not referenced anywhere in the code, hence remove it. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> Acked-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: None arch/x86/Kconfig | 8 -------- board/google/chromebook_link/Kconfig | 1 - board/google/chromebox_panther/Kconfig | 1 - 3 files changed, 10 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 0e308ce..0036344 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -194,14 +194,6 @@ config X86_RAMTEST to work correctly. It is not exhaustive but can save time by detecting obvious failures. -config MARK_GRAPHICS_MEM_WRCOMB - bool "Mark graphics memory as write-combining" - default n - help - The graphics performance may increase if the graphics - memory is set as write-combining cache type. This option - enables marking the graphics memory as write-combining. - config HAVE_FSP bool "Add an Firmware Support Package binary" help diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index 9c8d020..d3644a9 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -22,7 +22,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_IVYBRIDGE select SOUTHBRIDGE_INTEL_C216 select HAVE_ACPI_RESUME - select MARK_GRAPHICS_MEM_WRCOMB select BOARD_ROMSIZE_KB_8192 config PCIE_ECAM_BASE diff --git a/board/google/chromebox_panther/Kconfig b/board/google/chromebox_panther/Kconfig index e3604eb..d56d903 100644 --- a/board/google/chromebox_panther/Kconfig +++ b/board/google/chromebox_panther/Kconfig @@ -23,7 +23,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_IVYBRIDGE select SOUTHBRIDGE_INTEL_C216 select HAVE_ACPI_RESUME - select MARK_GRAPHICS_MEM_WRCOMB select BOARD_ROMSIZE_KB_8192 config SYS_CAR_ADDR -- 1.8.2.1

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[U-Boot] [PATCH v2 08/11] x86: Move VGA option rom macros to Kconfig
by Bin Meng 08 Jul '15

08 Jul '15

Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on HAVE_VGA_BIOS. The new names are consistent with other x86 binary blob options like HAVE_FSP/FSP_FILE/FSP_ADDR. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> Acked-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: None Makefile | 4 ++-- arch/x86/Kconfig | 22 ++++++++++++++++++++++ configs/chromebook_link_defconfig | 1 + configs/chromebox_panther_defconfig | 1 + configs/minnowmax_defconfig | 1 + doc/README.x86 | 2 +- drivers/pci/pci_rom.c | 6 +++--- include/configs/minnowmax.h | 3 --- include/configs/x86-chromebook.h | 3 --- 9 files changed, 31 insertions(+), 12 deletions(-) diff --git a/Makefile b/Makefile index 0a674bf..2601e87 100644 --- a/Makefile +++ b/Makefile @@ -1034,8 +1034,8 @@ ifneq ($(CONFIG_HAVE_CMC),) IFDTOOL_FLAGS += -w $(CONFIG_CMC_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_CMC_FILE) endif -ifneq ($(CONFIG_X86_OPTION_ROM_ADDR),) -IFDTOOL_FLAGS += -w $(CONFIG_X86_OPTION_ROM_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_X86_OPTION_ROM_FILE) +ifneq ($(CONFIG_HAVE_VGA_BIOS),) +IFDTOOL_FLAGS += -w $(CONFIG_VGA_BIOS_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_VGA_BIOS_FILE) endif quiet_cmd_ifdtool = IFDTOOL $@ diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 6b46ec4..0e308ce 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -293,6 +293,28 @@ config TSC_FREQ_IN_MHZ help The running frequency in MHz of Time-Stamp Counter (TSC). +config HAVE_VGA_BIOS + bool "Add a VGA BIOS image" + help + Select this option if you have a VGA BIOS image that you would + like to add to your ROM. + +config VGA_BIOS_FILE + string "VGA BIOS image filename" + depends on HAVE_VGA_BIOS + default "vga.bin" + help + The filename of the VGA BIOS image in the board directory. + +config VGA_BIOS_ADDR + hex "VGA BIOS image location" + depends on HAVE_VGA_BIOS + default 0xfff90000 + help + The location of VGA BIOS image in the SPI flash. For example, base + address of 0xfff90000 indicates that the image will be put at offset + 0x90000 from the beginning of a 1MB flash device. + menu "System tables" config GENERATE_PIRQ_TABLE diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index 4f7f779..08743f0 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -3,6 +3,7 @@ CONFIG_VENDOR_GOOGLE=y CONFIG_DEFAULT_DEVICE_TREE="chromebook_link" CONFIG_TARGET_CHROMEBOOK_LINK=y CONFIG_HAVE_MRC=y +CONFIG_HAVE_VGA_BIOS=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y CONFIG_CMD_NET=y diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index 941033f..9cd422a 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -3,6 +3,7 @@ CONFIG_VENDOR_GOOGLE=y CONFIG_DEFAULT_DEVICE_TREE="chromebox_panther" CONFIG_TARGET_CHROMEBOX_PANTHER=y CONFIG_HAVE_MRC=y +CONFIG_HAVE_VGA_BIOS=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y CONFIG_CMD_NET=y diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index 744aca3..bfe2cdf 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -3,6 +3,7 @@ CONFIG_VENDOR_INTEL=y CONFIG_DEFAULT_DEVICE_TREE="minnowmax" CONFIG_TARGET_MINNOWMAX=y CONFIG_HAVE_INTEL_ME=y +CONFIG_HAVE_VGA_BIOS=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y diff --git a/doc/README.x86 b/doc/README.x86 index 49d6e83..7f3914f 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -79,7 +79,7 @@ Find the following files: * ./northbridge/intel/sandybridge/systemagent-r6.bin The 3rd one should be renamed to mrc.bin. -As for the video ROM, you can get it here [3]. +As for the video ROM, you can get it here [3] and rename it to vga.bin. Make sure all these binary blobs are put in the board directory. Now you can build U-Boot and obtain u-boot.rom: diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index 83c69a5..4a91033 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -79,8 +79,8 @@ static int pci_rom_probe(pci_dev_t dev, uint class, if (vendev != mapped_vendev) debug("Device ID mapped to %#08x\n", mapped_vendev); -#ifdef CONFIG_X86_OPTION_ROM_ADDR - rom_address = CONFIG_X86_OPTION_ROM_ADDR; +#ifdef CONFIG_VGA_BIOS_ADDR + rom_address = CONFIG_VGA_BIOS_ADDR; #else pci_read_config_dword(dev, PCI_ROM_ADDRESS, &rom_address); @@ -103,7 +103,7 @@ static int pci_rom_probe(pci_dev_t dev, uint class, if (le16_to_cpu(rom_header->signature) != PCI_ROM_HDR) { printf("Incorrect expansion ROM header signature %04x\n", le16_to_cpu(rom_header->signature)); -#ifndef CONFIG_X86_OPTION_ROM_ADDR +#ifndef CONFIG_VGA_BIOS_ADDR /* Disable expansion ROM address decoding */ pci_write_config_dword(dev, PCI_ROM_ADDRESS, rom_address); #endif diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 547765d..8ee84a6 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -52,9 +52,6 @@ #undef CONFIG_USB_MAX_CONTROLLER_COUNT #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_X86_OPTION_ROM_FILE vga.bin -#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000 - #define VIDEO_IO_OFFSET 0 #define CONFIG_X86EMU_RAW_IO #define CONFIG_VGA_AS_SINGLE_DEVICE diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h index e0e7fca..408cbb1 100644 --- a/include/configs/x86-chromebook.h +++ b/include/configs/x86-chromebook.h @@ -26,9 +26,6 @@ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}, \ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI} -#define CONFIG_X86_OPTION_ROM_FILE pci8086,0166.bin -#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000 - #define CONFIG_PCI_MEM_BUS 0xe0000000 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS #define CONFIG_PCI_MEM_SIZE 0x10000000 -- 1.8.2.1

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[U-Boot] [PATCH v2 07/11] x86: cmd_mtrr: Improve MTRR list information
by Bin Meng 08 Jul '15

08 Jul '15

Print the meaningful base address and mask of an MTRR range without showing the memory type encoding or valid bit. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> Acked-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: None arch/x86/lib/cmd_mtrr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/lib/cmd_mtrr.c b/arch/x86/lib/cmd_mtrr.c index 7e0506b..f632f49 100644 --- a/arch/x86/lib/cmd_mtrr.c +++ b/arch/x86/lib/cmd_mtrr.c @@ -37,7 +37,8 @@ static int do_mtrr_list(void) valid = mask & MTRR_PHYS_MASK_VALID; type = mtrr_type_name[base & MTRR_BASE_TYPE_MASK]; printf("%d %-5s %-12s %016llx %016llx %016llx\n", i, - valid ? "Y" : "N", type, base, mask, size); + valid ? "Y" : "N", type, base & ~MTRR_BASE_TYPE_MASK, + mask & ~MTRR_PHYS_MASK_VALID, size); } return 0; -- 1.8.2.1

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[U-Boot] [PATCH v2 06/11] x86: queensbay: Change CPU_ADDR_BITS to 32
by Bin Meng 08 Jul '15

08 Jul '15

Per CPUID:80000008h result, the maximum physical address bits of TunnelCreek processor is 32 instead of default 36. This will fix the incorrect decoding of MTRR range mask. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> Acked-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: None arch/x86/cpu/queensbay/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig index 397e599..fbf85f2 100644 --- a/arch/x86/cpu/queensbay/Kconfig +++ b/arch/x86/cpu/queensbay/Kconfig @@ -38,4 +38,8 @@ config CMC_ADDR The default base address of 0xfffb0000 indicates that the binary must be located at offset 0xb0000 from the beginning of a 1MB flash device. +config CPU_ADDR_BITS + int + default 32 + endif -- 1.8.2.1

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[U-Boot] [PATCH v2 04/11] video: Add 32-bit color depth support for VBE
by Bin Meng 08 Jul '15

08 Jul '15

From: Jian Luo <jian.luo4(a)boschrexroth.de> The TunnelCreek IGD VBE reports 32-bit color depth regardless 24-bit color depth is configured. Since 24-bit mode already uses 4 bytes internally, it should be OK to just add this option in switch case. Signed-off-by: Jian Luo <jian.luo4(a)boschrexroth.de> Acked-by: Simon Glass <sjg(a)chromium.org> Tested-by: Bin Meng <bmeng.cn(a)gmail.com> --- Changes in v2: None drivers/pci/pci_rom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index e6f4806..83c69a5 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -202,6 +202,7 @@ int vbe_get_video_info(struct graphic_device *gdev) gdev->gdfBytesPP = vesa->bits_per_pixel / 8; switch (vesa->bits_per_pixel) { + case 32: case 24: gdev->gdfIndex = GDF_32BIT_X888RGB; break; -- 1.8.2.1

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[U-Boot] [PATCH v2 03/11] x86: bios: Allow pci config read/write to host bridge in int1a_handler
by Bin Meng 08 Jul '15

08 Jul '15

From: Jian Luo <jian.luo4(a)boschrexroth.de> We should allow pci config read/write to host bridge (b.d.f = 0.0.0) in the int1a_handler() which is a valid pci device. Signed-off-by: Jian Luo <jian.luo4(a)boschrexroth.de> Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> Acked-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: None arch/x86/lib/bios_interrupts.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/arch/x86/lib/bios_interrupts.c b/arch/x86/lib/bios_interrupts.c index 290990a..47d9f59 100644 --- a/arch/x86/lib/bios_interrupts.c +++ b/arch/x86/lib/bios_interrupts.c @@ -161,15 +161,7 @@ int int1a_handler(void) bus = M.x86.R_EBX >> 8; reg = M.x86.R_EDI; dev = PCI_BDF(bus, devfn >> 3, devfn & 7); - if (!dev) { - debug("0x%x: BAD DEVICE bus %d devfn 0x%x\n", func, - bus, devfn); - /* Or are we supposed to return PCIBIOS_NODEV? */ - M.x86.R_EAX &= 0xffff00ff; /* Clear AH */ - M.x86.R_EAX |= PCIBIOS_BADREG; - retval = 0; - return retval; - } + switch (func) { case 0xb108: /* Read Config Byte */ byte = x86_pci_read_config8(dev, reg); -- 1.8.2.1

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[U-Boot] [PATCH v2 01/11] video: vesa_fb: Look up VGA device by class instead of id
by Bin Meng 08 Jul '15

08 Jul '15

Per PCI spec, VGA device reports its class as standard 030000h in its configuration space, so we can use it to determine if we need run option rom instead of testing the supported vendor/device ids. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> Acked-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: None drivers/video/vesa_fb.c | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-) diff --git a/drivers/video/vesa_fb.c b/drivers/video/vesa_fb.c index 47f824a..909f8e8 100644 --- a/drivers/video/vesa_fb.c +++ b/drivers/video/vesa_fb.c @@ -1,6 +1,5 @@ /* - * - * Vesa frame buffer driver for x86 + * VESA frame buffer driver * * Copyright (C) 2014 Google, Inc * @@ -17,16 +16,6 @@ */ GraphicDevice ctfb; -/* Devices to allow - only the last one works fully */ -struct pci_device_id vesa_video_ids[] = { - { .vendor = 0x102b, .device = 0x0525 }, - { .vendor = 0x1002, .device = 0x5159 }, - { .vendor = 0x1002, .device = 0x4752 }, - { .vendor = 0x1002, .device = 0x5452 }, - { .vendor = 0x8086, .device = 0x0f31 }, - {}, -}; - void *video_hw_init(void) { GraphicDevice *gdev = &ctfb; @@ -36,8 +25,7 @@ void *video_hw_init(void) printf("Video: "); if (vbe_get_video_info(gdev)) { - /* TODO: Should we look these up by class? */ - dev = pci_find_devices(vesa_video_ids, 0); + dev = pci_find_class(PCI_CLASS_DISPLAY_VGA << 8, 0); if (dev == -1) { printf("no card detected\n"); return NULL; -- 1.8.2.1

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[U-Boot] [PATCH 00/22] Convert musb host mode code to the device-model
by Hans de Goede 07 Jul '15

07 Jul '15

Hi Marek and Simon, This series started out with the idea that it would be a nice small project for the weekend, but it turned out to be a bit more work... The main purpose of this series is to convert the musb host mode code to the device-model this has also resulted in various usb fixes / cleanups / reworking to make this possible, both in the generic usb code as well as in the device model usb code. Given that this touches both, I think it is probably best to merge the first 15 patches through Simon's tree like we did last time, then once those are place I can merge the sunxi bits. Note this is intended for v2015.10 (ofcourse). Note that this series is useful for a bunch more boards then just the single one the last patch updates to use musb + ehci + ohci, but that is the one I've been testing with other defconfig-s will be updated with followup patches. Please review. Regards, Hans

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[U-Boot] [PATCH v2 0/4] musb device model support series
by Hans de Goede 07 Jul '15

07 Jul '15

Hi Simon, Marek, Here is a series with just the patches which needed work after my v1 posting of this series. I've a rebased version of the entire series (some patches needed adjustment after the recent Kconfig / defconfig changes) in my personal tree. Simon, AFAIK the plan is still for this to go upstream through your tree, let me know when you're ready to take this series, and on which branch you want it based, and I'll create a branch for you to pull. Regards, Hans

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