July 2015 - U-Boot

[U-Boot] [PATCH 01/12] usb: USB_ARCH_HAS_HCD Kconfig option removal
by Paul Kocialkowski 27 Jul '15

27 Jul '15

The USB_ARCH_HAS_HCD currently serves no purpose and adds some confusion to the required Kconfig options that are required to have USB support. Dropping it makes things easier and doesn't break anything, since it was unused anyways. Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- drivers/usb/Kconfig | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 637ef3d..fe1ef11 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -1,9 +1,5 @@ -config USB_ARCH_HAS_HCD - def_bool y - config USB bool "Support for Host-side USB" - depends on USB_ARCH_HAS_HCD ---help--- Universal Serial Bus (USB) is a specification for a serial bus subsystem which offers higher speeds and more features than the -- 1.9.1

3 29

[U-Boot] [PATCH] am3517_evm: add FIT support
by yegorslists＠googlemail.com 27 Jul '15

27 Jul '15

From: Yegor Yefremov <yegorslists(a)googlemail.com> Enable DTS support (CONFIG_OF_LIBFDT), create ft_board_setup() stub and select CONFIG_FIT in defconfig. Signed-off-by: Yegor Yefremov <yegorslists(a)googlemail.com> --- board/logicpd/am3517evm/am3517evm.c | 5 +++++ configs/am3517_evm_defconfig | 1 + include/configs/am3517_evm.h | 3 +++ 3 files changed, 9 insertions(+) diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c index 24be6ea..cd37f85 100644 --- a/board/logicpd/am3517evm/am3517evm.c +++ b/board/logicpd/am3517evm/am3517evm.c @@ -50,6 +50,11 @@ int board_init(void) return 0; } +int ft_board_setup(void *blob, bd_t *bd) +{ + return 0; +} + #ifdef CONFIG_USB_MUSB_AM35X static struct musb_hdrc_config musb_config = { .multipoint = 1, diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig index 4589b30..c72d29e 100644 --- a/configs/am3517_evm_defconfig +++ b/configs/am3517_evm_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_AM3517_EVM=y CONFIG_SPL=y +CONFIG_FIT=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index b90a60d..c0ac5dc 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -42,6 +42,9 @@ #define CONFIG_MISC_INIT_R +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP + #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 -- 2.1.4

3 2

[U-Boot] [PATCH 1/2] omap3: fix NAND support for mcx board
by Stefano Babic 26 Jul '15

26 Jul '15

mcx was not updated according to changes in NAND driver. Signed-off-by: Stefano Babic <sbabic(a)denx.de> --- include/configs/mcx.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 0a7b7cf..d8766b9 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -309,7 +309,10 @@ */ /* **** PISMO SUPPORT *** */ +#define CONFIG_NAND +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_NAND_OMAP_GPMC +#define CONFIG_NAND_OMAP_GPMC_PREFETCH #define CONFIG_ENV_IS_IN_NAND #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ -- 1.9.1

2 4

[U-Boot] [PATCH 02/15][v4] imx: usb: ehci-mx7 add usb driver for i.MX7D
by Adrian Alonso 26 Jul '15

26 Jul '15

Add support for usb driver for i.MX7D SoC Signed-off-by: Adrian Alonso <aalonso(a)freescale.com> Signed-off-by: Ye.Li <B37916(a)freescale.com> Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> --- Changes for V2: Resend Changes for V3: - Integrate review obserbations - Add comments for fucntions board_ehci_hcd_init/board_ehci_power Changes for V4: - Follow kernel doc comments style drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-mx7.c | 113 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 114 insertions(+) create mode 100644 drivers/usb/host/ehci-mx7.c diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 4d35d3e..7267160 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o obj-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o obj-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o obj-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o +obj-$(CONFIG_USB_EHCI_MX7) += ehci-mx7.o obj-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o obj-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o diff --git a/drivers/usb/host/ehci-mx7.c b/drivers/usb/host/ehci-mx7.c new file mode 100644 index 0000000..da6b4dc --- /dev/null +++ b/drivers/usb/host/ehci-mx7.c @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2009 Daniel Mack <daniel(a)caiaq.de> + * Copyright (C) 2010-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <usb.h> +#include <errno.h> +#include <linux/compiler.h> +#include <usb/ehci-fsl.h> +#include <asm/io.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/clock.h> +#include <asm/imx-common/iomux-v3.h> + +#include "ehci.h" + +#define USB_NC_OFFSET 0x200 + +#define UCTRL_PM (1 << 9) /* OTG Power Mask */ +#define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */ +#define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */ + +/* USBCMD */ +#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */ +#define UCMD_RESET (1 << 1) /* controller reset */ + +/* Base address for this IP block is 0x02184800 */ +struct usbnc_regs { + u32 ctrl1; + u32 ctrl2; + u32 reserve1[11]; + u32 phy_ctrl2; + u32 reserve2[6]; + u32 adp_cfg1; + u32 reserve3; + u32 adp_status; +}; + +static void usb_oc_config(int index) +{ + struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + + (0x10000 * index) + USB_NC_OFFSET); + void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1); + + setbits_le32(ctrl, UCTRL_OVER_CUR_POL); + setbits_le32(ctrl, UCTRL_OVER_CUR_DIS | UCTRL_PM); +} + +/* + * board_ehci_hcd_init - set usb vbus voltage + * @port: usb otg port + * + * Setup iomux pad to setup supply vbus voltage for usb otg port. + * Machine board file overrides board_ehci_hcd_init + */ +int __weak board_ehci_hcd_init(int port) +{ + return 0; +} + +/* + * board_ehci_power - enables/disables usb vbus voltage + * @port: usb otg port + * @on: on/off vbus voltage + * + * Enables/disables supply vbus voltage for usb otg port. + * Machine board file overrides board_ehci_power + * + */ +int __weak board_ehci_power(int port, int on) +{ + return 0; +} + +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) +{ + struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR + + (0x10000 * index)); + + if (index > 3) + return -EINVAL; + enable_usboh3_clk(1); + mdelay(1); + + /* Do board specific initialization */ + board_ehci_hcd_init(index); + + usb_oc_config(index); + + *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); + *hcor = (struct ehci_hcor *)((uint32_t)*hccr + + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); + + board_ehci_power(index, (init == USB_INIT_DEVICE) ? 0 : 1); + if (init == USB_INIT_DEVICE) + return 0; + setbits_le32(&ehci->usbmode, CM_HOST); + writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); + setbits_le32(&ehci->portsc, USB_EN); + + mdelay(10); + + return 0; +} + +int ehci_hcd_stop(int index) +{ + return 0; +} -- 2.1.4

4 5

[U-Boot] [PATCH v2 1/2] power: pmic: Add support for MAX77696 PMIC
by Fabio Estevam 26 Jul '15

26 Jul '15

From: Fabio Estevam <fabio.estevam(a)freescale.com> Add support for MAX77696 PMIC. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- Changes since v1: - Fix the range of PMIC registers drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic_max77696.c | 32 ++++++++++++++++++++ include/power/max77696_pmic.h | 61 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 94 insertions(+) create mode 100644 drivers/power/pmic/pmic_max77696.c create mode 100644 include/power/max77696_pmic.h diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index ae86f04..4ad6df3 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_DM_PMIC) += pmic-uclass.o obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o +obj-$(CONFIG_POWER_MAX77696) += pmic_max77696.o obj-$(CONFIG_POWER_MAX8998) += pmic_max8998.o obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o diff --git a/drivers/power/pmic/pmic_max77696.c b/drivers/power/pmic/pmic_max77696.c new file mode 100644 index 0000000..93d92f5 --- /dev/null +++ b/drivers/power/pmic/pmic_max77696.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Fabio Estevam <fabio.estevam(a)freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <i2c.h> +#include <power/pmic.h> +#include <power/max77696_pmic.h> + +int power_max77696_init(unsigned char bus) +{ + static const char name[] = "MAX77696"; + struct pmic *p = pmic_alloc(); + + if (!p) { + printf("%s: POWER allocation error!\n", __func__); + return -ENOMEM; + } + + p->name = name; + p->interface = PMIC_I2C; + p->number_of_regs = PMIC_NUM_OF_REGS; + p->hw.i2c.addr = CONFIG_POWER_MAX77696_I2C_ADDR; + p->hw.i2c.tx_num = 1; + p->bus = bus; + + return 0; +} diff --git a/include/power/max77696_pmic.h b/include/power/max77696_pmic.h new file mode 100644 index 0000000..58f295c --- /dev/null +++ b/include/power/max77696_pmic.h @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Fabio Estevam <fabio.estevam(a)freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MAX77696_PMIC_H__ +#define __MAX77696_PMIC_H__ + +#define CONFIG_POWER_MAX77696_I2C_ADDR 0x3C + +enum { + L01_CNFG1 = 0x43, + L01_CNFG2, + L02_CNFG1, + L02_CNFG2, + L03_CNFG1, + L03_CNFG2, + L04_CNFG1, + L04_CNFG2, + L05_CNFG1, + L05_CNFG2, + L06_CNFG1, + L06_CNFG2, + L07_CNFG1, + L07_CNFG2, + L08_CNFG1, + L08_CNFG2, + L09_CNFG1, + L09_CNFG2, + L10_CNFG1, + L10_CNFG2, + LDO_INT1, + LDO_INT2, + LDO_INT1M, + LDO_INT2M, + LDO_CNFG3, + SW1_CNTRL, + SW2_CNTRL, + SW3_CNTRL, + SW4_CNTRL, + EPDCNFG, + EPDINTS, + EPDINT, + EPDINTM, + EPDVCOM, + EPDVEE, + EPDVNEG, + EPDVPOS, + EPDVDDH, + EPDSEQ, + EPDOKINTS, + CID = 0x9c, + EPDDIS = 0xb5, + PMIC_NUM_OF_REGS, +}; + +int power_max77696_init(unsigned char bus); + +#endif -- 1.9.1

2 3

[U-Boot] [PATCH] mx6sxsabresd: Use 'int' for return values
by Fabio Estevam 26 Jul '15

26 Jul '15

From: Fabio Estevam <fabio.estevam(a)freescale.com> The variable 'ret' is used to store the value returned by pfuze_mode_init(), so it should be of type 'int' instead of 'unsigned int' in order to correctly handle negative numbers. Fix the variable type. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- board/freescale/mx6sxsabresd/mx6sxsabresd.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 2ff960e..d58a79a 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -199,7 +199,8 @@ static struct i2c_pads_info i2c_pad_info1 = { int power_init_board(void) { struct pmic *p; - unsigned int reg, ret; + unsigned int reg; + int ret; p = pfuze_common_init(I2C_PMIC); if (!p) -- 1.9.1

2 1

[U-Boot] [PATCH] mx6sabresd: Use 'int' for return values
by Fabio Estevam 26 Jul '15

26 Jul '15

From: Fabio Estevam <fabio.estevam(a)freescale.com> The variable 'ret' is used to store the value returned by pfuze_mode_init(), so it should of type 'int' instead of 'unsigned int' in order to correctly handle negative numbers. Fix the variable type. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- board/freescale/mx6sabresd/mx6sabresd.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 23f8f6b..fa800f4 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -631,7 +631,8 @@ int board_init(void) int power_init_board(void) { struct pmic *p; - unsigned int reg, ret; + unsigned int reg; + int ret; p = pfuze_common_init(I2C_PMIC); if (!p) -- 1.9.1

2 1

[U-Boot] [PATCH][v3] imx: imximage: add new CHECK/CLR BIT command
by Adrian Alonso 26 Jul '15

26 Jul '15

* Extend imximage DCD version 2 to support DCD commands CMD_WRITE_CLR_BIT 4 [address] [mask bit] means: while ((*address & ~mask) != 0); CMD_CHECK_BITS_SET 4 [address] [mask bit] means: while ((*address & mask) != mask); CMD_CHECK_BITS_CLR 4 [address] [mask bit] means: *address = *address & ~mask; * Add set_dcd_param_v2 helper function to set DCD command parameters Signed-off-by: Adrian Alonso <aalonso(a)freescale.com> Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> --- Changes for V2 - Add set_dcd_param_v2 helper function to set DCD command tag and parameters Changes for V3 - Remove void set_dcd_param_v1, set_dcd_param to NULL for IMXIMAGE_V1 - Fix comments related to Check data command length tools/imximage.c | 95 ++++++++++++++++++++++++++++++++++++++++++++------------ tools/imximage.h | 25 ++++++++++----- 2 files changed, 93 insertions(+), 27 deletions(-) diff --git a/tools/imximage.c b/tools/imximage.c index 6f469ae..909efab 100644 --- a/tools/imximage.c +++ b/tools/imximage.c @@ -21,7 +21,10 @@ static table_entry_t imximage_cmds[] = { {CMD_BOOT_FROM, "BOOT_FROM", "boot command", }, {CMD_BOOT_OFFSET, "BOOT_OFFSET", "Boot offset", }, - {CMD_DATA, "DATA", "Reg Write Data", }, + {CMD_WRITE_DATA, "DATA", "Reg Write Data", }, + {CMD_WRITE_CLR_BIT, "CLR_BIT", "Reg clear bit", }, + {CMD_CHECK_BITS_SET, "CHECK_BITS_SET", "Reg Check bits set", }, + {CMD_CHECK_BITS_CLR, "CHECK_BITS_CLR", "Reg Check bits clr", }, {CMD_CSF, "CSF", "Command Sequence File", }, {CMD_IMAGE_VERSION, "IMAGE_VERSION", "image version", }, {-1, "", "", }, @@ -62,7 +65,7 @@ static table_entry_t imximage_boot_loadsize[] = { */ static table_entry_t imximage_versions[] = { {IMXIMAGE_V1, "", " (i.MX25/35/51 compatible)", }, - {IMXIMAGE_V2, "", " (i.MX53/6 compatible)", }, + {IMXIMAGE_V2, "", " (i.MX53/6/7 compatible)", }, {-1, "", " (Invalid)", }, }; @@ -79,6 +82,7 @@ static uint32_t imximage_csf_size = UNDEFINED; static uint32_t imximage_init_loadsize; static set_dcd_val_t set_dcd_val; +static set_dcd_param_t set_dcd_param; static set_dcd_rst_t set_dcd_rst; static set_imx_hdr_t set_imx_hdr; static uint32_t max_dcd_entries; @@ -156,6 +160,43 @@ static void set_dcd_val_v1(struct imx_header *imxhdr, char *name, int lineno, } } +static void set_dcd_param_v2(struct imx_header *imxhdr, uint32_t dcd_len, + int32_t cmd) +{ + dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table; + + switch (cmd) { + case CMD_WRITE_DATA: + dcd_v2->write_dcd_command.tag = DCD_WRITE_DATA_COMMAND_TAG; + dcd_v2->write_dcd_command.length = cpu_to_be16( + dcd_len * sizeof(dcd_addr_data_t) + 4); + dcd_v2->write_dcd_command.param = DCD_WRITE_DATA_PARAM; + break; + case CMD_WRITE_CLR_BIT: + dcd_v2->write_dcd_command.tag = DCD_WRITE_DATA_COMMAND_TAG; + dcd_v2->write_dcd_command.length = cpu_to_be16( + dcd_len * sizeof(dcd_addr_data_t) + 4); + dcd_v2->write_dcd_command.param = DCD_WRITE_CLR_BIT_PARAM; + break; + /* + * Check data command only supports one entry, + * so use 0xC = size(address + value + command). + */ + case CMD_CHECK_BITS_SET: + dcd_v2->write_dcd_command.tag = DCD_CHECK_DATA_COMMAND_TAG; + dcd_v2->write_dcd_command.length = cpu_to_be16(0xC); + dcd_v2->write_dcd_command.param = DCD_CHECK_BITS_SET_PARAM; + break; + case CMD_CHECK_BITS_CLR: + dcd_v2->write_dcd_command.tag = DCD_CHECK_DATA_COMMAND_TAG; + dcd_v2->write_dcd_command.length = cpu_to_be16(0xC); + dcd_v2->write_dcd_command.param = DCD_CHECK_BITS_SET_PARAM; + break; + default: + break; + } +} + static void set_dcd_val_v2(struct imx_header *imxhdr, char *name, int lineno, int fld, uint32_t value, uint32_t off) { @@ -200,10 +241,7 @@ static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len, dcd_v2->header.length = cpu_to_be16( dcd_len * sizeof(dcd_addr_data_t) + 8); dcd_v2->header.version = DCD_VERSION; - dcd_v2->write_dcd_command.tag = DCD_COMMAND_TAG; - dcd_v2->write_dcd_command.length = cpu_to_be16( - dcd_len * sizeof(dcd_addr_data_t) + 4); - dcd_v2->write_dcd_command.param = DCD_COMMAND_PARAM; + set_dcd_param_v2(imxhdr, dcd_len, CMD_WRITE_DATA); } static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len, @@ -266,12 +304,14 @@ static void set_hdr_func(void) switch (imximage_version) { case IMXIMAGE_V1: set_dcd_val = set_dcd_val_v1; + set_dcd_param = NULL; set_dcd_rst = set_dcd_rst_v1; set_imx_hdr = set_imx_hdr_v1; max_dcd_entries = MAX_HW_CFG_SIZE_V1; break; case IMXIMAGE_V2: set_dcd_val = set_dcd_val_v2; + set_dcd_param = set_dcd_param_v2; set_dcd_rst = set_dcd_rst_v2; set_imx_hdr = set_imx_hdr_v2; max_dcd_entries = MAX_HW_CFG_SIZE_V2; @@ -396,8 +436,13 @@ static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token, if (unlikely(cmd_ver_first != 1)) cmd_ver_first = 0; break; - case CMD_DATA: + case CMD_WRITE_DATA: + case CMD_WRITE_CLR_BIT: + case CMD_CHECK_BITS_SET: + case CMD_CHECK_BITS_CLR: value = get_cfg_value(token, name, lineno); + if (set_dcd_param) + (*set_dcd_param)(imxhdr, dcd_len, cmd); (*set_dcd_val)(imxhdr, name, lineno, fld, value, dcd_len); if (unlikely(cmd_ver_first != 1)) cmd_ver_first = 0; @@ -436,20 +481,30 @@ static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd, break; case CFG_REG_ADDRESS: case CFG_REG_VALUE: - if (*cmd != CMD_DATA) - return; - - value = get_cfg_value(token, name, lineno); - (*set_dcd_val)(imxhdr, name, lineno, fld, value, *dcd_len); - - if (fld == CFG_REG_VALUE) { - (*dcd_len)++; - if (*dcd_len > max_dcd_entries) { - fprintf(stderr, "Error: %s[%d] -" - "DCD table exceeds maximum size(%d)\n", - name, lineno, max_dcd_entries); - exit(EXIT_FAILURE); + switch(*cmd) { + case CMD_WRITE_DATA: + case CMD_WRITE_CLR_BIT: + case CMD_CHECK_BITS_SET: + case CMD_CHECK_BITS_CLR: + + value = get_cfg_value(token, name, lineno); + if (set_dcd_param) + (*set_dcd_param)(imxhdr, *dcd_len, *cmd); + (*set_dcd_val)(imxhdr, name, lineno, fld, value, + *dcd_len); + + if (fld == CFG_REG_VALUE) { + (*dcd_len)++; + if (*dcd_len > max_dcd_entries) { + fprintf(stderr, "Error: %s[%d] -" + "DCD table exceeds maximum size(%d)\n", + name, lineno, max_dcd_entries); + exit(EXIT_FAILURE); + } } + break; + default: + break; } break; default: diff --git a/tools/imximage.h b/tools/imximage.h index 36fe095..c199814 100644 --- a/tools/imximage.h +++ b/tools/imximage.h @@ -42,19 +42,27 @@ #define FLASH_LOADSIZE_SATA FLASH_LOADSIZE_STANDARD #define FLASH_LOADSIZE_QSPI 0x0 /* entire image */ -#define IVT_HEADER_TAG 0xD1 -#define IVT_VERSION 0x40 -#define DCD_HEADER_TAG 0xD2 -#define DCD_COMMAND_TAG 0xCC -#define DCD_VERSION 0x40 -#define DCD_COMMAND_PARAM 0x4 +/* Command tags and parameters */ +#define IVT_HEADER_TAG 0xD1 +#define IVT_VERSION 0x40 +#define DCD_HEADER_TAG 0xD2 +#define DCD_VERSION 0x40 +#define DCD_WRITE_DATA_COMMAND_TAG 0xCC +#define DCD_WRITE_DATA_PARAM 0x4 +#define DCD_WRITE_CLR_BIT_PARAM 0xC +#define DCD_CHECK_DATA_COMMAND_TAG 0xCF +#define DCD_CHECK_BITS_SET_PARAM 0x14 +#define DCD_CHECK_BITS_CLR_PARAM 0x04 enum imximage_cmd { CMD_INVALID, CMD_IMAGE_VERSION, CMD_BOOT_FROM, CMD_BOOT_OFFSET, - CMD_DATA, + CMD_WRITE_DATA, + CMD_WRITE_CLR_BIT, + CMD_CHECK_BITS_SET, + CMD_CHECK_BITS_CLR, CMD_CSF, }; @@ -167,6 +175,9 @@ typedef void (*set_dcd_val_t)(struct imx_header *imxhdr, int fld, uint32_t value, uint32_t off); +typedef void (*set_dcd_param_t)(struct imx_header *imxhdr, uint32_t dcd_len, + int32_t cmd); + typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr, uint32_t dcd_len, char *name, int lineno); -- 2.1.4

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[U-Boot] [PATCH v2] arm: mx6: tqma6: Add WRU-IV baseboard for the TQMa6 SoM
by Stefan Roese 26 Jul '15

26 Jul '15

This patch adds support for the "OHB System AG" baseboard with is equipped with the TQMa6S SoM. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Markus Niebel <Markus.Niebel(a)tq-group.com> Cc: Stefano Babic <sbabic(a)denx.de> --- v2: - board_eth_init() simplified as suggested by Markus - PHY reset GPIO only defined once as suggested by Markus - All GPIOs are now requested before usage as suggested by Markus - Used new tqma6 Kconfig IF as suggested by Markus board/tqc/tqma6/Kconfig | 5 + board/tqc/tqma6/Makefile | 1 + board/tqc/tqma6/tqma6_wru4.c | 346 ++++++++++++++++++++++++++++++++++++++ configs/tqma6s_wru4_mmc_defconfig | 12 ++ include/configs/tqma6.h | 2 + include/configs/tqma6_wru4.h | 71 ++++++++ 6 files changed, 437 insertions(+) create mode 100644 board/tqc/tqma6/tqma6_wru4.c create mode 100644 configs/tqma6s_wru4_mmc_defconfig create mode 100644 include/configs/tqma6_wru4.h diff --git a/board/tqc/tqma6/Kconfig b/board/tqc/tqma6/Kconfig index b56237d..dbd8787 100644 --- a/board/tqc/tqma6/Kconfig +++ b/board/tqc/tqma6/Kconfig @@ -64,6 +64,11 @@ config MBA6 Select the MBa6 starterkit. This features a GigE Phy, USB, SD-Card etc. +config WRU4 + bool "OHB WRU-IV" + help + Select the OHB Systems AG WRU-IV baseboard. + endchoice config IMX_CONFIG diff --git a/board/tqc/tqma6/Makefile b/board/tqc/tqma6/Makefile index 9ee6920..19b56d0 100644 --- a/board/tqc/tqma6/Makefile +++ b/board/tqc/tqma6/Makefile @@ -7,3 +7,4 @@ obj-y := tqma6.o obj-$(CONFIG_MBA6) += tqma6_mba6.o +obj-$(CONFIG_WRU4) += tqma6_wru4.o diff --git a/board/tqc/tqma6/tqma6_wru4.c b/board/tqc/tqma6/tqma6_wru4.c new file mode 100644 index 0000000..4427799 --- /dev/null +++ b/board/tqc/tqma6/tqma6_wru4.c @@ -0,0 +1,346 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Author: Fabio Estevam <fabio.estevam(a)freescale.com> + * + * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x) + * Author: Markus Niebel <markus.niebel(a)tq-group.com> + * + * Copyright (C) 2015 Stefan Roese <sr(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/sys_proto.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/mxc_i2c.h> + +#include <common.h> +#include <fsl_esdhc.h> +#include <libfdt.h> +#include <malloc.h> +#include <i2c.h> +#include <micrel.h> +#include <miiphy.h> +#include <mmc.h> +#include <netdev.h> + +#include "tqma6_bb.h" + +/* UART */ +#define UART4_PAD_CTRL ( \ + PAD_CTL_HYS | \ + PAD_CTL_PUS_100K_UP | \ + PAD_CTL_PUE | \ + PAD_CTL_PKE | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_SLOW \ + ) + +static iomux_v3_cfg_t const uart4_pads[] = { + NEW_PAD_CTRL(MX6_PAD_CSI0_DAT17__UART4_CTS_B, UART4_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_CSI0_DAT16__UART4_RTS_B, UART4_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_CSI0_DAT13__UART4_RX_DATA, UART4_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_CSI0_DAT12__UART4_TX_DATA, UART4_PAD_CTRL), +}; + +static void setup_iomuxc_uart4(void) +{ + imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); +} + +/* MMC */ +#define USDHC2_PAD_CTRL ( \ + PAD_CTL_HYS | \ + PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST \ + ) + +#define USDHC2_CLK_PAD_CTRL ( \ + PAD_CTL_HYS | \ + PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST \ + ) + +static iomux_v3_cfg_t const usdhc2_pads[] = { + NEW_PAD_CTRL(MX6_PAD_SD2_CLK__SD2_CLK, USDHC2_CLK_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD2_CMD__SD2_CMD, USDHC2_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD2_DAT0__SD2_DATA0, USDHC2_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD2_DAT1__SD2_DATA1, USDHC2_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD2_DAT2__SD2_DATA2, USDHC2_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD2_DAT3__SD2_DATA3, USDHC2_PAD_CTRL), + + NEW_PAD_CTRL(MX6_PAD_GPIO_4__GPIO1_IO04, USDHC2_PAD_CTRL), /* CD */ + NEW_PAD_CTRL(MX6_PAD_GPIO_2__SD2_WP, USDHC2_PAD_CTRL), /* WP */ +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) +#define USDHC2_WP_GPIO IMX_GPIO_NR(1, 2) + +static struct fsl_esdhc_cfg usdhc2_cfg = { + .esdhc_base = USDHC2_BASE_ADDR, + .max_bus_width = 4, +}; + +int tqma6_bb_board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC2_BASE_ADDR) + ret = !gpio_get_value(USDHC2_CD_GPIO); + + return ret; +} + +int tqma6_bb_board_mmc_getwp(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC2_BASE_ADDR) + ret = gpio_get_value(USDHC2_WP_GPIO); + + return ret; +} + +int tqma6_bb_board_mmc_init(bd_t *bis) +{ + int ret; + + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + + ret = gpio_request(USDHC2_CD_GPIO, "mmc-cd"); + if (!ret) + gpio_direction_input(USDHC2_CD_GPIO); + ret = gpio_request(USDHC2_WP_GPIO, "mmc-wp"); + if (!ret) + gpio_direction_input(USDHC2_WP_GPIO); + + usdhc2_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + if(fsl_esdhc_initialize(bis, &usdhc2_cfg)) + puts("WARNING: failed to initialize SD\n"); + + return 0; +} + +/* Ethernet */ +#define ENET_PAD_CTRL ( \ + PAD_CTL_HYS | \ + PAD_CTL_PUS_100K_UP | \ + PAD_CTL_PUE | \ + PAD_CTL_PKE | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_SLOW \ + ) + +static iomux_v3_cfg_t const enet_pads[] = { + NEW_PAD_CTRL(MX6_PAD_ENET_MDC__ENET_MDC, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_GPIO_16__ENET_REF_CLK, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_ENET_RXD0__ENET_RX_DATA0, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_ENET_RXD1__ENET_RX_DATA1, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_ENET_CRS_DV__ENET_RX_EN, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_ENET_RX_ER__ENET_RX_ER, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_ENET_TXD0__ENET_TX_DATA0, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_ENET_TXD1__ENET_TX_DATA1, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_ENET_TX_EN__ENET_TX_EN, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_GPIO_19__ENET_TX_ER, ENET_PAD_CTRL), + + /* ENET1 reset */ + NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, ENET_PAD_CTRL), + /* ENET1 interrupt */ + NEW_PAD_CTRL(MX6_PAD_GPIO_9__GPIO1_IO09, ENET_PAD_CTRL), +}; + +#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 8) + +static void setup_iomuxc_enet(void) +{ + int ret; + + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); + + /* Reset LAN8720 PHY */ + ret = gpio_request(ENET_PHY_RESET_GPIO, "phy-reset"); + if (!ret) + gpio_direction_output(ENET_PHY_RESET_GPIO , 0); + udelay(1000); + gpio_set_value(ENET_PHY_RESET_GPIO, 1); +} + +int board_eth_init(bd_t *bis) +{ + return cpu_eth_init(bis); +} + +/* GPIO */ +#define GPIO_PAD_CTRL ( \ + PAD_CTL_HYS | \ + PAD_CTL_PUS_100K_UP | \ + PAD_CTL_PUE | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_SLOW \ + ) + +#define GPIO_OD_PAD_CTRL ( \ + PAD_CTL_HYS | \ + PAD_CTL_PUS_100K_UP | \ + PAD_CTL_PUE | \ + PAD_CTL_ODE | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_SLOW \ + ) + +static iomux_v3_cfg_t const gpio_pads[] = { + /* USB_H_PWR */ + NEW_PAD_CTRL(MX6_PAD_GPIO_0__GPIO1_IO00, GPIO_PAD_CTRL), + /* USB_OTG_PWR */ + NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, GPIO_PAD_CTRL), + /* PCIE_RST */ + NEW_PAD_CTRL(MX6_PAD_NANDF_CLE__GPIO6_IO07, GPIO_OD_PAD_CTRL), + /* UART1_PWRON */ + NEW_PAD_CTRL(MX6_PAD_DISP0_DAT14__GPIO5_IO08, GPIO_PAD_CTRL), + /* UART2_PWRON */ + NEW_PAD_CTRL(MX6_PAD_DISP0_DAT16__GPIO5_IO10, GPIO_PAD_CTRL), + /* UART3_PWRON */ + NEW_PAD_CTRL(MX6_PAD_DISP0_DAT18__GPIO5_IO12, GPIO_PAD_CTRL), +}; + +#define GPIO_USB_H_PWR IMX_GPIO_NR(1, 0) +#define GPIO_USB_OTG_PWR IMX_GPIO_NR(3, 22) +#define GPIO_PCIE_RST IMX_GPIO_NR(6, 7) +#define GPIO_UART1_PWRON IMX_GPIO_NR(5, 8) +#define GPIO_UART2_PWRON IMX_GPIO_NR(5, 10) +#define GPIO_UART3_PWRON IMX_GPIO_NR(5, 12) + +static void gpio_init(void) +{ + int ret; + + imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); + + ret = gpio_request(GPIO_USB_H_PWR, "usb-h-pwr"); + if (!ret) + gpio_direction_output(GPIO_USB_H_PWR, 1); + ret = gpio_request(GPIO_USB_OTG_PWR, "usb-otg-pwr"); + if (!ret) + gpio_direction_output(GPIO_USB_OTG_PWR, 1); + ret = gpio_request(GPIO_PCIE_RST, "pcie-reset"); + if (!ret) + gpio_direction_output(GPIO_PCIE_RST, 1); + ret = gpio_request(GPIO_UART1_PWRON, "uart1-pwr"); + if (!ret) + gpio_direction_output(GPIO_UART1_PWRON, 0); + ret = gpio_request(GPIO_UART2_PWRON, "uart2-pwr"); + if (!ret) + gpio_direction_output(GPIO_UART2_PWRON, 0); + ret = gpio_request(GPIO_UART3_PWRON, "uart3-pwr"); + if (!ret) + gpio_direction_output(GPIO_UART3_PWRON, 0); +} + +void tqma6_iomuxc_spi(void) +{ + /* No SPI on this baseboard */ +} + +int tqma6_bb_board_early_init_f(void) +{ + setup_iomuxc_uart4(); + + return 0; +} + +int tqma6_bb_board_init(void) +{ + setup_iomuxc_enet(); + + gpio_init(); + + /* Turn the UART-couplers on one-after-another */ + gpio_set_value(GPIO_UART1_PWRON, 1); + mdelay(10); + gpio_set_value(GPIO_UART2_PWRON, 1); + mdelay(10); + gpio_set_value(GPIO_UART3_PWRON, 1); + + return 0; +} + +int tqma6_bb_board_late_init(void) +{ + return 0; +} + +const char *tqma6_bb_get_boardname(void) +{ + return "WRU-IV"; +} + +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + /* 8 bit bus width */ + {"emmc", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + { NULL, 0 }, +}; + +int misc_init_r(void) +{ + add_board_boot_modes(board_boot_modes); + + return 0; +} + +#define WRU4_USB_H1_PWR IMX_GPIO_NR(1, 0) +#define WRU4_USB_OTG_PWR IMX_GPIO_NR(3, 22) + +int board_ehci_hcd_init(int port) +{ + int ret; + + ret = gpio_request(WRU4_USB_H1_PWR, "usb-h1-pwr"); + if (!ret) + gpio_direction_output(WRU4_USB_H1_PWR, 1); + + ret = gpio_request(WRU4_USB_OTG_PWR, "usb-OTG-pwr"); + if (!ret) + gpio_direction_output(WRU4_USB_OTG_PWR, 1); + + return 0; +} + +int board_ehci_power(int port, int on) +{ + if (port) + gpio_set_value(WRU4_USB_OTG_PWR, on); + else + gpio_set_value(WRU4_USB_H1_PWR, on); + + return 0; +} + +/* + * Device Tree Support + */ +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +void tqma6_bb_ft_board_setup(void *blob, bd_t *bd) +{ + /* TBD */ +} +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/configs/tqma6s_wru4_mmc_defconfig b/configs/tqma6s_wru4_mmc_defconfig new file mode 100644 index 0000000..f362760 --- /dev/null +++ b/configs/tqma6s_wru4_mmc_defconfig @@ -0,0 +1,12 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_TQMA6=y +CONFIG_TQMA6S=y +CONFIG_WRU4=y +CONFIG_CMD_SETEXPR=y +CONFIG_CMD_NET=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Enter password in %d seconds to stop autoboot\n" +CONFIG_AUTOBOOT_ENCRYPTION=y +CONFIG_AUTOBOOT_STOP_STR_SHA256="36a9e7f1c95b82ffb99743e0c5c4ce95d83c9a430aac59f84ef3cbfab6145068" +CONFIG_PCA9551_LED=y diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index aa19f11..706b972 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -395,6 +395,8 @@ */ #ifdef CONFIG_MBA6 #include "tqma6_mba6.h" +#elif CONFIG_WRU4 +#include "tqma6_wru4.h" #else #error "No baseboard for the TQMa6 defined!" #endif diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h new file mode 100644 index 0000000..1c86bc0 --- /dev/null +++ b/include/configs/tqma6_wru4.h @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2015 Stefan Roese <sr(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_TQMA6_WRU4_H +#define __CONFIG_TQMA6_WRU4_H + +#define CONFIG_DEFAULT_FDT_FILE "imx6s-wru4.dtb" + +/* DTT sensors */ +#define CONFIG_DTT_SENSORS { 0, 1 } +#define CONFIG_SYS_DTT_BUS_NUM 2 + +/* Ethernet */ +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0x01 +#define CONFIG_PHY_SMSC + +/* UART */ +#define CONFIG_MXC_UART_BASE UART4_BASE +#define CONFIG_CONSOLE_DEV "ttymxc3" + +#define CONFIG_MISC_INIT_R + +/* Watchdog */ +#define CONFIG_HW_WATCHDOG +#define CONFIG_IMX_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000 + +/* Config on-board RTC */ +#define CONFIG_RTC_DS1337 +#define CONFIG_SYS_RTC_BUS_NUM 2 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +/* Turn off RTC square-wave output to save battery */ +#define CONFIG_SYS_RTC_DS1337_NOOSC +#define CONFIG_CMD_DATE + +#define CONFIG_CMD_GPIO + +/* LED */ +#define CONFIG_CMD_LED +#define CONFIG_STATUS_LED +#define CONFIG_BOARD_SPECIFIC_LED +#define STATUS_LED_BIT 0 +#define STATUS_LED_STATE STATUS_LED_ON +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) +#define STATUS_LED_BIT1 1 +#define STATUS_LED_STATE1 STATUS_LED_ON +#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) +#define STATUS_LED_BIT2 2 +#define STATUS_LED_STATE2 STATUS_LED_ON +#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2) +#define STATUS_LED_BIT3 3 +#define STATUS_LED_STATE3 STATUS_LED_ON +#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2) +#define STATUS_LED_BIT4 4 +#define STATUS_LED_STATE4 STATUS_LED_ON +#define STATUS_LED_PERIOD4 (CONFIG_SYS_HZ / 2) +#define STATUS_LED_BIT5 5 +#define STATUS_LED_STATE5 STATUS_LED_ON +#define STATUS_LED_PERIOD5 (CONFIG_SYS_HZ / 2) + +/* Bootcounter */ +#define CONFIG_BOOTCOUNT_LIMIT +#define CONFIG_SYS_BOOTCOUNT_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_BOOTCOUNT_BE + +#endif /* __CONFIG_TQMA6_WRU4_H */ -- 2.4.5

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[U-Boot] [PATCH v3 01/15] cgtqmx6eval: Use default prompt
by Otavio Salvador 26 Jul '15

26 Jul '15

Remove the custom prompt and use the default instead. Signed-off-by: Otavio Salvador <otavio(a)ossystems.com.br> --- Changes in v3: None Changes in v2: None include/configs/cgtqmx6eval.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index dd06c05..5f753e7 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -87,9 +87,6 @@ "fi; " \ "else echo ERR: Fail to boot from mmc; fi" -/* Miscellaneous configurable options */ -#define CONFIG_SYS_PROMPT "CGT-QMX6-Quad U-Boot > " - /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -- 2.4.6

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