July 2015 - U-Boot

[U-Boot] [PATCH] zynq: enable CONFIG_NET_RANDOM_ETHADDR
by Masahiro Yamada 12 Aug '15

12 Aug '15

We have to set a MAC address to use network. Otherwise, the tftpboot command fails with the following message: Gem.e000b000 Waiting for PHY auto negotiation to complete........ done *** ERROR: `ethaddr' not set Since commit 92ac52082140 ("net: Remove all references to CONFIG_ETHADDR and friends"), we can not use CONFIG_ETHADDR. The easiest way to set a MAC address is to enable CONFIG_NET_RANDOM_ETHADDR. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- configs/zynq_microzed_defconfig | 1 + configs/zynq_picozed_defconfig | 1 + configs/zynq_zc702_defconfig | 1 + configs/zynq_zc706_defconfig | 1 + configs/zynq_zc70x_defconfig | 1 + configs/zynq_zc770_xm010_defconfig | 1 + configs/zynq_zc770_xm012_defconfig | 1 + configs/zynq_zc770_xm013_defconfig | 1 + configs/zynq_zed_defconfig | 1 + configs/zynq_zybo_defconfig | 1 + 10 files changed, 10 insertions(+) diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index c878924..7914222 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -10,3 +10,4 @@ CONFIG_FIT_SIGNATURE=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig index af77a9d..a10bc85 100644 --- a/configs/zynq_picozed_defconfig +++ b/configs/zynq_picozed_defconfig @@ -6,3 +6,4 @@ CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig index 5dde452..53b03ca 100644 --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@ -10,3 +10,4 @@ CONFIG_FIT_SIGNATURE=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index 0f96d16..657af84 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -10,3 +10,4 @@ CONFIG_FIT_SIGNATURE=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/zynq_zc70x_defconfig b/configs/zynq_zc70x_defconfig index 525c538..6358146 100644 --- a/configs/zynq_zc70x_defconfig +++ b/configs/zynq_zc70x_defconfig @@ -10,3 +10,4 @@ CONFIG_FIT_SIGNATURE=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig index f1fc283..6d2e4d4 100644 --- a/configs/zynq_zc770_xm010_defconfig +++ b/configs/zynq_zc770_xm010_defconfig @@ -11,4 +11,5 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig index 73ed13d..5968c52 100644 --- a/configs/zynq_zc770_xm012_defconfig +++ b/configs/zynq_zc770_xm012_defconfig @@ -9,3 +9,4 @@ CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012" # CONFIG_CMD_SETEXPR is not set +CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig index 211a41d..198e000 100644 --- a/configs/zynq_zc770_xm013_defconfig +++ b/configs/zynq_zc770_xm013_defconfig @@ -11,3 +11,4 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index f3c63f9..4a98646 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -10,3 +10,4 @@ CONFIG_FIT_SIGNATURE=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index 0c6117d..c9073d5 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -10,3 +10,4 @@ CONFIG_FIT_SIGNATURE=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_NET_RANDOM_ETHADDR=y -- 1.9.1

3 2

[U-Boot] [PATCH] power: regulator: max77686 correct variable type
by Peng Fan 12 Aug '15

12 Aug '15

The return type of pmic_read and pmic_write is signed int, so correct variable 'ret' from type unsigned int to int. Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Przemyslaw Marczak <p.marczak(a)samsung.com> --- drivers/power/regulator/max77686.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/power/regulator/max77686.c b/drivers/power/regulator/max77686.c index 37ebe94..29d2632 100644 --- a/drivers/power/regulator/max77686.c +++ b/drivers/power/regulator/max77686.c @@ -313,9 +313,9 @@ static int max77686_ldo_modes(int ldo, struct dm_regulator_mode **modesp, static int max77686_ldo_val(struct udevice *dev, int op, int *uV) { - unsigned int ret, hex, adr; + unsigned int hex, adr; unsigned char val; - int ldo; + int ldo, ret; if (op == PMIC_OP_GET) *uV = 0; @@ -354,9 +354,9 @@ static int max77686_ldo_val(struct udevice *dev, int op, int *uV) static int max77686_buck_val(struct udevice *dev, int op, int *uV) { - unsigned int hex, ret, mask, adr; + unsigned int hex, mask, adr; unsigned char val; - int buck; + int buck, ret; buck = dev->driver_data; if (buck < 1 || buck > MAX77686_BUCK_NUM) { @@ -408,9 +408,9 @@ static int max77686_buck_val(struct udevice *dev, int op, int *uV) static int max77686_ldo_mode(struct udevice *dev, int op, int *opmode) { - unsigned int ret, adr, mode; + unsigned int adr, mode; unsigned char val; - int ldo; + int ldo, ret; if (op == PMIC_OP_GET) *opmode = -EINVAL; @@ -539,9 +539,9 @@ static int max77686_ldo_enable(struct udevice *dev, int op, bool *enable) static int max77686_buck_mode(struct udevice *dev, int op, int *opmode) { - unsigned int ret, mask, adr, mode, mode_shift; + unsigned int mask, adr, mode, mode_shift; unsigned char val; - int buck; + int buck, ret; buck = dev->driver_data; if (buck < 1 || buck > MAX77686_BUCK_NUM) { -- 1.8.4

3 2

[U-Boot] [PATCH] ls2085a: esdhc: flush D-cache before 'mmc read'
by Yangbo Lu 12 Aug '15

12 Aug '15

It needs to flush D-cache before 'mmc read' so that we can see the right data in DDR. And fix parameter for invalidate_dcache_range() after 'mmc read'. Signed-off-by: Yangbo Lu <yangbo.lu(a)freescale.com> Cc: York Sun <yorksun(a)freescale.com> --- drivers/mmc/fsl_esdhc.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index c4719e6..3ca25bd 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -192,6 +192,17 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) wml_value = data->blocksize/4; if (data->flags & MMC_DATA_READ) { +#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO +#ifdef CONFIG_LS2085A + /* + * It's temporary for ls2085a so that + * we can see right data in DDR + */ + flush_dcache_range((ulong)data->dest, + (ulong)data->dest+data->blocks + *data->blocksize); +#endif +#endif if (wml_value > WML_RD_WML_MAX) wml_value = WML_RD_WML_MAX_VAL; @@ -278,14 +289,9 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) static void check_and_invalidate_dcache_range (struct mmc_cmd *cmd, struct mmc_data *data) { -#ifdef CONFIG_LS2085A - unsigned start = 0; -#else - unsigned start = (unsigned)data->dest ; -#endif + unsigned start, end; unsigned size = roundup(ARCH_DMA_MINALIGN, data->blocks*data->blocksize); - unsigned end = start+size ; #ifdef CONFIG_LS2085A dma_addr_t addr; @@ -294,7 +300,10 @@ static void check_and_invalidate_dcache_range printf("Error found for upper 32 bits\n"); else start = lower_32_bits(addr); +#else + start = (unsigned)data->dest; #endif + end = start + size; invalidate_dcache_range(start, end); } #endif -- 2.1.0.27.g96db324

3 2

[U-Boot] [PATCH] net/fm: Update FMan Compatibels
by Igal.Liberman 12 Aug '15

12 Aug '15

From: Igal Liberman <igal.liberman(a)freescale.com> During FMan upstreaming, the FMan Port and MAC compatibles changed. This patch aligns the FMan Port and MAC compatibles to the FMan device tree binding document. The FMan device tree binding document can be found in the Linux kernel: ./Documentation/devicetree/bindings/powerpc/fsl/fman.txt Signed-off-by: Igal Liberman <igal.liberman(a)freescale.com> --- arch/powerpc/include/asm/fsl_liodn.h | 20 ++++++++++++++++---- drivers/net/fm/init.c | 4 ++-- 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index 811f034..d493f8c 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -133,15 +133,27 @@ extern void fdt_fixup_liodn(void *blob); CONFIG_SYS_FSL_FM##fmNum##_OFFSET + \ offsetof(struct ccsr_fman, fm_bmi_common.fmbm_ppid[portID - 1]) -/* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */ +#ifdef CONFIG_SYS_FMAN_V3 +#define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \ + _SET_FMAN_RX_1G_LIODN("fsl,fman-v3-port-rx", fmNum, enetNum, liodn) +#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \ + _SET_FMAN_RX_10G_LION("fsl,fman-v3-port-rx", fmNum, enetNum, liodn) +#else #define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \ - SET_LIODN_ENTRY_1("fsl,fman-port-1g-rx", liodn, \ + _SET_FMAN_RX_1G_LIODN("fsl,fman-v2-port-rx", fmNum, enetNum, liodn) +#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \ + _SET_FMAN_RX_10G_LIODN("fsl,fman-v2-port-rx", fmNum, enetNum, liodn) +#endif + +/* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */ +#define _SET_FMAN_RX_1G_LIODN(compatible, fmNum, enetNum, liodn) \ + SET_LIODN_ENTRY_1(compatible, liodn, \ FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \ CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) \ /* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */ -#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \ - SET_LIODN_ENTRY_1("fsl,fman-port-10g-rx", liodn, \ +#define _SET_FMAN_RX_10G_LIODN(compatible, fmNum, enetNum, liodn) \ + SET_LIODN_ENTRY_1(compatible, liodn, \ FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \ CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) \ diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c index 9a8a007..4e43cca 100644 --- a/drivers/net/fm/init.c +++ b/drivers/net/fm/init.c @@ -306,9 +306,9 @@ void fdt_fixup_fman_ethernet(void *blob) #else for (i = 0; i < ARRAY_SIZE(fm_info); i++) { if (fm_info[i].type == FM_ETH_1G_E) - ft_fixup_port(blob, &fm_info[i], "fsl,fman-1g-mac"); + ft_fixup_port(blob, &fm_info[i], "fsl,fman-dtsec"); else - ft_fixup_port(blob, &fm_info[i], "fsl,fman-10g-mac"); + ft_fixup_port(blob, &fm_info[i], "fsl,fman-xgec"); } #endif } -- 1.7.9.5

4 3

[U-Boot] [PATCH] mmc_spi: Big-endian support
by Yoshinori Sato 12 Aug '15

12 Aug '15

Currently implement always swap for big-endian value. So doesn't work big-endian environment. Signed-off-by: Yoshinori Sato <ysato(a)users.sourceforge.jp> --- drivers/mmc/mmc_spi.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/mmc_spi.c b/drivers/mmc/mmc_spi.c index 5b5b33a..9032a73 100644 --- a/drivers/mmc/mmc_spi.c +++ b/drivers/mmc/mmc_spi.c @@ -11,7 +11,7 @@ #include <spi.h> #include <crc.h> #include <linux/crc7.h> -#include <linux/byteorder/swab.h> +#include <asm/byteorder.h> /* MMC/SD in SPI mode reports R1 status always */ #define R1_SPI_IDLE (1 << 0) @@ -91,7 +91,7 @@ static uint mmc_spi_readdata(struct mmc *mmc, void *xbuf, spi_xfer(spi, bsize * 8, NULL, buf, 0); spi_xfer(spi, 2 * 8, NULL, &crc, 0); #ifdef CONFIG_MMC_SPI_CRC_ON - if (swab16(cyg_crc16(buf, bsize)) != crc) { + if (be_to_cpu16(cyg_crc16(buf, bsize)) != crc) { debug("%s: CRC error\n", mmc->cfg->name); r1 = R1_SPI_COM_CRC; break; @@ -120,7 +120,7 @@ static uint mmc_spi_writedata(struct mmc *mmc, const void *xbuf, tok[1] = multi ? SPI_TOKEN_MULTI_WRITE : SPI_TOKEN_SINGLE; while (bcnt--) { #ifdef CONFIG_MMC_SPI_CRC_ON - crc = swab16(cyg_crc16((u8 *)buf, bsize)); + crc = cpu_to_be16(cyg_crc16((u8 *)buf, bsize)); #endif spi_xfer(spi, 2 * 8, tok, NULL, 0); spi_xfer(spi, bsize * 8, buf, NULL, 0); @@ -193,7 +193,7 @@ static int mmc_spi_request(struct mmc *mmc, struct mmc_cmd *cmd, } else if (cmd->resp_type == MMC_RSP_R2) { r1 = mmc_spi_readdata(mmc, cmd->response, 1, 16); for (i = 0; i < 4; i++) - cmd->response[i] = swab32(cmd->response[i]); + cmd->response[i] = be32_to_cpu(cmd->response[i]); debug("r128 %x %x %x %x\n", cmd->response[0], cmd->response[1], cmd->response[2], cmd->response[3]); } else if (!data) { @@ -205,7 +205,7 @@ static int mmc_spi_request(struct mmc *mmc, struct mmc_cmd *cmd, case SD_CMD_SEND_IF_COND: case MMC_CMD_SPI_READ_OCR: spi_xfer(spi, 4 * 8, NULL, cmd->response, 0); - cmd->response[0] = swab32(cmd->response[0]); + cmd->response[0] = be32_to_cpu(cmd->response[0]); debug("r32 %x\n", cmd->response[0]); break; case MMC_CMD_SEND_STATUS: -- 2.1.4

2 1

[U-Boot] [PATCH 0/3] DM9000 support for multiple interfaces
by Andrew Ruder 11 Aug '15

11 Aug '15

This is a rework of the DM9000 driver to support registering interfaces dynamically (i.e. determine how many ethernet chips we have at boot and register 0, 1, 2, or more). It was tested on a yet-to-be-submitted board which is based on the PXA270 + 0, 1, or 2 DM9000 chips. To maintain backwards compatibility with older board files, we add a new initialize function taking the io address, data address, and availability of a SROM chip. The old initialize function is now a shim around this new initialize function but provides the parameters based on the old DM9000 preprocessor symbols. I have compile-tested this on all the arm-based boards. Cc: Joe Hershberger <joe.hershberger(a)gmail.com> Andrew Ruder (3): dm9000: mark dump_regs() function as unused dm9000: Add struct eth_device * to SROM functions dm9000: rework dm9000 to support multiple devices board/trizepsiv/eeprom.c | 5 +- drivers/net/dm9000x.c | 382 +++++++++++++++++++++++++++-------------------- include/dm9000.h | 8 +- include/netdev.h | 1 + 4 files changed, 224 insertions(+), 172 deletions(-) -- 2.1.1

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[U-Boot] [PATCH v1 0/3] sparc: Add support for Gaisler GR712RC-BOARD Development Kit
by Francois Retief 11 Aug '15

11 Aug '15

This patch series add support for the Aeroflex Gaisler GR712RC-BOARD Development Kit. It builds on top of the previous SPARC architecture update series. Francois Retief (3): sparc: Make LEON serial drivers use readl/writel macros sparc: Add MDIO support to GRETH driver sparc: Add support for gr712rc-board arch/sparc/Kconfig | 8 + arch/sparc/cpu/leon2/serial.c | 121 +++++----- arch/sparc/cpu/leon3/serial.c | 93 ++++---- arch/sparc/include/asm/io.h | 43 ++-- board/gaisler/gr712rc_board/Kconfig | 9 + board/gaisler/gr712rc_board/MAINTAINERS | 6 + board/gaisler/gr712rc_board/Makefile | 8 + board/gaisler/gr712rc_board/README | 24 ++ board/gaisler/gr712rc_board/gr712rc_board.c | 68 ++++++ common/cmd_bdinfo.c | 4 + configs/gr712rc_board_defconfig | 3 + drivers/net/greth.c | 57 +++++ include/configs/gr712rc_board.h | 333 ++++++++++++++++++++++++++++ include/configs/gr_cpci_ax2000.h | 4 - include/configs/gr_ep2s60.h | 4 - include/configs/gr_xc3s_1500.h | 4 - include/configs/grsim.h | 3 - 17 files changed, 650 insertions(+), 142 deletions(-) create mode 100644 board/gaisler/gr712rc_board/Kconfig create mode 100644 board/gaisler/gr712rc_board/MAINTAINERS create mode 100644 board/gaisler/gr712rc_board/Makefile create mode 100644 board/gaisler/gr712rc_board/README create mode 100644 board/gaisler/gr712rc_board/gr712rc_board.c create mode 100644 configs/gr712rc_board_defconfig create mode 100644 include/configs/gr712rc_board.h -- 1.9.3 ________________________________ Disclaimer and confidentiality note – refer to our website for further details: www.spaceteq.co.za <http://www.spaceteq.co.za/home/emaildisclaimer/>

3 5

[U-Boot] [V4 1/2] sf: Add clear flag status register operation on Micron chips
by Zhiqiang Hou 11 Aug '15

11 Aug '15

From: Hou Zhiqiang <B48286(a)freescale.com> Add clear flag status register operation that was required by Micron SPI flash chips after reading the flag status register to check if the erase and program operations complete or an error occur. Signed-off-by: Hou Zhiqiang <B48286(a)freescale.com> Signed-off-by: Mingkai.Hu <Mingkai.Hu(a)freescale.com> --- drivers/mtd/spi/sf_internal.h | 9 +++++++++ drivers/mtd/spi/sf_ops.c | 40 ++++++++++++++++++++++++++++++++-------- 2 files changed, 41 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 9fb5557..703d4a7 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -73,6 +73,7 @@ enum { #define CMD_WRITE_ENABLE 0x06 #define CMD_READ_CONFIG 0x35 #define CMD_FLAG_STATUS 0x70 +#define CMD_CLEAR_FLAG_STATUS 0x50 /* Read commands */ #define CMD_READ_ARRAY_SLOW 0x03 @@ -96,6 +97,8 @@ enum { #define STATUS_QEB_WINSPAN (1 << 1) #define STATUS_QEB_MXIC (1 << 6) #define STATUS_PEC (1 << 7) +#define STATUS_PROT (1 << 1) +#define STATUS_ERASE (1 << 5) /* Flash timeout values */ #define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ) @@ -182,6 +185,12 @@ static inline int spi_flash_cmd_write_disable(struct spi_flash *flash) return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0); } +/* Clear flag status register */ +static inline int spi_flash_cmd_clear_flag_status(struct spi_slave *spi) +{ + return spi_flash_cmd(spi, CMD_CLEAR_FLAG_STATUS, NULL, 0); +} + /* * Send the read status command to the device and wait for the wip * (write-in-progress) bit to clear itself. diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index 38592f5..cbb9f00 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -160,6 +160,7 @@ static int spi_flash_poll_status(struct spi_slave *spi, unsigned long timeout, unsigned long timebase; unsigned long flags = SPI_XFER_BEGIN; int ret; + int out_of_time = 1; u8 status; u8 check_status = 0x0; @@ -182,22 +183,45 @@ static int spi_flash_poll_status(struct spi_slave *spi, unsigned long timeout, WATCHDOG_RESET(); ret = spi_xfer(spi, 8, NULL, &status, 0); - if (ret) + if (ret) { + spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END); return -1; + } - if ((status & poll_bit) == check_status) + if ((status & poll_bit) == check_status) { + out_of_time = 0; break; + } } while (get_timer(timebase) < timeout); spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END); - if ((status & poll_bit) == check_status) - return 0; + if (out_of_time) { + /* Timed out */ + debug("SF: time out!\n"); + if (cmd == CMD_FLAG_STATUS) { + if (spi_flash_cmd_clear_flag_status(spi) < 0) + debug("SF: clear flag status failed\n"); + } + ret = -1; + } +#ifdef CONFIG_SPI_FLASH_STMICRO + else if (cmd == CMD_FLAG_STATUS) { + if (!(status & (STATUS_PROT | STATUS_ERASE))) { + ret = 0; + } else { + debug("SF: flag status error"); + ret = -1; + } - /* Timed out */ - debug("SF: time out!\n"); - return -1; + if (spi_flash_cmd_clear_flag_status(spi) < 0) { + debug("SF: clear flag status failed\n"); + ret = -1; + } + } +#endif + return ret; } int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) @@ -252,7 +276,7 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, ret = spi_flash_cmd_wait_ready(flash, timeout); if (ret < 0) { - debug("SF: write %s timed out\n", + debug("SF: write %s failed\n", timeout == SPI_FLASH_PROG_TIMEOUT ? "program" : "page erase"); return ret; -- 2.1.0.27.g96db324

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[U-Boot] [PATCH v3 00/15] imx: Add i.MX6UL and basic board support
by Peng Fan 11 Aug '15

11 Aug '15

Add i.MX 6UltraLite support and include mx6ul_14x14_evk basic board support. i.MX 6UltraLite is a high performance, ultra-efficient processor family featuring an advanced implementation of a single Cortex-A7 core. This patch set is based on i.MX6QP patch v5 set: https://patchwork.ozlabs.org/patch/493961/ https://patchwork.ozlabs.org/patch/493962/ https://patchwork.ozlabs.org/patch/493963/ https://patchwork.ozlabs.org/patch/493964/ https://patchwork.ozlabs.org/patch/493965/ https://patchwork.ozlabs.org/patch/493966/ Changes v3: 1. fix WDOG3_BASE_ADDR according Marek's suggestion for patch 3/15 2. Add uboot boot log for patch 15/15 Changes v2: 1. refine commit msg 2. split CONFIG_SYS_CACHELINE_SIZE part into a single patch 3. discard system counter, default use GPT now. 4. SPL support Peng Fan (15): imx: mx6ul: Add i.MX6UL CPU type imx: mx6ul: Add pins IOMUX head file imx: mx6ul: Update imx registers head file imx: mx6ul Add CONFIG_SYS_CACHELINE_SIZE for i.MX6UL imx-common: timer: add i.MX6UL support imx: mx6ul remove errata for i.MX6UL imx:mx6ul add clock support imx: mx6ul select SYS_L2CACHE_OFF imx: mx6ul update soc related settings imx: mx6 add PAD_CTL_SPEED_LOW for i.MX6SX/UL mxc: gpio add i.MX6UL support mx6_common: Fix LOADADDR and SYS_TEXT_BASE for i.MX6UL imx:mx6ul add dram spl configuration and header file imx: imx6_spl add mx6ul support imx: mx6ul_14x14_evk add basic board support arch/arm/Kconfig | 8 + arch/arm/cpu/armv7/mx6/Kconfig | 4 + arch/arm/cpu/armv7/mx6/clock.c | 151 +-- arch/arm/cpu/armv7/mx6/ddr.c | 61 +- arch/arm/cpu/armv7/mx6/soc.c | 9 +- arch/arm/imx-common/cpu.c | 2 + arch/arm/imx-common/timer.c | 8 +- arch/arm/include/asm/arch-imx/cpu.h | 3 +- arch/arm/include/asm/arch-mx6/crm_regs.h | 98 +- arch/arm/include/asm/arch-mx6/imx-regs.h | 64 +- arch/arm/include/asm/arch-mx6/mx6-ddr.h | 45 + arch/arm/include/asm/arch-mx6/mx6-pins.h | 2 + arch/arm/include/asm/arch-mx6/mx6ul-ddr.h | 45 + arch/arm/include/asm/arch-mx6/mx6ul_pins.h | 1065 +++++++++++++++++++++ arch/arm/include/asm/imx-common/iomux-v3.h | 4 + board/freescale/mx6ul_14x14_evk/Kconfig | 15 + board/freescale/mx6ul_14x14_evk/MAINTAINERS | 6 + board/freescale/mx6ul_14x14_evk/Makefile | 6 + board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 636 ++++++++++++ configs/mx6ul_14x14_evk_defconfig | 4 + drivers/gpio/mxc_gpio.c | 4 + include/configs/imx6_spl.h | 2 +- include/configs/mx6_common.h | 6 +- include/configs/mx6ul_14x14_evk.h | 227 +++++ 24 files changed, 2338 insertions(+), 137 deletions(-) create mode 100644 arch/arm/include/asm/arch-mx6/mx6ul-ddr.h create mode 100644 arch/arm/include/asm/arch-mx6/mx6ul_pins.h create mode 100644 board/freescale/mx6ul_14x14_evk/Kconfig create mode 100644 board/freescale/mx6ul_14x14_evk/MAINTAINERS create mode 100644 board/freescale/mx6ul_14x14_evk/Makefile create mode 100644 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c create mode 100644 configs/mx6ul_14x14_evk_defconfig create mode 100644 include/configs/mx6ul_14x14_evk.h -- 1.8.4

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[U-Boot] [PATCH] dfu: Delete superfluous initialization of the dfu_buf_size static variable
by Lukasz Majewski 11 Aug '15

11 Aug '15

After extension of the dfu_get_buf() to also setup (implicitly) the dfu_buf_size variable it is not needed to set dfu_buf_size to CONFIG_SYS_DFU_DATA_BUF_SIZE. This variable is set in the dfu_get_buf() by not only considering CONFIG_SYS_DFU_DATA_BUF but more importantly the "dfu_bufsiz" env variable. Therefore, dfu_get_buf() should be used for initialization. Signed-off-by: Lukasz Majewski <l.majewski(a)majess.pl> --- drivers/dfu/dfu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index 0560afa..332be67 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -76,7 +76,7 @@ int dfu_init_env_entities(char *interface, char *devstr) } static unsigned char *dfu_buf; -static unsigned long dfu_buf_size = CONFIG_SYS_DFU_DATA_BUF_SIZE; +static unsigned long dfu_buf_size; unsigned char *dfu_free_buf(void) { -- 2.1.4

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