May 2015 - U-Boot

Re: [U-Boot] [PATCH 5/6] mmc: hi6220_dw_mmc: Add hi6220 glue code for dw_mmc controller.
by Marek Vasut 13 May '15

13 May '15

On Tuesday, May 12, 2015 at 03:38:31 PM, Peter Griffin wrote: > This patch adds the glue code for hi6220 SoC which has 2x synopsis > dw_mmc controllers. This will be used by the hikey board support > in subsequent patches. > > Signed-off-by: Peter Griffin <peter.griffin(a)linaro.org> [...] > diff --git a/drivers/mmc/hi6220_dw_mmc.c b/drivers/mmc/hi6220_dw_mmc.c > new file mode 100644 > index 0000000..a3880a3 > --- /dev/null > +++ b/drivers/mmc/hi6220_dw_mmc.c > @@ -0,0 +1,63 @@ > +/* > + * (C) Copyright 2015 Linaro > + * peter.griffin <peter.griffin(a)linaro.org> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <dwmmc.h> > +#include <malloc.h> > +#include <asm-generic/errno.h> > + > +#define DWMMC_MAX_CH_NUM 4 > + > +/* > +#define DWMMC_MAX_FREQ 52000000 > +#define DWMMC_MIN_FREQ 400000 > +*/ Please zap these dead macros. > +/*TODO we should probably use the frequencies above, but ATF uses > + the ones below so stick with that for the moment */ > +#define DWMMC_MAX_FREQ 50000000 > +#define DWMMC_MIN_FREQ 378000 > + > +/* Source clock is configured to 100Mhz by ATF bl1*/ > +#define MMC0_DEFAULT_FREQ 100000000 [...] > +int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width) > +{ > + struct dwmci_host *host = NULL; > + > + host = malloc(sizeof(struct dwmci_host)); calloc(1, sizeof(...)) so the data are inited/zero'd out please. [...]

2 1

[U-Boot] [PATCH] ARM: at91: trival: fix typo for the nand partition name
by Josh Wu 13 May '15

13 May '15

We should use 'env' to present environment instead of 'evn' Signed-off-by: Josh Wu <josh.wu(a)atmel.com> --- include/configs/at91-sama5_common.h | 2 +- include/configs/at91sam9rlek.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h index dedb785..94981e7 100644 --- a/include/configs/at91-sama5_common.h +++ b/include/configs/at91-sama5_common.h @@ -64,7 +64,7 @@ #define CONFIG_BOOTARGS \ "console=ttyS0,115200 earlyprintk " \ "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ - "256K(env),256k(evn_redundent),256k(spare)," \ + "256K(env),256k(env_redundent),256k(spare)," \ "512k(dtb),6M(kernel)ro,-(rootfs) " \ "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" #endif diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index 6c1bd30..e43795b 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -171,7 +171,7 @@ #define CONFIG_BOOTARGS \ "console=ttyS0,115200 earlyprintk " \ "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ - "256K(env),256k(evn_redundent),256k(spare)," \ + "256K(env),256k(env_redundent),256k(spare)," \ "512k(dtb),6M(kernel)ro,-(rootfs) " \ "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" -- 1.9.1

2 1

[U-Boot] [PATCH 0/3] ARM: remove non-generic boards.
by Masahiro Yamada 13 May '15

13 May '15

In spite of several times alerts, there are still many boards left unconverted. This series removes some of non-generic (=unmaitained) boards. If there is a problem with this series, please speak up! Masahiro Yamada (3): ARM: at91: remove non-generic boards ARM: davinci: remove non-generic boards ARM: omap3: remove non-generic boards arch/arm/cpu/armv7/omap3/Kconfig | 21 - arch/arm/mach-at91/Kconfig | 15 - arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c | 2 +- arch/arm/mach-davinci/Kconfig | 37 - arch/arm/mach-davinci/Makefile | 5 - arch/arm/mach-davinci/cpu.c | 54 - arch/arm/mach-davinci/dm355.c | 30 - arch/arm/mach-davinci/dm365.c | 20 - arch/arm/mach-davinci/dm365_lowlevel.c | 460 -------- arch/arm/mach-davinci/dm644x.c | 81 -- arch/arm/mach-davinci/dm646x.c | 26 - arch/arm/mach-davinci/include/mach/aintc_defs.h | 36 - arch/arm/mach-davinci/include/mach/emac_defs.h | 25 +- arch/arm/mach-davinci/include/mach/gpio.h | 5 +- arch/arm/mach-davinci/include/mach/hardware.h | 61 -- arch/arm/mach-davinci/include/mach/psc_defs.h | 70 -- arch/arm/mach-davinci/include/mach/syscfg_defs.h | 50 - arch/arm/mach-davinci/lowlevel_init.S | 664 ------------ arch/arm/mach-davinci/psc.c | 63 -- arch/arm/mach-davinci/spl.c | 3 - board/afeb9260/Kconfig | 9 - board/afeb9260/MAINTAINERS | 6 - board/afeb9260/Makefile | 13 - board/afeb9260/afeb9260.c | 159 --- board/afeb9260/config.mk | 1 - board/afeb9260/partition.c | 21 - board/ait/cam_enc_4xx/Kconfig | 12 - board/ait/cam_enc_4xx/MAINTAINERS | 6 - board/ait/cam_enc_4xx/Makefile | 10 - board/ait/cam_enc_4xx/cam_enc_4xx.c | 1106 -------------------- board/ait/cam_enc_4xx/config.mk | 20 - board/ait/cam_enc_4xx/u-boot-spl.lds | 57 - board/ait/cam_enc_4xx/ublimage.cfg | 31 - board/calao/sbc35_a9g20/Kconfig | 12 - board/calao/sbc35_a9g20/MAINTAINERS | 7 - board/calao/sbc35_a9g20/Makefile | 13 - board/calao/sbc35_a9g20/config.mk | 1 - board/calao/sbc35_a9g20/sbc35_a9g20.c | 155 --- board/calao/sbc35_a9g20/spi.c | 41 - board/calao/tny_a9260/Kconfig | 12 - board/calao/tny_a9260/MAINTAINERS | 9 - board/calao/tny_a9260/Makefile | 13 - board/calao/tny_a9260/config.mk | 1 - board/calao/tny_a9260/spi.c | 34 - board/calao/tny_a9260/tny_a9260.c | 85 -- board/comelit/dig297/Kconfig | 12 - board/comelit/dig297/MAINTAINERS | 6 - board/comelit/dig297/Makefile | 8 - board/comelit/dig297/dig297.c | 182 ---- board/comelit/dig297/dig297.h | 367 ------- board/davinci/dm355evm/Kconfig | 12 - board/davinci/dm355evm/MAINTAINERS | 6 - board/davinci/dm355evm/Makefile | 10 - board/davinci/dm355evm/config.mk | 11 - board/davinci/dm355evm/dm355evm.c | 144 --- board/davinci/dm355leopard/Kconfig | 12 - board/davinci/dm355leopard/MAINTAINERS | 6 - board/davinci/dm355leopard/Makefile | 10 - board/davinci/dm355leopard/config.mk | 6 - board/davinci/dm355leopard/dm355leopard.c | 86 -- board/davinci/dm365evm/Kconfig | 12 - board/davinci/dm365evm/MAINTAINERS | 6 - board/davinci/dm365evm/Makefile | 10 - board/davinci/dm365evm/config.mk | 11 - board/davinci/dm365evm/dm365evm.c | 139 --- board/davinci/dm6467evm/Kconfig | 12 - board/davinci/dm6467evm/MAINTAINERS | 7 - board/davinci/dm6467evm/Makefile | 10 - board/davinci/dm6467evm/config.mk | 2 - board/davinci/dm6467evm/dm6467evm.c | 76 -- board/davinci/dvevm/Kconfig | 12 - board/davinci/dvevm/MAINTAINERS | 6 - board/davinci/dvevm/Makefile | 11 - board/davinci/dvevm/board_init.S | 16 - board/davinci/dvevm/config.mk | 39 - board/davinci/dvevm/dvevm.c | 91 -- board/davinci/schmoogie/Kconfig | 12 - board/davinci/schmoogie/MAINTAINERS | 6 - board/davinci/schmoogie/Makefile | 11 - board/davinci/schmoogie/board_init.S | 16 - board/davinci/schmoogie/config.mk | 39 - board/davinci/schmoogie/schmoogie.c | 119 --- board/davinci/sffsdr/Kconfig | 12 - board/davinci/sffsdr/MAINTAINERS | 6 - board/davinci/sffsdr/Makefile | 11 - board/davinci/sffsdr/board_init.S | 16 - board/davinci/sffsdr/config.mk | 23 - board/davinci/sffsdr/sffsdr.c | 132 --- board/davinci/sonata/Kconfig | 12 - board/davinci/sonata/MAINTAINERS | 6 - board/davinci/sonata/Makefile | 11 - board/davinci/sonata/board_init.S | 87 -- board/davinci/sonata/config.mk | 39 - board/davinci/sonata/sonata.c | 87 -- board/htkw/mcx/Kconfig | 12 - board/htkw/mcx/MAINTAINERS | 6 - board/htkw/mcx/Makefile | 9 - board/htkw/mcx/mcx.c | 142 --- board/htkw/mcx/mcx.h | 401 ------- board/matrix_vision/mvblx/Kconfig | 12 - board/matrix_vision/mvblx/MAINTAINERS | 6 - board/matrix_vision/mvblx/Makefile | 11 - board/matrix_vision/mvblx/config.mk | 17 - board/matrix_vision/mvblx/fpga.c | 214 ---- board/matrix_vision/mvblx/fpga.h | 15 - board/matrix_vision/mvblx/mvblx.c | 159 --- board/matrix_vision/mvblx/mvblx.h | 346 ------ board/matrix_vision/mvblx/sys_eeprom.c | 403 ------- board/pandora/Kconfig | 9 - board/pandora/MAINTAINERS | 6 - board/pandora/Makefile | 8 - board/pandora/pandora.c | 134 --- board/pandora/pandora.h | 392 ------- board/ti/sdp3430/Kconfig | 12 - board/ti/sdp3430/MAINTAINERS | 6 - board/ti/sdp3430/Makefile | 8 - board/ti/sdp3430/config.mk | 17 - board/ti/sdp3430/sdp.c | 203 ---- board/ti/sdp3430/sdp.h | 401 ------- configs/afeb9260_defconfig | 3 - configs/cam_enc_4xx_defconfig | 4 - configs/davinci_dm355evm_defconfig | 3 - configs/davinci_dm355leopard_defconfig | 3 - configs/davinci_dm365evm_defconfig | 3 - configs/davinci_dm6467Tevm_defconfig | 4 - configs/davinci_dm6467evm_defconfig | 4 - configs/davinci_dvevm_defconfig | 3 - configs/davinci_schmoogie_defconfig | 3 - configs/davinci_sffsdr_defconfig | 3 - configs/davinci_sonata_defconfig | 3 - configs/dig297_defconfig | 6 - configs/mcx_defconfig | 7 - configs/omap3_mvblx_defconfig | 6 - configs/omap3_pandora_defconfig | 6 - configs/omap3_sdp3430_defconfig | 6 - configs/sbc35_a9g20_eeprom_defconfig | 4 - configs/sbc35_a9g20_nandflash_defconfig | 4 - configs/tny_a9260_eeprom_defconfig | 4 - configs/tny_a9260_nandflash_defconfig | 4 - configs/tny_a9g20_eeprom_defconfig | 4 - configs/tny_a9g20_nandflash_defconfig | 4 - doc/README.scrapyard | 33 +- drivers/mtd/nand/davinci_nand.c | 33 - drivers/usb/musb/musb_hcd.c | 9 +- include/configs/afeb9260.h | 156 --- include/configs/cam_enc_4xx.h | 512 --------- include/configs/davinci_dm355evm.h | 203 ---- include/configs/davinci_dm355leopard.h | 148 --- include/configs/davinci_dm365evm.h | 228 ---- include/configs/davinci_dm6467evm.h | 146 --- include/configs/davinci_dvevm.h | 223 ---- include/configs/davinci_schmoogie.h | 143 --- include/configs/davinci_sffsdr.h | 136 --- include/configs/davinci_sonata.h | 194 ---- include/configs/dig297.h | 278 ----- include/configs/mcx.h | 421 -------- include/configs/omap3_mvblx.h | 287 ----- include/configs/omap3_pandora.h | 244 ----- include/configs/omap3_sdp3430.h | 327 ------ include/configs/sbc35_a9g20.h | 169 --- include/configs/tny_a9260.h | 150 --- 161 files changed, 32 insertions(+), 12593 deletions(-) delete mode 100644 arch/arm/mach-davinci/dm355.c delete mode 100644 arch/arm/mach-davinci/dm365.c delete mode 100644 arch/arm/mach-davinci/dm365_lowlevel.c delete mode 100644 arch/arm/mach-davinci/dm644x.c delete mode 100644 arch/arm/mach-davinci/dm646x.c delete mode 100644 arch/arm/mach-davinci/include/mach/aintc_defs.h delete mode 100644 arch/arm/mach-davinci/include/mach/psc_defs.h delete mode 100644 arch/arm/mach-davinci/include/mach/syscfg_defs.h delete mode 100644 board/afeb9260/Kconfig delete mode 100644 board/afeb9260/MAINTAINERS delete mode 100644 board/afeb9260/Makefile delete mode 100644 board/afeb9260/afeb9260.c delete mode 100644 board/afeb9260/config.mk delete mode 100644 board/afeb9260/partition.c delete mode 100644 board/ait/cam_enc_4xx/Kconfig delete mode 100644 board/ait/cam_enc_4xx/MAINTAINERS delete mode 100644 board/ait/cam_enc_4xx/Makefile delete mode 100644 board/ait/cam_enc_4xx/cam_enc_4xx.c delete mode 100644 board/ait/cam_enc_4xx/config.mk delete mode 100644 board/ait/cam_enc_4xx/u-boot-spl.lds delete mode 100644 board/ait/cam_enc_4xx/ublimage.cfg delete mode 100644 board/calao/sbc35_a9g20/Kconfig delete mode 100644 board/calao/sbc35_a9g20/MAINTAINERS delete mode 100644 board/calao/sbc35_a9g20/Makefile delete mode 100644 board/calao/sbc35_a9g20/config.mk delete mode 100644 board/calao/sbc35_a9g20/sbc35_a9g20.c delete mode 100644 board/calao/sbc35_a9g20/spi.c delete mode 100644 board/calao/tny_a9260/Kconfig delete mode 100644 board/calao/tny_a9260/MAINTAINERS delete mode 100644 board/calao/tny_a9260/Makefile delete mode 100644 board/calao/tny_a9260/config.mk delete mode 100644 board/calao/tny_a9260/spi.c delete mode 100644 board/calao/tny_a9260/tny_a9260.c delete mode 100644 board/comelit/dig297/Kconfig delete mode 100644 board/comelit/dig297/MAINTAINERS delete mode 100644 board/comelit/dig297/Makefile delete mode 100644 board/comelit/dig297/dig297.c delete mode 100644 board/comelit/dig297/dig297.h delete mode 100644 board/davinci/dm355evm/Kconfig delete mode 100644 board/davinci/dm355evm/MAINTAINERS delete mode 100644 board/davinci/dm355evm/Makefile delete mode 100644 board/davinci/dm355evm/config.mk delete mode 100644 board/davinci/dm355evm/dm355evm.c delete mode 100644 board/davinci/dm355leopard/Kconfig delete mode 100644 board/davinci/dm355leopard/MAINTAINERS delete mode 100644 board/davinci/dm355leopard/Makefile delete mode 100644 board/davinci/dm355leopard/config.mk delete mode 100644 board/davinci/dm355leopard/dm355leopard.c delete mode 100644 board/davinci/dm365evm/Kconfig delete mode 100644 board/davinci/dm365evm/MAINTAINERS delete mode 100644 board/davinci/dm365evm/Makefile delete mode 100644 board/davinci/dm365evm/config.mk delete mode 100644 board/davinci/dm365evm/dm365evm.c delete mode 100644 board/davinci/dm6467evm/Kconfig delete mode 100644 board/davinci/dm6467evm/MAINTAINERS delete mode 100644 board/davinci/dm6467evm/Makefile delete mode 100644 board/davinci/dm6467evm/config.mk delete mode 100644 board/davinci/dm6467evm/dm6467evm.c delete mode 100644 board/davinci/dvevm/Kconfig delete mode 100644 board/davinci/dvevm/MAINTAINERS delete mode 100644 board/davinci/dvevm/Makefile delete mode 100644 board/davinci/dvevm/board_init.S delete mode 100644 board/davinci/dvevm/config.mk delete mode 100644 board/davinci/dvevm/dvevm.c delete mode 100644 board/davinci/schmoogie/Kconfig delete mode 100644 board/davinci/schmoogie/MAINTAINERS delete mode 100644 board/davinci/schmoogie/Makefile delete mode 100644 board/davinci/schmoogie/board_init.S delete mode 100644 board/davinci/schmoogie/config.mk delete mode 100644 board/davinci/schmoogie/schmoogie.c delete mode 100644 board/davinci/sffsdr/Kconfig delete mode 100644 board/davinci/sffsdr/MAINTAINERS delete mode 100644 board/davinci/sffsdr/Makefile delete mode 100644 board/davinci/sffsdr/board_init.S delete mode 100644 board/davinci/sffsdr/config.mk delete mode 100644 board/davinci/sffsdr/sffsdr.c delete mode 100644 board/davinci/sonata/Kconfig delete mode 100644 board/davinci/sonata/MAINTAINERS delete mode 100644 board/davinci/sonata/Makefile delete mode 100644 board/davinci/sonata/board_init.S delete mode 100644 board/davinci/sonata/config.mk delete mode 100644 board/davinci/sonata/sonata.c delete mode 100644 board/htkw/mcx/Kconfig delete mode 100644 board/htkw/mcx/MAINTAINERS delete mode 100644 board/htkw/mcx/Makefile delete mode 100644 board/htkw/mcx/mcx.c delete mode 100644 board/htkw/mcx/mcx.h delete mode 100644 board/matrix_vision/mvblx/Kconfig delete mode 100644 board/matrix_vision/mvblx/MAINTAINERS delete mode 100644 board/matrix_vision/mvblx/Makefile delete mode 100644 board/matrix_vision/mvblx/config.mk delete mode 100644 board/matrix_vision/mvblx/fpga.c delete mode 100644 board/matrix_vision/mvblx/fpga.h delete mode 100644 board/matrix_vision/mvblx/mvblx.c delete mode 100644 board/matrix_vision/mvblx/mvblx.h delete mode 100644 board/matrix_vision/mvblx/sys_eeprom.c delete mode 100644 board/pandora/Kconfig delete mode 100644 board/pandora/MAINTAINERS delete mode 100644 board/pandora/Makefile delete mode 100644 board/pandora/pandora.c delete mode 100644 board/pandora/pandora.h delete mode 100644 board/ti/sdp3430/Kconfig delete mode 100644 board/ti/sdp3430/MAINTAINERS delete mode 100644 board/ti/sdp3430/Makefile delete mode 100644 board/ti/sdp3430/config.mk delete mode 100644 board/ti/sdp3430/sdp.c delete mode 100644 board/ti/sdp3430/sdp.h delete mode 100644 configs/afeb9260_defconfig delete mode 100644 configs/cam_enc_4xx_defconfig delete mode 100644 configs/davinci_dm355evm_defconfig delete mode 100644 configs/davinci_dm355leopard_defconfig delete mode 100644 configs/davinci_dm365evm_defconfig delete mode 100644 configs/davinci_dm6467Tevm_defconfig delete mode 100644 configs/davinci_dm6467evm_defconfig delete mode 100644 configs/davinci_dvevm_defconfig delete mode 100644 configs/davinci_schmoogie_defconfig delete mode 100644 configs/davinci_sffsdr_defconfig delete mode 100644 configs/davinci_sonata_defconfig delete mode 100644 configs/dig297_defconfig delete mode 100644 configs/mcx_defconfig delete mode 100644 configs/omap3_mvblx_defconfig delete mode 100644 configs/omap3_pandora_defconfig delete mode 100644 configs/omap3_sdp3430_defconfig delete mode 100644 configs/sbc35_a9g20_eeprom_defconfig delete mode 100644 configs/sbc35_a9g20_nandflash_defconfig delete mode 100644 configs/tny_a9260_eeprom_defconfig delete mode 100644 configs/tny_a9260_nandflash_defconfig delete mode 100644 configs/tny_a9g20_eeprom_defconfig delete mode 100644 configs/tny_a9g20_nandflash_defconfig delete mode 100644 include/configs/afeb9260.h delete mode 100644 include/configs/cam_enc_4xx.h delete mode 100644 include/configs/davinci_dm355evm.h delete mode 100644 include/configs/davinci_dm355leopard.h delete mode 100644 include/configs/davinci_dm365evm.h delete mode 100644 include/configs/davinci_dm6467evm.h delete mode 100644 include/configs/davinci_dvevm.h delete mode 100644 include/configs/davinci_schmoogie.h delete mode 100644 include/configs/davinci_sffsdr.h delete mode 100644 include/configs/davinci_sonata.h delete mode 100644 include/configs/dig297.h delete mode 100644 include/configs/mcx.h delete mode 100644 include/configs/omap3_mvblx.h delete mode 100644 include/configs/omap3_pandora.h delete mode 100644 include/configs/omap3_sdp3430.h delete mode 100644 include/configs/sbc35_a9g20.h delete mode 100644 include/configs/tny_a9260.h -- 1.9.1

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[U-Boot] [PATCH v2] arc: use more universal prefix for default CROSS_COMPILE
by Masahiro Yamada 13 May '15

13 May '15

As doc/README.ARC says, pre-build ARC toolchains are available at the Synopsys GitHub page. The bin files are prefixed with arc(eb)-buildroot-linux- for earlier releases, but with arc(eb)-snps-linux- for the latest releases. The symbolic links prefixed with arc(eb)-linux- are also available for all the release, so those prefixes can be used as the default CROSS_COMPILE regardless of the toolchains version/variants. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- Changes in v2: - Use "arc(eb)-linux-" rather than "arc(eb)-linux-uclibc-" arch/arc/config.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arc/config.mk b/arch/arc/config.mk index 04c034b..74943d9 100644 --- a/arch/arc/config.mk +++ b/arch/arc/config.mk @@ -11,13 +11,13 @@ CONFIG_SYS_BIG_ENDIAN = 1 endif ifdef CONFIG_SYS_LITTLE_ENDIAN -ARC_CROSS_COMPILE := arc-buildroot-linux-uclibc- +ARC_CROSS_COMPILE := arc-linux- PLATFORM_LDFLAGS += -EL PLATFORM_CPPFLAGS += -mlittle-endian endif ifdef CONFIG_SYS_BIG_ENDIAN -ARC_CROSS_COMPILE := arceb-buildroot-linux-uclibc- +ARC_CROSS_COMPILE := arceb-linux- PLATFORM_LDFLAGS += -EB PLATFORM_CPPFLAGS += -mbig-endian endif -- 1.9.1

2 1

[U-Boot] [PATCH] ARC: change the default CROSS_COMPILE for ARC
by Masahiro Yamada 13 May '15

13 May '15

As doc/README.ARC says, pre-build ARC toolchains are available at the Synopsys GitHub page. The bin files are prefixed with arc(eb)-buildroot-linux- for earlier releases, but with arc(eb)-snps-linux- for the latest releases (arc_gnu_2014.12_prebuilt_*). For all the releases, the symbolic link, arc(eb)-linux-* is also prepared for each bin file, so it can be used as the default CROSS_COMPILE regardless of the toolchains version. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- arch/arc/config.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arc/config.mk b/arch/arc/config.mk index 04c034b..9aed147 100644 --- a/arch/arc/config.mk +++ b/arch/arc/config.mk @@ -11,13 +11,13 @@ CONFIG_SYS_BIG_ENDIAN = 1 endif ifdef CONFIG_SYS_LITTLE_ENDIAN -ARC_CROSS_COMPILE := arc-buildroot-linux-uclibc- +ARC_CROSS_COMPILE := arc-linux-uclibc- PLATFORM_LDFLAGS += -EL PLATFORM_CPPFLAGS += -mlittle-endian endif ifdef CONFIG_SYS_BIG_ENDIAN -ARC_CROSS_COMPILE := arceb-buildroot-linux-uclibc- +ARC_CROSS_COMPILE := arceb-linux-uclibc- PLATFORM_LDFLAGS += -EB PLATFORM_CPPFLAGS += -mbig-endian endif -- 1.9.1

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[U-Boot] [PATCH] arm, imx6: add support for aristainetos2 board
by Heiko Schocher 13 May '15

13 May '15

add support for imx6dl based aristainetos2 board U-Boot 2015.04-rc5-00066-g60f6ed4 (Apr 10 2015 - 08:46:27) CPU: Freescale i.MX6DL rev1.1 at 792 MHz Reset cause: WDOG Board: aristaitenos2 Watchdog enabled I2C: ready DRAM: 1 GiB NAND: 1024 MiB MMC: FSL_SDHC: 0 SF: Detected N25Q128A with page size 256 Bytes, erase size 64 KiB, total 16 MiB Display: lg4573 (480x800) In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 => Signed-off-by: Heiko Schocher <hs(a)denx.de> --- arch/arm/Kconfig | 5 + board/aristainetos2/Kconfig | 12 + board/aristainetos2/MAINTAINERS | 6 + board/aristainetos2/Makefile | 12 + board/aristainetos2/aristainetos2.c | 917 ++++++++++++++++++++++++++++++++++ board/aristainetos2/aristainetos2.cfg | 34 ++ board/aristainetos2/axi.cfg | 22 + board/aristainetos2/clocks.cfg | 24 + board/aristainetos2/ddr-setup.cfg | 59 +++ board/aristainetos2/nt5cc256m16cp.cfg | 60 +++ configs/aristainetos2_defconfig | 3 + include/configs/aristainetos2.h | 351 +++++++++++++ 12 files changed, 1505 insertions(+) create mode 100644 board/aristainetos2/Kconfig create mode 100644 board/aristainetos2/MAINTAINERS create mode 100644 board/aristainetos2/Makefile create mode 100644 board/aristainetos2/aristainetos2.c create mode 100644 board/aristainetos2/aristainetos2.cfg create mode 100644 board/aristainetos2/axi.cfg create mode 100644 board/aristainetos2/clocks.cfg create mode 100644 board/aristainetos2/ddr-setup.cfg create mode 100644 board/aristainetos2/nt5cc256m16cp.cfg create mode 100644 configs/aristainetos2_defconfig create mode 100644 include/configs/aristainetos2.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 80b0d34..ea4923f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -501,6 +501,10 @@ config TARGET_ARISTAINETOS bool "Support aristainetos" select CPU_V7 +config TARGET_ARISTAINETOS2 + bool "Support aristainetos2" + select CPU_V7 + config TARGET_MX6QARM2 bool "Support mx6qarm2" select CPU_V7 @@ -765,6 +769,7 @@ source "arch/arm/cpu/armv8/Kconfig" source "arch/arm/imx-common/Kconfig" source "board/aristainetos/Kconfig" +source "board/aristainetos2/Kconfig" source "board/BuR/kwb/Kconfig" source "board/BuR/tseries/Kconfig" source "board/CarMediaLab/flea3/Kconfig" diff --git a/board/aristainetos2/Kconfig b/board/aristainetos2/Kconfig new file mode 100644 index 0000000..2cf13e4 --- /dev/null +++ b/board/aristainetos2/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ARISTAINETOS2 + +config SYS_BOARD + default "aristainetos2" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "aristainetos2" + +endif diff --git a/board/aristainetos2/MAINTAINERS b/board/aristainetos2/MAINTAINERS new file mode 100644 index 0000000..d155f86 --- /dev/null +++ b/board/aristainetos2/MAINTAINERS @@ -0,0 +1,6 @@ +ARISTAINETOS BOARD +M: Heiko Schocher <hs(a)denx.de> +S: Maintained +F: board/aristainetos2/ +F: include/configs/aristainetos2.h +F: configs/aristainetos2_defconfig diff --git a/board/aristainetos2/Makefile b/board/aristainetos2/Makefile new file mode 100644 index 0000000..2513744 --- /dev/null +++ b/board/aristainetos2/Makefile @@ -0,0 +1,12 @@ +# +# (C) Copyright 2015 +# Heiko Schocher, DENX Software Engineering, hs(a)denx.de. +# +# Copyright (C) 2007, Guennadi Liakhovetski <lg(a)denx.de> +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := aristainetos2.o diff --git a/board/aristainetos2/aristainetos2.c b/board/aristainetos2/aristainetos2.c new file mode 100644 index 0000000..98e1bc7 --- /dev/null +++ b/board/aristainetos2/aristainetos2.c @@ -0,0 +1,917 @@ +/* + * (C) Copyright 2015 + * Heiko Schocher, DENX Software Engineering, hs(a)denx.de. + * + * Based on: + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam(a)freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/mxc_i2c.h> +#include <asm/imx-common/video.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <micrel.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/arch/mxc_hdmi.h> +#include <asm/arch/crm_regs.h> +#include <linux/fb.h> +#include <ipu_pixfmt.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <pwm.h> +#include <spi.h> +#include <video.h> +#include <../drivers/video/ipu.h> +#if defined(CONFIG_VIDEO_BMP_LOGO) + #include <bmp_logo.h> +#endif +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC2_PAD_CTRL (PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +#define DISP_PAD_CTRL (0x10) + +#define ECSPI1_CS0 IMX_GPIO_NR(4, 9) /* 4.3 display controller */ +#define ECSPI4_CS0 IMX_GPIO_NR(3, 29) +#define ECSPI4_CS1 IMX_GPIO_NR(5, 2) /* NOR boot flash */ + +#define SOFT_RESET_GPIO IMX_GPIO_NR(7, 13) +#define SD2_DRIVER_ENABLE IMX_GPIO_NR(7, 8) + + +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC, + .gp = IMX_GPIO_NR(5, 27) + }, + .sda = { + .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC, + .gp = IMX_GPIO_NR(5, 26) + } +}; + +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC, + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, + .gp = IMX_GPIO_NR(4, 13) + } +}; + +struct i2c_pads_info i2c_pad_info3 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC, + .gp = IMX_GPIO_NR(1, 5) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC, + .gp = IMX_GPIO_NR(1, 6) + } +}; + +struct i2c_pads_info i2c_pad_info4 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_7__I2C4_SCL | PC, + .gpio_mode = MX6_PAD_GPIO_7__GPIO1_IO07 | PC, + .gp = IMX_GPIO_NR(1, 7) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_8__I2C4_SDA | PC, + .gpio_mode = MX6_PAD_GPIO_8__GPIO1_IO08 | PC, + .gp = IMX_GPIO_NR(1, 8) + } +}; + +static int lgdisplay; + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D19__UART1_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D20__UART1_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart3_pads[] = { + MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart4_pads[] = { + MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const gpio_pads[] = { + /* LED enable*/ + MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* LED yellow */ + MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* LED red */ + MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* LED green */ + MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* LED blue */ + MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* spi flash WP protect */ + MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* spi CS 0 */ + MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* spi bus #2 SS driver enable */ + MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* RST_LOC# PHY reset input (has pull-down!)*/ + MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* SD 2 level shifter output enable */ + MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* SD1 card detect input */ + MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* SD1 write protect input */ + MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* SD2 card detect input */ + MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* SD2 write protect input */ + MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* Touchscreen IRQ */ + MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const misc_pads[] = { + /* USB_OTG_ID = GPIO1_24*/ + MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), + /* H1 Power enable = GPIO1_0*/ + MX6_PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + /* OTG Power enable = GPIO4_15*/ + MX6_PAD_KEY_ROW4__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); +} + +iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC2_PAD_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC2_PAD_CTRL), + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC2_PAD_CTRL), + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC2_PAD_CTRL), + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC2_PAD_CTRL), + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC2_PAD_CTRL), + MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const ecspi1_pads[] = { + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(SPI_PAD_CTRL), +}; + +iomux_v3_cfg_t const ecspi4_pads[] = { + MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +/* only used for 4.3" display */ +static iomux_v3_cfg_t const display_pads[] = { + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL), + MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16, + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17, + MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18, + MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19, + MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20, + MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21, + MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22, + MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23, +}; + +static iomux_v3_cfg_t const backlight_pads[] = { + /* backlight PWM brightness control */ + MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), + /* backlight enable */ + MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* LCD power enable */ + MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + if (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS) + return IMX_GPIO_NR(5, 2); + + if (bus == 0 && cs == 0) + return IMX_GPIO_NR(4, 9); + + return -1; +} + +static void setup_spi(void) +{ + int i; + + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); + imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads)); + for (i = 0; i < 4; i++) + enable_spi_clk(true, i); + + gpio_direction_output(ECSPI1_CS0, 1); + gpio_direction_output(ECSPI4_CS1, 0); + + /* set cs0 to high (second device on spi bus #4) */ + gpio_direction_output(ECSPI4_CS0, 1); +} + +static void setup_iomux_gpio(void) +{ + imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); +} + +static void setup_iomux_uart(void) +{ + switch (CONFIG_MXC_UART_BASE) { + case UART1_BASE: + imx_iomux_v3_setup_multiple_pads(uart1_pads, + ARRAY_SIZE(uart1_pads)); + break; + case UART2_BASE: + imx_iomux_v3_setup_multiple_pads(uart2_pads, + ARRAY_SIZE(uart2_pads)); + break; + case UART3_BASE: + imx_iomux_v3_setup_multiple_pads(uart3_pads, + ARRAY_SIZE(uart3_pads)); + break; + case UART4_BASE: + imx_iomux_v3_setup_multiple_pads(uart4_pads, + ARRAY_SIZE(uart4_pads)); + break; + } +} + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR}, + {USDHC2_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; +} + +int board_mmc_init(bd_t *bis) +{ + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + +#if defined(CONFIG_USE_SDHC2) + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]) | + fsl_esdhc_initialize(bis, &usdhc_cfg[1]); +#else + /* + * usdhc2 has a levelshifter on the carrier board Rev. DV1, + * that will automatically detect the driving direction. + * During initialisation this isn't working correctly, + * which causes DAT3 to be driven low towards the SD-card. + * This causes a SD-card enetring the SPI-Mode + * and therefore getting inaccessible until next power cycle. + * As workaround we drive the DAT3 line as GPIO and set it high. + * This makes usdhc2 unusable in u-boot, but works for the + * initialisation in Linux + */ + imx_iomux_v3_setup_pad(MX6_PAD_SD2_DAT3__GPIO1_IO12 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(1, 12) , 1); + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +#endif +} +#endif + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +int board_phy_config(struct phy_device *phydev) +{ +#if defined(CONFIG_PHY_MICREL_KSZ9031) + /* control data pad skew - devaddr = 0x02, register = 0x04 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); + /* rx data pad skew - devaddr = 0x02, register = 0x05 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); + /* tx data pad skew - devaddr = 0x02, register = 0x06 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); + /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF); +#endif /* CONFIG_PHY_MICREL_KSZ9031 */ + + if (phydev->drv->config) + phydev->drv->config(phydev); + + + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + setup_iomux_enet(); + return cpu_eth_init(bis); +} + +#if defined(CONFIG_VIDEO_IPUV3) + +#if defined(CONFIG_VIDEO_BMP_LOGO) +static int rotate_logo_one(unsigned char *out, unsigned char *in) +{ + int i, j; + + for (i = 0; i < BMP_LOGO_WIDTH; i++) + for (j = 0; j < BMP_LOGO_HEIGHT; j++) + out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] = + in[i * BMP_LOGO_WIDTH + j]; + return 0; +} + +/* + * Rotate the BMP_LOGO (only) + * Will only work, if the logo is square, as + * BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables + */ +void rotate_logo(int rotations) +{ + unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT]; + unsigned char *in_logo; + int i, j; + + if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT) + return; + + in_logo = bmp_logo_bitmap; + + /* one 90 degree rotation */ + if (rotations == 1 || rotations == 2 || rotations == 3) + rotate_logo_one(out_logo, in_logo); + + /* second 90 degree rotation */ + if (rotations == 2 || rotations == 3) + rotate_logo_one(in_logo, out_logo); + + /* third 90 degree rotation */ + if (rotations == 3) + rotate_logo_one(out_logo, in_logo); + + /* copy result back to original array */ + if (rotations == 1 || rotations == 3) + for (i = 0; i < BMP_LOGO_WIDTH; i++) + for (j = 0; j < BMP_LOGO_HEIGHT; j++) + in_logo[i * BMP_LOGO_WIDTH + j] = + out_logo[i * BMP_LOGO_WIDTH + j]; +} +#endif + +static void enable_display_power(void) +{ + imx_iomux_v3_setup_multiple_pads(backlight_pads, + ARRAY_SIZE(backlight_pads)); + + /* backlight enable */ + gpio_direction_output(IMX_GPIO_NR(6, 31), 1); + /* LCD power enable */ + gpio_direction_output(IMX_GPIO_NR(6, 15), 1); + + /* enable backlight PWM 1 */ + if (pwm_init(0, 0, 0)) + goto error; + /* duty cycle 500ns, period: 3000ns */ + if (pwm_config(0, 50000, 300000)) + goto error; + if (pwm_enable(0)) + goto error; + return; + +error: + puts("error init pwm for backlight\n"); + return; +} + +static void enable_lvds(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + int reg; + s32 timeout = 100000; + + /* set PLL5 clock */ + reg = readl(&ccm->analog_pll_video); + reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN; + writel(reg, &ccm->analog_pll_video); + + /* set PLL5 to 232720000Hz */ + reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT; + reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26); + reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT; + reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0); + writel(reg, &ccm->analog_pll_video); + + writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238), + &ccm->analog_pll_video_num); + writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240), + &ccm->analog_pll_video_denom); + + reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN; + writel(reg, &ccm->analog_pll_video); + + while (timeout--) + if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) + break; + if (timeout < 0) + printf("Warning: video pll lock timeout!\n"); + + reg = readl(&ccm->analog_pll_video); + reg |= BM_ANADIG_PLL_VIDEO_ENABLE; + reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; + writel(reg, &ccm->analog_pll_video); + + /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */ + reg = readl(&ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK + | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) + | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); + writel(reg, &ccm->cs2cdr); + + reg = readl(&ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; + writel(reg, &ccm->cscmr2); + + reg = readl(&ccm->chsccdr); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + writel(reg, &ccm->chsccdr); + + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES + | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH + | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH + | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT + | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED + | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[2]); + + reg = readl(&iomux->gpr[3]); + reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 + << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); + writel(reg, &iomux->gpr[3]); + + return; +} + +static void enable_spi(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + int reg; + s32 timeout = 100000; + +#if defined(CONFIG_VIDEO_BMP_LOGO) + rotate_logo(3); /* portrait display in landscape mode */ +#endif + + lgdisplay = 1; + ipu_set_ldb_clock(28341000); + + reg = readl(&ccm->cs2cdr); + + /* select pll 5 clock */ + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK + | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + writel(reg, &ccm->cs2cdr); + + /* set PLL5 to 197994996Hz */ + reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT; + reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21); + reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT; + reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0); + writel(reg, &ccm->analog_pll_video); + + writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4), + &ccm->analog_pll_video_num); + writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240), + &ccm->analog_pll_video_denom); + + reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN; + writel(reg, &ccm->analog_pll_video); + + while (timeout--) + if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) + break; + if (timeout < 0) + printf("Warning: video pll lock timeout!\n"); + + reg = readl(&ccm->analog_pll_video); + reg |= BM_ANADIG_PLL_VIDEO_ENABLE; + reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; + writel(reg, &ccm->analog_pll_video); + + /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */ + reg = readl(&ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK + | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) + | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); + writel(reg, &ccm->cs2cdr); + + reg = readl(&ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; + writel(reg, &ccm->cscmr2); + + reg = readl(&ccm->chsccdr); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK; + reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET); + reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK; + reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); + writel(reg, &ccm->chsccdr); + + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES + | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH + | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH + | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT + | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED + | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[2]); + + reg = readl(&iomux->gpr[3]); + reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 + << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); + writel(reg, &iomux->gpr[3]); + + imx_iomux_v3_setup_multiple_pads( + display_pads, + ARRAY_SIZE(display_pads)); + + return; +} + +struct display_info_t const displays[] = {{ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = NULL, + .enable = enable_lvds, + .mode = { + .name = "lb07wv8", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 30066, + .left_margin = 88, + .right_margin = 88, + .upper_margin = 20, + .lower_margin = 20, + .hsync_len = 80, + .vsync_len = 5, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = NULL, + .enable = enable_spi, + .mode = { + .name = "lg4573", + .refresh = 57, + .xres = 480, + .yres = 800, + .pixclock = 37037, + .left_margin = 59, + .right_margin = 10, + .upper_margin = 15, + .lower_margin = 15, + .hsync_len = 10, + .vsync_len = 15, + .sync = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT | + FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); + +static void setup_display(void) +{ + enable_ipu_clock(); + enable_display_power(); +} + +/* no console on this board */ +int board_cfb_skip(void) +{ + return 1; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + setup_iomux_gpio(); + + gpio_direction_output(SOFT_RESET_GPIO, 1); + gpio_direction_output(SD2_DRIVER_ENABLE, 1); + +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif + return 0; +} + +iomux_v3_cfg_t nfc_pads[] = { + MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(nfc_pads, + ARRAY_SIZE(nfc_pads)); + + /* gate ENFC_CLK_ROOT clock first,before clk source switch */ + clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); + + /* config gpmi and bch clock to 100 MHz */ + clrsetbits_le32(&mxc_ccm->cs2cdr, + MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, + MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); + + /* enable ENFC_CLK_ROOT clock */ + setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); + + /* enable gpmi and bch clock gating */ + setbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} + +int board_init(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + setup_spi(); + + setup_i2c(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, + &i2c_pad_info1); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, + &i2c_pad_info2); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, + &i2c_pad_info3); + setup_i2c(3, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, + &i2c_pad_info4); + + /* SPI NOR Flash read only */ + gpio_request(CONFIG_GPIO_ENABLE_SPI_FLASH, "ena_spi_nor"); + gpio_direction_output(CONFIG_GPIO_ENABLE_SPI_FLASH, 0); + gpio_free(CONFIG_GPIO_ENABLE_SPI_FLASH); + + /* enable all LEDs */ + gpio_request(IMX_GPIO_NR(2, 13), "LED ena"); /* 25 */ + gpio_direction_output(IMX_GPIO_NR(1, 25), 0); + + /* switch off Status LEDs */ + gpio_request(IMX_GPIO_NR(6, 16), "LED yellow"); /* 176 */ + gpio_direction_output(IMX_GPIO_NR(6, 16), 1); + gpio_request(IMX_GPIO_NR(2, 28), "LED red"); /* 60 */ + gpio_direction_output(IMX_GPIO_NR(2, 28), 1); + gpio_request(IMX_GPIO_NR(5, 4), "LED green"); /* 132 */ + gpio_direction_output(IMX_GPIO_NR(5, 4), 1); + gpio_request(IMX_GPIO_NR(2, 29), "LED blue"); /* 61 */ + gpio_direction_output(IMX_GPIO_NR(2, 29), 1); + + setup_gpmi_nand(); + + /* ENET_RX_ER for USB_OTG_ID */ + clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0); + imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads)); + + /* enable spi bus #2 SS drivers */ + gpio_direction_output(IMX_GPIO_NR(6, 6), 1); + + return 0; +} + +int board_late_init(void) +{ + char *my_bootdelay; + char bootmode = 0; + + /* + * Check the boot-source. If booting from NOR Flash, + * disable bootdelay + */ + gpio_request(IMX_GPIO_NR(7, 6), "bootsel0"); + gpio_direction_input(IMX_GPIO_NR(7, 6)); + gpio_request(IMX_GPIO_NR(7, 7), "bootsel1"); + gpio_direction_input(IMX_GPIO_NR(7, 7)); + gpio_request(IMX_GPIO_NR(7, 1), "bootsel2"); + gpio_direction_input(IMX_GPIO_NR(7, 1)); + bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 6)) ? 1 : 0) << 0; + bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 7)) ? 1 : 0) << 1; + bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 1)) ? 1 : 0) << 2; + + if (bootmode == 7) { + my_bootdelay = getenv("nor_bootdelay"); + if (my_bootdelay != NULL) + setenv("bootdelay", my_bootdelay); + else + setenv("bootdelay", "-2"); + } + + if (lgdisplay) + lg4573_spi_startup(0, 0, 10000000, SPI_MODE_0); + + return 0; +} + +int checkboard(void) +{ + puts("Board: aristaitenos2\n"); + return 0; +} + +#ifdef CONFIG_USB_EHCI_MX6 +int board_ehci_hcd_init(int port) +{ + int ret; + + ret = gpio_request(ARISTAINETOS2_USB_H1_PWR, "usb-h1-pwr"); + if (!ret) + gpio_direction_output(ARISTAINETOS2_USB_H1_PWR, 1); + ret = gpio_request(ARISTAINETOS2_USB_OTG_PWR, "usb-OTG-pwr"); + if (!ret) + gpio_direction_output(ARISTAINETOS2_USB_OTG_PWR, 1); + return 0; +} + +int board_ehci_power(int port, int on) +{ + if (port) + gpio_set_value(ARISTAINETOS2_USB_OTG_PWR, on); + else + gpio_set_value(ARISTAINETOS2_USB_H1_PWR, on); + return 0; +} +#endif diff --git a/board/aristainetos2/aristainetos2.cfg b/board/aristainetos2/aristainetos2.cfg new file mode 100644 index 0000000..a66bc1c --- /dev/null +++ b/board/aristainetos2/aristainetos2.cfg @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2014 + * Heiko Schocher, DENX Software Engineering, hs(a)denx.de. + * + * Based on: + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd + */ +BOOT_FROM spi + +#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "nt5cc256m16cp.cfg" +#include "clocks.cfg" +#include "axi.cfg" diff --git a/board/aristainetos2/axi.cfg b/board/aristainetos2/axi.cfg new file mode 100644 index 0000000..0bb816c --- /dev/null +++ b/board/aristainetos2/axi.cfg @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF + +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F diff --git a/board/aristainetos2/clocks.cfg b/board/aristainetos2/clocks.cfg new file mode 100644 index 0000000..987d9a4 --- /dev/null +++ b/board/aristainetos2/clocks.cfg @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00c03f3f +DATA 4, CCM_CCGR1, 0x0030fcff +DATA 4, CCM_CCGR2, 0x0fffcfc0 +DATA 4, CCM_CCGR3, 0x3ff0300f +DATA 4, CCM_CCGR4, 0xfffff300 +DATA 4, CCM_CCGR5, 0x0f0000c3 +DATA 4, CCM_CCGR6, 0x00000fff diff --git a/board/aristainetos2/ddr-setup.cfg b/board/aristainetos2/ddr-setup.cfg new file mode 100644 index 0000000..3d5d894 --- /dev/null +++ b/board/aristainetos2/ddr-setup.cfg @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* DDR IO TYPE */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +/* Clock */ +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030 +/* Address */ +DATA 4, MX6_IOM_DRAM_CAS, 0x00000030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00000030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +/* Control */ +DATA 4, MX6_IOM_DRAM_RESET, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030 +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 +/* Data Strobe */ +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000028 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000028 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000028 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000028 +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +DATA 4, MX6_IOM_GRP_B0DS, 0x00000028 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000028 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000028 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000028 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000028 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000028 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000028 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000028 +DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00000028 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00000028 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00000028 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00000028 diff --git a/board/aristainetos2/nt5cc256m16cp.cfg b/board/aristainetos2/nt5cc256m16cp.cfg new file mode 100644 index 0000000..2ff41e9 --- /dev/null +++ b/board/aristainetos2/nt5cc256m16cp.cfg @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/* ZQ Calibration */ +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F +/* + * DQS gating, read delay, write delay calibration values + */ +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42190217 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x017B017B +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4176017B +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x015F016C +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4C4C4D4C +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4A4D4C48 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3F40 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3538382E +/* read data bit delay */ +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 +/* Complete calibration by forced measurment */ +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +/* in DDR3, 64-bit mode, only MMDC0 is initiated */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020025 +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x676B5313 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8B63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2 +DATA 4, MX6_MMDC_P0_MDOR, 0x006B1023 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000 + +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 + +/* final ddr setup */ +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117 +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025565 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig new file mode 100644 index 0000000..26292fd --- /dev/null +++ b/configs/aristainetos2_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos2/aristainetos2.cfg,MX6DL" +CONFIG_ARM=y +CONFIG_TARGET_ARISTAINETOS2=y diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h new file mode 100644 index 0000000..0294359 --- /dev/null +++ b/include/configs/aristainetos2.h @@ -0,0 +1,351 @@ +/* + * (C) Copyright 2015 + * Heiko Schocher, DENX Software Engineering, hs(a)denx.de. + * + * Based on: + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6DL aristainetos2 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ARISTAINETOS2_CONFIG_H +#define __ARISTAINETOS2_CONFIG_H + +#define CONFIG_MX6 + +#include "mx6_common.h" +#include <linux/sizes.h> + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#include <asm/arch/imx-regs.h> +#include <asm/imx-common/gpio.h> + +#define CONFIG_MACH_TYPE 4501 +#define CONFIG_MMCROOT "/dev/mmcblk0p1" +#define CONFIG_HOSTNAME aristainetos2 +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) + +#define CONFIG_SYS_GENERIC_BOARD + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (64 * SZ_1M) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART2_BASE +#define CONFIG_CONSOLE_DEV "ttymxc1" + +#define CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9031 + +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_MTD +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 3 +#define CONFIG_SF_DEFAULT_CS 1 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_BMODE +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_SETEXPR +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=u-boot.scr\0" \ + "fit_file=/boot/system.itb\0" \ + "loadaddr=0x12000000\0" \ + "fit_addr_r=0x14000000\0" \ + "uboot=/boot/u-boot.imx\0" \ + "uboot_sz=d0000\0" \ + "rescue_sys_addr=f0000\0" \ + "rescue_sys_length=f10000\0" \ + "board_type=aristainetos2_7@1\0" \ + "panel=lb07wv8\0" \ + "splashpos=m,m\0" \ + "console=" CONFIG_CONSOLE_DEV "\0" \ + "nor_bootdelay=-2\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "mtdids=nand0=gpmi-nand,nor0=spi3.1\0" \ + "mtdparts=mtdparts=spi3.1:832k(u-boot),64k(env),64k(env-red)," \ + "-(rescue-system);gpmi-nand:-(ubi)\0" \ + "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "set_fit_default=fdt addr ${fit_addr_r};fdt set /configurations " \ + "default ${board_type}\0" \ + "get_env=mw ${loadaddr} 0 0x20000;" \ + "mmc rescan;" \ + "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} env.txt;" \ + "env import -t ${loadaddr}\0" \ + "default_env=mw ${loadaddr} 0 0x20000;" \ + "env export -t ${loadaddr} serial# ethaddr eth1addr " \ + "board_type panel;" \ + "env default -a;" \ + "env import -t ${loadaddr}\0" \ + "loadbootscript=" \ + "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "mmcpart=1\0" \ + "mmcdev=0\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs addmtd addmisc set_fit_default;" \ + "bootm ${fit_addr_r}\0" \ + "mmc_load_fit=ext2load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ + "${fit_file}\0" \ + "mmc_load_uboot=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "${uboot}\0" \ + "mmc_upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \ + "setexpr cmp_buf ${loadaddr} + ${uboot_sz};" \ + "setexpr uboot_maxsize ${uboot_sz} - 400;" \ + "mw.b ${cmp_buf} 0x00 ${uboot_sz};" \ + "run mmc_load_uboot;sf probe;sf erase 0 ${uboot_sz};" \ + "sf write ${loadaddr} 400 ${filesize};" \ + "sf read ${cmp_buf} 400 ${uboot_sz};" \ + "cmp.b ${loadaddr} ${cmp_buf} ${uboot_maxsize}\0" \ + "ubiargs=setenv bootargs console=${console},${baudrate} " \ + "ubi.mtd=0,4096 root=ubi0:rootfs rootfstype=ubifs\0 " \ + "ubiboot=echo Booting from ubi ...; " \ + "run ubiargs addmtd addmisc set_fit_default;" \ + "bootm ${fit_addr_r}\0" \ + "ubifs_load_fit=sf probe;ubi part ubi 4096;ubifsmount ubi:rootfs;" \ + "ubifsload ${fit_addr_r} /boot/system.itb; " \ + "imi ${fit_addr_r}\0 " \ + "rescueargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/ram rw\0 " \ + "rescueboot=echo Booting rescue system from NOR ...; " \ + "run rescueargs addmtd addmisc set_fit_default;" \ + "bootm ${fit_addr_r}\0" \ + "rescue_load_fit=sf probe;sf read ${fit_addr_r} ${rescue_sys_addr} " \ + "${rescue_sys_length}; imi ${fit_addr_r}\0 " + + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run mmc_load_fit; then " \ + "run mmcboot; " \ + "else " \ + "if run ubifs_load_fit; then " \ + "run ubiboot; " \ + "else " \ + "if run rescue_load_fit; then " \ + "run rescueboot; " \ + "else " \ + "echo RESCUE SYSTEM BOOT " \ + "FAILURE;" \ + "fi; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "else " \ + "if run ubifs_load_fit; then " \ + "run ubiboot; " \ + "else " \ + "if run rescue_load_fit; then " \ + "run rescueboot; " \ + "else " \ + "echo RESCUE SYSTEM BOOT FAILURE;" \ + "fi; " \ + "fi; " \ + "fi" + +#define CONFIG_ARP_TIMEOUT 200UL + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_STACKSIZE (128 * 1024) + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_SIZE (12 * 1024) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SECT_SIZE (0x010000) +#define CONFIG_ENV_OFFSET (0x0d0000) +#define CONFIG_ENV_OFFSET_REDUND (0x0e0000) + +#define CONFIG_OF_LIBFDT + +#define CONFIG_CMD_CACHE + +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0x7f +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x00} } +#define CONFIG_SYS_NUM_I2C_ADAPTERS 4 + +#define CONFIG_CMD_GPIO +#define CONFIG_GPIO_ENABLE_SPI_FLASH IMX_GPIO_NR(2, 15) + +/* NAND stuff */ +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 + +/* RTC */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_RTC_BUS_NUM 2 +#define CONFIG_RTC_M41T11 +#define CONFIG_CMD_DATE + +/* USB Configs */ +#define CONFIG_CMD_USB +#define CONFIG_CMD_FAT +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + +#define ARISTAINETOS2_USB_OTG_PWR IMX_GPIO_NR(4, 15) +#define ARISTAINETOS2_USB_H1_PWR IMX_GPIO_NR(1, 0) + +/* UBI support */ +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS + +#define CONFIG_MTD_UBI_FASTMAP +#define CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT 1 + +#define CONFIG_HW_WATCHDOG +#define CONFIG_IMX_WATCHDOG + +#define CONFIG_FIT + +/* Framebuffer */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +/* check this console not needed, after test remove it */ +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IPUV3_CLK 198000000 +#define CONFIG_IMX_VIDEO_SKIP +#define CONFIG_SYS_LDB_CLOCK 33246000 +#define CONFIG_LG4573 + +#define CONFIG_CMD_BMP + +#define CONFIG_PWM_IMX +#define CONFIG_IMX6_PWM_PER_CLK 66000000 + +#endif /* __ARISTAINETOS2_CONFIG_H */ -- 2.1.0

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[U-Boot] [PATCH v7 00/17] Add PSCI support for Jetson TK1/Tegra124 + CNTFRQ fix
by Jan Kiszka 13 May '15

13 May '15

Changes in v7: - rebased over master - fixed issue that prevented secure boot with all cores => replace ap_pm_init with psci_board_init hook - enable CONFIG_ARMV7_BOOT_SEC_DEFAULT for tegra to avoid problems with default config of current Linux - add cleanup patch for CONFIG_ARMV7_NONSEC/VIRT/PSCI Note that I've removed reviewed and tested tags from modified patches. Jan CC: Andre Przywara <andre.przywara(a)linaro.org> CC: Ian Campbell <ijc(a)hellion.org.uk> CC: Marc Zyngier <marc.zyngier(a)arm.com> CC: Steve Rae <srae(a)broadcom.com> CC: Tang Yuantian <Yuantian.Tang(a)freescale.com> CC: Thierry Reding <treding(a)nvidia.com> CC: York Sun <yorksun(a)freescale.com> Ian Campbell (3): tegra124: Add more registers to struct mc_ctlr tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0 jetson-tk1: Add PSCI configuration options and reserve secure code Jan Kiszka (13): ARM: Clean up CONFIG_ARMV7_NONSEC/VIRT/PSCI conditions sun7i: Remove duplicate call to psci_arch_init ARM: Factor out common psci_get_cpu_id ARM: Factor out reusable psci_cpu_off_common ARM: Factor out reusable psci_cpu_entry ARM: Factor out reusable psci_get_cpu_stack_top ARM: Put target PC for PSCI CPU_ON on per-CPU stack virt-dt: Allow reservation of secure region when in a RAM carveout tegra: Make tegra_powergate_power_on public ARM: Add board-specific initialization hook for PSCI tegra124: Add PSCI support for Tegra124 tegra: Set CNTFRQ for secondary CPUs tegra: Boot in non-secure mode by default Thierry Reding (1): ARM: tegra: Enable SMMU when going non-secure arch/arm/cpu/armv7/Kconfig | 2 +- arch/arm/cpu/armv7/Makefile | 2 +- arch/arm/cpu/armv7/ls102xa/cpu.c | 2 +- arch/arm/cpu/armv7/psci.S | 121 ++++++++++++++++++++++++++++ arch/arm/cpu/armv7/sunxi/psci.S | 112 ++++--------------------- arch/arm/cpu/armv7/virt-dt.c | 31 ++++++- arch/arm/cpu/armv7/virt-v7.c | 11 +++ arch/arm/cpu/u-boot.lds | 2 +- arch/arm/include/asm/arch-tegra/powergate.h | 1 + arch/arm/include/asm/arch-tegra124/flow.h | 6 ++ arch/arm/include/asm/arch-tegra124/mc.h | 37 ++++++++- arch/arm/include/asm/armv7.h | 5 +- arch/arm/include/asm/psci.h | 1 + arch/arm/include/asm/system.h | 1 + arch/arm/lib/bootm-fdt.c | 8 +- arch/arm/lib/bootm.c | 6 +- arch/arm/mach-tegra/Makefile | 4 + arch/arm/mach-tegra/ap.c | 55 +++++++++++++ arch/arm/mach-tegra/powergate.c | 2 +- arch/arm/mach-tegra/psci.S | 114 ++++++++++++++++++++++++++ arch/arm/mach-tegra/tegra124/Kconfig | 2 + arch/arm/mach-tegra/tegra124/Makefile | 4 + arch/arm/mach-tegra/tegra124/psci.c | 59 ++++++++++++++ board/armltd/vexpress/vexpress_common.c | 2 +- board/broadcom/bcm_ep/board.c | 2 +- board/freescale/common/arm_sleep.c | 2 +- include/configs/jetson-tk1.h | 5 ++ 27 files changed, 487 insertions(+), 112 deletions(-) create mode 100644 arch/arm/mach-tegra/psci.S create mode 100644 arch/arm/mach-tegra/tegra124/psci.c -- 2.1.4

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[U-Boot] [PATCH v2] mpc85xx/T1040D4RDB: Disable all CPLD interrupts, except QSGMI1 and QSGMI2
by Codrin Ciubotariu 13 May '15

13 May '15

By default, CPLD used by Freescale's T1040D4RDB has all the interrupt sources enabled. If the interrupt line is enabled in the OS and one of these sources rises the interrupt without having a driver to handle it, then the board will get an interrupt storm. This patch masks all the interrupts available in CPLD with exception for QSGMII PHY interrupts, for which we have a driver in Linux. This patch depends on patches: mpc85xx/T104xD4RDB: Add T104xD4RDB boards support mpc85xx/T1042D4RDB: Select DIU in cpld mux for T1042D4RDB Changes in v2: - assure that the new CPLD register is available only for T104XD4RDB boards; - added debug message if the CPLD verison doesn't support the int_mask register; - add defines for all interrupt mask bits. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu(a)freescale.com> --- board/freescale/t104xrdb/cpld.c | 4 ++++ board/freescale/t104xrdb/cpld.h | 4 ++++ board/freescale/t104xrdb/t104xrdb.c | 11 +++++++++++ include/configs/T104xRDB.h | 12 ++++++++++++ 4 files changed, 31 insertions(+) diff --git a/board/freescale/t104xrdb/cpld.c b/board/freescale/t104xrdb/cpld.c index df0e348..0ce4e47 100644 --- a/board/freescale/t104xrdb/cpld.c +++ b/board/freescale/t104xrdb/cpld.c @@ -69,7 +69,11 @@ static void cpld_dump_regs(void) printf("int_status = 0x%02x\n", CPLD_READ(int_status)); printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status)); printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status)); +#if defined(CONFIG_T104XD4RDB) + printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); +#else printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status)); +#endif printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status)); printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status)); printf("boot_override = 0x%02x\n", CPLD_READ(boot_override)); diff --git a/board/freescale/t104xrdb/cpld.h b/board/freescale/t104xrdb/cpld.h index 543ab53..2fb4105 100644 --- a/board/freescale/t104xrdb/cpld.h +++ b/board/freescale/t104xrdb/cpld.h @@ -21,7 +21,11 @@ struct cpld_data { u8 int_status; /* 0x12 - Interrupt status Register */ u8 flash_ctl_status; /* 0x13 - Flash control and status register */ u8 fan_ctl_status; /* 0x14 - Fan control and status register */ +#if defined(CONFIG_T104XD4RDB) + u8 int_mask; /* 0x15 - Interrupt mask Register */ +#else u8 led_ctl_status; /* 0x15 - LED control and status register */ +#endif u8 sfp_ctl_status; /* 0x16 - SFP control and status register */ u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/ u8 boot_override; /* 0x18 - Boot override register */ diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index 963cae4..c4b658d 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -112,6 +112,17 @@ int misc_init_r(void) CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) | MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL); +#if defined(CONFIG_T1040D4RDB) + /* Mask all CPLD interrupt sources, except QSGMII interrupts */ + if (CPLD_READ(sw_ver) < 0x03) { + debug("CPLD SW version 0x%02x doesn't support int_mask\n", + CPLD_READ(sw_ver)); + } else { + CPLD_WRITE(int_mask, CPLD_INT_MASK_ALL & + ~(CPLD_INT_MASK_QSGMII1 | CPLD_INT_MASK_QSGMII2)); + } +#endif + return 0; } diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index baccbb5..d37f063 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -295,6 +295,18 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg #define CPLD_DIU_SEL_DFP 0xc0 #endif +#if defined(CONFIG_T1040D4RDB) +#define CPLD_INT_MASK_ALL 0xFF +#define CPLD_INT_MASK_THERM 0x80 +#define CPLD_INT_MASK_DVI_DFP 0x40 +#define CPLD_INT_MASK_QSGMII1 0x20 +#define CPLD_INT_MASK_QSGMII2 0x10 +#define CPLD_INT_MASK_SGMI1 0x08 +#define CPLD_INT_MASK_SGMI2 0x04 +#define CPLD_INT_MASK_TDMR1 0x02 +#define CPLD_INT_MASK_TDMR2 0x01 +#endif + #define CONFIG_SYS_CPLD_BASE 0xffdf0000 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) #define CONFIG_SYS_CSPR2_EXT (0xf) -- 1.9.3

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[U-Boot] [PATCH] i2c, mxc: rework i2c base address names for different SoCs
by Heiko Schocher 13 May '15

13 May '15

rework and unify i2c address names for different SoCs, which use the mxc_i2c driver. Signed-off-by: Heiko Schocher <hs(a)denx.de> --- arch/arm/include/asm/arch-imx/imx-regs.h | 2 +- arch/arm/include/asm/arch-mx25/imx-regs.h | 6 ++--- arch/arm/include/asm/arch-mx27/imx-regs.h | 4 +-- arch/arm/include/asm/arch-vf610/imx-regs.h | 2 +- drivers/i2c/mxc_i2c.c | 43 +++++++++++++++--------------- 5 files changed, 28 insertions(+), 29 deletions(-) diff --git a/arch/arm/include/asm/arch-imx/imx-regs.h b/arch/arm/include/asm/arch-imx/imx-regs.h index 4de0779..93e3369 100644 --- a/arch/arm/include/asm/arch-imx/imx-regs.h +++ b/arch/arm/include/asm/arch-imx/imx-regs.h @@ -42,7 +42,7 @@ #define IMX_MMC_BASE (0x14000 + IMX_IO_BASE) #define IMX_ASP_BASE (0x15000 + IMX_IO_BASE) #define IMX_BTA_BASE (0x16000 + IMX_IO_BASE) -#define IMX_I2C_BASE (0x17000 + IMX_IO_BASE) +#define I2C1_BASE_ADDR (0x17000 + IMX_IO_BASE) #define IMX_SSI_BASE (0x18000 + IMX_IO_BASE) #define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE) #define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE) diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h index 3dffa4a..78c4e9b 100644 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ b/arch/arm/include/asm/arch-mx25/imx-regs.h @@ -293,13 +293,13 @@ struct cspi_regs { #define IMX_ETB_SLOT4_BASE (0x43F0C000) #define IMX_ETB_SLOT5_BASE (0x43F10000) #define IMX_ECT_CTIO_BASE (0x43F18000) -#define IMX_I2C_BASE (0x43F80000) -#define IMX_I2C3_BASE (0x43F84000) +#define I2C1_BASE_ADDR (0x43F80000) +#define I2C3_BASE_ADDR (0x43F84000) #define IMX_CAN1_BASE (0x43F88000) #define IMX_CAN2_BASE (0x43F8C000) #define UART1_BASE (0x43F90000) #define UART2_BASE (0x43F94000) -#define IMX_I2C2_BASE (0x43F98000) +#define I2C2_BASE_ADDR (0x43F98000) #define IMX_OWIRE_BASE (0x43F9C000) #define IMX_CSPI1_BASE (0x43FA4000) #define IMX_KPP_BASE (0x43FA8000) diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h index 92c847e..82cee19 100644 --- a/arch/arm/include/asm/arch-mx27/imx-regs.h +++ b/arch/arm/include/asm/arch-mx27/imx-regs.h @@ -194,13 +194,13 @@ struct fuse_bank0_regs { #define UART2_BASE (0x0b000 + IMX_IO_BASE) #define UART3_BASE (0x0c000 + IMX_IO_BASE) #define UART4_BASE (0x0d000 + IMX_IO_BASE) -#define IMX_I2C1_BASE (0x12000 + IMX_IO_BASE) +#define I2C1_BASE_ADDR (0x12000 + IMX_IO_BASE) #define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE) #define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE) #define IMX_TIM5_BASE (0x1a000 + IMX_IO_BASE) #define IMX_UART5_BASE (0x1b000 + IMX_IO_BASE) #define IMX_UART6_BASE (0x1c000 + IMX_IO_BASE) -#define IMX_I2C2_BASE (0x1D000 + IMX_IO_BASE) +#define I2C2_BASE_ADDR (0x1D000 + IMX_IO_BASE) #define IMX_TIM6_BASE (0x1f000 + IMX_IO_BASE) #define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE) #define IMX_PLL_BASE (0x27000 + IMX_IO_BASE) diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index a7d765a..2021981 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -74,7 +74,7 @@ #define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000) #define ESAI_FIFO_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000) #define WDOG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00065000) -#define I2C0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00066000) +#define I2C1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00066000) #define WKUP_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006A000) #define CCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006B000) #define GPC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000) diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index c258a2b..d0fca96 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -174,6 +174,9 @@ static int bus_i2c_set_bus_speed(void *base, int speed) u8 clk_idx = i2c_imx_get_clk(speed); u8 idx = i2c_clk_div[clk_idx][1]; + if (!base) + return -ENODEV; + /* Store divider value */ writeb(idx, &i2c_regs->ifdr); @@ -336,6 +339,9 @@ int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf, int i; struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base; + if (!base) + return -ENODEV; + ret = i2c_init_transfer(i2c_regs, chip, addr, alen); if (ret < 0) return ret; @@ -395,6 +401,9 @@ int bus_i2c_write(void *base, uchar chip, uint addr, int alen, int i; struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base; + if (!base) + return -ENODEV; + ret = i2c_init_transfer(i2c_regs, chip, addr, alen); if (ret < 0) return ret; @@ -408,33 +417,23 @@ int bus_i2c_write(void *base, uchar chip, uint addr, int alen, return ret; } -static void * const i2c_bases[] = { -#if defined(CONFIG_MX25) - (void *)IMX_I2C_BASE, - (void *)IMX_I2C2_BASE, - (void *)IMX_I2C3_BASE -#elif defined(CONFIG_MX27) - (void *)IMX_I2C1_BASE, - (void *)IMX_I2C2_BASE -#elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \ - defined(CONFIG_MX51) || defined(CONFIG_MX53) || \ - defined(CONFIG_MX6) || defined(CONFIG_LS102XA) - (void *)I2C1_BASE_ADDR, - (void *)I2C2_BASE_ADDR, - (void *)I2C3_BASE_ADDR, -#if defined(CONFIG_MX6DL) - (void *)I2C4_BASE_ADDR +#if !defined(I2C2_BASE_ADDR) +#define I2C2_BASE_ADDR NULL #endif -#elif defined(CONFIG_VF610) - (void *)I2C0_BASE_ADDR -#elif defined(CONFIG_FSL_LSCH3) + +#if !defined(I2C3_BASE_ADDR) +#define I2C3_BASE_ADDR NULL +#endif + +#if !defined(I2C4_BASE_ADDR) +#define I2C4_BASE_ADDR NULL +#endif + +static void * const i2c_bases[] = { (void *)I2C1_BASE_ADDR, (void *)I2C2_BASE_ADDR, (void *)I2C3_BASE_ADDR, (void *)I2C4_BASE_ADDR -#else -#error "architecture not supported" -#endif }; struct i2c_parms { -- 2.1.0

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[U-Boot] [PATCH v1 0/3] New tag for Flattened Image Trees (FIT) - Booting Xen from a FIT.
by Karl Apsite 13 May '15

13 May '15

The FIT config now supports a tag named "loadables:" which is a comma separated list. Users can add any number of images to the list, and u-boot will move the selected binaries to their listed load_addresses. This allows u-boot to boot xen from using an FIT configuration. Xen expects a kernel to be placed at a predetermined location, however the "kernel" field was already filled by xen itself. This change allows the user to move the required binary before xen boots, all within the FIT's configuration. Karl Apsite (3): add test for two 'loadables' mkimage will now report information about loadable add boot_get_loadables() to load listed images common/bootm.c | 22 +++++++++ common/image-fit.c | 25 +++++++++- common/image.c | 93 +++++++++++++++++++++++++++++++++++ doc/uImage.FIT/source_file_format.txt | 4 ++ include/bootstage.h | 1 + include/image.h | 6 ++- test/image/test-fit.py | 73 +++++++++++++++++++++++---- 7 files changed, 213 insertions(+), 11 deletions(-) -- 2.3.7

2 1