May 2015 - U-Boot

[U-Boot] i.MX53 USB Client not working
by Matthew Starr 14 May '15

14 May '15

I have a custom board loosely based off the i.MX53 QSB with a dedicated USB client port and separate dedicated USB host port. I am trying to get USB client functionality working in mainline u-boot 2015.04. I have verified that USB client/gadget functionality works when booted into Linux on the board. In u-boot I have tried testing USB client with USB Mass Storage, DFU, and FastBoot and none of them seem to work. Here is my USB client #defines from my config header file: #define CONFIG_CI_UDC #define CONFIG_USBD_HS #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET #define CONFIG_CMD_USB_MASS_STORAGE #define CONFIG_USB_GADGET_MASS_STORAGE #define CONFIG_USBDOWNLOAD_GADGET #define CONFIG_USB_GADGET_VBUS_DRAW 2 #define CONFIG_USB_ETHER #define CONFIG_USB_ETH_CDC #define CONFIG_G_DNL_VENDOR_NUM 0x0525 #define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5 #define CONFIG_G_DNL_MANUFACTURER "FSL" #define CONFIG_SYS_CACHELINE_SIZE 64 Additionally here are my #defines for the USB host functionality: /* USB Host Configs */ #define CONFIG_CMD_USB #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_MX5 #define CONFIG_USB_STORAGE #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX #define CONFIG_USB_ETHER_MCS7830 #define CONFIG_USB_ETHER_SMSC95XX #define CONFIG_MXC_USB_PORT 1 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 Here is my board file content related to USB: #ifdef CONFIG_USB_EHCI_MX5 static void setup_usb(void) { imx_iomux_v3_setup_pad(MX53_PAD_GPIO_0__GPIO1_0); } int board_ehci_hcd_init(int port) { /* Enable USB_H1_VBUS power with GPIO1_0 */ gpio_direction_output(IMX_GPIO_NR(1, 0), 1); return 0; } #endif int board_usb_phy_mode(int port) { if (port == 1) return USB_INIT_HOST; else return USB_INIT_DEVICE; } Then later on in board_init(), I have: #ifdef CONFIG_USB_EHCI_MX5 setup_usb(); #endif When I run the 'ums 0 mmc 0' command, I get the following: UMS: disk start sector: 0x0, count: 0xe88000 and then I get an infinite spinning progress indicator. At this point when I connect the USB cable to a Host PC, I see nothing on the host PC side (Windows or Liunx). Any ideas on what I am missing to get USB client working or any hints on how to debug this further. Best regards, Matthew Starr

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[U-Boot] Bug: boot_fdt_add_mem_rsv_regions() can drop upper 32 bits of physical addresses
by Dan Hettena 14 May '15

14 May '15

When phys_addr_t is 32 bits wide, boot_fdt_add_mem_rsv_regions() implicitly uses only the low 32 bits of each memory reservation's address and length to determine what to reserve. So, for example, an FDT memory reservation like /memreserve/ 0x180000000 0x40000000; will actually reserve physical memory starting at 0x80000000, not 0x180000000 (though the printf() will claim it is reserving starting at 0x180000000). Dan

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[U-Boot] [PATCH] tools: moveconfig: a tool to move CONFIGs from headers to defconfigs
by Masahiro Yamada 14 May '15

14 May '15

This tool was originally written for my local use to ease the task of tons of CONFIG moves, but there have been some requests for mainlining it. So, I have tidied up the code with nicer comments, and here it is. See the comment block of the script for usage. The first draft was http://patchwork.ozlabs.org/patch/430422/ Main updates are: - Adapted to the single .config configuration - Support colored log - Support moving multiple options at once (and take configs from an input file only) - Continue even if some boards fail (Idea provided by Joe Hershberger) - More comments and code cleanups Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> Signed-off-by: Joe Hershberger <joe.hershberger(a)ni.com> --- tools/moveconfig.py | 843 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 843 insertions(+) create mode 100755 tools/moveconfig.py diff --git a/tools/moveconfig.py b/tools/moveconfig.py new file mode 100755 index 0000000..02e2d6a --- /dev/null +++ b/tools/moveconfig.py @@ -0,0 +1,843 @@ +#!/usr/bin/env python2 +# +# Author: Masahiro Yamada <yamada.masahiro(a)socionext.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +""" +Move config option(s) from headers to defconfig. + +Since Kconfig was introduced to U-Boot, we have worked on moving +config options from headers to Kconfig (defconfig). + +This tool intends to help this tremendous work. + + +Usage +----- + +This tool takes one input file. (let's say 'recipe' file here.) +The recipe describes the list of config options you want to move. +Each line takes the form: +<config_name> <type> <default> +(the fields must be separated with whitespaces.) + +<config_name> is the name of config option. + +<type> is the type of the option. It must be one of bool, tristate, +string, int, and hex. + +<default> is the default value of the option. It must be appropriate +value corresponding to the value type. It must be either y or n for +the bool type. Tristate options can also take m (although U-Boot has +not supported the module feature). + +You can add two or more lines in the recipe file, so you can move +multiple options at once. + +Let's say, for example, you want to move CONFIG_CMD_USB and +CONFIG_SYS_TEXT_BASE. + +The type should be bool, hex, respectively. So, the recipe file +should look like this: + + $ cat recipe + CONFIG_SYS_GENERIC_BOARD bool n + CONFIG_SYS_TEXT_BASE hex 0x00000000 + +And then run this tool giving the file name of the recipe + + $ tools/moveconfig.py recipe + +The tool walks through all the defconfig files to move the config +options specified by the recipe file. + +The log is also displayed on the terminal. + +Each line is printed in the format +<defconfig_name> : <action> + +<defconfig_name> is the name of the defconfig +(without the suffix _defconfig). + +<action> shows what the tool did for that defconfig. +It looks like one of the followings: + + - Move 'CONFIG_... ' + This config option was moved to the defconfig + + - Default value 'CONFIG_...'. Do nothing. + The value of this option is the same as default. + We do not have to add it to the defconfig. + + - 'CONFIG_...' already exists in Kconfig. Do nothing. + This config option is already defined in Kconfig. + We do not need/want to touch it. + + - Undefined. Do nothing. + This config option was not found in the config header. + Nothing to do. + + - Failed to process. Skip. + An error occurred during processing this defconfig. Skipped. + (If -e option is passed, the tool exits immediately on error.) + +Finally, you will be asked, Clean up headers? [y/n]: + +If you say 'y' here, the unnecessary config defines are removed +from the config headers (include/configs/*.h). +It just uses the regex method, so you should not rely on it. +Just in case, please do 'git diff' to see what happened. + + +How does it works? +------------------ + +This tool runs configuration and builds include/autoconf.mk for every +defconfig. The config options defined in Kconfig appear in the .config +file (unless they are hidden because of unmet dependency.) +On the other hand, the config options defined by board headers are seen +in include/autoconf.mk. The tool looks for the specified options in both +of them to decide the appropriate action for the options. If the option +is found in the .config or the value is the same as the specified default, +the option does not need to be touched. If the option is found in +include/autoconf.mk, but not in the .config, and the value is different +from the default, the tools adds the option to the defconfig. + +For faster processing, this tool handles multi-threading. It creates +separate build directories where the out-of-tree build is run. The +temporary build directories are automatically created and deleted as +needed. The number of threads are chosen based on the number of the CPU +cores of your system although you can change it via -j (--jobs) option. + + +Toolchains +---------- + +Appropriate toolchain are necessary to generate include/autoconf.mk +for all the architectures supported by U-Boot. Most of them are available +at the kernel.org site, some are not provided by kernel.org. + +The default per-arch CROSS_COMPILE used by this tool is specified by +the list below, CROSS_COMPILE. You may wish to update the list to +use your own. Instead of modifying the list directly, you can give +them via environments. + + +Available options +----------------- + + -c, --color + Surround each portion of the log with escape sequences to display it + in color on the terminal. + + -e, --exit-on-error + Exit immediately if Make exits with a non-zero status while processing + a defconfig file. + + -j, --jobs + Specify the number of threads to run simultaneously. If not specified, + the number of threads is the same as the number of CPU cores. + +To see the complete list of supported options, run + + $ tools/moveconfig.py -h + +""" + +import fnmatch +import multiprocessing +import optparse +import os +import re +import shutil +import subprocess +import sys +import tempfile +import time + +SHOW_GNU_MAKE = 'scripts/show-gnu-make' +SLEEP_TIME=0.03 + +# Here is the list of cross-tools I use. +# Most of them are available at kernel.org +# (https://www.kernel.org/pub/tools/crosstool/files/bin/), except, +# arc: https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases +# blackfin: http://sourceforge.net/projects/adi-toolchain/files/ +# nios2: https://sourcery.mentor.com/GNUToolchain/subscription42544 +# nds32, sh: http://dev.gentoo.org/~vapier/u-boot +CROSS_COMPILE = { + # The default arc CROSS_COMPILE is defined by arch/arc/config.mk + 'aarch64': 'aarch64-linux-', + 'arm': 'arm-unknown-linux-gnueabi-', + 'avr32': 'avr32-linux-', + 'blackfin': 'bfin-elf-', + 'm68k': 'm68k-linux-', + 'microblaze': 'microblaze-linux-', + 'mips': 'mips-linux-', + 'nds32': 'nds32le-linux-', + 'nios2': 'nios2-linux-', + 'openrisc': 'or32-linux-', + 'powerpc': 'powerpc-linux-', + 'sh': 'sh4-gentoo-linux-gnu-', + 'sparc': 'sparc-linux-', + 'x86': 'i386-linux-' +} + +STATE_IDLE = 0 +STATE_DEFCONFIG = 1 +STATE_AUTOCONF = 2 + +ACTION_MOVE = 0 +ACTION_DEFAULT_VALUE = 1 +ACTION_ALREADY_EXIST = 2 +ACTION_UNDEFINED = 3 + +COLOR_BLACK = '0;30' +COLOR_RED = '0;31' +COLOR_GREEN = '0;32' +COLOR_BROWN = '0;33' +COLOR_BLUE = '0;34' +COLOR_PURPLE = '0;35' +COLOR_CYAN = '0;36' +COLOR_LIGHT_GRAY = '0;37' +COLOR_DARK_GRAY = '1;30' +COLOR_LIGHT_RED = '1;31' +COLOR_LIGHT_GREEN = '1;32' +COLOR_YELLOW = '1;33' +COLOR_LIGHT_BLUE = '1;34' +COLOR_LIGHT_PURPLE = '1;35' +COLOR_LIGHT_CYAN = '1;36' +COLOR_WHITE = '1;37' + +### helper functions ### +def get_devnull(): + """Get the file object of '/dev/null' device.""" + try: + devnull = subprocess.DEVNULL # py3k + except AttributeError: + devnull = open(os.devnull, 'wb') + return devnull + +def check_top_directory(): + """Exit if we are not at the top of source directory.""" + for f in ('README', 'Licenses'): + if not os.path.exists(f): + sys.exit('Please run at the top of source directory.') + +def get_make_cmd(): + """Get the command name of GNU Make. + + U-Boot needs GNU Make for building, but the command name is not + necessarily "make". (for example, "gmake" on FreeBSD). + Returns the most appropriate command name on your system. + """ + process = subprocess.Popen([SHOW_GNU_MAKE], stdout=subprocess.PIPE) + ret = process.communicate() + if process.returncode: + sys.exit('GNU Make not found') + return ret[0].rstrip() + +def color_text(color_enabled, color, string): + """Return colored string.""" + if color_enabled: + return '\033[' + color + 'm' + string + '\033[0m' + else: + return string + +def log_msg(color_enabled, color, defconfig, msg): + """Return the formated line for the log.""" + return defconfig[:-len('_defconfig')].ljust(37) + ': ' + \ + color_text(color_enabled, color, msg) + '\n' + +def update_cross_compile(): + """Update per-arch CROSS_COMPILE via enviroment variables + + The default CROSS_COMPILE values are available + in the CROSS_COMPILE list above. + + You can override them via enviroment variables + CROSS_COMPILE_{ARCH}. + + For example, if you want to override toolchain prefixes + for ARM and PowerPC, you can do as follows in your shell: + + export CROSS_COMPILE_ARM=... + export CROSS_COMPILE_POWERPC=... + """ + archs = [] + + for arch in os.listdir('arch'): + if os.path.exists(os.path.join('arch', arch, 'Makefile')): + archs.append(arch) + + # arm64 is a special case + archs.append('aarch64') + + for arch in archs: + env = 'CROSS_COMPILE_' + arch.upper() + cross_compile = os.environ.get(env) + if cross_compile: + CROSS_COMPILE[arch] = cross_compile + +def cleanup_one_header(header_path, patterns): + """Clean regex-matched lines away from a file. + + Arguments: + header_path: path to the cleaned file. + patterns: list of regex patterns. Any lines matching to these + patterns are deleted. + """ + with open(header_path) as f: + lines = f.readlines() + + matched = [] + for i, line in enumerate(lines): + for pattern in patterns: + m = pattern.search(line) + if m: + print '%s: %s: %s' % (header_path, i + 1, line), + matched.append(i) + break + + if not matched: + return + + with open(header_path, 'w') as f: + for i, line in enumerate(lines): + if not i in matched: + f.write(line) + +def cleanup_headers(config_attrs): + """Delete config defines from board headers. + + Arguments: + config_attrs: A list of dictionaris, each of them includes the name, + the type, and the default value of the target config. + """ + while True: + choice = raw_input('Clean up headers? [y/n]: ').lower() + print choice + if choice == 'y' or choice == 'n': + break + + if choice == 'n': + return + + patterns = [] + for config_attr in config_attrs: + config = config_attr['config'] + patterns.append(re.compile(r'#\s*define\s+%s\W' % config)) + patterns.append(re.compile(r'#\s*undef\s+%s\W' % config)) + + for (dirpath, dirnames, filenames) in os.walk('include'): + for filename in filenames: + if not fnmatch.fnmatch(filename, '*~'): + cleanup_one_header(os.path.join(dirpath, filename), patterns) + +### classes ### +class KconfigParser: + + """A parser of .config and include/autoconf.mk.""" + + re_arch = re.compile(r'CONFIG_SYS_ARCH="(.*)"') + re_cpu = re.compile(r'CONFIG_SYS_CPU="(.*)"') + + def __init__(self, config_attrs, options, build_dir): + """Create a new parser. + + Arguments: + config_attrs: A list of dictionaris, each of them includes the name, + the type, and the default value of the target config. + options: option flags. + build_dir: Build directory. + """ + self.config_attrs = config_attrs + self.options = options + self.build_dir = build_dir + + def get_cross_compile(self): + """Parse .config file and return CROSS_COMPILE. + + Returns: + A string storing the compiler prefix for the architecture. + """ + arch = '' + cpu = '' + dotconfig = os.path.join(self.build_dir, '.config') + for line in open(dotconfig): + m = self.re_arch.match(line) + if m: + arch = m.group(1) + continue + m = self.re_cpu.match(line) + if m: + cpu = m.group(1) + + assert arch, 'Error: arch is not defined in %s' % defconfig + + # fix-up for aarch64 + if arch == 'arm' and cpu == 'armv8': + arch = 'aarch64' + + return CROSS_COMPILE.get(arch, '') + + def parse_one_config(self, config_attr, defconfig_lines, + dotconfig_lines, autoconf_lines): + """Parse .config, defconfig, include/autoconf.mk for one config. + + This function looks for the config options in the lines from + defconfig, .config, and include/autoconf.mk in order to decide + which action should be taken for this defconfig. + + Arguments: + config_attr: A dictionary including the name, the type, + and the default value of the target config. + defconfig_lines: lines from the original defconfig file. + dotconfig_lines: lines from the .config file. + autoconf_lines: lines from the include/autoconf.mk file. + + Returns: + A tupple of the action for this defconfig and the line + matched for the config. + """ + config = config_attr['config'] + not_set = '# %s is not set' % config + + if config_attr['type'] in ('bool', 'tristate') and \ + config_attr['default'] == 'n': + default = not_set + else: + default = config + '=' + config_attr['default'] + + for line in defconfig_lines + dotconfig_lines: + line = line.rstrip() + if line.startswith(config + '=') or line == not_set: + return (ACTION_ALREADY_EXIST, line) + + if config_attr['type'] in ('bool', 'tristate'): + value = not_set + else: + value = '(undefined)' + + for line in autoconf_lines: + line = line.rstrip() + if line.startswith(config + '='): + value = line + break + + if value == default: + action = ACTION_DEFAULT_VALUE + elif value == '(undefined)': + action = ACTION_UNDEFINED + else: + action = ACTION_MOVE + + return (action, value) + + def update_defconfig(self, defconfig): + """Parse files for the config options and update the defconfig. + + This function parses the given defconfig, the generated .config + and include/autoconf.mk searching the target options. + Move the config option(s) to the defconfig or do nothing if unneeded. + Also, display the log to show what happened to this defconfig. + + Arguments: + defconfig: defconfig name. + """ + + defconfig_path = os.path.join('configs', defconfig) + dotconfig_path = os.path.join(self.build_dir, '.config') + autoconf_path = os.path.join(self.build_dir, 'include', 'autoconf.mk') + results = [] + + with open(defconfig_path) as f: + defconfig_lines = f.readlines() + + with open(dotconfig_path) as f: + dotconfig_lines = f.readlines() + + with open(autoconf_path) as f: + autoconf_lines = f.readlines() + + for config_attr in self.config_attrs: + result = self.parse_one_config(config_attr, defconfig_lines, + dotconfig_lines, autoconf_lines) + results.append(result) + + log = '' + + for (action, value) in results: + if action == ACTION_MOVE: + actlog = "Move '%s'" % value + log_color = COLOR_LIGHT_GREEN + elif action == ACTION_DEFAULT_VALUE: + actlog = "Default value '%s'. Do nothing." % value + log_color = COLOR_LIGHT_BLUE + elif action == ACTION_ALREADY_EXIST: + actlog = "'%s' already defined in Kconfig. Do nothing." % value + log_color = COLOR_LIGHT_PURPLE + elif action == ACTION_UNDEFINED: + actlog = "Undefined. Do nothing." + log_color = COLOR_DARK_GRAY + else: + sys.exit("Internal Error. This should not happen.") + + log += log_msg(self.options.color, log_color, defconfig, actlog) + + # Some threads are running in parallel. + # Print log in one shot to not mix up logs from different threads. + print log, + + with open(defconfig_path, 'a') as f: + for (action, value) in results: + if action == ACTION_MOVE: + f.write(value + '\n') + + os.remove(os.path.join(self.build_dir, 'include', 'config', 'auto.conf')) + os.remove(autoconf_path) + +class Slot: + + """A slot to store a subprocess. + + Each instance of this class handles one subprocess. + This class is useful to control multiple threads + for faster processing. + """ + + def __init__(self, config_attrs, options, devnull, make_cmd): + """Create a new process slot. + + Arguments: + config_attrs: A list of dictionaris, each of them includes the name, + the type, and the default value of the target config. + options: option flags. + devnull: A file object of '/dev/null'. + make_cmd: command name of GNU Make. + """ + self.options = options + self.build_dir = tempfile.mkdtemp() + self.devnull = devnull + self.make_cmd = (make_cmd, 'O=' + self.build_dir) + self.parser = KconfigParser(config_attrs, options, self.build_dir) + self.state = STATE_IDLE + self.failed_boards = [] + + def __del__(self): + """Delete the working directory + + This function makes sure the temporary directory is cleaned away + even if Python suddenly dies due to error. It should be done in here + because it is guranteed the destructor is always invoked when the + instance of the class gets unreferenced. + + If the subprocess is still running, wait until it finishes. + """ + if self.state != STATE_IDLE: + while self.ps.poll() == None: + pass + shutil.rmtree(self.build_dir) + + def add(self, defconfig): + """Assign a new subprocess for defconfig and add it to the slot. + + If the slot is vacant, create a new subprocess for processing the + given defconfig and add it to the slot. Just returns False if + the slot is occupied (i.e. the current subprocess is still running). + + Arguments: + defconfig: defconfig name. + + Returns: + Return True on success or False on failure + """ + if self.state != STATE_IDLE: + return False + cmd = list(self.make_cmd) + cmd.append(defconfig) + self.ps = subprocess.Popen(cmd, stdout=self.devnull) + self.defconfig = defconfig + self.state = STATE_DEFCONFIG + return True + + def poll(self): + """Check the status of the subprocess and handle it as needed. + + Returns True if the slot is vacant (i.e. in idle state). + If the configuration is successfully finished, assign a new + subprocess to build include/autoconf.mk. + If include/autoconf.mk is generated, invoke the parser to + parse the .config and the include/autoconf.mk, and then set the + slot back to the idle state. + + Returns: + Return True if the subprocess is terminated, False otherwise + """ + if self.state == STATE_IDLE: + return True + + if self.ps.poll() == None: + return False + + if self.ps.poll() != 0: + + print >> sys.stderr, log_msg(self.options.color, + COLOR_LIGHT_RED, + self.defconfig, + "failed to process.") + if self.options.exit_on_error: + sys.exit("Exit on error.") + else: + # If --exit-on-error flag is not set, + # skip this board and continue. + # Record the failed board. + self.failed_boards.append(self.defconfig) + self.state = STATE_IDLE + return True + + if self.state == STATE_AUTOCONF: + self.parser.update_defconfig(self.defconfig) + self.state = STATE_IDLE + return True + + cross_compile = self.parser.get_cross_compile() + cmd = list(self.make_cmd) + if cross_compile: + cmd.append('CROSS_COMPILE=%s' % cross_compile) + cmd.append('include/config/auto.conf') + self.ps = subprocess.Popen(cmd, stdout=self.devnull) + self.state = STATE_AUTOCONF + return False + + def get_failed_boards(self): + """Returns a list of failed boards (defconfigs) in this slot. + """ + return self.failed_boards + +class Slots: + + """Controller of the array of subprocess slots.""" + + def __init__(self, config_attrs, options): + """Create a new slots controller. + + Arguments: + config_attrs: A list of dictionaris containing the name, the type, + and the default value of the target CONFIG. + options: option flags. + """ + self.options = options + self.slots = [] + devnull = get_devnull() + make_cmd = get_make_cmd() + for i in range(options.jobs): + self.slots.append(Slot(config_attrs, options, devnull, make_cmd)) + + def add(self, defconfig): + """Add a new subprocess if a vacant slot is found. + + Arguments: + defconfig: defconfig name to be put into. + + Returns: + Return True on success or False on failure + """ + for slot in self.slots: + if slot.add(defconfig): + return True + return False + + def available(self): + """Check if there is a vacant slot. + + Returns: + Return True if at lease one vacant slot is found, False otherwise. + """ + for slot in self.slots: + if slot.poll(): + return True + return False + + def empty(self): + """Check if all slots are vacant. + + Returns: + Return True if all the slots are vacant, False otherwise. + """ + ret = True + for slot in self.slots: + if not slot.poll(): + ret = False + return ret + + def show_failed_boards(self): + """Display all of the failed boards (defconfigs).""" + failed_boards = [] + + for slot in self.slots: + failed_boards += slot.get_failed_boards() + + if len(failed_boards) > 0: + msg = [ "The following boards were not processed due to error:" ] + msg += failed_boards + print msg + for line in msg: + print >> sys.stderr, color_text(self.options.color, + COLOR_LIGHT_RED, line) + +def move_config(config_attrs, options): + """Move config options to defconfig files. + + Arguments: + config_attrs: A list of dictionaris, each of them includes the name, + the type, and the default value of the target config. + options: option flags + """ + check_top_directory() + + if len(config_attrs) == 0: + print 'Nothing to do. exit.' + sys.exit(0) + + print 'Move the following CONFIG options (jobs: %d)' % options.jobs + for config_attr in config_attrs: + print ' %s (type: %s, default: %s)' % (config_attr['config'], + config_attr['type'], + config_attr['default']) + + # All the defconfig files to be processed + defconfigs = [] + for (dirpath, dirnames, filenames) in os.walk('configs'): + dirpath = dirpath[len('configs') + 1:] + for filename in fnmatch.filter(filenames, '*_defconfig'): + defconfigs.append(os.path.join(dirpath, filename)) + + slots = Slots(config_attrs, options) + + # Main loop to process defconfig files: + # Add a new subprocess into a vacant slot. + # Sleep if there is no available slot. + for defconfig in defconfigs: + while not slots.add(defconfig): + while not slots.available(): + # No available slot: sleep for a while + time.sleep(SLEEP_TIME) + + # wait until all the subprocesses finish + while not slots.empty(): + time.sleep(SLEEP_TIME) + + slots.show_failed_boards() + + cleanup_headers(config_attrs) + +def bad_recipe(filename, linenum, msg): + """Print error message with the file name and the line number and exit.""" + sys.exit("%s: line %d: error : " % (filename, linenum) + msg) + +def parse_recipe(filename): + """Parse the recipe file and retrieve the config attributes. + + This function parses the given recipe file and gets the name, + the type, and the default value of the target config options. + + Arguments: + filename: path to file to be parsed. + Returns: + A list of dictionaris, each of them includes the name, + the type, and the default value of the target config. + """ + config_attrs = [] + linenum = 1 + + for line in open(filename): + tokens = line.split() + if len(tokens) != 3: + bad_recipe(filename, linenum, + "%d fields in this line. Each line must contain 3 fields" + % len(tokens)) + + (config, type, default) = tokens + + # prefix the option name with CONFIG_ if missing + if not config.startswith('CONFIG_'): + config = 'CONFIG_' + config + + # sanity check of default values + if type == 'bool': + if not default in ('y', 'n'): + bad_recipe(filename, linenum, + "default for bool type must be either y or n") + elif type == 'tristate': + if not default in ('y', 'm', 'n'): + bad_recipe(filename, linenum, + "default for tristate type must be y, m, or n") + elif type == 'string': + if default[0] != '"' or default[-1] != '"': + bad_recipe(filename, linenum, + "default for string type must be surrounded by double-quotations") + elif type == 'int': + try: + int(default) + except: + bad_recipe(filename, linenum, + "type is int, but default value is not decimal") + elif type == 'hex': + if len(default) < 2 or default[:2] != '0x': + bad_recipe(filename, linenum, + "default for hex type must be prefixed with 0x") + try: + int(default, 16) + except: + bad_recipe(filename, linenum, + "type is hex, but default value is not hexadecimal") + else: + bad_recipe(filename, linenum, + "unsupported type '%s'. type must be one of bool, tristate, string, int, hex" + % type) + + config_attrs.append({'config': config, 'type': type, 'default': default}) + linenum += 1 + + return config_attrs + +def main(): + try: + cpu_count = multiprocessing.cpu_count() + except NotImplementedError: + cpu_count = 1 + + parser = optparse.OptionParser() + # Add options here + parser.add_option('-c', '--color', action='store_true', default=False, + help='display the log in color') + parser.add_option('-e', '--exit-on-error', action='store_true', + default=False, + help='exit immediately on any error') + parser.add_option('-j', '--jobs', type='int', default=cpu_count, + help='the number of jobs to run simultaneously') + parser.usage += ' recipe_file\n\n' + \ + 'The recipe_file should describe config options you want to move.\n' + \ + 'Each line should contain config_name, type, default_value\n\n' + \ + 'Example:\n' + \ + 'CONFIG_FOO bool n\n' + \ + 'CONFIG_BAR int 100\n' + \ + 'CONFIG_BAZ string "hello"\n' + + (options, args) = parser.parse_args() + + if len(args) != 1: + parser.print_usage() + sys.exit(1) + + config_attrs = parse_recipe(args[0]) + + update_cross_compile() + + move_config(config_attrs, options) + +if __name__ == '__main__': + main() -- 1.9.1

1 0

[U-Boot] [PATCH] spl: Correct address in spl_relocate_stack_gd()
by Simon Glass 14 May '15

14 May '15

During the Kconfig conversion one of the changes was missed. CONFIG_SPL_STACK_R should be CONFIG_SPL_STACK_R_ADDR since we want the address. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- common/spl/spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/spl/spl.c b/common/spl/spl.c index 690c9b0..aeb0645 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -328,7 +328,7 @@ ulong spl_relocate_stack_gd(void) ulong ptr; /* Get stack position: use 8-byte alignment for ABI compliance */ - ptr = CONFIG_SPL_STACK_R - sizeof(gd_t); + ptr = CONFIG_SPL_STACK_R_ADDR - sizeof(gd_t); ptr &= ~7; new_gd = (gd_t *)ptr; memcpy(new_gd, (void *)gd, sizeof(gd_t)); -- 2.2.0.rc0.207.ga3a616c

2 1

[U-Boot] Uboot 2011-12 watchdog enable build failed
by deepak kumar Pradhan 14 May '15

14 May '15

Hi, Pardon me if I am sending this mail to wrong community. I am new to uboot loader and trying to enable watchdog in uboot for freescale P1020RDB_PC cpu for NAND. I enabled the CONFIG_WATCHDOG flag in "include/configs/p1_p2_rdb_pc. h" file. When I building the uboot source code i am getting the bellow errors as "uboot-custom/nand_spl/board/freescale/p1_p2_rdb_pc/cache.c:39: undefined reference to `watchdog_reset' 'uboot-custom/nand_spl/board/freescale/p1_p2_rdb_pc/cache.c:47: undefined reference to `watchdog_reset'' " Can someone point me what I am missing for nand uboot? When I am building the same source code for SPI, I am able to build successfully. Can you please suggest me or point me what steps do I need to follow to enable watchdog in Uboot? Thanks in advance. Regards, Deepak Kumar Pradhan

1 0

[U-Boot] [PATCH] net: phy: Add support for all targets which requires MANUAL_RELOC
by Michal Simek 14 May '15

14 May '15

Targets with CONFIG_NEEDS_MANUAL_RELOC do not use REL/RELA relocation (mostly only GOT) where functions aray are not updated. This patch is fixing function pointers passed to phy_register function. This patch was tested on Microblaze architecture. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/net/phy/phy.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index f5221a3833fe..c8d08e8f4f1c 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -21,6 +21,8 @@ #include <linux/err.h> #include <linux/compiler.h> +DECLARE_GLOBAL_DATA_PTR; + /* Generic PHY support and helper functions */ /** @@ -494,6 +496,20 @@ int phy_register(struct phy_driver *drv) INIT_LIST_HEAD(&drv->list); list_add_tail(&drv->list, &phy_drivers); +#ifdef CONFIG_NEEDS_MANUAL_RELOC + if (drv->probe) + drv->probe += gd->reloc_off; + if (drv->config) + drv->config += gd->reloc_off; + if (drv->startup) + drv->startup += gd->reloc_off; + if (drv->shutdown) + drv->shutdown += gd->reloc_off; + if (drv->readext) + drv->readext += gd->reloc_off; + if (drv->writeext) + drv->writeext += gd->reloc_off; +#endif return 0; } -- 2.3.5

2 3

[U-Boot] [PATCH v2] armv8: caches: Added routine to set non cacheable region
by Michal Simek 14 May '15

14 May '15

Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable. Define dummy routine for mmu_set_region_dcache_behaviour() to handle incase of dcache off. Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- Changes in v2: - Fix patch subject (remove addional zzz from v1) - Remove armv8: caches: Disable dcache after flush patch from this series based on the talk with Mark Rutland (patch is not needed anymore) arch/arm/cpu/armv8/cache_v8.c | 23 +++++++++++++++++++++++ arch/arm/include/asm/system.h | 28 ++++++++++++++++++---------- 2 files changed, 41 insertions(+), 10 deletions(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index c5ec5297cd39..25a2136a3cdf 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -139,6 +139,24 @@ int dcache_status(void) return (get_sctlr() & CR_C) != 0; } +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, + enum dcache_option option) +{ + /* get the level2_table0 start address */ + u64 *page_table = (u64 *)(gd->arch.tlb_addr + 0x3000); + u64 upto, end; + + end = ALIGN(start + size, (1 << MMU_SECTION_SHIFT)) >> + MMU_SECTION_SHIFT; + start = start >> MMU_SECTION_SHIFT; + for (upto = start; upto < end; upto++) { + page_table[upto] &= ~PMD_ATTRINDX_MASK; + page_table[upto] |= PMD_ATTRINDX(option); + } + + flush_dcache_range(page_table[start], page_table[end]); + __asm_invalidate_tlb_all(); +} #else /* CONFIG_SYS_DCACHE_OFF */ void invalidate_dcache_all(void) @@ -170,6 +188,11 @@ int dcache_status(void) return 0; } +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, + enum dcache_option option) +{ +} + #endif /* CONFIG_SYS_DCACHE_OFF */ #ifndef CONFIG_SYS_ICACHE_OFF diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 2a5bed2e46b6..c88687860ec1 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -15,9 +15,15 @@ #define CR_EE (1 << 25) /* Exception (Big) Endian */ #define PGTABLE_SIZE (0x10000) +/* 2M granularity */ +#define MMU_SECTION_SHIFT 21 #ifndef __ASSEMBLY__ +enum dcache_option { + DCACHE_OFF = 0x3, +}; + #define isb() \ ({asm volatile( \ "isb" : : : "memory"); \ @@ -211,16 +217,6 @@ enum { }; /** - * Change the cache settings for a region. - * - * \param start start address of memory region to change - * \param size size of memory region to change - * \param option dcache option to select - */ -void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, - enum dcache_option option); - -/** * Register an update to the page tables, and flush the TLB * * \param start start address of update in page table @@ -241,4 +237,16 @@ phys_addr_t noncached_alloc(size_t size, size_t align); #endif /* CONFIG_ARM64 */ +#ifndef __ASSEMBLY__ +/** + * Change the cache settings for a region. + * + * \param start start address of memory region to change + * \param size size of memory region to change + * \param option dcache option to select + */ +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, + enum dcache_option option); +#endif /* __ASSEMBLY__ */ + #endif -- 2.3.5

4 5

[U-Boot] [RFC PATCH 0/8] Complex config moves
by Joe Hershberger 14 May '15

14 May '15

2 9

[U-Boot] [PATCH V3] i2c: mxc: refactor i2c driver and support dm
by Peng Fan 14 May '15

14 May '15

1. Introduce a new structure `struct mxc_i2c_bus`, this structure will used for non-DM and DM. 2. Remove `struct mxc_i2c_regs` structure, but use register offset to access registers based on `base` entry of `struct mxc_i2c_bus`. 3. Remove most `#ifdef I2C_QUIRK_REG`. Using driver_data to contain platform flags. A new flag is introduced, I2C_QUIRK_FLAG. 4. Most functions use `struct mxc_i2c_bus` as one of the parameters. Make most functions common to DM and non-DM, try to avoid duplicated code. 5. Support DM. Pinmux setting is still set by setup_i2c, but we do not need bus_i2c_init for DM. 6. struct i2c_parms and struct sram_data are removed. 7. Remove bus_i2c_read bus_i2c_write prototype in header file. The frist paramter of bus_i2c_init is modified to i2c index. Add new prototype i2c_idle_bus and force_idle_bus. Since bus_i2c_init is not good for DM I2C and pinctrl is missed, we use a weak function for i2c_idle_bus for DM part. Board file take the responsibility to implement this function, like this: " int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus) { if (i2c_bus->index == 0) force_idle_bus(i2c_pads_info0); else if (i2c_bus->index == 1) force_idle_bus(i2c_pads_info1); else xxxxxx } " Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> --- Changes v3: 1. remove bus_i2c_init for DM, introuduce a weak function i2c_idle_bus. 2. remove static return type for force_idle_bus, since we need to call it in i2c_idle_bus which may be implemented in board file. This does not hurt for non-DM. Changes v2: 1. Refactor driver, remove register access based on structure, but use 'base + offset' 2. Introduce mxc_i2c_bus structure 3. Introduce I2C_QUIRK_FLAG and remove most I2C_QUIRK_REG and use driver_data to contain the flags for different platforms 4. Avoid duplicated code between DM and non-DM part 5. The function name i2c_init_transfer is not changed. 6. Remove bus_i2c_read/write prototype from header file 7. change bus_i2c_init's first parameter to i2c index 8. Rename patch name, since refactor non-DM part. arch/arm/imx-common/i2c-mxv7.c | 7 +- arch/arm/include/asm/imx-common/mxc_i2c.h | 38 +- drivers/i2c/mxc_i2c.c | 575 ++++++++++++++++++++---------- 3 files changed, 426 insertions(+), 194 deletions(-) diff --git a/arch/arm/imx-common/i2c-mxv7.c b/arch/arm/imx-common/i2c-mxv7.c index 1a632e7..f3a5c3f 100644 --- a/arch/arm/imx-common/i2c-mxv7.c +++ b/arch/arm/imx-common/i2c-mxv7.c @@ -12,7 +12,7 @@ #include <asm/imx-common/mxc_i2c.h> #include <watchdog.h> -static int force_idle_bus(void *priv) +int force_idle_bus(void *priv) { int i; int sda, scl; @@ -99,8 +99,9 @@ int setup_i2c(unsigned i2c_index, int speed, int slave_addr, if (ret) goto err_idle; - bus_i2c_init(i2c_bases[i2c_index], speed, slave_addr, - force_idle_bus, p); +#ifndef CONFIG_DM_I2C + bus_i2c_init(i2c_index, speed, slave_addr, force_idle_bus, p); +#endif return 0; diff --git a/arch/arm/include/asm/imx-common/mxc_i2c.h b/arch/arm/include/asm/imx-common/mxc_i2c.h index af86163..355b25e 100644 --- a/arch/arm/include/asm/imx-common/mxc_i2c.h +++ b/arch/arm/include/asm/imx-common/mxc_i2c.h @@ -19,6 +19,36 @@ struct i2c_pads_info { struct i2c_pin_ctrl sda; }; +/* + * Information about i2c controller + * struct mxc_i2c_bus - information about the i2c[x] bus + * @index: i2c bus index + * @base: Address of I2C bus controller + * @driver_data: Flags for different platforms, such as I2C_QUIRK_FLAG. + * @speed: Speed of I2C bus + * @pads_info: pinctrl info for this i2c bus, will be used when pinctrl is ok. + * The following two is only to be compatible with non-DM part. + * @idle_bus_fn: function to force bus idle + * @idle_bus_data: parameter for idle_bus_fun + */ +struct mxc_i2c_bus { + /* + * board file can use this index to locate which i2c_pads_info is for + * i2c_idle_bus. When pinmux is implement, this entry can be + * discarded. Here we do not use dev->seq, because we do not want to + * export device to board file. + */ + int index; + ulong base; + ulong driver_data; + int speed; + struct i2c_pads_info *pads_info; +#ifndef CONFIG_DM_I2C + int (*idle_bus_fn)(void *p); + void *idle_bus_data; +#endif +}; + #if defined(CONFIG_MX6QDL) #define I2C_PADS(name, scl_i2c, scl_gpio, scl_gp, sda_i2c, sda_gpio, sda_gp) \ struct i2c_pads_info mx6q_##name = { \ @@ -54,10 +84,8 @@ struct i2c_pads_info { int setup_i2c(unsigned i2c_index, int speed, int slave_addr, struct i2c_pads_info *p); -void bus_i2c_init(void *base, int speed, int slave_addr, +void bus_i2c_init(int index, int speed, int slave_addr, int (*idle_bus_fn)(void *p), void *p); -int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf, - int len); -int bus_i2c_write(void *base, uchar chip, uint addr, int alen, - const uchar *buf, int len); +int force_idle_bus(void *priv); +int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus); #endif diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index fc5ee35..02483b0 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -18,29 +18,25 @@ #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> #include <asm/errno.h> +#include <asm/imx-common/mxc_i2c.h> #include <asm/io.h> #include <i2c.h> #include <watchdog.h> +#include <dm.h> +#include <fdtdec.h> DECLARE_GLOBAL_DATA_PTR; -#ifdef I2C_QUIRK_REG -struct mxc_i2c_regs { - uint8_t iadr; - uint8_t ifdr; - uint8_t i2cr; - uint8_t i2sr; - uint8_t i2dr; -}; -#else -struct mxc_i2c_regs { - uint32_t iadr; - uint32_t ifdr; - uint32_t i2cr; - uint32_t i2sr; - uint32_t i2dr; -}; -#endif +#define I2C_QUIRK_FLAG (1 << 0) + +#define IMX_I2C_REGSHIFT 2 +#define VF610_I2C_REGSHIFT 0 +/* Register index */ +#define IADR 0 +#define IFDR 1 +#define I2CR 2 +#define I2SR 3 +#define I2DR 4 #define I2CR_IIEN (1 << 6) #define I2CR_MSTA (1 << 5) @@ -104,7 +100,6 @@ static u16 i2c_clk_div[50][2] = { }; #endif - #ifndef CONFIG_SYS_MXC_I2C1_SPEED #define CONFIG_SYS_MXC_I2C1_SPEED 100000 #endif @@ -125,11 +120,10 @@ static u16 i2c_clk_div[50][2] = { #define CONFIG_SYS_MXC_I2C3_SLAVE 0 #endif - /* * Calculate and set proper clock divider */ -static uint8_t i2c_imx_get_clk(unsigned int rate) +static uint8_t i2c_imx_get_clk(struct mxc_i2c_bus *i2c_bus, unsigned int rate) { unsigned int i2c_clk_rate; unsigned int div; @@ -162,18 +156,20 @@ static uint8_t i2c_imx_get_clk(unsigned int rate) /* * Set I2C Bus speed */ -static int bus_i2c_set_bus_speed(void *base, int speed) +static int bus_i2c_set_bus_speed(struct mxc_i2c_bus *i2c_bus, int speed) { - struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base; - u8 clk_idx = i2c_imx_get_clk(speed); + ulong base = i2c_bus->base; + bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false; + u8 clk_idx = i2c_imx_get_clk(i2c_bus, speed); u8 idx = i2c_clk_div[clk_idx][1]; + int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; /* Store divider value */ - writeb(idx, &i2c_regs->ifdr); + writeb(idx, base + (IFDR << reg_shift)); /* Reset module */ - writeb(I2CR_IDIS, &i2c_regs->i2cr); - writeb(0, &i2c_regs->i2sr); + writeb(I2CR_IDIS, base + (I2CR << reg_shift)); + writeb(0, base + (I2SR << reg_shift)); return 0; } @@ -181,21 +177,26 @@ static int bus_i2c_set_bus_speed(void *base, int speed) #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8)) #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8)) -static int wait_for_sr_state(struct mxc_i2c_regs *i2c_regs, unsigned state) +static int wait_for_sr_state(struct mxc_i2c_bus *i2c_bus, unsigned state) { unsigned sr; ulong elapsed; + bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false; + int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; + ulong base = i2c_bus->base; ulong start_time = get_timer(0); for (;;) { - sr = readb(&i2c_regs->i2sr); + sr = readb(base + (I2SR << reg_shift)); if (sr & I2SR_IAL) { -#ifdef I2C_QUIRK_REG - writeb(sr | I2SR_IAL, &i2c_regs->i2sr); -#else - writeb(sr & ~I2SR_IAL, &i2c_regs->i2sr); -#endif + if (quirk) + writeb(sr | I2SR_IAL, base + + (I2SR << reg_shift)); + else + writeb(sr & ~I2SR_IAL, base + + (I2SR << reg_shift)); printf("%s: Arbitration lost sr=%x cr=%x state=%x\n", - __func__, sr, readb(&i2c_regs->i2cr), state); + __func__, sr, readb(base + (I2CR << reg_shift)), + state); return -ERESTART; } if ((sr & (state >> 8)) == (unsigned char)state) @@ -206,17 +207,21 @@ static int wait_for_sr_state(struct mxc_i2c_regs *i2c_regs, unsigned state) break; } printf("%s: failed sr=%x cr=%x state=%x\n", __func__, - sr, readb(&i2c_regs->i2cr), state); + sr, readb(base + (I2CR << reg_shift)), state); return -ETIMEDOUT; } -static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte) +static int tx_byte(struct mxc_i2c_bus *i2c_bus, u8 byte) { int ret; + int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? + VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; + ulong base = i2c_bus->base; - writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); - writeb(byte, &i2c_regs->i2dr); - ret = wait_for_sr_state(i2c_regs, ST_IIF); + writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift)); + writeb(byte, base + (I2DR << reg_shift)); + + ret = wait_for_sr_state(i2c_bus, ST_IIF); if (ret < 0) return ret; if (ret & I2SR_RX_NO_AK) @@ -225,16 +230,28 @@ static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte) } /* + * Stub implementations for outer i2c slave operations. + */ +void __i2c_force_reset_slave(void) +{ +} +void i2c_force_reset_slave(void) + __attribute__((weak, alias("__i2c_force_reset_slave"))); + +/* * Stop I2C transaction */ -static void i2c_imx_stop(struct mxc_i2c_regs *i2c_regs) +static void i2c_imx_stop(struct mxc_i2c_bus *i2c_bus) { int ret; - unsigned int temp = readb(&i2c_regs->i2cr); + int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? + VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; + ulong base = i2c_bus->base; + unsigned int temp = readb(base + (I2CR << reg_shift)); temp &= ~(I2CR_MSTA | I2CR_MTX); - writeb(temp, &i2c_regs->i2cr); - ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE); + writeb(temp, base + (I2CR << reg_shift)); + ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE); if (ret < 0) printf("%s:trigger stop failed\n", __func__); } @@ -243,66 +260,96 @@ static void i2c_imx_stop(struct mxc_i2c_regs *i2c_regs) * Send start signal, chip address and * write register address */ -static int i2c_init_transfer_(struct mxc_i2c_regs *i2c_regs, - uchar chip, uint addr, int alen) +static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip, + u32 addr, int alen) { unsigned int temp; int ret; + bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false; + ulong base = i2c_bus->base; + int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; + + /* Reset i2c slave */ + i2c_force_reset_slave(); /* Enable I2C controller */ -#ifdef I2C_QUIRK_REG - if (readb(&i2c_regs->i2cr) & I2CR_IDIS) { -#else - if (!(readb(&i2c_regs->i2cr) & I2CR_IEN)) { -#endif - writeb(I2CR_IEN, &i2c_regs->i2cr); + if (quirk) + ret = readb(base + (I2CR << reg_shift)) & I2CR_IDIS; + else + ret = !(readb(base + (I2CR << reg_shift)) & I2CR_IEN); + + if (ret) { + writeb(I2CR_IEN, base + (I2CR << reg_shift)); /* Wait for controller to be stable */ udelay(50); } - if (readb(&i2c_regs->iadr) == (chip << 1)) - writeb((chip << 1) ^ 2, &i2c_regs->iadr); - writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); - ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE); + + if (readb(base + (IADR << reg_shift)) == (chip << 1)) + writeb((chip << 1) ^ 2, base + (IADR << reg_shift)); + writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift)); + ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE); if (ret < 0) return ret; /* Start I2C transaction */ - temp = readb(&i2c_regs->i2cr); + temp = readb(base + (I2CR << reg_shift)); temp |= I2CR_MSTA; - writeb(temp, &i2c_regs->i2cr); + writeb(temp, base + (I2CR << reg_shift)); - ret = wait_for_sr_state(i2c_regs, ST_BUS_BUSY); + ret = wait_for_sr_state(i2c_bus, ST_BUS_BUSY); if (ret < 0) return ret; temp |= I2CR_MTX | I2CR_TX_NO_AK; - writeb(temp, &i2c_regs->i2cr); + writeb(temp, base + (I2CR << reg_shift)); /* write slave address */ - ret = tx_byte(i2c_regs, chip << 1); + ret = tx_byte(i2c_bus, chip << 1); if (ret < 0) return ret; while (alen--) { - ret = tx_byte(i2c_regs, (addr >> (alen * 8)) & 0xff); + ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff); if (ret < 0) return ret; } return 0; } -static int i2c_idle_bus(void *base); +#ifndef CONFIG_DM_I2C +int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus) +{ + if (i2c_bus && i2c_bus->idle_bus_fn) + return i2c_bus->idle_bus_fn(i2c_bus->idle_bus_data); + return 0; +} +#else +/* + * Since pinmux is not supported, implement a weak function here. + * You can implement your i2c_bus_idle in board file. When pinctrl + * is supported, this can be removed. + */ +int __i2c_idle_bus(struct mxc_i2c_bus *i2c_bus) +{ + return 0; +} + +int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus) + __attribute__((weak, alias("__i2c_idle_bus"))); +#endif -static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs, - uchar chip, uint addr, int alen) +static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip, + u32 addr, int alen) { int retry; int ret; + int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? + VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; for (retry = 0; retry < 3; retry++) { - ret = i2c_init_transfer_(i2c_regs, chip, addr, alen); + ret = i2c_init_transfer_(i2c_bus, chip, addr, alen); if (ret >= 0) return 0; - i2c_imx_stop(i2c_regs); + i2c_imx_stop(i2c_bus); if (ret == -ENODEV) return ret; @@ -310,54 +357,67 @@ static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs, retry); if (ret != -ERESTART) /* Disable controller */ - writeb(I2CR_IDIS, &i2c_regs->i2cr); + writeb(I2CR_IDIS, i2c_bus->base + (I2CR << reg_shift)); udelay(100); - if (i2c_idle_bus(i2c_regs) < 0) + if (i2c_idle_bus(i2c_bus) < 0) break; } - printf("%s: give up i2c_regs=%p\n", __func__, i2c_regs); + printf("%s: give up i2c_regs=0x%lx\n", __func__, i2c_bus->base); return ret; } -/* - * Read data from I2C device - */ -int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf, - int len) + +static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf, + int len) +{ + int i, ret = 0; + + debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len); + debug("write_data: "); + /* use rc for counter */ + for (i = 0; i < len; ++i) + debug(" 0x%02x", buf[i]); + debug("\n"); + + for (i = 0; i < len; i++) { + ret = tx_byte(i2c_bus, buf[i]); + if (ret < 0) { + debug("i2c_write_data(): rc=%d\n", ret); + break; + } + } + + return ret; +} + +static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf, + int len) { int ret; unsigned int temp; int i; - struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base; + int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? + VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; + ulong base = i2c_bus->base; - ret = i2c_init_transfer(i2c_regs, chip, addr, alen); - if (ret < 0) - return ret; - - temp = readb(&i2c_regs->i2cr); - temp |= I2CR_RSTA; - writeb(temp, &i2c_regs->i2cr); - - ret = tx_byte(i2c_regs, (chip << 1) | 1); - if (ret < 0) { - i2c_imx_stop(i2c_regs); - return ret; - } + debug("i2c_read_data: chip=0x%x, len=0x%x\n", chip, len); /* setup bus to read data */ - temp = readb(&i2c_regs->i2cr); + temp = readb(base + (I2CR << reg_shift)); temp &= ~(I2CR_MTX | I2CR_TX_NO_AK); if (len == 1) temp |= I2CR_TX_NO_AK; - writeb(temp, &i2c_regs->i2cr); - writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); - readb(&i2c_regs->i2dr); /* dummy read to clear ICF */ + writeb(temp, base + (I2CR << reg_shift)); + writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift)); + /* dummy read to clear ICF */ + readb(base + (I2DR << reg_shift)); /* read data */ for (i = 0; i < len; i++) { - ret = wait_for_sr_state(i2c_regs, ST_IIF); + ret = wait_for_sr_state(i2c_bus, ST_IIF); if (ret < 0) { - i2c_imx_stop(i2c_regs); + debug("i2c_read_data(): ret=%d\n", ret); + i2c_imx_stop(i2c_bus); return ret; } @@ -366,105 +426,111 @@ int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf, * controller from generating another clock cycle */ if (i == (len - 1)) { - i2c_imx_stop(i2c_regs); + i2c_imx_stop(i2c_bus); } else if (i == (len - 2)) { - temp = readb(&i2c_regs->i2cr); + temp = readb(base + (I2CR << reg_shift)); temp |= I2CR_TX_NO_AK; - writeb(temp, &i2c_regs->i2cr); + writeb(temp, base + (I2CR << reg_shift)); } - writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); - buf[i] = readb(&i2c_regs->i2dr); + writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift)); + buf[i] = readb(base + (I2DR << reg_shift)); } - i2c_imx_stop(i2c_regs); + + /* reuse ret for counter*/ + for (ret = 0; ret < len; ++ret) + debug(" 0x%02x", buf[ret]); + debug("\n"); + + i2c_imx_stop(i2c_bus); return 0; } +#ifndef CONFIG_DM_I2C /* - * Write data to I2C device + * Read data from I2C device */ -int bus_i2c_write(void *base, uchar chip, uint addr, int alen, - const uchar *buf, int len) +static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr, + int alen, u8 *buf, int len) { - int ret; - int i; - struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base; + int ret = 0; + u32 temp; + int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? + VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; + ulong base = i2c_bus->base; - ret = i2c_init_transfer(i2c_regs, chip, addr, alen); + ret = i2c_init_transfer(i2c_bus, chip, addr, alen); if (ret < 0) return ret; - for (i = 0; i < len; i++) { - ret = tx_byte(i2c_regs, buf[i]); - if (ret < 0) - break; + temp = readb(base + (I2CR << reg_shift)); + temp |= I2CR_RSTA; + writeb(temp, base + (I2CR << reg_shift)); + + ret = tx_byte(i2c_bus, (chip << 1) | 1); + if (ret < 0) { + i2c_imx_stop(i2c_bus); + return ret; } - i2c_imx_stop(i2c_regs); + + ret = i2c_read_data(i2c_bus, chip, buf, len); + + i2c_imx_stop(i2c_bus); + return ret; +} + +/* + * Write data to I2C device + */ +static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr, + int alen, const u8 *buf, int len) +{ + int ret = 0; + + ret = i2c_init_transfer(i2c_bus, chip, addr, alen); + if (ret < 0) + return ret; + + ret = i2c_write_data(i2c_bus, chip, buf, len); + + i2c_imx_stop(i2c_bus); + return ret; } -static void * const i2c_bases[] = { +static struct mxc_i2c_bus mxc_i2c_buses[] = { #if defined(CONFIG_MX25) - (void *)IMX_I2C_BASE, - (void *)IMX_I2C2_BASE, - (void *)IMX_I2C3_BASE + { 0, IMX_I2C_BASE }, + { 1, IMX_I2C2_BASE }, + { 2, IMX_I2C3_BASE }, #elif defined(CONFIG_MX27) - (void *)IMX_I2C1_BASE, - (void *)IMX_I2C2_BASE + { 0, IMX_I2C1_BASE }, + { 1, IMX_I2C2_BASE }, #elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \ defined(CONFIG_MX51) || defined(CONFIG_MX53) || \ - defined(CONFIG_MX6) || defined(CONFIG_LS102XA) - (void *)I2C1_BASE_ADDR, - (void *)I2C2_BASE_ADDR, - (void *)I2C3_BASE_ADDR -#elif defined(CONFIG_VF610) - (void *)I2C0_BASE_ADDR + defined(CONFIG_MX6) + { 0, I2C1_BASE_ADDR }, + { 1, I2C2_BASE_ADDR }, + { 2, I2C3_BASE_ADDR }, +#elif defined(CONFIG_LS102XA) + { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG }, + { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG }, + { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG }, +#elif def ined(CONFIG_VF610) + { 0, I2C0_BASE_ADDR, I2C_QUIRK_FLAG }, #elif defined(CONFIG_FSL_LSCH3) - (void *)I2C1_BASE_ADDR, - (void *)I2C2_BASE_ADDR, - (void *)I2C3_BASE_ADDR, - (void *)I2C4_BASE_ADDR + { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG }, + { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG }, + { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG }, + { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG }, #else #error "architecture not supported" #endif + { } }; -struct i2c_parms { - void *base; - void *idle_bus_data; - int (*idle_bus_fn)(void *p); -}; - -struct sram_data { - unsigned curr_i2c_bus; - struct i2c_parms i2c_data[ARRAY_SIZE(i2c_bases)]; -}; - -void *i2c_get_base(struct i2c_adapter *adap) +struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap) { - return i2c_bases[adap->hwadapnr]; -} - -static struct i2c_parms *i2c_get_parms(void *base) -{ - struct sram_data *srdata = (void *)gd->srdata; - int i = 0; - struct i2c_parms *p = srdata->i2c_data; - while (i < ARRAY_SIZE(srdata->i2c_data)) { - if (p->base == base) - return p; - p++; - i++; - } - printf("Invalid I2C base: %p\n", base); - return NULL; -} - -static int i2c_idle_bus(void *base) -{ - struct i2c_parms *p = i2c_get_parms(base); - if (p && p->idle_bus_fn) - return p->idle_bus_fn(p->idle_bus_data); - return 0; + return &mxc_i2c_buses[adap->hwadapnr]; } static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip, @@ -489,29 +555,26 @@ static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip) return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0); } -void bus_i2c_init(void *base, int speed, int unused, - int (*idle_bus_fn)(void *p), void *idle_bus_data) +void bus_i2c_init(int index, int speed, int unused, + int (*idle_bus_fn)(void *p), void *idle_bus_data) { - struct sram_data *srdata = (void *)gd->srdata; - int i = 0; - struct i2c_parms *p = srdata->i2c_data; - if (!base) + int ret; + + if (index >= ARRAY_SIZE(mxc_i2c_buses)) { + debug("Error i2c index\n"); return; - for (;;) { - if (!p->base || (p->base == base)) { - p->base = base; - if (idle_bus_fn) { - p->idle_bus_fn = idle_bus_fn; - p->idle_bus_data = idle_bus_data; - } - break; - } - p++; - i++; - if (i >= ARRAY_SIZE(srdata->i2c_data)) - return; } - bus_i2c_set_bus_speed(base, speed); + + mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn; + mxc_i2c_buses[index].idle_bus_data = idle_bus_data; + + ret = enable_i2c_clk(1, index); + if (ret < 0) { + debug("I2C-%d clk fail to enable.\n", index); + return ret + } + + bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed); } /* @@ -519,13 +582,13 @@ void bus_i2c_init(void *base, int speed, int unused, */ static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) { - bus_i2c_init(i2c_get_base(adap), speed, slaveaddr, NULL, NULL); + bus_i2c_init(adap->hwadapnr, speed, slaveaddr, NULL, NULL); } /* * Set I2C Speed */ -static uint mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) +static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) { return bus_i2c_set_bus_speed(i2c_get_base(adap), speed); } @@ -552,3 +615,143 @@ U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe, CONFIG_SYS_MXC_I2C3_SPEED, CONFIG_SYS_MXC_I2C3_SLAVE, 2) #endif + +#else + +static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) +{ + struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus); + + return bus_i2c_set_bus_speed(i2c_bus, speed); +} + +static int mxc_i2c_probe(struct udevice *bus) +{ + struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus); + fdt_addr_t addr; + int ret; + + i2c_bus->driver_data = dev_get_driver_data(bus); + + addr = dev_get_addr(bus); + if (addr == FDT_ADDR_T_NONE) + return -ENODEV; + + i2c_bus->base = addr; + i2c_bus->index = bus->seq; + + /* Enable clk */ + ret = enable_i2c_clk(1, bus->seq); + if (ret < 0) + return ret; + + ret = i2c_idle_bus(i2c_bus); + if (ret < 0) { + /* Disable clk */ + enable_i2c_clk(0, bus->seq); + return ret; + } + + /* + * Pinmux settings are in board file now, until pinmux is supported, + * we can set pinmux here in probe function. + */ + + debug("i2c : controller bus %d at %lu , speed %d: ", + bus->seq, i2c_bus->base, + i2c_bus->speed); + + return 0; +} + +static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr, + u32 chip_flags) +{ + int ret; + struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus); + + ret = i2c_init_transfer(i2c_bus, chip_addr, 0, 0); + if (ret < 0) { + debug("%s failed, ret = %d\n", __func__, ret); + return ret; + } + + i2c_imx_stop(i2c_bus); + + return 0; +} + +static int mxc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) +{ + struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus); + int ret = 0; + ulong base = i2c_bus->base; + int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? + VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; + + /* + * Here the 3rd parameter addr and the 4th one alen are set to 0, + * because here we only want to send out chip address. The register + * address is wrapped in msg. + */ + ret = i2c_init_transfer(i2c_bus, msg->addr, 0, 0); + if (ret < 0) { + debug("i2c_init_transfer error: %d\n", ret); + return ret; + } + + for (; nmsgs > 0; nmsgs--, msg++) { + bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD); + debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); + if (msg->flags & I2C_M_RD) + ret = i2c_read_data(i2c_bus, msg->addr, msg->buf, + msg->len); + else { + ret = i2c_write_data(i2c_bus, msg->addr, msg->buf, + msg->len); + if (ret) + break; + if (next_is_read) { + /* Reuse ret */ + ret = readb(base + (I2CR << reg_shift)); + ret |= I2CR_RSTA; + writeb(ret, base + (I2CR << reg_shift)); + + ret = tx_byte(i2c_bus, (msg->addr << 1) | 1); + if (ret < 0) { + i2c_imx_stop(i2c_bus); + break; + } + } + } + } + + if (ret) + debug("i2c_write: error sending\n"); + + i2c_imx_stop(i2c_bus); + + return ret; +} + +static const struct dm_i2c_ops mxc_i2c_ops = { + .xfer = mxc_i2c_xfer, + .probe_chip = mxc_i2c_probe_chip, + .set_bus_speed = mxc_i2c_set_bus_speed, +}; + +static const struct udevice_id mxc_i2c_ids[] = { + { .compatible = "fsl,imx21-i2c", }, + { .compatible = "fsl,vf610-i2c", .data = I2C_QUIRK_FLAG, }, + {} +}; + +U_BOOT_DRIVER(i2c_mxc) = { + .name = "i2c_mxc", + .id = UCLASS_I2C, + .of_match = mxc_i2c_ids, + .probe = mxc_i2c_probe, + .priv_auto_alloc_size = sizeof(struct mxc_i2c_bus), + .ops = &mxc_i2c_ops, +}; +#endif -- 1.8.4

4 6

[U-Boot] [UBOOT PATCH] arasan: nfc: Add initial nand driver support for arasan
by Siva Durga Prasad Paladugu 14 May '15

14 May '15

Added initial nand driver support for arasan nand flash controller.This supports nand erase,nand read, nand write This uses the hardware ECC for read and write operations Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> --- drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/arasan_nfc.c | 1187 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 1188 insertions(+) create mode 100644 drivers/mtd/nand/arasan_nfc.c diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 347ea62..9080835 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -66,6 +66,7 @@ obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o obj-$(CONFIG_NAND_PLAT) += nand_plat.o obj-$(CONFIG_NAND_DOCG4) += docg4.o +obj-$(CONFIG_ARASAN_NFC) += arasan_nfc.o else # minimal SPL drivers diff --git a/drivers/mtd/nand/arasan_nfc.c b/drivers/mtd/nand/arasan_nfc.c new file mode 100644 index 0000000..3eaab8f --- /dev/null +++ b/drivers/mtd/nand/arasan_nfc.c @@ -0,0 +1,1187 @@ +/* + * Arasan NAND Flash Controller Driver + * + * Copyright (C) 2014 - 2015 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <malloc.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/nand_ecc.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sys_proto.h> +#include <nand.h> + +struct arasan_nand_info { +#ifdef CONFIG_MTD_PARTITIONS + struct mtd_partition *parts; +#endif + void __iomem *nand_base; + u32 page; +}; + +struct nand_regs { + u32 pkt_reg; + u32 memadr_reg1; + u32 memadr_reg2; + u32 cmd_reg; + u32 pgm_reg; + u32 intsts_enr; + u32 intsig_enr; + u32 intsts_reg; + u32 rdy_busy; + u32 cms_sysadr_reg; + u32 flash_sts_reg; + u32 tmg_reg; + u32 buf_dataport; + u32 ecc_reg; + u32 ecc_errcnt_reg; + u32 ecc_sprcmd_reg; + u32 errcnt_1bitreg; + u32 errcnt_2bitreg; + u32 errcnt_3bitreg; + u32 errcnt_4bitreg; + u32 dma_sysadr0_reg; + u32 dma_bufbdry_reg; + u32 cpu_rls_reg; + u32 errcnt_5bitreg; + u32 errcnt_6bitreg; + u32 errcnt_7bitreg; + u32 errcnt_8bitreg; + u32 data_if_reg; +}; +#define arasan_nand_base ((struct nand_regs *)ARASAN_NAND_BASEADDR) + +struct arasan_nand_command_format { + u8 cmd1; + u8 cmd2; + u8 addr_cycles; + u32 pgm; +}; + +#define ONDIE_ECC_FEATURE_ADDR 0x90 + +#define ARASAN_PROG_RD_MASK 0x00000001 +#define ARASAN_PROG_BLK_ERS_MASK 0x00000004 +#define ARASAN_PROG_RD_ID_MASK 0x00000040 +#define ARASAN_PROG_RD_STS_MASK 0x00000008 +#define ARASAN_PROG_PG_PROG_MASK 0x00000010 +#define ARASAN_PROG_RD_PARAM_PG_MASK 0x00000080 +#define ARASAN_PROG_RST_MASK 0x00000100 +#define ARASAN_PROG_GET_FTRS_MASK 0x00000200 +#define ARASAN_PROG_SET_FTRS_MASK 0x00000400 +#define ARASAN_PROG_CHNG_ROWADR_END_MASK 0x00400000 + +#define ARASAN_NAND_CMD_ECC_ON_MASK 0x80000000 +#define ARASAN_NAND_CMD_CMD12_MASK 0xFFFF +#define ARASAN_NAND_CMD_PG_SIZE_MASK 0x3800000 +#define ARASAN_NAND_CMD_PG_SIZE_SHIFT 23 +#define ARASAN_NAND_CMD_CMD2_SHIFT 8 +#define ARASAN_NAND_CMD_ADDR_CYCL_MASK 0x70000000 +#define ARASAN_NAND_CMD_ADDR_CYCL_SHIFT 28 + +#define ARASAN_NAND_MEM_ADDR1_PAGE_MASK 0xFFFF0000 +#define ARASAN_NAND_MEM_ADDR1_COL_MASK 0xFFFF +#define ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT 16 +#define ARASAN_NAND_MEM_ADDR2_PAGE_MASK 0xFF +#define ARASAN_NAND_MEM_ADDR2_CS_MASK 0xC0000000 +#define ARASAN_NAND_MEM_ADDR2_BCH_MASK 0xE000000 +#define ARASAN_NAND_MEM_ADDR2_BCH_SHIFT 25 + +#define ARASAN_NAND_INT_STS_ERR_EN_MASK 0x10 +#define ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK 0x08 +#define ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK 0x02 +#define ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK 0x01 +#define ARASAN_NAND_INT_STS_XFR_CMPLT_MASK 0x04 + +#define ARASAN_NAND_PKT_REG_PKT_CNT_MASK 0xFFF000 +#define ARASAN_NAND_PKT_REG_PKT_SIZE_MASK 0x7FF +#define ARASAN_NAND_PKT_REG_PKT_CNT_SHFT 12 + +#define ARASAN_NAND_ROW_ADDR_CYCL_MASK 0x0F +#define ARASAN_NAND_COL_ADDR_CYCL_MASK 0xF0 +#define ARASAN_NAND_COL_ADDR_CYCL_SHIFT 4 + +#define ARASAN_NAND_PKTSIZE_1K 1024 +#define ARASAN_NAND_PKTSIZE_512 512 + +#define ARASAN_NAND_POLL_TIMEOUT 1000000 +#define ARASAN_NAND_INVALID_ADDR_CYCL 0xFF + +struct arasan_nand_command_format *curr_cmd; + +typedef enum { + NAND_ADDR_CYCL_NONE, + NAND_ADDR_CYCL_ONE, + NAND_ADDR_CYCL_ROW, + NAND_ADDR_CYCL_COL, + NAND_ADDR_CYCL_BOTH, +} addr_cycles_t; + +static struct arasan_nand_command_format arasan_nand_commands[] = { + {NAND_CMD_READ0, NAND_CMD_READSTART, NAND_ADDR_CYCL_BOTH, + ARASAN_PROG_RD_MASK}, + {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, NAND_ADDR_CYCL_COL, + ARASAN_PROG_RD_MASK}, + {NAND_CMD_READID, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE, + ARASAN_PROG_RD_ID_MASK}, + {NAND_CMD_STATUS, NAND_CMD_NONE, NAND_ADDR_CYCL_NONE, + ARASAN_PROG_RD_STS_MASK}, + {NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, NAND_ADDR_CYCL_BOTH, + ARASAN_PROG_PG_PROG_MASK}, + {NAND_CMD_RNDIN, NAND_CMD_NONE, NAND_ADDR_CYCL_COL, + ARASAN_PROG_CHNG_ROWADR_END_MASK}, + {NAND_CMD_ERASE1, NAND_CMD_ERASE2, NAND_ADDR_CYCL_ROW, + ARASAN_PROG_BLK_ERS_MASK}, + {NAND_CMD_RESET, NAND_CMD_NONE, NAND_ADDR_CYCL_NONE, + ARASAN_PROG_RST_MASK}, + {NAND_CMD_PARAM, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE, + ARASAN_PROG_RD_PARAM_PG_MASK}, + {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE, + ARASAN_PROG_GET_FTRS_MASK}, + {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE, + ARASAN_PROG_SET_FTRS_MASK}, + {NAND_CMD_NONE, NAND_CMD_NONE, NAND_ADDR_CYCL_NONE, 0}, +}; + +struct arasan_ecc_matrix { + u32 pagesize; + u8 ecc_codeword_size; + u8 eccbits; + u8 slcmlc; + u16 eccaddr; + u16 eccsize; +}; + +static const struct arasan_ecc_matrix ecc_matrix[] = { + {512, 9, 1, 0, 0x20D, 0x3}, + {512, 9, 4, 1, 0x209, 0x7}, + {512, 9, 8, 1, 0x203, 0xD}, + /* + * 2K byte page + */ + {2048, 9, 1, 0, 0x834, 0xC}, + {2048, 9, 4, 1, 0x826, 0x1A}, + {2048, 9, 8, 1, 0x80c, 0x34}, + {2048, 9, 12, 1, 0x822, 0x4E}, + {2048, 9, 16, 1, 0x808, 0x68}, + {2048, 10, 24, 1, 0x81c, 0x54}, + /* + * 4K byte page + */ + {4096, 9, 1, 0, 0x1068, 0x18}, + {4096, 9, 4, 1, 0x104c, 0x34}, + {4096, 9, 8, 1, 0x1018, 0x68}, + {4096, 9, 12, 1, 0x1044, 0x9C}, + {4096, 9, 16, 1, 0x1010, 0xD0}, + {4096, 10, 24, 1, 0x1038, 0xA8}, + /* + * 8K byte page + */ + {8192, 9, 1, 0, 0x20d0, 0x30}, + {8192, 9, 4, 1, 0x2098, 0x68}, + {8192, 9, 8, 1, 0x2030, 0xD0}, + {8192, 9, 12, 1, 0x2088, 0x138}, + {8192, 9, 16, 1, 0x2020, 0x1A0}, + {8192, 24, 10, 1, 0x2070, 0x150}, + /* + * 16K byte page + */ + {16384, 9, 1, 0, 0x4460, 0x60}, + {16384, 9, 4, 1, 0x43f0, 0xD0}, + {16384, 9, 8, 1, 0x4320, 0x1A0}, + {16384, 9, 12, 1, 0x4250, 0x270}, + {16384, 9, 16, 1, 0x4180, 0x340}, + {16384, 10, 24, 1, 0x4220, 0x2A0} +}; + +u32 buf_data[16384]; +u32 buf_index = 0; + +static struct nand_ecclayout nand_oob; + +static void arasan_nand_select_chip(struct mtd_info *mtd, int chip) +{ +} + +static void arasan_nand_enable_ecc(void) +{ + u32 reg_val; + + reg_val = readl(&arasan_nand_base->cmd_reg); + reg_val |= ARASAN_NAND_CMD_ECC_ON_MASK; + + writel(reg_val, &arasan_nand_base->cmd_reg); +} + +static u8 arasan_nand_get_addrcycle(struct mtd_info *mtd) +{ + u8 addrcycles; + struct nand_chip *chip = mtd->priv; + + switch (curr_cmd->addr_cycles) { + case NAND_ADDR_CYCL_NONE: + addrcycles = 0; + break; + case NAND_ADDR_CYCL_ONE: + addrcycles = 1; + break; + case NAND_ADDR_CYCL_ROW: + addrcycles = chip->onfi_params.addr_cycles & + ARASAN_NAND_ROW_ADDR_CYCL_MASK; + break; + case NAND_ADDR_CYCL_COL: + addrcycles = (chip->onfi_params.addr_cycles & + ARASAN_NAND_COL_ADDR_CYCL_MASK) >> + ARASAN_NAND_COL_ADDR_CYCL_SHIFT; + break; + case NAND_ADDR_CYCL_BOTH: + addrcycles = chip->onfi_params.addr_cycles & + ARASAN_NAND_ROW_ADDR_CYCL_MASK; + addrcycles += (chip->onfi_params.addr_cycles & + ARASAN_NAND_COL_ADDR_CYCL_MASK) >> + ARASAN_NAND_COL_ADDR_CYCL_SHIFT; + break; + default: + addrcycles = ARASAN_NAND_INVALID_ADDR_CYCL; + break; + } + return addrcycles; +} + +static int arasan_nand_read_page(struct mtd_info *mtd, u8 *buf, u32 size) +{ + struct nand_chip *chip = mtd->priv; + u32 reg_val, i, pktsize, pktnum; + u32 *bufptr = (u32 *)buf; + u32 timeout = ARASAN_NAND_POLL_TIMEOUT; + u32 rdcount = 0; + u8 addr_cycles; + + if (chip->ecc_step_ds >= ARASAN_NAND_PKTSIZE_1K) + pktsize = ARASAN_NAND_PKTSIZE_1K; + else + pktsize = ARASAN_NAND_PKTSIZE_512; + + if (size%pktsize) + pktnum = size/pktsize + 1; + else + pktnum = size/pktsize; + + reg_val = readl(&arasan_nand_base->intsts_enr); + reg_val |= ARASAN_NAND_INT_STS_ERR_EN_MASK | + ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK; + writel(reg_val, &arasan_nand_base->intsts_enr); + + reg_val = readl(&arasan_nand_base->pkt_reg); + reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK | + ARASAN_NAND_PKT_REG_PKT_SIZE_MASK); + reg_val |= (pktnum << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | + pktsize; + writel(reg_val, &arasan_nand_base->pkt_reg); + + arasan_nand_enable_ecc(); + addr_cycles = arasan_nand_get_addrcycle(mtd); + writel((NAND_CMD_RNDOUTSTART << 8) | NAND_CMD_RNDOUT | + (addr_cycles << 28), &arasan_nand_base->ecc_sprcmd_reg); + writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg); + + while (rdcount < pktnum) { + timeout = ARASAN_NAND_POLL_TIMEOUT; + while (!(readl(&arasan_nand_base->intsts_reg) & + ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK) && timeout) { + timeout--; + } + if (!timeout) { + puts("arasan_read_page: timedout:Buff RDY\n"); + return -1; + } + + rdcount++; + + if (pktnum == rdcount) { + reg_val = readl(&arasan_nand_base->intsts_enr); + reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK; + writel(reg_val, &arasan_nand_base->intsts_enr); + } else { + reg_val = readl(&arasan_nand_base->intsts_enr); + writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK, + &arasan_nand_base->intsts_enr); + } + reg_val = readl(&arasan_nand_base->intsts_reg); + writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK, + &arasan_nand_base->intsts_reg); + + for (i = 0; i < pktsize/4; i++) + bufptr[i] = readl(&arasan_nand_base->buf_dataport); + + + bufptr += pktsize/4; + + if (rdcount >= pktnum) + break; + + writel(ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK, + &arasan_nand_base->intsts_enr); + } + + timeout = ARASAN_NAND_POLL_TIMEOUT; + + while (!(readl(&arasan_nand_base->intsts_reg) & + ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { + timeout--; + } + if (!timeout) { + puts("arasan rd_page timedout:Xfer CMPLT\n"); + return -1; + } + + reg_val = readl(&arasan_nand_base->intsts_enr); + writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_enr); + reg_val = readl(&arasan_nand_base->intsts_reg); + writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_reg); + + if (readl(&arasan_nand_base->intsts_reg) & + ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK) { + printf("arasan rd_page:sbiterror\n"); + return -1; + } + + if (readl(&arasan_nand_base->intsts_reg) & + ARASAN_NAND_INT_STS_ERR_EN_MASK) { + mtd->ecc_stats.failed++; + printf("arasan rd_page:multibiterror\n"); + return -1; + } + + return 0; +} + +static int arasan_nand_read_page_hwecc(struct mtd_info *mtd, + struct nand_chip *chip, u8 *buf, int oob_required, int page) +{ + int status; + + status = arasan_nand_read_page(mtd, buf, (mtd->writesize)); + + if (oob_required) + chip->ecc.read_oob(mtd, chip, page); + + return status; +} + +static void arasan_nand_fill_tx(const u8 *buf, int len) +{ + u32 *nand = &arasan_nand_base->buf_dataport; + + if (((unsigned long)buf & 0x3) != 0) { + if (((unsigned long)buf & 0x1) != 0) { + if (len) { + writeb(*buf, nand); + buf += 1; + len--; + } + } + + if (((unsigned long)buf & 0x3) != 0) { + if (len >= 2) { + writew(*(u16 *)buf, nand); + buf += 2; + len -= 2; + } + } + } + + while (len >= 4) { + writel(*(u32 *)buf, nand); + buf += 4; + len -= 4; + } + + if (len) { + if (len >= 2) { + writew(*(u16 *)buf, nand); + buf += 2; + len -= 2; + } + + if (len) + writeb(*buf, nand); + } +} + +static int arasan_nand_write_page_hwecc(struct mtd_info *mtd, + struct nand_chip *chip, const u8 *buf, int oob_required) +{ + u32 reg_val, i, pktsize, pktnum; + u32 *bufptr = (u32 *)buf; + u32 timeout = ARASAN_NAND_POLL_TIMEOUT; + u32 size = mtd->writesize; + u32 rdcount = 0; + u8 column_addr_cycles; + struct arasan_nand_info *xnand = chip->priv; + + if (chip->ecc_step_ds >= ARASAN_NAND_PKTSIZE_1K) + pktsize = ARASAN_NAND_PKTSIZE_1K; + else + pktsize = ARASAN_NAND_PKTSIZE_512; + + if (size % pktsize) + pktnum = size/pktsize + 1; + else + pktnum = size/pktsize; + + reg_val = readl(&arasan_nand_base->pkt_reg); + reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK | + ARASAN_NAND_PKT_REG_PKT_SIZE_MASK); + reg_val |= (pktnum << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | pktsize; + writel(reg_val, &arasan_nand_base->pkt_reg); + + arasan_nand_enable_ecc(); + column_addr_cycles = (chip->onfi_params.addr_cycles & + ARASAN_NAND_COL_ADDR_CYCL_MASK) >> + ARASAN_NAND_COL_ADDR_CYCL_SHIFT; + writel((NAND_CMD_RNDIN | (column_addr_cycles << 28)), + &arasan_nand_base->ecc_sprcmd_reg); + writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg); + + while (rdcount < pktnum) { + timeout = ARASAN_NAND_POLL_TIMEOUT; + while (!(readl(&arasan_nand_base->intsts_reg) & + ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK) && timeout) { + timeout--; + } + + if (!timeout) { + puts("arasan_write_page: timedout:Buff RDY\n"); + return -1; + } + + rdcount++; + + if (pktnum == rdcount) { + reg_val = readl(&arasan_nand_base->intsts_enr); + reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK; + writel(reg_val, &arasan_nand_base->intsts_enr); + } else { + reg_val = readl(&arasan_nand_base->intsts_enr); + writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK, + &arasan_nand_base->intsts_enr); + } + + reg_val = readl(&arasan_nand_base->intsts_reg); + writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK, + &arasan_nand_base->intsts_reg); + + for (i = 0; i < pktsize/4; i++) + writel(bufptr[i], &arasan_nand_base->buf_dataport); + + bufptr += pktsize/4; + + if (rdcount >= pktnum) + break; + + writel(ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK, + &arasan_nand_base->intsts_enr); + } + + timeout = ARASAN_NAND_POLL_TIMEOUT; + + while (!(readl(&arasan_nand_base->intsts_reg) & + ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { + timeout--; + } + if (!timeout) { + puts("arasan write_page timedout:Xfer CMPLT\n"); + return -1; + } + + reg_val = readl(&arasan_nand_base->intsts_enr); + writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_enr); + reg_val = readl(&arasan_nand_base->intsts_reg); + writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK , + &arasan_nand_base->intsts_reg); + + if (oob_required) + chip->ecc.write_oob(mtd, chip, xnand->page); + + return 0; +} + +static int arasan_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); + chip->read_buf(mtd, chip->oob_poi, (mtd->oobsize)); + + return 0; +} + +static int arasan_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + int status = 0; + const u8 *buf = chip->oob_poi; + + chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); + chip->write_buf(mtd, buf, (mtd->oobsize)); + + return status; +} + +static void arasan_nand_reset(struct arasan_nand_command_format *curr_cmd) +{ + u32 timeout = ARASAN_NAND_POLL_TIMEOUT; + u32 cmd_reg = 0; + + writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_enr); + cmd_reg = readl(&arasan_nand_base->cmd_reg); + cmd_reg &= ~ARASAN_NAND_CMD_CMD12_MASK; + + cmd_reg |= curr_cmd->cmd1 | + (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT); + writel(cmd_reg, &arasan_nand_base->cmd_reg); + writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg); + + while (!(readl(&arasan_nand_base->intsts_reg) & + ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { + timeout--; + } + if (!timeout) + puts("ERROR:arasan_nand_reset timedout\n"); + + writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_enr); + + writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_reg); +} + +static u8 arasan_nand_page(struct mtd_info *mtd) +{ + u8 page_val = 0; + + switch (mtd->writesize) { + case 512: + page_val = 0; + break; + case 2048: + page_val = 1; + break; + case 4096: + page_val = 2; + break; + case 8192: + page_val = 3; + break; + case 16384: + page_val = 4; + break; + case 1024: + page_val = 5; + break; + default: + break; + } + + return page_val; +} + +static void arasan_nand_send_wrcmd(struct arasan_nand_command_format *curr_cmd, + int column, int page_addr, struct mtd_info *mtd) +{ + u32 reg_val, page; + u8 page_val, addr_cycles; + + writel(ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK, + &arasan_nand_base->intsts_enr); + reg_val = readl(&arasan_nand_base->cmd_reg); + reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK; + reg_val |= curr_cmd->cmd1 | + (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT); + if (curr_cmd->cmd1 == NAND_CMD_SEQIN) { + reg_val &= ~ARASAN_NAND_CMD_PG_SIZE_MASK; + page_val = arasan_nand_page(mtd); + reg_val |= (page_val << ARASAN_NAND_CMD_PG_SIZE_SHIFT); + } + + reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK; + addr_cycles = arasan_nand_get_addrcycle(mtd); + reg_val |= (addr_cycles << + ARASAN_NAND_CMD_ADDR_CYCL_SHIFT); + writel(reg_val, &arasan_nand_base->cmd_reg); + + if (page_addr == -1) + page_addr = 0; + + page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) & + ARASAN_NAND_MEM_ADDR1_PAGE_MASK; + column &= ARASAN_NAND_MEM_ADDR1_COL_MASK; + writel(page|column, &arasan_nand_base->memadr_reg1); + + reg_val = readl(&arasan_nand_base->memadr_reg2); + reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK; + reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT); + writel(reg_val, &arasan_nand_base->memadr_reg2); + reg_val = readl(&arasan_nand_base->memadr_reg2); + reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK; + writel(reg_val, &arasan_nand_base->memadr_reg2); +} + +static void arasan_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) +{ + u32 reg_val; + u32 timeout = ARASAN_NAND_POLL_TIMEOUT; + + reg_val = readl(&arasan_nand_base->pkt_reg); + reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK | + ARASAN_NAND_PKT_REG_PKT_SIZE_MASK); + + reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | len; + writel(reg_val, &arasan_nand_base->pkt_reg); + writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg); + + while (!(readl(&arasan_nand_base->intsts_reg) & + ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK) && timeout) { + timeout--; + } + + if (!timeout) + puts("ERROR:arasan_nand_write_buf timedout:Buff RDY\n"); + + reg_val = readl(&arasan_nand_base->intsts_enr); + reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK; + writel(reg_val, &arasan_nand_base->intsts_enr); + writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK, + &arasan_nand_base->intsts_enr); + reg_val = readl(&arasan_nand_base->intsts_reg); + writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK, + &arasan_nand_base->intsts_reg); + + arasan_nand_fill_tx(buf, len); + + timeout = ARASAN_NAND_POLL_TIMEOUT; + while (!(readl(&arasan_nand_base->intsts_reg) & + ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { + timeout--; + } + if (!timeout) + puts("ERROR:arasan_nand_write_buf timedout:Xfer CMPLT\n"); + + writel(readl(&arasan_nand_base->intsts_enr) | + ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_enr); + writel(readl(&arasan_nand_base->intsts_reg) | + ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_reg); +} + +static void arasan_nand_erase(struct arasan_nand_command_format *curr_cmd, + int column, int page_addr, struct mtd_info *mtd) +{ + u32 reg_val, page; + u32 timeout = ARASAN_NAND_POLL_TIMEOUT; + u8 row_addr_cycles; + + writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_enr); + reg_val = readl(&arasan_nand_base->cmd_reg); + reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK; + reg_val |= curr_cmd->cmd1 | + (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT); + row_addr_cycles = arasan_nand_get_addrcycle(mtd); + reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK; + reg_val |= (row_addr_cycles << + ARASAN_NAND_CMD_ADDR_CYCL_SHIFT); + + writel(reg_val, &arasan_nand_base->cmd_reg); + + page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) & + ARASAN_NAND_MEM_ADDR1_PAGE_MASK; + column = page_addr & ARASAN_NAND_MEM_ADDR1_COL_MASK; + writel(page | column, &arasan_nand_base->memadr_reg1); + + reg_val = readl(&arasan_nand_base->memadr_reg2); + reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK; + reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT); + writel(reg_val, &arasan_nand_base->memadr_reg2); + reg_val = readl(&arasan_nand_base->memadr_reg2); + reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK; + writel(reg_val, &arasan_nand_base->memadr_reg2); + writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg); + + while (!(readl(&arasan_nand_base->intsts_reg) & + ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { + timeout--; + } + if (!timeout) + puts("ERROR:arasan_nand_erase timedout:Xfer CMPLT\n"); + + reg_val = readl(&arasan_nand_base->intsts_enr); + writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_enr); + reg_val = readl(&arasan_nand_base->intsts_reg); + writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_reg); +} + +static void arasan_nand_read_status(struct arasan_nand_command_format *curr_cmd, + int column, int page_addr, struct mtd_info *mtd) +{ + u32 reg_val; + u32 timeout = ARASAN_NAND_POLL_TIMEOUT; + u8 addr_cycles; + + writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_enr); + reg_val = readl(&arasan_nand_base->cmd_reg); + reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK; + reg_val |= curr_cmd->cmd1 | + (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT); + addr_cycles = arasan_nand_get_addrcycle(mtd); + reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK; + reg_val |= (addr_cycles << + ARASAN_NAND_CMD_ADDR_CYCL_SHIFT); + + writel(reg_val, &arasan_nand_base->cmd_reg); + + reg_val = readl(&arasan_nand_base->pkt_reg); + reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK | + ARASAN_NAND_PKT_REG_PKT_SIZE_MASK); + reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | 1; + writel(reg_val, &arasan_nand_base->pkt_reg); + + reg_val = readl(&arasan_nand_base->memadr_reg2); + reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK; + writel(reg_val, &arasan_nand_base->memadr_reg2); + + writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg); + while (!(readl(&arasan_nand_base->intsts_reg) & + ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { + timeout--; + } + + if (!timeout) + puts("ERROR:arasan_nand_read_status timedout:Xfer CMPLT\n"); + + reg_val = readl(&arasan_nand_base->intsts_enr); + writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_enr); + reg_val = readl(&arasan_nand_base->intsts_reg); + writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_reg); +} + +static void arasan_nand_send_rdcmd(struct arasan_nand_command_format *curr_cmd, + int column, int page_addr, struct mtd_info *mtd) +{ + u32 reg_val, addr_cycles, page; + u8 page_val; + + reg_val = readl(&arasan_nand_base->intsts_enr); + writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK, + &arasan_nand_base->intsts_enr); + + reg_val = readl(&arasan_nand_base->cmd_reg); + reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK; + reg_val |= curr_cmd->cmd1 | + (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT); + + if (curr_cmd->cmd1 == NAND_CMD_RNDOUT || + curr_cmd->cmd1 == NAND_CMD_READ0) { + reg_val &= ~ARASAN_NAND_CMD_PG_SIZE_MASK; + page_val = arasan_nand_page(mtd); + reg_val |= (page_val << ARASAN_NAND_CMD_PG_SIZE_SHIFT); + } + + reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK; + + addr_cycles = arasan_nand_get_addrcycle(mtd); + reg_val |= (addr_cycles << 28); + writel(reg_val, &arasan_nand_base->cmd_reg); + + if (page_addr == -1) + page_addr = 0; + + page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) & + ARASAN_NAND_MEM_ADDR1_PAGE_MASK; + column &= ARASAN_NAND_MEM_ADDR1_COL_MASK; + writel(page | column, &arasan_nand_base->memadr_reg1); + + reg_val = readl(&arasan_nand_base->memadr_reg2); + reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK; + reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT); + writel(reg_val, &arasan_nand_base->memadr_reg2); + + reg_val = readl(&arasan_nand_base->memadr_reg2); + reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK; + writel(reg_val, &arasan_nand_base->memadr_reg2); + buf_index = 0; +} + +static u8 arasan_read_byte(void) +{ + u8 *bufptr = (u8 *)&buf_data[0]; + u8 val; + + val = *(bufptr + buf_index); + buf_index++; + + return val; +} + +static void arasan_nand_read_buf(struct mtd_info *mtd, u8 *buf, int size) +{ + u32 reg_val, i; + u32 *bufptr = (u32 *)buf; + u32 timeout = ARASAN_NAND_POLL_TIMEOUT; + + reg_val = readl(&arasan_nand_base->pkt_reg); + reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK | + ARASAN_NAND_PKT_REG_PKT_SIZE_MASK); + reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | size; + writel(reg_val, &arasan_nand_base->pkt_reg); + + writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg); + + while (!(readl(&arasan_nand_base->intsts_reg) & + ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK) && timeout) { + timeout--; + } + + if (!timeout) + puts("ERROR:arasan_nand_read_buf timedout:Buff RDY\n"); + + reg_val = readl(&arasan_nand_base->intsts_enr); + reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK; + writel(reg_val, &arasan_nand_base->intsts_enr); + + writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK, + &arasan_nand_base->intsts_enr); + reg_val = readl(&arasan_nand_base->intsts_reg); + writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK, + &arasan_nand_base->intsts_reg); + + buf_index = 0; + for (i = 0; i < size / 4; i++) + bufptr[i] = readl(&arasan_nand_base->buf_dataport); + + if (size & 0x03) + bufptr[i] = readl(&arasan_nand_base->buf_dataport); + + timeout = ARASAN_NAND_POLL_TIMEOUT; + + while (!(readl(&arasan_nand_base->intsts_reg) & + ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { + timeout--; + } + + if (!timeout) + puts("ERROR:arasan_nand_read_buf timedout:Xfer CMPLT\n"); + + reg_val = readl(&arasan_nand_base->intsts_enr); + writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_enr); + reg_val = readl(&arasan_nand_base->intsts_reg); + writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_reg); +} + +static u8 arasan_nand_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + u32 size; + struct nand_onfi_params *p; + + if (buf_index == 0) { + p = &chip->onfi_params; + if (curr_cmd->cmd1 == NAND_CMD_READID) + size = 4; + else if (curr_cmd->cmd1 == NAND_CMD_PARAM) + size = sizeof(struct nand_onfi_params); + else if (curr_cmd->cmd1 == NAND_CMD_RNDOUT) + size = le16_to_cpu(p->ext_param_page_length) * 16; + else if (curr_cmd->cmd1 == NAND_CMD_GET_FEATURES) + size = 4; + else if (curr_cmd->cmd1 == NAND_CMD_STATUS) + return readb(&arasan_nand_base->flash_sts_reg); + else + size = 8; + chip->read_buf(mtd, (u8 *)&buf_data[0], size); + } + + return arasan_read_byte(); +} + +static void arasan_nand_cmd_function(struct mtd_info *mtd, unsigned int command, + int column, int page_addr) +{ + u32 i; + struct nand_chip *chip = mtd->priv; + struct arasan_nand_info *xnand = chip->priv; + + curr_cmd = NULL; + writel(0x4, &arasan_nand_base->intsts_enr); + + if ((command == NAND_CMD_READOOB) && + (mtd->writesize > 512)) { + column += mtd->writesize; + command = NAND_CMD_READ0; + } + + /* Get the command format */ + for (i = 0; (arasan_nand_commands[i].cmd1 != NAND_CMD_NONE || + arasan_nand_commands[i].cmd2 != NAND_CMD_NONE); i++) { + if (command == arasan_nand_commands[i].cmd1) { + curr_cmd = &arasan_nand_commands[i]; + break; + } + } + + if (curr_cmd == NULL) { + printf("Unsupported Command; 0x%x\n", command); + return; + } + + if (curr_cmd->cmd1 == NAND_CMD_RESET) + arasan_nand_reset(curr_cmd); + + if ((curr_cmd->cmd1 == NAND_CMD_READID) || + (curr_cmd->cmd1 == NAND_CMD_PARAM) || + (curr_cmd->cmd1 == NAND_CMD_RNDOUT) || + (curr_cmd->cmd1 == NAND_CMD_GET_FEATURES) || + (curr_cmd->cmd1 == NAND_CMD_READ0)) + arasan_nand_send_rdcmd(curr_cmd, column, page_addr, mtd); + + if ((curr_cmd->cmd1 == NAND_CMD_SET_FEATURES) || + (curr_cmd->cmd1 == NAND_CMD_SEQIN)) { + xnand->page = page_addr; + arasan_nand_send_wrcmd(curr_cmd, column, page_addr, mtd); + } + + if (curr_cmd->cmd1 == NAND_CMD_ERASE1) + arasan_nand_erase(curr_cmd, column, page_addr, mtd); + + if (curr_cmd->cmd1 == NAND_CMD_STATUS) + arasan_nand_read_status(curr_cmd, column, page_addr, mtd); +} + +static void arasan_nand_ecc_init(struct mtd_info *mtd) +{ + u32 found = 0; + u8 bchmodeval = 0; + u32 regval, eccpos_start, i; + struct nand_chip *nand_chip = mtd->priv; + + for (i = 0; i < sizeof(ecc_matrix)/sizeof(struct arasan_ecc_matrix); + i++) { + if ((ecc_matrix[i].pagesize == mtd->writesize) && + ((1 << ecc_matrix[i].ecc_codeword_size) >= + nand_chip->ecc_step_ds)) { + if (ecc_matrix[i].eccbits >= + nand_chip->ecc_strength_ds) { + found = i; + break; + } else { + found = i; + } + } + } + + if (found) { + regval = ecc_matrix[i].eccaddr | (ecc_matrix[i].eccsize << 16) | + (ecc_matrix[i].slcmlc << 27); + writel(regval, &arasan_nand_base->ecc_reg); + + if (ecc_matrix[i].slcmlc) { + switch (ecc_matrix[i].eccbits) { + case 16: + bchmodeval = 0x0; + break; + case 12: + bchmodeval = 0x1; + break; + case 8: + bchmodeval = 0x2; + break; + case 4: + bchmodeval = 0x3; + break; + case 24: + bchmodeval = 0x4; + break; + default: + bchmodeval = 0x0; + } + regval = readl(&arasan_nand_base->memadr_reg2); + regval &= ~ARASAN_NAND_MEM_ADDR2_BCH_MASK; + regval |= (bchmodeval << + ARASAN_NAND_MEM_ADDR2_BCH_SHIFT); + writel(regval, &arasan_nand_base->memadr_reg2); + } + + nand_oob.eccbytes = ecc_matrix[i].eccsize; + eccpos_start = mtd->oobsize - nand_oob.eccbytes; + + for (i = 0; i < nand_oob.eccbytes; i++) + nand_oob.eccpos[i] = eccpos_start + i; + + nand_oob.oobfree[0].offset = 2; + nand_oob.oobfree[0].length = eccpos_start - 2; + + if (ecc_matrix[i].eccbits == 24) + nand_chip->ecc.size = 1024; + else + nand_chip->ecc.size = 512; + + nand_chip->ecc.bytes = ecc_matrix[i].eccsize; + nand_chip->ecc.layout = &nand_oob; + } +} + +static int arasan_nand_init(struct nand_chip *nand_chip, int devnum) +{ + struct arasan_nand_info *xnand; + struct mtd_info *mtd; + u8 maf_id, dev_id; + int err = -1; + u8 get_feature[4]; + u8 set_feature[4] = {0x08, 0x00, 0x00, 0x00}; + int ondie_ecc_enabled = 0; + u32 timeout = ARASAN_NAND_POLL_TIMEOUT; + u32 i; + + xnand = calloc(1, sizeof(struct arasan_nand_info)); + if (!xnand) { + printf("%s: failed to allocate\n", __func__); + return -1; + } + + xnand->nand_base = (void *)ARASAN_NAND_BASEADDR; + mtd = &nand_info[0]; + nand_chip->priv = xnand; + mtd->priv = nand_chip; + + /* Set address of NAND IO lines */ + nand_chip->IO_ADDR_R = (void *)&arasan_nand_base->buf_dataport; + nand_chip->IO_ADDR_W = (void *)&arasan_nand_base->buf_dataport; + + /* Set the driver entry points for MTD */ + nand_chip->cmdfunc = arasan_nand_cmd_function; + nand_chip->select_chip = arasan_nand_select_chip; + nand_chip->read_byte = arasan_nand_read_byte; + + /* Buffer read/write routines */ + nand_chip->read_buf = arasan_nand_read_buf; + nand_chip->write_buf = arasan_nand_write_buf; + nand_chip->bbt_options = NAND_BBT_USE_FLASH; + + writel(0x0, &arasan_nand_base->cmd_reg); + writel(0x0, &arasan_nand_base->pgm_reg); + + /* first scan to find the device and get the page size */ + if (nand_scan_ident(mtd, 1, NULL)) { + printf("%s: nand_scan_ident failed\n", __func__); + goto fail; + } + + mtd->size = nand_chip->chipsize; + + /* Send the command for reading device ID */ + nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); + nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); + + /* Read manufacturer and device IDs */ + maf_id = nand_chip->read_byte(mtd); + dev_id = nand_chip->read_byte(mtd); + + if ((maf_id == 0x2c) && ((dev_id == 0xf1) || + (dev_id == 0xa1) || (dev_id == 0xb1) || + (dev_id == 0xaa) || (dev_id == 0xba) || + (dev_id == 0xda) || (dev_id == 0xca) || + (dev_id == 0xac) || (dev_id == 0xbc) || + (dev_id == 0xdc) || (dev_id == 0xcc) || + (dev_id == 0xa3) || (dev_id == 0xb3) || + (dev_id == 0xd3) || (dev_id == 0xc3))) { + nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, + ONDIE_ECC_FEATURE_ADDR, -1); + + for (i = 0; i < 4; i++) + writeb(set_feature[i], nand_chip->IO_ADDR_W); + + while (!(readl(&arasan_nand_base->intsts_reg) & + ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { + timeout--; + } + + if (!timeout) { + puts("ERROR:arasan_nand_init timedout:Xfer CMPLT\n"); + goto fail; + } + + writel(readl(&arasan_nand_base->intsts_enr) | + ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_enr); + writel(readl(&arasan_nand_base->intsts_reg) | + ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, + &arasan_nand_base->intsts_reg); + + nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, + ONDIE_ECC_FEATURE_ADDR, -1); + + for (i = 0; i < 4; i++) + get_feature[i] = nand_chip->read_byte(mtd); + + if (get_feature[0] & 0x08) { + debug("%s: OnDie ECC flash\n", __func__); + ondie_ecc_enabled = 1; + } else { + printf("%s: Unable to detect OnDie ECC\n", __func__); + } + } + + if (!ondie_ecc_enabled) { + nand_chip->ecc.mode = NAND_ECC_HW; + nand_chip->ecc.strength = 1; + nand_chip->ecc.hwctl = NULL; + nand_chip->ecc.read_page = arasan_nand_read_page_hwecc; + nand_chip->ecc.write_page = arasan_nand_write_page_hwecc; + nand_chip->ecc.read_oob = arasan_nand_read_oob; + nand_chip->ecc.write_oob = arasan_nand_write_oob; + } + + arasan_nand_ecc_init(mtd); + + if (nand_scan_tail(mtd)) { + printf("%s: nand_scan_tailfailed\n", __func__); + goto fail; + } + if (nand_register(devnum)) { + printf("Nand Register Fail\n"); + goto fail; + } + + return 0; +fail: + kfree(xnand); + return err; +} +static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; + +void board_nand_init(void) +{ + struct nand_chip *nand = &nand_chip[0]; + + if (arasan_nand_init(nand, 0)) + puts("NAND init failed\n"); +} -- 2.1.1

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