May 2015 - U-Boot

[U-Boot] [PATCH v2 0/4]: imx: mx6: use OTP for temperature grade info
by Tim Harvey 18 May '15

18 May '15

This is a second take on my last series to obtain and use CPU temperature grade in print_cpuinfo(). Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> -- v2: - split into two series: 1 for CPU frequency, other for Temperature grade Tim Harvey (4): mx6: add OTP bank1 registers imx: mx6: add get_cpu_temp_grade to obtain cpu temperature grade from OTP imx: mx6: add display of CPU temperature grade in print_cpuinfo() thermal: imx_thermal: use CPU temperature grade for trip points arch/arm/cpu/armv7/mx6/soc.c | 38 +++++++++++++++++++++++++++++++ arch/arm/imx-common/cpu.c | 27 ++++++++++++++++++---- arch/arm/include/asm/arch-mx6/imx-regs.h | 19 ++++++++++++++++ arch/arm/include/asm/arch-mx6/sys_proto.h | 1 + drivers/thermal/imx_thermal.c | 29 +++++++++++++++-------- include/imx_thermal.h | 6 +++++ 6 files changed, 106 insertions(+), 14 deletions(-) -- 1.9.1

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[U-Boot] [PATCH] arc: gitignore: ignore ARC DTBs
by Masahiro Yamada 18 May '15

18 May '15

Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- arch/arc/dts/.gitignore | 1 + 1 file changed, 1 insertion(+) create mode 100644 arch/arc/dts/.gitignore diff --git a/arch/arc/dts/.gitignore b/arch/arc/dts/.gitignore new file mode 100644 index 0000000..b60ed20 --- /dev/null +++ b/arch/arc/dts/.gitignore @@ -0,0 +1 @@ +*.dtb -- 1.9.1

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[U-Boot] [PATCH] exynos: clock: clean up checkpatch issues
by Minkyu Kang 18 May '15

18 May '15

Signed-off-by: Minkyu Kang <mk7.kang(a)samsung.com> --- arch/arm/cpu/armv7/exynos/clock.c | 65 +++++++++++++++++++++---------------- 1 file changed, 37 insertions(+), 28 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index df4d473..1c6baa1 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -1362,7 +1362,7 @@ int exynos5_set_i2s_clk_prescaler(unsigned int src_frq, } clrsetbits_le32(&clk->div_mau, AUDIO_0_RATIO_MASK, (div & AUDIO_0_RATIO_MASK)); - } else if(i2s_id == 1) { + } else if (i2s_id == 1) { if (div > AUDIO_1_RATIO_MASK) { debug("%s: Frequency ratio is out of range\n", __func__); @@ -1579,45 +1579,49 @@ unsigned long get_pll_clk(int pllreg) if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos542x_get_pll_clk(pllreg); return exynos5_get_pll_clk(pllreg); - } else { + } else if (cpu_is_exynos4()) { if (proid_is_exynos4412()) return exynos4x12_get_pll_clk(pllreg); return exynos4_get_pll_clk(pllreg); } + + return 0; } unsigned long get_arm_clk(void) { - if (cpu_is_exynos5()) + if (cpu_is_exynos5()) { return exynos5_get_arm_clk(); - else { + } else if (cpu_is_exynos4()) { if (proid_is_exynos4412()) return exynos4x12_get_arm_clk(); return exynos4_get_arm_clk(); } + + return 0; } unsigned long get_i2c_clk(void) { - if (cpu_is_exynos5()) { + if (cpu_is_exynos5()) return clock_get_periph_rate(PERIPH_ID_I2C0); - } else if (cpu_is_exynos4()) { + else if (cpu_is_exynos4()) return exynos4_get_i2c_clk(); - } else { - debug("I2C clock is not set for this CPU\n"); - return 0; - } + + return 0; } unsigned long get_pwm_clk(void) { if (cpu_is_exynos5()) { return clock_get_periph_rate(PERIPH_ID_PWM0); - } else { + } else if (cpu_is_exynos4()) { if (proid_is_exynos4412()) return exynos4x12_get_pwm_clk(); return exynos4_get_pwm_clk(); } + + return 0; } unsigned long get_uart_clk(int dev_index) @@ -1644,11 +1648,13 @@ unsigned long get_uart_clk(int dev_index) if (cpu_is_exynos5()) { return clock_get_periph_rate(id); - } else { + } else if (cpu_is_exynos4()) { if (proid_is_exynos4412()) return exynos4x12_get_uart_clk(dev_index); return exynos4_get_uart_clk(dev_index); } + + return 0; } unsigned long get_mmc_clk(int dev_index) @@ -1673,11 +1679,12 @@ unsigned long get_mmc_clk(int dev_index) return -1; } - if (cpu_is_exynos5()) { + if (cpu_is_exynos5()) return clock_get_periph_rate(id); - } else { + else if (cpu_is_exynos4()) return exynos4_get_mmc_clk(dev_index); - } + + return 0; } void set_mmc_clk(int dev_index, unsigned int div) @@ -1691,16 +1698,16 @@ void set_mmc_clk(int dev_index, unsigned int div) exynos5420_set_mmc_clk(dev_index, div); else exynos5_set_mmc_clk(dev_index, div); - } else { + } else if (cpu_is_exynos4()) { exynos4_set_mmc_clk(dev_index, div); } } unsigned long get_lcd_clk(void) { - if (cpu_is_exynos4()) + if (cpu_is_exynos4()) { return exynos4_get_lcd_clk(); - else { + } else if (cpu_is_exynos5()) { if (proid_is_exynos5420()) return exynos5420_get_lcd_clk(); else if (proid_is_exynos5800()) @@ -1708,13 +1715,15 @@ unsigned long get_lcd_clk(void) else return exynos5_get_lcd_clk(); } + + return 0; } void set_lcd_clk(void) { - if (cpu_is_exynos4()) + if (cpu_is_exynos4()) { exynos4_set_lcd_clk(); - else { + } else if (cpu_is_exynos5()) { if (proid_is_exynos5250()) exynos5_set_lcd_clk(); else if (proid_is_exynos5420()) @@ -1736,9 +1745,9 @@ int set_spi_clk(int periph_id, unsigned int rate) if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_set_spi_clk(periph_id, rate); return exynos5_set_spi_clk(periph_id, rate); - } else { - return 0; } + + return 0; } int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq, @@ -1746,22 +1755,22 @@ int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq, { if (cpu_is_exynos5()) return exynos5_set_i2s_clk_prescaler(src_frq, dst_frq, i2s_id); - else - return 0; + + return 0; } int set_i2s_clk_source(unsigned int i2s_id) { if (cpu_is_exynos5()) return exynos5_set_i2s_clk_source(i2s_id); - else - return 0; + + return 0; } int set_epll_clk(unsigned long rate) { if (cpu_is_exynos5()) return exynos5_set_epll_clk(rate); - else - return 0; + + return 0; } -- 1.7.9.5 -- Thanks, Minkyu Kang.

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[U-Boot] [PATCH 1/2] sunxi: Fix dram initialization not working on some a33 devices
by Hans de Goede 18 May '15

18 May '15

When porting the allwinner dram init code to u-boot we missed some code setting an extra bit when doing auto dram config. This commits add this bit, fixing dram init not working on the ga10h 10" a33 tablet which I'm bringing up atm. Signed-off-by: Hans de Goede <hdegoede(a)redhat.com> --- arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c index d03f00d..979bb3c 100644 --- a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c +++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c @@ -195,7 +195,7 @@ static int mctl_train_dram(struct dram_para *para) (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; mctl_data_train_cfg(para); - mctl_set_pir(0x1f3); + mctl_set_pir(0x5f3); return ((readl(&mctl_ctl->pgsr0) >> 20) & 0xff) ? -EIO : 0; } -- 2.4.0

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[U-Boot] Status of squashsfs support
by leszek Hanusz 18 May '15

18 May '15

Hi, I was wondering what is the status of the squashfs support in u-boot ? The wiki page http://elinux.org/Squashfs_filesystem_support_for_u-boot is linking to a mail indicating that support for squashfs version 3 exists but the link is broken ? Anything new ? Best Regards, Leszek

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[U-Boot] [PATCH 20/20] armv8/ls2085a: enable debug server
by Prabhakar Kushwaha 18 May '15

18 May '15

From: Stuart Yoder <stuart.yoder(a)freescale.com> Signed-off-by: Stuart Yoder <stuart.yoder(a)freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- include/configs/ls2085a_common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index c895291..12d6b46 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -163,6 +163,7 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 /* Debug Server firmware */ +#define CONFIG_FSL_DEBUG_SERVER /* 2 sec timeout */ #define CONFIG_SYS_DEBUG_SERVER_TIMEOUT (2 * 1000 * 1000) -- 1.9.1

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[U-Boot] [PATCH 18/20] arm/errata: Update required bits for A57 cores erratas
by Prabhakar Kushwaha 18 May '15

18 May '15

From: Bhupesh Sharma <bhupesh.sharma(a)freescale.com> This patch updates the setting of required bits for A57 cores erratas - 828024 and 826974 Signed-off-by: Bhupesh Sharma <bhupesh.sharma(a)freescale.com> Signed-off-by: Dai Haruki <dai.haruki(a)freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- arch/arm/cpu/armv8/start.S | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index e5f2766..e70bed4 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -115,18 +115,18 @@ apply_a57_core_errata: #ifdef CONFIG_ARM_ERRATA_828024 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ /* Disable non-allocate hint of w-b-n-a memory type */ - mov x0, #0x1 << 49 + orr x0, x0, #1 << 49 /* Disable write streaming no L1-allocate threshold */ - mov x0, #0x3 << 25 + orr x0, x0, #3 << 25 /* Disable write streaming no-allocate threshold */ - mov x0, #0x3 << 27 + orr x0, x0, #3 << 27 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ #endif #ifdef CONFIG_ARM_ERRATA_826974 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ /* Disable speculative load execution ahead of a DMB */ - mov x0, #0x1 << 59 + orr x0, x0, #1 << 59 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ #endif -- 1.9.1

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[U-Boot] [PATCH 16/20] armv8/ls2085a: Expose all DDR region(s) to Linux
by Prabhakar Kushwaha 18 May '15

18 May '15

From: Bhupesh Sharma <bhupesh.sharma(a)freescale.com> This patch allows u-boot to expose the complete DDR region(s) to Linux (after subtracting the memory hidden via MEM_TOP_HIDE mechanism). This allows the u-boot to support the 48-bit VA support provided by ARM64 Linux in flavors 3.18 and above, by passing the appropriate 'memory' DTS nodes. Signed-off-by: Bhupesh Sharma <bhupesh.sharma(a)freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- board/freescale/ls2085a/README | 11 +++++++++++ board/freescale/ls2085a/ls2085a.c | 15 +++++++++------ board/freescale/ls2085aqds/README | 19 +++++++++++++++++++ board/freescale/ls2085aqds/ls2085aqds.c | 15 +++++++++------ board/freescale/ls2085ardb/README | 11 +++++++++++ board/freescale/ls2085ardb/ls2085ardb.c | 15 +++++++++------ 6 files changed, 68 insertions(+), 18 deletions(-) diff --git a/board/freescale/ls2085a/README b/board/freescale/ls2085a/README index b7023e1..bc1d0bb 100644 --- a/board/freescale/ls2085a/README +++ b/board/freescale/ls2085a/README @@ -14,3 +14,14 @@ Memory map from core's view Other addresses are either reserved, or not used directly by u-boot. This list should be updated when more addresses are used. + +Booting Linux flavors which do not support 48-bit VA (< Linux 3.18) +------------------------------------------------------------------- +One needs to use appropriate bootargs to boot Linux flavors which do +not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown +below: + +=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram + earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m + hugepages=16 mem=2048M' + diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2085a/ls2085a.c index afb99d1..bcb99de 100644 --- a/board/freescale/ls2085a/ls2085a.c +++ b/board/freescale/ls2085a/ls2085a.c @@ -127,15 +127,18 @@ void fdt_fixup_board_enet(void *fdt) #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { - phys_addr_t base; - phys_size_t size; + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; ft_cpu_setup(blob, bd); - /* limit the memory size to bank 1 until Linux can handle 40-bit PA */ - base = getenv_bootm_low(); - size = getenv_bootm_size(); - fdt_fixup_memory(blob, (u64)base, (u64)size); + /* fixup DT for the two GPP DDR banks */ + base[0] = gd->bd->bi_dram[0].start; + size[0] = gd->bd->bi_dram[0].size; + base[1] = gd->bd->bi_dram[1].start; + size[1] = gd->bd->bi_dram[1].size; + + fdt_fixup_memory_banks(blob, base, size, 2); #ifdef CONFIG_FSL_MC_ENET fdt_fixup_board_enet(blob); diff --git a/board/freescale/ls2085aqds/README b/board/freescale/ls2085aqds/README index fb3938e..11b2e79 100644 --- a/board/freescale/ls2085aqds/README +++ b/board/freescale/ls2085aqds/README @@ -127,3 +127,22 @@ b) NOR boot c) NAND boot d) SD boot e) QSPI boot + +Environment Variables +--------------------- +- mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined + the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed. + +- mcmemsize: MC DRAM block size. If this variable is not defined + the value CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed. + +Booting Linux flavors which do not support 48-bit VA (< Linux 3.18) +------------------------------------------------------------------- +One needs to use appropriate bootargs to boot Linux flavors which do +not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown +below: + +=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram + earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m + hugepages=16 mem=2048M' + diff --git a/board/freescale/ls2085aqds/ls2085aqds.c b/board/freescale/ls2085aqds/ls2085aqds.c index 5e15ab2..67b3062 100644 --- a/board/freescale/ls2085aqds/ls2085aqds.c +++ b/board/freescale/ls2085aqds/ls2085aqds.c @@ -244,15 +244,18 @@ void fdt_fixup_board_enet(void *fdt) #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { - phys_addr_t base; - phys_size_t size; + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; ft_cpu_setup(blob, bd); - /* limit the memory size to bank 1 until Linux can handle 40-bit PA */ - base = getenv_bootm_low(); - size = getenv_bootm_size(); - fdt_fixup_memory(blob, (u64)base, (u64)size); + /* fixup DT for the two GPP DDR banks */ + base[0] = gd->bd->bi_dram[0].start; + size[0] = gd->bd->bi_dram[0].size; + base[1] = gd->bd->bi_dram[1].start; + size[1] = gd->bd->bi_dram[1].size; + + fdt_fixup_memory_banks(blob, base, size, 2); #ifdef CONFIG_FSL_MC_ENET fdt_fixup_board_enet(blob); diff --git a/board/freescale/ls2085ardb/README b/board/freescale/ls2085ardb/README index cfd5185..2f18243 100644 --- a/board/freescale/ls2085ardb/README +++ b/board/freescale/ls2085ardb/README @@ -107,3 +107,14 @@ Booting Options --------------- a) NOR boot b) NAND boot + +Booting Linux flavors which do not support 48-bit VA (< Linux 3.18) +------------------------------------------------------------------- +One needs to use appropriate bootargs to boot Linux flavors which do +not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown +below: + +=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram + earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m + hugepages=16 mem=2048M' + diff --git a/board/freescale/ls2085ardb/ls2085ardb.c b/board/freescale/ls2085ardb/ls2085ardb.c index 78efa32..531ecf3 100644 --- a/board/freescale/ls2085ardb/ls2085ardb.c +++ b/board/freescale/ls2085ardb/ls2085ardb.c @@ -241,15 +241,18 @@ void fdt_fixup_board_enet(void *fdt) #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { - phys_addr_t base; - phys_size_t size; + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; ft_cpu_setup(blob, bd); - /* limit the memory size to bank 1 until Linux can handle 40-bit PA */ - base = getenv_bootm_low(); - size = getenv_bootm_size(); - fdt_fixup_memory(blob, (u64)base, (u64)size); + /* fixup DT for the two GPP DDR banks */ + base[0] = gd->bd->bi_dram[0].start; + size[0] = gd->bd->bi_dram[0].size; + base[1] = gd->bd->bi_dram[1].start; + size[1] = gd->bd->bi_dram[1].size; + + fdt_fixup_memory_banks(blob, base, size, 2); #ifdef CONFIG_FSL_MC_ENET fdt_fixup_board_enet(blob); -- 1.9.1

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[U-Boot] [PATCH 15/20] armv8/ls2085ardb: Fix SPD address error on early boards
by Prabhakar Kushwaha 18 May '15

18 May '15

From: York Sun <yorksun(a)freescale.com> Board rev C and earlier has duplicated SPD address on 2nd DDR controller slots. It is fixed on rev D and later. SPD addresses need to be updated accordingly. Signed-off-by: York Sun <yorksun(a)freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- board/freescale/ls2085ardb/ls2085ardb.c | 19 +++++++++++++++++++ include/configs/ls2085ardb.h | 4 ++-- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/board/freescale/ls2085ardb/ls2085ardb.c b/board/freescale/ls2085ardb/ls2085ardb.c index 175943e..78efa32 100644 --- a/board/freescale/ls2085ardb/ls2085ardb.c +++ b/board/freescale/ls2085ardb/ls2085ardb.c @@ -277,3 +277,22 @@ void qixis_dump_switch(void) printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); } } + +/* + * Board rev C and earlier has duplicated I2C addresses for 2nd controller. + * Both slots has 0x54, resulting 2nd slot unusable. + */ +void update_spd_address(unsigned int ctrl_num, + unsigned int slot, + unsigned int *addr) +{ + u8 sw; + + sw = QIXIS_READ(arch); + if ((sw & 0xf) < 0x3) { + if (ctrl_num == 1 && slot == 0) + *addr = SPD_EEPROM_ADDRESS4; + else if (ctrl_num == 1 && slot == 1) + *addr = SPD_EEPROM_ADDRESS3; + } +} diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h index 5a5884c..a0f0f6c 100644 --- a/include/configs/ls2085ardb.h +++ b/include/configs/ls2085ardb.h @@ -29,8 +29,8 @@ unsigned long get_board_sys_clk(void); #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 -#define SPD_EEPROM_ADDRESS3 0x54 -#define SPD_EEPROM_ADDRESS4 0x53 /* Board error */ +#define SPD_EEPROM_ADDRESS3 0x53 +#define SPD_EEPROM_ADDRESS4 0x54 #define SPD_EEPROM_ADDRESS5 0x55 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 -- 1.9.1

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[U-Boot] [PATCH 14/20] driver/ddr/fsl: Add a hook to update SPD address
by Prabhakar Kushwaha 18 May '15

18 May '15

From: York Sun <yorksun(a)freescale.com> In case SPD address changes between board revisions, updating SPD address can be called from board file. Signed-off-by: York Sun <yorksun(a)freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- drivers/ddr/fsl/main.c | 8 ++++++++ include/fsl_ddr.h | 3 +++ 2 files changed, 11 insertions(+) diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index fa22383..14ecf12 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -135,6 +135,13 @@ static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) __attribute__((weak, alias("__get_spd"))) void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address); +/* This function allows boards to update SPD address */ +__weak void update_spd_address(unsigned int ctrl_num, + unsigned int slot, + unsigned int *addr) +{ +} + void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl) { @@ -148,6 +155,7 @@ void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, for (i = 0; i < dimm_slots_per_ctrl; i++) { i2c_address = spd_i2c_addr[ctrl_num][i]; + update_spd_address(ctrl_num, i, &i2c_address); get_spd(&(ctrl_dimms_spd[i]), i2c_address); } } diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h index 4099a74..728503b 100644 --- a/include/fsl_ddr.h +++ b/include/fsl_ddr.h @@ -136,4 +136,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, unsigned int controller_number, unsigned int dimm_number); +void update_spd_address(unsigned int ctrl_num, + unsigned int slot, + unsigned int *addr); #endif -- 1.9.1

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