May 2015 - U-Boot

Re: [U-Boot] Quark compile errors
by Bin Meng 20 May '15

20 May '15

Hi Andy, On Wed, May 20, 2015 at 10:58 PM, Andy Pont <andy.pont(a)sdcsystems.com> wrote: > Hi Bin, > >> > It is using the standard version of gcc that comes as part of the >> > CentOS 6.6 installation which is 4.4.7. >> > >> >> I have been using 4.6.1 and 4.7.2, and both work. Can you please try >> some newer gcc? > > Good call. Having found a gcc version 4.8.4 then it has all compiled successfully! > > Thanks for your help! > Good to know. BTW, so you are working on this board? http://www.siliconmotion.com/EW_Pages/Osprey.html Looks like a quark based board with graphics support! Are you planning to submit patches to enable it? Regards, Bin

2 1

[U-Boot] [Patch v3 0/4] imx: mx6: use OTP for teperature grade info
by Tim Harvey 20 May '15

20 May '15

Use Temperature grade info in OTP/eFUSE for thermal management and display of thermal data. Cc: Stefan Roese <sr(a)denx.de> Cc: Eric Nelson <eric.nelson(a)boundarydevices.com> Cc: Heiko Schocher <hs(a)denx.de> Cc: Nikita Kiryanov <nikita(a)compulab.co.il> Cc: Jon Nettleton <jon.nettleton(a)gmail.com> Cc: Jason Liu <r64343(a)freescale.com> Cc: Ye Li <b37916(a)freescale.com> Cc: Fabio Estevam <fabio.estevam(a)freescale.com> Cc: Christian Gmeiner <christian.gmeiner(a)gmail.com> Cc: Markus Niebel <Markus.Niebel(a)tq-group.com> Cc: Peng Fan <b51431(a)freescale.com> Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- v3: - include display of temperature grade for IMX6SX v2: - split into two series: 1 for CPU frequency, other for Temperature grade Tim Harvey (4): mx6: add OTP bank1 registers imx: mx6: add get_cpu_temp_grade to obtain cpu temperature grade from OTP imx: mx6: add display of CPU temperature grade in print_cpuinfo() thermal: imx_thermal: use CPU temperature grade for trip points arch/arm/cpu/armv7/mx6/soc.c | 38 +++++++++++++++++++++++++++++++ arch/arm/imx-common/cpu.c | 25 ++++++++++++++++---- arch/arm/include/asm/arch-mx6/imx-regs.h | 19 ++++++++++++++++ arch/arm/include/asm/arch-mx6/sys_proto.h | 1 + drivers/thermal/imx_thermal.c | 29 +++++++++++++++-------- include/imx_thermal.h | 6 +++++ 6 files changed, 104 insertions(+), 14 deletions(-) -- 1.9.1

5 10

Re: [U-Boot] Quark compile errors
by Bin Meng 20 May '15

20 May '15

Hi Andy, On Wed, May 20, 2015 at 10:50 PM, Andy Pont <andy.pont(a)sdcsystems.com> wrote: > Hi Bin, > >> >> Can you post your full configuration here? >> > >> > I have attached the autoconf.mk and U-Boot .config files. Hopefully they tell you what you need. >> > >> >> Looks OK. What gcc version are you using? It seems that your compiler >> does not understand the macro DOWNTO8 and DOWNTO16 in >> arch/x86/lib/bios.h > > It is using the standard version of gcc that comes as part of the CentOS 6.6 installation which is 4.4.7. > I have been using 4.6.1 and 4.7.2, and both work. Can you please try some newer gcc? Regards, Bin

2 1

Re: [U-Boot] Quark compile errors
by Bin Meng 20 May '15

20 May '15

Hi Andy, On Wed, May 20, 2015 at 6:20 PM, Andy Pont <andy.pont(a)sdcsystems.com> wrote: > Hi Bin, > >> Can you post your full configuration here? > > I have attached the autoconf.mk and U-Boot .config files. Hopefully they tell you what you need. > Looks OK. What gcc version are you using? It seems that your compiler does not understand the macro DOWNTO8 and DOWNTO16 in arch/x86/lib/bios.h >> > Also, if anyone can tell me what $TERM setting I need to get the rogue "b" >> > characters to actually display bold/bright then that would be great too! >> >> I am using xterm, not sure if this helps. >> >> $ echo $TERM >> xterm > > That is what I have too. I guess it might be down to the way SecureCRT is interpreting what it is being sent rather than the Linux machine itself. > Regards, Bin

2 1

Re: [U-Boot] Quark compile errors
by Simon Glass 20 May '15

20 May '15

Hi Andy, On 20 May 2015 at 04:20, Andy Pont <andy.pont(a)sdcsystems.com> wrote: > Hi Bin, > >> Can you post your full configuration here? > > I have attached the autoconf.mk and U-Boot .config files. Hopefully they tell you what you need. > >> > Also, if anyone can tell me what $TERM setting I need to get the rogue "b" >> > characters to actually display bold/bright then that would be great too! >> >> I am using xterm, not sure if this helps. >> >> $ echo $TERM >> xterm > > That is what I have too. I guess it might be down to the way SecureCRT is interpreting what it is being sent rather than the Linux machine itself. You might be able to set that terminal program to support 'xterm' emulation, or perhaps change TERM to whatever it does support. Regards, Simon

2 1

[U-Boot] [PATCH v2 2/6] pci: Do not skip legacy IDE device configuration
by Bin Meng 20 May '15

20 May '15

The legacy IDE device has a BAR4 (Bus Master Interface BAR) which needs to be configured. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- Changes in v2: - Correct a typo in the commit message title drivers/pci/pci_auto.c | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index 43965d8..7c10983 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -20,8 +20,6 @@ #define DEBUGF(x...) #endif /* DEBUG */ -#define PCIAUTO_IDE_MODE_MASK 0x05 - /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */ #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 @@ -424,7 +422,6 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) { unsigned int sub_bus = PCI_BUS(dev); unsigned short class; - unsigned char prg_iface; int n; pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); @@ -460,17 +457,6 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) #endif break; - case PCI_CLASS_STORAGE_IDE: - pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface); - if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) { - DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n"); - return sub_bus; - } - - pciauto_setup_device(hose, dev, 6, hose->pci_mem, - hose->pci_prefetch, hose->pci_io); - break; - case PCI_CLASS_BRIDGE_CARDBUS: /* * just do a minimal setup of the bridge, -- 1.8.2.1

2 3

[U-Boot] [PATCH 0/20] tegra: Expand Nyan-big support
by Simon Glass 20 May '15

20 May '15

This series expands Nyan-big support: - Enable Chrome OS EC, so that the keyboard works - Add some extra clock and pre-kernel init required for reliable operation - Add Chrome OS environment variables, including 'run nvboot' to allow booting Chrome OS more easily Still missing are audio and USB. Doug Anderson (1): Add Chrome OS config header Simon Glass (19): dm: spi: Avoid setting the speed with every transfer cros_ec: Show the protocol version in the debug message cros_ec: Handle the single duplex requirement in cros_ec tegra: Provide more accurate microsecond time tegra: cros_ec: Add tegra support for Chrome OS EC tegra: spi: Drop the claim_bus() method to correct delays dm: tegra: cros_ec: Enable Chrome OS EC on Nyan-big dm: gpio: Add an implementation for gpio_get_number() tegra: spi: Support slow SPI rates tegra: clock: Support enabling external clocks tegra: clock: Adjust PLL access to avoid a warning tegra: Introduce SRAM repair on tegra124 tegra: Add missing tegra124 peripherals tegra: Increase maximum arguments to 32 tegra: lcd: Tidy up clock init tegra: Allow board-specific init tegra: nyan-big: Add additional clock and kernel init tegra: config: Allow Chrome OS environment settings to be included tegra: config: nyan-big: Add options required by Chrome OS boot arch/arm/cpu/tegra-common/Makefile | 1 + arch/arm/cpu/tegra-common/clock.c | 24 +- arch/arm/cpu/tegra-common/powergate.c | 20 +- arch/arm/cpu/tegra-common/timer.c | 87 ++++ arch/arm/cpu/tegra124-common/clock.c | 2 +- arch/arm/dts/tegra124-nyan-big.dts | 6 +- arch/arm/include/asm/arch-tegra/clock.h | 8 + arch/arm/include/asm/arch-tegra/sys_proto.h | 7 + arch/arm/include/asm/arch-tegra124/clock-tables.h | 12 +- arch/arm/include/asm/arch-tegra124/flow.h | 12 + board/nvidia/common/board.c | 8 +- board/nvidia/nyan-big/nyan-big.c | 76 ++++ configs/nyan-big_defconfig | 5 + drivers/gpio/gpio-uclass.c | 12 + drivers/misc/cros_ec.c | 3 +- drivers/misc/cros_ec_spi.c | 23 +- drivers/spi/spi-uclass.c | 9 +- drivers/spi/tegra114_spi.c | 51 +-- drivers/video/tegra124/tegra124-lcd.c | 4 +- include/configs/chromeos.h | 464 ++++++++++++++++++++++ include/configs/nyan-big.h | 8 + include/configs/tegra-common-post.h | 15 +- include/configs/tegra-common.h | 2 +- include/spi.h | 3 + 24 files changed, 804 insertions(+), 58 deletions(-) create mode 100644 arch/arm/cpu/tegra-common/timer.c create mode 100644 include/configs/chromeos.h -- 2.2.0.rc0.207.ga3a616c

5 54

Re: [U-Boot] Quark compile errors
by Bin Meng 20 May '15

20 May '15

Hi Andy, On Wed, May 20, 2015 at 6:00 PM, Andy Pont <andy.pont(a)sdcsystems.com> wrote: > Hello, > > I am trying to create a configuration for the Silicon Motion Osprey board > which is a Quark SoC and their SM750 graphics controller. > > I have cloned the Intel Galileo files and changed them accordingly and have > defined the options for the VBIOS for the graphics controller but when I try > to compile I get the following build failure: > Can you post your full configuration here? > CC arch/x86/lib/bios.o > arch/x86/lib/bios.c: In function bint_exception_handlerb: > arch/x86/lib/bios.c:61: error: unknown field beaxb specified in initializer > arch/x86/lib/bios.c:61: warning: missing braces around initializer > arch/x86/lib/bios.c:61: warning: (near initialization for > breg_info.<anonymous>b) > arch/x86/lib/bios.c:62: error: unknown field becxb specified in initializer > arch/x86/lib/bios.c:63: error: unknown field bedxb specified in initializer > arch/x86/lib/bios.c:64: error: unknown field bebxb specified in initializer > arch/x86/lib/bios.c:65: error: unknown field bespb specified in initializer > arch/x86/lib/bios.c:66: error: unknown field bebpb specified in initializer > arch/x86/lib/bios.c:67: error: unknown field besib specified in initializer > arch/x86/lib/bios.c:68: error: unknown field bedib specified in initializer > make[1]: *** [arch/x86/lib/bios.o] Error 1 > > Could you advise what setting I have missed that is causing this build issue > or is it the case that the bios.c file is defined for x86 capabilities > beyond those of Quark? > > Also, if anyone can tell me what $TERM setting I need to get the rogue "b" > characters to actually display bold/bright then that would be great too! > I am using xterm, not sure if this helps. $ echo $TERM xterm Regards, Bin

2 1

[U-Boot] Quark compile errors
by Andy Pont 20 May '15

20 May '15

Hello, I am trying to create a configuration for the Silicon Motion Osprey board which is a Quark SoC and their SM750 graphics controller. I have cloned the Intel Galileo files and changed them accordingly and have defined the options for the VBIOS for the graphics controller but when I try to compile I get the following build failure: CC arch/x86/lib/bios.o arch/x86/lib/bios.c: In function bint_exception_handlerb: arch/x86/lib/bios.c:61: error: unknown field beaxb specified in initializer arch/x86/lib/bios.c:61: warning: missing braces around initializer arch/x86/lib/bios.c:61: warning: (near initialization for breg_info.<anonymous>b) arch/x86/lib/bios.c:62: error: unknown field becxb specified in initializer arch/x86/lib/bios.c:63: error: unknown field bedxb specified in initializer arch/x86/lib/bios.c:64: error: unknown field bebxb specified in initializer arch/x86/lib/bios.c:65: error: unknown field bespb specified in initializer arch/x86/lib/bios.c:66: error: unknown field bebpb specified in initializer arch/x86/lib/bios.c:67: error: unknown field besib specified in initializer arch/x86/lib/bios.c:68: error: unknown field bedib specified in initializer make[1]: *** [arch/x86/lib/bios.o] Error 1 Could you advise what setting I have missed that is causing this build issue or is it the case that the bios.c file is defined for x86 capabilities beyond those of Quark? Also, if anyone can tell me what $TERM setting I need to get the rogue "b" characters to actually display bold/bright then that would be great too! Thanks, Andy.

1 0

[U-Boot] [PATCH 2/4] x86: Document irq router device tree bindings
by Bin Meng 20 May '15

20 May '15

Describe all required properties needed by the irq router device tree. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- doc/device-tree-bindings/misc/intel,irq-router.txt | 50 ++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 doc/device-tree-bindings/misc/intel,irq-router.txt diff --git a/doc/device-tree-bindings/misc/intel,irq-router.txt b/doc/device-tree-bindings/misc/intel,irq-router.txt new file mode 100644 index 0000000..54112f4 --- /dev/null +++ b/doc/device-tree-bindings/misc/intel,irq-router.txt @@ -0,0 +1,50 @@ +Intel Interrupt Router Device Binding +===================================== + +The device tree node which describes the operation of the Intel Interrupt Router +device is as follows: + +Required properties : +- reg : Specifies the interrupt router's PCI configuration space address as + defined by the Open Firmware spec. +- compatible = "intel,irq-router" +- intel,pirq-config : Specifies the IRQ routing register programming mechanism. + Valid values are: + "pci": IRQ routing is controlled by PCI configuraiton registers + "ibase": IRQ routing is in the memory-mapped IBASE register block +- intel,ibase-offset : IBASE register offset in the interrupt router's PCI + configuration space, required only if intel,pirq-config = "ibase". +- intel,pirq-link : Specifies the PIRQ link information with two cells. The + first cell is the register offset that controls the first PIRQ link routing. + The second cell is the total number of PIRQ links the router supports. +- intel,pirq-mask : Specifies the IRQ mask reprenting the 16 IRQs in 8259 PIC. + Bit N is 1 means IRQ N is available to be routed. +- intel,pirq-routing : Specifies all PCI devices' IRQ routing information, + encoded as 3 cells a group for a device. The first cell is the device's PCI + bus number, device number and function number encoding with PCI_BDF() macro. + The second cell is the PCI interrupt pin used by this device. The last cell + is which PIRQ line the PCI interrupt pin is routed to. + + +Example +------- + +#include <dt-bindings/interrupt-router/intel-irq.h> + + irq-router@1f,0 { + reg = <0x0000f800 0 0 0 0>; + compatible = "intel,irq-router"; + intel,pirq-config = "pci"; + intel,pirq-link = <0x60 8>; + intel,pirq-mask = <0xdef8>; + intel,pirq-routing = < + PCI_BDF(0, 2, 0) INTA PIRQA + PCI_BDF(0, 3, 0) INTA PIRQB + PCI_BDF(0, 8, 0) INTA PIRQC + PCI_BDF(0, 8, 1) INTB PIRQD + PCI_BDF(1, 6, 0) INTA PIRQE + PCI_BDF(1, 6, 1) INTB PIRQF + PCI_BDF(1, 6, 2) INTC PIRQG + PCI_BDF(1, 6, 3) INTD PIRQH + >; + }; -- 1.8.2.1

2 1