May 2015 - U-Boot

[U-Boot] Pull request: u-boot-net.git master
by Joe Hershberger 27 May '15

27 May '15

Hi Tom, This fixes a few mistakes I made in the rand rework stuff. The following changes since commit 980267a1445b7b4d8e8d05ef57799d92ba4a2ee3: Merge git://git.denx.de/u-boot-nand-flash (2015-05-24 21:01:30 -0400) are available in the git repository at: git://git.denx.de/u-boot-net.git master for you to fetch changes up to 91fed5574600142f68dac7807bc06173d1f29eb5: blackfin: fix build error on bct-brettl2 board (2015-05-26 12:18:42 -0500) ---------------------------------------------------------------- Joe Hershberger (1): net: Fix a warning added by 76ec988 Masahiro Yamada (2): sparc: fix build error on gr_ep2s60 board blackfin: fix build error on bct-brettl2 board Michal Simek (1): net: Fix NET_RANDOM_ETHADDR dependencies board/buffalo/lsxl/lsxl.c | 2 -- configs/bct-brettl2_defconfig | 1 + include/configs/gr_ep2s60.h | 1 + lib/Kconfig | 3 +++ net/Kconfig | 1 + 5 files changed, 6 insertions(+), 2 deletions(-)

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[U-Boot] [PATCH v2 3/6] x86: Make QEMU the default vendor
by Bin Meng 27 May '15

27 May '15

Now that we have QEMU support, make it the default vendor in the 'make menuconfig' screen. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> Acked-by: Simon Glass <sjg(a)chromium.org> Tested-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: None arch/x86/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 3d02620..0b78f10 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -12,7 +12,7 @@ config SYS_VSNPRINTF choice prompt "Mainboard vendor" - default VENDOR_COREBOOT + default VENDOR_EMULATION config VENDOR_COREBOOT bool "coreboot" -- 1.8.2.1

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[U-Boot] Falcon mode with initrd
by Tim Harvey 27 May '15

27 May '15

Stefano, You may perhaps be the most knowledgeable about Falcon mode based on the presentations I've found on the web. It seems to me that there is currently no support in U-Boot for using Falcon mode where the kernel is separate from the initrd. I see that the 'spl' command is passed the initrd_addr so that it can setup atags/fdt (I haven't followed through the code to understand what it does with this addr yet) but there is no support in any of the common/spl/spl_*.c files for loading anything other than args or kernel. Have you had any thoughts on this? It seems to me a new #define would need to be created per storage medium pointing to the offset/sector of initrd and used at compile time. Perhaps your thoughts have always been that if you want to use an initrd for falcon mode you must always build it into the kernel? Regards, Tim

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[U-Boot] [PATCH 01/20] armv8/ls2085ardb: Add eth & phy f/w loading support
by Prabhakar Kushwaha 27 May '15

27 May '15

Add support for board eth initialization and support for loading phy firmware. PHY firmware needs to be loaded from board_eth_init() because all the MACs are not initialized by ldpaa_eth driver. Signed-off-by: pankaj chauhan <pankaj.chauhan(a)freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- board/freescale/ls2085ardb/Makefile | 2 +- board/freescale/ls2085ardb/eth_ls2085rdb.c | 133 +++++++++++++++++++++++++++++ board/freescale/ls2085ardb/ls2085ardb.c | 13 --- include/configs/ls2085ardb.h | 23 +++++ 4 files changed, 157 insertions(+), 14 deletions(-) create mode 100644 board/freescale/ls2085ardb/eth_ls2085rdb.c diff --git a/board/freescale/ls2085ardb/Makefile b/board/freescale/ls2085ardb/Makefile index 0bfe21c..de383cc 100644 --- a/board/freescale/ls2085ardb/Makefile +++ b/board/freescale/ls2085ardb/Makefile @@ -4,5 +4,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += ls2085ardb.o +obj-y += ls2085ardb.o eth_ls2085rdb.o obj-y += ddr.o diff --git a/board/freescale/ls2085ardb/eth_ls2085rdb.c b/board/freescale/ls2085ardb/eth_ls2085rdb.c new file mode 100644 index 0000000..60af079 --- /dev/null +++ b/board/freescale/ls2085ardb/eth_ls2085rdb.c @@ -0,0 +1,133 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <netdev.h> +#include <malloc.h> +#include <fsl_mdio.h> +#include <miiphy.h> +#include <phy.h> +#include <fm_eth.h> +#include <asm/io.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch-fsl-lsch3/immap_lsch3.h> +#include <fsl-mc/ldpaa_wriop.h> + +int load_firmware_cortina(struct phy_device *phy_dev) +{ + if (phy_dev->drv->config) + return phy_dev->drv->config(phy_dev); + + return 0; +} + +void load_phy_firmware(void) +{ + int i; + u8 phy_addr; + struct phy_device *phy_dev; + struct mii_dev *dev; + phy_interface_t interface; + + /*Initialize and upload firmware for all the PHYs*/ + for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC8; i++) { + interface = wriop_get_enet_if(i); + if (interface == PHY_INTERFACE_MODE_XGMII) { + dev = wriop_get_mdio(i); + phy_addr = wriop_get_phy_address(i); + phy_dev = phy_find_by_mask(dev, 1 << phy_addr, + interface); + if (!phy_dev) { + printf("No phydev for phyaddr %d\n", phy_addr); + continue; + } + + /*Flash firmware for All CS4340 PHYS */ + if (phy_dev->phy_id == PHY_UID_CS4340) + load_firmware_cortina(phy_dev); + } + } +} + +int board_eth_init(bd_t *bis) +{ +#if defined(CONFIG_FSL_MC_ENET) + int i, interface; + struct memac_mdio_info mdio_info; + struct mii_dev *dev; + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 srds_s1; + struct memac_mdio_controller *reg; + + srds_s1 = in_le32(&gur->rcwsr[28]) & + FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + + reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1; + mdio_info.regs = reg; + mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME; + + /* Register the EMI 1 */ + fm_memac_mdio_init(bis, &mdio_info); + + reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2; + mdio_info.regs = reg; + mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; + + /* Register the EMI 2 */ + fm_memac_mdio_init(bis, &mdio_info); + + switch (srds_s1) { + case 0x2A: + wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2); + wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3); + wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4); + wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2); + wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3); + wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4); + + break; + default: + printf("SerDes1 protocol 0x%x is not supported on LS2085aRDB\n", + srds_s1); + break; + } + + for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) { + interface = wriop_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_XGMII: + dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME); + wriop_set_mdio(i, dev); + break; + default: + break; + } + } + + for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) { + switch (wriop_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); + wriop_set_mdio(i, dev); + break; + default: + break; + } + } + + /* Load CORTINA CS4340 PHY firmware */ + load_phy_firmware(); + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ + + return pci_eth_init(bis); +} diff --git a/board/freescale/ls2085ardb/ls2085ardb.c b/board/freescale/ls2085ardb/ls2085ardb.c index d05f2bc..6cb7b13 100644 --- a/board/freescale/ls2085ardb/ls2085ardb.c +++ b/board/freescale/ls2085ardb/ls2085ardb.c @@ -176,19 +176,6 @@ unsigned long get_dram_size_to_hide(void) return dram_to_hide; } -int board_eth_init(bd_t *bis) -{ - int error = 0; - -#ifdef CONFIG_FSL_MC_ENET - error = cpu_eth_init(bis); -#endif - - error = pci_eth_init(bis); - - return error; -} - #ifdef CONFIG_FSL_MC_ENET void fdt_fixup_board_enet(void *fdt) { diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h index d1c2548..62f13f9 100644 --- a/include/configs/ls2085ardb.h +++ b/include/configs/ls2085ardb.h @@ -302,4 +302,27 @@ unsigned long get_board_sys_clk(void); "kernel_load=0xa0000000\0" \ "kernel_size=0x1000000\0" +/* MAC/PHY configuration */ +#ifdef CONFIG_FSL_MC_ENET +#define CONFIG_PHYLIB_10G +#define CONFIG_PHY_CORTINA +#define CONFIG_PHYLIB +#define CONFIG_SYS_CORTINA_FW_IN_NOR +#define CONFIG_CORTINA_FW_ADDR 0x581000000 +#define CONFIG_CORTINA_FW_LENGTH 0x40000 + +#define CORTINA_PHY_ADDR1 0x10 +#define CORTINA_PHY_ADDR2 0x11 +#define CORTINA_PHY_ADDR3 0x12 +#define CORTINA_PHY_ADDR4 0x13 +#define AQ_PHY_ADDR1 0x00 +#define AQ_PHY_ADDR2 0x01 +#define AQ_PHY_ADDR3 0x02 +#define AQ_PHY_ADDR4 0x03 + +#define CONFIG_MII +#define CONFIG_ETHPRIME "DPNI1" +#define CONFIG_PHY_GIGE +#endif + #endif /* __LS2_RDB_H */ -- 1.9.1

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[U-Boot] FW: eTSEC0 internal loopback test
by Sanjeev Majumdar 27 May '15

27 May '15

Hi I am using EP8548A board based on MPC8548E with u boot 1.2 flashed. We have done the following experiments for testing the ETSEC loopback test U-boot erased : When I test the ETSEC controller for loopback test by initializing the board through code warrior 10.3 using "8458CDS_Core.tcl" initialization script file, the loopback test is passing. U-boot flashed: When I do the same initializations for ETSEC through u-boot command prompt, the tests are failing. Kindly anybody tell us the difference or the initializations done in u-boot (ver 1.2) which is affecting the ETSEC controllers loopback test. Please find the attached initialization sequence plus loopback test which we have followed for the eTSEC test. Sanjeev Majumdar Tel No. +918067745124 Sr. Design Engineer Spectrum Infotech Pvt Ltd (A Wholly owned subsidiary of Larsen & Toubro Ltd) Larsen & Toubro Limited www.larsentoubro.com This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.

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[U-Boot] [PATCH v2 0/2] kbuild: create a symbolic link only when necessary
by Masahiro Yamada 27 May '15

27 May '15

1/2: refactors a little because NDS32 actually need not the symbolic link 2/2: introduce a new config to avoid broken symbolic links. Changes in v2: - Use 'ifdef CONFIG_CREATE_ARCH_SYMLINK' for readability Masahiro Yamada (2): nds32: include <asm/arch-*/*.h> instead of <asm/arch/*.h> kbuild: create symbolic link only for ARM, SPARC, PowerPC, x86 arch/Kconfig | 6 ++++++ arch/powerpc/Kconfig | 3 +++ include/configs/adp-ag101.h | 2 +- include/configs/adp-ag101p.h | 2 +- include/configs/adp-ag102.h | 2 +- scripts/Makefile.autoconf | 2 ++ 6 files changed, 14 insertions(+), 3 deletions(-) -- 1.9.1

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[U-Boot] [PATCH v2 0/7] UniPhier updates for v2015.07-rc2
by Masahiro Yamada 27 May '15

27 May '15

Masahiro Yamada (7): ARM: UniPhier: use 32 bit register access for debug UART setting ARM: UniPhier: remove unnecessary cache coherency code ARM: UniPhier: remove meaningless CONFIG_SPL_BUILD ifdefs ARM: UniPhier: move CONFIG_SYS_TEXT_BASE to Kconfig ARM: UniPhier: set MACH_PH1_PRO4 as default SoC ARM: UniPhier: enable CONFIG_NET_RANDOM_ETHADDR ARM: UniPhier: update DDR PHY register map for PH1-Pro5 Kconfig | 2 +- arch/arm/mach-uniphier/Kconfig | 2 +- arch/arm/mach-uniphier/ddrphy_training.c | 9 +++------ arch/arm/mach-uniphier/include/mach/ddrphy-regs.h | 13 +++++++++---- arch/arm/mach-uniphier/include/mach/debug-uart.S | 9 +++++---- arch/arm/mach-uniphier/lowlevel_init.S | 20 -------------------- configs/ph1_ld4_defconfig | 3 +++ configs/ph1_pro4_defconfig | 4 +++- configs/ph1_sld8_defconfig | 3 +++ include/configs/uniphier.h | 2 -- 10 files changed, 28 insertions(+), 39 deletions(-) -- 1.9.1

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[U-Boot] [PATCH v2 3/3] x86: qemu: Add graphics support
by Bin Meng 27 May '15

27 May '15

It turns out that QEMU x86 emulated graphic card has a built-in option ROM which can be run perfectly with native mode by U-Boot. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- Changes in v2: - Drop the patch that tries to clean up the CONFIG_VGA_AS_SINGLE_DEVICE wraps - Update README.x86 to mention QEMU version arch/x86/cpu/qemu/pci.c | 24 +++++++++++++++++++++++- configs/qemu-x86_defconfig | 3 +++ doc/README.x86 | 7 ++++++- include/configs/qemu-x86.h | 10 +++------- 4 files changed, 35 insertions(+), 9 deletions(-) diff --git a/arch/x86/cpu/qemu/pci.c b/arch/x86/cpu/qemu/pci.c index d50ab75..ac9c056 100644 --- a/arch/x86/cpu/qemu/pci.c +++ b/arch/x86/cpu/qemu/pci.c @@ -6,6 +6,7 @@ #include <common.h> #include <pci.h> +#include <pci_rom.h> DECLARE_GLOBAL_DATA_PTR; @@ -45,5 +46,26 @@ void board_pci_setup_hose(struct pci_controller *hose) int board_pci_post_scan(struct pci_controller *hose) { - return 0; + int ret = 0; + ulong start; + pci_dev_t bdf; + struct pci_device_id graphic_card[] = { { 0x1234, 0x1111 } }; + + /* + * QEMU emulated graphic card shows in the PCI configuration space with + * PCI vendor id and device id as an artificial pair 0x1234:0x1111. + * It is on PCI bus 0, function 0, but device number is not consistent + * for the two x86 targets it supports. For i440FX and PIIX chipset + * board, it shows as device 2, while for Q35 and ICH9 chipset board, + * it shows as device 1. Here we locate its bdf at run-time based on + * its vendor id and device id pair so we can support both boards. + */ + bdf = pci_find_devices(graphic_card, 0); + if (bdf != -1) { + start = get_timer(0); + ret = pci_run_vga_bios(bdf, NULL, PCI_ROM_USE_NATIVE); + debug("BIOS ran in %lums\n", get_timer(start)); + } + + return ret; } diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index 9b02322..198ab97 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -4,3 +4,6 @@ CONFIG_TARGET_QEMU_X86=y CONFIG_OF_CONTROL=y CONFIG_OF_SEPARATE=y CONFIG_DEFAULT_DEVICE_TREE="qemu-x86" +CONFIG_VIDEO_VESA=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_111=y diff --git a/doc/README.x86 b/doc/README.x86 index 4a30f68..0726205 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -218,7 +218,8 @@ works correctly for link though. Test with QEMU -------------- QEMU is a fancy emulator that can enable us to test U-Boot without access to -a real x86 board. To launch QEMU with u-boot.rom, call QEMU as follows: +a real x86 board. Please make sure your QEMU version is 2.3.0 or above test +U-Boot. To launch QEMU with u-boot.rom, call QEMU as follows: $ qemu-system-i386 -nographic -bios path/to/u-boot.rom @@ -239,6 +240,10 @@ supports 3 GiB maximum system memory and reserves the last 1 GiB address space for PCI device memory-mapped I/O and other stuff, so the maximum value of '-m' would be 3072. +QEMU emulates a graphic card which U-Boot supports. Removing '-nographic' will +show QEMU's VGA console window. Note this will disable QEMU's serial output. +If you want to check both consoles, use '-serial stdio'. + CPU Microcode ------------- Modern CPUs usually require a special bit stream called microcode [6] to be diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h index 281aaa5..6467c38 100644 --- a/include/configs/qemu-x86.h +++ b/include/configs/qemu-x86.h @@ -36,9 +36,9 @@ #define CONFIG_E1000 #endif -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga\0" \ + "stdout=serial,vga\0" \ + "stderr=serial,vga\0" #define CONFIG_SCSI_DEV_LIST \ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1} @@ -52,8 +52,4 @@ #undef CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_IS_NOWHERE -/* Video is not supported */ -#undef CONFIG_VIDEO -#undef CONFIG_CFB_CONSOLE - #endif /* __CONFIG_H */ -- 1.8.2.1

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[U-Boot] [PATCH 6/6] x86: qemu: Implement PIRQ routing
by Bin Meng 27 May '15

27 May '15

Support QEMU PIRQ routing via device tree on both i440fx and q35 platforms. With this commit, Linux booting on QEMU from U-Boot has working ATA/SATA, USB and ethernet. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/cpu/coreboot/coreboot.c | 5 +++++ arch/x86/cpu/qemu/qemu.c | 8 ++++++++ arch/x86/dts/qemu-x86_i440fx.dts | 16 ++++++++++++++++ arch/x86/dts/qemu-x86_q35.dts | 32 ++++++++++++++++++++++++++++++++ configs/qemu-x86_defconfig | 1 + include/configs/qemu-x86_i440fx.h | 1 + include/configs/qemu-x86_q35.h | 1 + 7 files changed, 64 insertions(+) diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index 12b07bf..041e51e 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -78,3 +78,8 @@ int misc_init_r(void) { return 0; } + +int arch_misc_init(void) +{ + return 0; +} diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c index 0f98476..930d2b6 100644 --- a/arch/x86/cpu/qemu/qemu.c +++ b/arch/x86/cpu/qemu/qemu.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <asm/irq.h> #include <asm/post.h> #include <asm/processor.h> @@ -35,3 +36,10 @@ void reset_cpu(ulong addr) /* cold reset */ x86_full_reset(); } + +int arch_misc_init(void) +{ + pirq_init(); + + return 0; +} diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts index 4cf843b..557428a 100644 --- a/arch/x86/dts/qemu-x86_i440fx.dts +++ b/arch/x86/dts/qemu-x86_i440fx.dts @@ -6,6 +6,8 @@ /dts-v1/; +#include <dt-bindings/interrupt-router/intel-irq.h> + /include/ "skeleton.dtsi" /include/ "serial.dtsi" @@ -29,6 +31,20 @@ ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + + irq-router@1,0 { + reg = <0x00000800 0 0 0 0>; + compatible = "intel,irq-router"; + intel,pirq-config = "pci"; + intel,pirq-link = <0x60 4>; + intel,pirq-mask = <0x0e40>; + intel,pirq-routing = < + /* PIIX UHCI */ + PCI_BDF(0, 1, 2) INTD PIRQD + /* e1000 NIC */ + PCI_BDF(0, 3, 0) INTA PIRQC + >; + }; }; }; diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts index 6c89283..c8e1a55 100644 --- a/arch/x86/dts/qemu-x86_q35.dts +++ b/arch/x86/dts/qemu-x86_q35.dts @@ -6,6 +6,18 @@ /dts-v1/; +#include <dt-bindings/interrupt-router/intel-irq.h> + +/* ICH9 IRQ router has discrete PIRQ control registers */ +#undef PIRQE +#undef PIRQF +#undef PIRQG +#undef PIRQH +#define PIRQE 8 +#define PIRQF 9 +#define PIRQG 10 +#define PIRQH 11 + /include/ "skeleton.dtsi" /include/ "serial.dtsi" @@ -29,6 +41,26 @@ ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + + irq-router@1f,0 { + reg = <0x0000f800 0 0 0 0>; + compatible = "intel,irq-router"; + intel,pirq-config = "pci"; + intel,pirq-link = <0x60 8>; + intel,pirq-mask = <0x0e40>; + intel,pirq-routing = < + /* e1000 NIC */ + PCI_BDF(0, 2, 0) INTA PIRQG + /* ICH9 UHCI */ + PCI_BDF(0, 29, 0) INTA PIRQA + PCI_BDF(0, 29, 1) INTB PIRQB + PCI_BDF(0, 29, 2) INTC PIRQC + /* ICH9 EHCI */ + PCI_BDF(0, 29, 7) INTD PIRQD + /* ICH9 SATA */ + PCI_BDF(0, 31, 2) INTA PIRQA + >; + }; }; }; diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index a894db6..a5251b5 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -6,3 +6,4 @@ CONFIG_OF_SEPARATE=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_111=y +CONFIG_GENERATE_PIRQ_TABLE=y diff --git a/include/configs/qemu-x86_i440fx.h b/include/configs/qemu-x86_i440fx.h index 53d917d..b710cf7 100644 --- a/include/configs/qemu-x86_i440fx.h +++ b/include/configs/qemu-x86_i440fx.h @@ -14,6 +14,7 @@ #include <configs/x86-common.h> #define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_ARCH_MISC_INIT #define CONFIG_X86_SERIAL diff --git a/include/configs/qemu-x86_q35.h b/include/configs/qemu-x86_q35.h index ef81ad3..db26676 100644 --- a/include/configs/qemu-x86_q35.h +++ b/include/configs/qemu-x86_q35.h @@ -14,6 +14,7 @@ #include <configs/x86-common.h> #define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_ARCH_MISC_INIT #define CONFIG_X86_SERIAL -- 1.8.2.1

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[U-Boot] [PATCH 4/6] x86: coreboot: Fix cosmetic issues
by Bin Meng 27 May '15

27 May '15

Clean up arch/x86/cpu/coreboot.c to fix several cosmetic issues. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/cpu/coreboot/coreboot.c | 26 ++------------------------ arch/x86/include/asm/u-boot-x86.h | 1 - 2 files changed, 2 insertions(+), 25 deletions(-) diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index 2234cf0..12b07bf 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -7,16 +7,9 @@ */ #include <common.h> -#include <asm/u-boot-x86.h> -#include <flash.h> #include <netdev.h> -#include <ns16550.h> #include <asm/msr.h> -#include <asm/cache.h> -#include <asm/cpu.h> -#include <asm/io.h> #include <asm/mtrr.h> -#include <asm/arch/tables.h> #include <asm/arch/sysinfo.h> #include <asm/arch/timestamp.h> @@ -53,13 +46,6 @@ int last_stage_init(void) return 0; } -#ifndef CONFIG_SYS_NO_FLASH -ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) -{ - return 0; -} -#endif - int board_eth_init(bd_t *bis) { return pci_eth_init(bis); @@ -67,7 +53,8 @@ int board_eth_init(bd_t *bis) void board_final_cleanup(void) { - /* Un-cache the ROM so the kernel has one + /* + * Un-cache the ROM so the kernel has one * more MTRR available. * * Coreboot should have assigned this to the @@ -87,15 +74,6 @@ void board_final_cleanup(void) } } -void panic_puts(const char *str) -{ - NS16550_t port = (NS16550_t)0x3f8; - - NS16550_init(port, 1); - while (*str) - NS16550_putc(port, *str++); -} - int misc_init_r(void) { return 0; diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index be103c0..d1d21ed 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -16,7 +16,6 @@ void init_gd(gd_t *id, u64 *gdt_addr); void setup_gdt(gd_t *id, u64 *gdt_addr); int init_cache(void); int cleanup_before_linux(void); -void panic_puts(const char *str); /* cpu/.../timer.c */ void timer_isr(void *); -- 1.8.2.1

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