May 2015 - U-Boot

[U-Boot] [PATCH] mx6_common: Fix LOADADDR and SYS_TEXT_BASE for MX6SL and MX6SX
by Fabio Estevam 28 May '15

28 May '15

From: Fabio Estevam <fabio.estevam(a)freescale.com> Commit 8183058188cd2d942 ("imx6: centralise common boot options in mx6_common.h") broke boot on mx6sl and mx6sx by assuming that all mx6 SoCs use the same LOADADDR/SYS_TEXT_BASE range, which is not correct. DDR on mx6sx/mx6sl starts at 0x80000000. Adjust LOADADDR/SYS_TEXT_BASE to the proper values for mx6sx/mx6sl, so that these SoCs can boot again. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- include/configs/mx6_common.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 233c6d2..bd16ec2 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -53,10 +53,15 @@ #define CONFIG_REVISION_TAG /* Boot options */ +#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL)) +#define CONFIG_LOADADDR 0x82000000 +#define CONFIG_SYS_TEXT_BASE 0x87800000 +#else #define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 +#endif #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0x17800000 #endif #ifndef CONFIG_BOOTDELAY #define CONFIG_BOOTDELAY 3 -- 1.9.1

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[U-Boot] [PATCH] sunxi/spl: Detect at runtime where SPL was read from
by Daniel Kochmański 28 May '15

28 May '15

This patch makes possible using single `u-boot-sunxi-with-spl.bin` binary for both NAND memory and SD card. Detection where SPL was read from is implemented in `spl_boot_device`. Detection is performed only if `CONFIG_SPL_NAND_SUPPORT` is defined. Unless SD card contains valid signature we assume, that SPL was read from NAND. Signed-off-by: Daniel Kochmański <dkochmanski(a)turtle-solutions.eu> CC: Roy Spliet <r.spliet(a)ultimaker.com> Cc: Ian Campbell <ijc(a)hellion.org.uk> Cc: Hans De Goede <hdegoede(a)redhat.com> --- arch/arm/cpu/armv7/sunxi/board.c | 53 ++++++++++++++++++++++++++-------------- include/configs/sunxi-common.h | 2 -- 2 files changed, 35 insertions(+), 20 deletions(-) diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 70f413f..5e441ba 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -11,6 +11,7 @@ */ #include <common.h> +#include <mmc.h> #include <i2c.h> #include <serial.h> #ifdef CONFIG_SPL_BUILD @@ -109,12 +110,10 @@ void s_init(void) } #ifdef CONFIG_SPL_BUILD +DECLARE_GLOBAL_DATA_PTR; + /* The sunxi internal brom will try to loader external bootloader * from mmc0, nand flash, mmc2. - * - * Unfortunately we can't check how SPL was loaded so assume it's - * always the first SD/MMC controller, unless it was explicitly - * stated that SPL is on nand flash. */ u32 spl_boot_device(void) { @@ -124,17 +123,13 @@ u32 spl_boot_device(void) * enabled build. It has many restrictions and can only boot over USB. */ return BOOT_DEVICE_BOARD; -#elif defined(CONFIG_SPL_NAND_SUPPORT) - /* - * This is compile time configuration informing SPL, that it - * was loaded from nand flash. - */ - return BOOT_DEVICE_NAND; #else + __maybe_unused struct mmc *mmc0; + __maybe_unused char buf[512]; /* - * When booting from the SD card, the "eGON.BT0" signature is expected - * to be found in memory at the address 0x0004 (see the "mksunxiboot" - * tool, which generates this header). + * When booting from the SD card or NAND memory, the "eGON.BT0" + * signature is expected to be found in memory at the address 0x0004 + * (see the "mksunxiboot" tool, which generates this header). * * When booting in the FEL mode over USB, this signature is patched in * memory and replaced with something else by the 'fel' tool. This other @@ -142,13 +137,35 @@ u32 spl_boot_device(void) * valid bootable SD card image (because the BROM would refuse to * execute the SPL in this case). * - * This branch is just making a decision at runtime whether to load - * the main u-boot binary from the SD card (if the "eGON.BT0" signature - * is found) or return to the FEL code in the BROM to wait and receive - * the main u-boot binary over USB. + * This branch is just making a decision at runtime whether to load the + * main u-boot binary from the SD card or NAND memory (if the "eGON.BT0" + * signature is found) or return to the FEL code in the BROM to wait and + * receive the main u-boot binary over USB. If signature is present, + * decision where to boot from (SD card or NAND memory) depends on + * compile options (if SPL_NAND_SUPPORT isn't defined, we assume we boot + * from SD card), and runtime check - if SD card doesn't contain valid + * signature we assume that SPL was loaded from NAND. */ - if (readl(4) == 0x4E4F4765 && readl(8) == 0x3054422E) /* eGON.BT0 */ + if (readl(4) == 0x4E4F4765 && readl(8) == 0x3054422E) { /* eGON.BT0 */ +#if !defined(CONFIG_SPL_NAND_SUPPORT) return BOOT_DEVICE_MMC1; +#else + mmc_initialize(gd->bd); + mmc0 = find_mmc_device(0); + /* + * Figure out where we're booting from. Try mmc0 first, just + * like the brom does. If it doesn't contain valid signature, + * assume SPL was loaded from NAND memory. + */ + if (mmc0 && mmc_getcd(mmc0) && mmc_init(mmc0) == 0 && + mmc0->block_dev.block_read(0, 16, 1, buf) == 1) { + buf[12] = 0; + if (strcmp(&buf[4], "eGON.BT0") == 0) + return BOOT_DEVICE_MMC1; + } + return BOOT_DEVICE_NAND; +#endif + } else return BOOT_DEVICE_BOARD; #endif diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index cce0441..e4db777 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -106,10 +106,8 @@ #define CONFIG_CMD_MMC #define CONFIG_MMC_SUNXI #define CONFIG_MMC_SUNXI_SLOT 0 -#if !defined(CONFIG_SPL_NAND_SUPPORT) #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */ -#endif /* CONFIG_SPL_NAND_SUPPORT */ #endif /* 4MB of malloc() pool */ -- 2.4.1

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[U-Boot] [PATCH 1/5] warp: Adjust CONFIG_SYS_DFU_DATA_BUF_SIZE
by Fabio Estevam 28 May '15

28 May '15

From: Fabio Estevam <fabio.estevam(a)freescale.com> Adjust CONFIG_SYS_DFU_DATA_BUF_SIZE in order to avoid the following error when running the dfu command: => dfu 0 mmc 0 dfu_get_buf: Could not memalign 0x2000000 bytes Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- include/configs/warp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/warp.h b/include/configs/warp.h index 2673948..f0a912b 100644 --- a/include/configs/warp.h +++ b/include/configs/warp.h @@ -94,7 +94,7 @@ #define CONFIG_CMD_DFU #define CONFIG_DFU_FUNCTION #define CONFIG_DFU_MMC -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M #define DFU_DEFAULT_POLL_TIMEOUT 300 #define CONFIG_EXTRA_ENV_SETTINGS \ -- 1.9.1

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[U-Boot] [PATCH] pci: imx: display message if no pcie link
by Tim Harvey 28 May '15

28 May '15

If CONFIG_PCI_SCAN_SHOW enabled then lets print a message of no link was detected. Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- drivers/pci/pcie_imx.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index fd7e4d4..ca485ba 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -588,7 +588,9 @@ static int imx_pcie_link_up(void) udelay(10); count++; if (count >= 2000) { - debug("phy link never came up\n"); +#ifdef CONFIG_PCI_SCAN_SHOW + puts("PCI: pcie phy link never came up\n"); +#endif debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0), readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1)); -- 1.9.1

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[U-Boot] [PATCH 1/4] zynqmp: gem: Set data bus with to 64bit for arm64
by Michal Simek 28 May '15

28 May '15

From: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Set the data bus width to 64-bit AMBA Databus width in config register. Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/net/zynq_gem.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index c723dbb0a694..22195805e6d6 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -58,7 +58,14 @@ #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */ #define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */ -#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_NWCFG_FDEN | \ +#ifdef CONFIG_TARGET_XILINX_ZYNQMP +# define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ +#else +# define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */ +#endif + +#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ + ZYNQ_GEM_NWCFG_FDEN | \ ZYNQ_GEM_NWCFG_FSREM | \ ZYNQ_GEM_NWCFG_MDCCLKDIV) -- 2.3.5

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[U-Boot] [PATCH] board: add support for Vision System's Baltos Industrial PC
by Felipe Balbi 28 May '15

28 May '15

From: Yegor Yefremov <yegorslists(a)googlemail.com> Vision Systems's Baltos is based on AM335x SoC from Texas Instruments. This patch adds support such Industrial PCs in mainline u-boot. [ balbi(a)ti.com: updated original patch to current u-boot ] Signed-off-by: Yegor Yefremov <yegorslists(a)googlemail.com> Signed-off-by: Felipe Balbi <balbi(a)ti.com> --- This is a respin of patch available from [1] [1] https://github.com/visionsystemsgmbh/onrisc_br_bsp/blob/master/board/vscom/… arch/arm/Kconfig | 6 + board/vscom/baltos/Kconfig | 33 +++ board/vscom/baltos/Makefile | 13 ++ board/vscom/baltos/README | 1 + board/vscom/baltos/board.c | 474 ++++++++++++++++++++++++++++++++++++++++ board/vscom/baltos/board.h | 90 ++++++++ board/vscom/baltos/mux.c | 194 ++++++++++++++++ board/vscom/baltos/u-boot.lds | 128 +++++++++++ configs/am335x_baltos_defconfig | 7 + include/configs/baltos.h | 346 +++++++++++++++++++++++++++++ 10 files changed, 1292 insertions(+) create mode 100644 board/vscom/baltos/Kconfig create mode 100644 board/vscom/baltos/Makefile create mode 100644 board/vscom/baltos/README create mode 100644 board/vscom/baltos/board.c create mode 100644 board/vscom/baltos/board.h create mode 100644 board/vscom/baltos/mux.c create mode 100644 board/vscom/baltos/u-boot.lds create mode 100644 configs/am335x_baltos_defconfig create mode 100644 include/configs/baltos.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7ed0e2052107..608c39f91843 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -376,6 +376,11 @@ config TARGET_AM335X_EVM select CPU_V7 select SUPPORT_SPL +config TARGET_AM335X_BALTOS + bool "Support am335x_baltos" + select CPU_V7 + select SUPPORT_SPL + config TARGET_AM43XX_EVM bool "Support am43xx_evm" select CPU_V7 @@ -868,6 +873,7 @@ source "board/st/stv0991/Kconfig" source "board/sunxi/Kconfig" source "board/syteco/zmx25/Kconfig" source "board/tbs/tbs2910/Kconfig" +source "board/vscom/baltos/Kconfig" source "board/ti/am335x/Kconfig" source "board/ti/am43xx/Kconfig" source "board/birdland/bav335x/Kconfig" diff --git a/board/vscom/baltos/Kconfig b/board/vscom/baltos/Kconfig new file mode 100644 index 000000000000..880b6f2ee5f3 --- /dev/null +++ b/board/vscom/baltos/Kconfig @@ -0,0 +1,33 @@ +if TARGET_AM335X_BALTOS + +config SYS_BOARD + default "baltos" + +config SYS_VENDOR + default "vscom" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "baltos" + +config CONS_INDEX + int "UART used for console" + range 1 6 + default 1 + help + The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced + in documentation, etc) available to it. Depending on your specific + board you may want something other than UART0. + +config DM + default y + +config DM_GPIO + default y if DM + +config DM_SERIAL + default y if DM + +endif diff --git a/board/vscom/baltos/Makefile b/board/vscom/baltos/Makefile new file mode 100644 index 000000000000..804ac379dbd4 --- /dev/null +++ b/board/vscom/baltos/Makefile @@ -0,0 +1,13 @@ +# +# Makefile +# +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) +obj-y := mux.o +endif + +obj-y += board.o diff --git a/board/vscom/baltos/README b/board/vscom/baltos/README new file mode 100644 index 000000000000..f744ace9972f --- /dev/null +++ b/board/vscom/baltos/README @@ -0,0 +1 @@ +BSP for VScom OnRISC Balios family devices, like Balios iR 5221. diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c new file mode 100644 index 000000000000..69264b706b10 --- /dev/null +++ b/board/vscom/baltos/board.c @@ -0,0 +1,474 @@ +/* + * board.c + * + * Board functions for TI AM335X based boards + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <spl.h> +#include <asm/arch/cpu.h> +#include <asm/arch/hardware.h> +#include <asm/arch/omap.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mem.h> +#include <asm/arch/mux.h> +#include <asm/io.h> +#include <asm/emif.h> +#include <asm/gpio.h> +#include <i2c.h> +#include <miiphy.h> +#include <cpsw.h> +#include <power/tps65217.h> +#include <power/tps65910.h> +#include <environment.h> +#include <watchdog.h> +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* GPIO that controls power to DDR on EVM-SK */ +#define GPIO_DDR_VTT_EN 7 +#define DIP_S1 44 + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +static int baltos_set_console(void) +{ + int val, i, dips = 0; + char buf[7]; + + for (i = 0; i < 4; i++) { + sprintf(buf, "dip_s%d", i + 1); + + if (gpio_request(DIP_S1 + i, buf)) { + printf("failed to export GPIO %d\n", DIP_S1 + i); + return 0; + } + + if (gpio_direction_input(DIP_S1 + i)) { + printf("failed to set GPIO %d direction\n", DIP_S1 + i); + return 0; + } + + val = gpio_get_value(DIP_S1 + i); + dips |= val << i; + } + + printf("DIPs: 0x%1x\n", (~dips) & 0xf); + + if ((dips & 0xf) == 0xe) + setenv("console", "ttyUSB0,115200n8"); + + return 0; +} + +static int read_eeprom(BSP_VS_HWPARAM *header) +{ + i2c_set_bus_num(1); + + /* Check if baseboard eeprom is available */ + if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { + puts("Could not probe the EEPROM; something fundamentally " + "wrong on the I2C bus.\n"); + return -ENODEV; + } + + /* read the eeprom using i2c */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, + sizeof(BSP_VS_HWPARAM))) { + puts("Could not read the EEPROM; something fundamentally" + " wrong on the I2C bus.\n"); + return -EIO; + } + + if (header->Magic != 0xDEADBEEF) { + + printf("Incorrect magic number (0x%x) in EEPROM\n", + header->Magic); + + /* fill default values */ + header->SystemId = 211; + header->MAC1[0] = 0x00; + header->MAC1[1] = 0x00; + header->MAC1[2] = 0x00; + header->MAC1[3] = 0x00; + header->MAC1[4] = 0x00; + header->MAC1[5] = 0x01; + + header->MAC2[0] = 0x00; + header->MAC2[1] = 0x00; + header->MAC2[2] = 0x00; + header->MAC2[3] = 0x00; + header->MAC2[4] = 0x00; + header->MAC2[5] = 0x02; + + header->MAC3[0] = 0x00; + header->MAC3[1] = 0x00; + header->MAC3[2] = 0x00; + header->MAC3[3] = 0x00; + header->MAC3[4] = 0x00; + header->MAC3[5] = 0x03; + } + + return 0; +} + +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) + +static const struct ddr_data ddr3_baltos_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, +}; + +static const struct cmd_control ddr3_baltos_cmd_ctrl_data = { + .cmd0csratio = MT41K256M16HA125E_RATIO, + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd1csratio = MT41K256M16HA125E_RATIO, + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd2csratio = MT41K256M16HA125E_RATIO, + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_baltos_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, +}; + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + return (serial_tstc() && serial_getc() == 'c'); +} +#endif + +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr = { + 266, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_ddr_evm_sk = { + 303, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_ddr_baltos = { + 400, OSC-1, 1, -1, -1, -1, -1}; + +void am33xx_spl_board_init(void) +{ + int mpu_vdd; + int sil_rev; + + /* Get the frequency */ + dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); + + /* + * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all + * MPU frequencies we support we use a CORE voltage of + * 1.1375V. For MPU voltage we need to switch based on + * the frequency we are running at. + */ + i2c_set_bus_num(1); + + if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) { + puts("i2c: cannot access TPS65910\n"); + return; + } + + /* + * Depending on MPU clock and PG we will need a different + * VDD to drive at that speed. + */ + sil_rev = readl(&cdev->deviceid) >> 28; + mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, + dpll_mpu_opp100.m); + + /* Tell the TPS65910 to use i2c */ + tps65910_set_i2c_control(); + + /* First update MPU voltage. */ + if (tps65910_voltage_update(MPU, mpu_vdd)) + return; + + /* Second, update the CORE voltage. */ + if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3)) + return; + + /* Set CORE Frequencies to OPP100 */ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + + /* Set MPU Frequency to what we detected now that voltages are set */ + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); + + writel(0x000010ff, PRM_DEVICE_INST + 4); +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + enable_i2c1_pin_mux(); + i2c_set_bus_num(1); + + return &dpll_ddr_baltos; +} + +void set_uart_mux_conf(void) +{ + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + enable_board_pin_mux(); +} + +const struct ctrl_ioregs ioregs_baltos = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + +void sdram_init(void) +{ + gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); + gpio_direction_output(GPIO_DDR_VTT_EN, 1); + + config_ddr(400, &ioregs_baltos, + &ddr3_baltos_data, + &ddr3_baltos_cmd_ctrl_data, + &ddr3_baltos_emif_reg_data, 0); +} +#endif + +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ +#if defined(CONFIG_HW_WATCHDOG) + hw_watchdog_init(); +#endif + + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; +#if defined(CONFIG_NOR) || defined(CONFIG_NAND) + gpmc_init(); +#endif + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + int node, ret; + unsigned char mac_addr[6]; + BSP_VS_HWPARAM header; + + /* get production data */ + if (read_eeprom(&header)) + return 0; + + /* setup MAC1 */ + mac_addr[0] = header.MAC1[0]; + mac_addr[1] = header.MAC1[1]; + mac_addr[2] = header.MAC1[2]; + mac_addr[3] = header.MAC1[3]; + mac_addr[4] = header.MAC1[4]; + mac_addr[5] = header.MAC1[5]; + + + node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100200"); + if (node < 0) { + printf("no /soc/fman/ethernet path offset\n"); + return -ENODEV; + } + + ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6); + if (ret) { + printf("error setting local-mac-address property\n"); + return -ENODEV; + } + + /* setup MAC2 */ + mac_addr[0] = header.MAC2[0]; + mac_addr[1] = header.MAC2[1]; + mac_addr[2] = header.MAC2[2]; + mac_addr[3] = header.MAC2[3]; + mac_addr[4] = header.MAC2[4]; + mac_addr[5] = header.MAC2[5]; + + node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100300"); + if (node < 0) { + printf("no /soc/fman/ethernet path offset\n"); + return -ENODEV; + } + + ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6); + if (ret) { + printf("error setting local-mac-address property\n"); + return -ENODEV; + } + + printf("\nFDT was successfully setup\n"); + + return 0; +} + +static struct module_pin_mux dip_pin_mux[] = { + {OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )}, /* GPIO1_12 */ + {OFFSET(gpmc_ad13), (MODE(7) | RXACTIVE )}, /* GPIO1_13 */ + {OFFSET(gpmc_ad14), (MODE(7) | RXACTIVE )}, /* GPIO1_14 */ + {OFFSET(gpmc_ad15), (MODE(7) | RXACTIVE )}, /* GPIO1_15 */ + {-1}, +}; + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + BSP_VS_HWPARAM header; + char model[4]; + + /* get production data */ + if (read_eeprom(&header)) { + sprintf(model, "211"); + } else { + sprintf(model, "%d", header.SystemId); + if (header.SystemId == 215) { + configure_module_pin_mux(dip_pin_mux); + baltos_set_console(); + } + } + setenv("board_name", model); +#endif + + return 0; +} +#endif + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 0, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 7, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 2, + .slave_data = cpsw_slaves, + .active_slave = 1, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; +#endif + +#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \ + && defined(CONFIG_SPL_BUILD)) || \ + ((defined(CONFIG_DRIVER_TI_CPSW) || \ + defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \ + !defined(CONFIG_SPL_BUILD)) +int board_eth_init(bd_t *bis) +{ + int rv, n = 0; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + __maybe_unused struct am335x_baseboard_id header; + + /* + * Note here that we're using CPSW1 since that has a 1Gbit PHY while + * CSPW0 has a 100Mbit PHY. + * + * On product, CPSW1 maps to port labeled WAN. + */ + + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid1l); + mac_hi = readl(&cdev->macid1h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) + if (!getenv("ethaddr")) { + printf("<ethaddr> not set. Validating first E-fuse MAC\n"); + + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + +#ifdef CONFIG_DRIVER_TI_CPSW + writel((GMII1_SEL_RMII | GMII2_SEL_RGMII | RGMII2_IDMODE), &cdev->miisel); + cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII; + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; +#endif + + /* + * + * CPSW RGMII Internal Delay Mode is not supported in all PVT + * operating points. So we must set the TX clock delay feature + * in the AR8051 PHY. Since we only support a single ethernet + * device in U-Boot, we only do this for the first instance. + */ +#define AR8051_PHY_DEBUG_ADDR_REG 0x1d +#define AR8051_PHY_DEBUG_DATA_REG 0x1e +#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 +#define AR8051_RGMII_TX_CLK_DLY 0x100 + const char *devname; + devname = miiphy_get_current_dev(); + + miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_ADDR_REG, + AR8051_DEBUG_RGMII_CLK_DLY_REG); + miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_DATA_REG, + AR8051_RGMII_TX_CLK_DLY); +#endif + return n; +} +#endif diff --git a/board/vscom/baltos/board.h b/board/vscom/baltos/board.h new file mode 100644 index 000000000000..1ae59a7f66ca --- /dev/null +++ b/board/vscom/baltos/board.h @@ -0,0 +1,90 @@ +/* + * board.h + * + * TI AM335x boards information header + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * TI AM335x parts define a system EEPROM that defines certain sub-fields. + * We use these fields to in turn see what board we are on, and what + * that might require us to set or not set. + */ +#define HDR_NO_OF_MAC_ADDR 3 +#define HDR_ETH_ALEN 6 +#define HDR_NAME_LEN 8 + +struct am335x_baseboard_id { + unsigned int magic; + char name[HDR_NAME_LEN]; + char version[4]; + char serial[12]; + char config[32]; + char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN]; +}; + +typedef struct _BSP_VS_HWPARAM // v1.0 +{ + uint32_t Magic; + uint32_t HwRev; + uint32_t SerialNumber; + char PrdDate[11]; // as a string ie. "01.01.2006" + uint16_t SystemId; + uint8_t MAC1[6]; // internal EMAC + uint8_t MAC2[6]; // SMSC9514 + uint8_t MAC3[6]; // WL1271 WLAN +} __attribute__ ((packed)) BSP_VS_HWPARAM; + +static inline int board_is_bone(struct am335x_baseboard_id *header) +{ + return !strncmp(header->name, "A335BONE", HDR_NAME_LEN); +} + +static inline int board_is_bone_lt(struct am335x_baseboard_id *header) +{ + return !strncmp(header->name, "A335BNLT", HDR_NAME_LEN); +} + +static inline int board_is_evm_sk(struct am335x_baseboard_id *header) +{ + return !strncmp("A335X_SK", header->name, HDR_NAME_LEN); +} + +static inline int board_is_idk(struct am335x_baseboard_id *header) +{ + return !strncmp(header->config, "SKU#02", 6); +} + +static inline int board_is_gp_evm(struct am335x_baseboard_id *header) +{ + return !strncmp("A33515BB", header->name, HDR_NAME_LEN); +} + +static inline int board_is_evm_15_or_later(struct am335x_baseboard_id *header) +{ + return (board_is_gp_evm(header) && + strncmp("1.5", header->version, 3) <= 0); +} + +/* + * We have three pin mux functions that must exist. We must be able to enable + * uart0, for initial output and i2c0 to read the main EEPROM. We then have a + * main pinmux function that can be overridden to enable all other pinmux that + * is required on the board. + */ +void enable_uart0_pin_mux(void); +void enable_uart1_pin_mux(void); +void enable_uart2_pin_mux(void); +void enable_uart3_pin_mux(void); +void enable_uart4_pin_mux(void); +void enable_uart5_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_i2c1_pin_mux(void); +void enable_board_pin_mux(void); +#endif diff --git a/board/vscom/baltos/mux.c b/board/vscom/baltos/mux.c new file mode 100644 index 000000000000..8783b25b5f32 --- /dev/null +++ b/board/vscom/baltos/mux.c @@ -0,0 +1,194 @@ +/* + * mux.c + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/hardware.h> +#include <asm/arch/mux.h> +#include <asm/io.h> +#include <i2c.h> +#include "board.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {-1}, +}; + +static struct module_pin_mux uart1_pin_mux[] = { + {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */ + {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */ + {-1}, +}; + +static struct module_pin_mux uart2_pin_mux[] = { + {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */ + {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */ + {-1}, +}; + +static struct module_pin_mux uart3_pin_mux[] = { + {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ + {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ + {-1}, +}; + +static struct module_pin_mux uart4_pin_mux[] = { + {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */ + {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */ + {-1}, +}; + +static struct module_pin_mux uart5_pin_mux[] = { + {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */ + {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */ + {-1}, +}; + +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ + //{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ + {-1}, +}; + +static struct module_pin_mux i2c1_pin_mux[] = { + {OFFSET(spi0_d1), (MODE(2) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ + {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ + {-1}, +}; + +static struct module_pin_mux gpio0_7_pin_mux[] = { + {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */ + {-1}, +}; + +static struct module_pin_mux rmii1_pin_mux[] = { + {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */ + {OFFSET(mii1_txen), MODE(1)}, /* RGMII1_TCTL */ + {OFFSET(mii1_txd1), MODE(1)}, /* RGMII1_TCTL */ + {OFFSET(mii1_txd0), MODE(1)}, /* RGMII1_TCTL */ + {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */ + {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */ + {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RGMII1_TCTL */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux rgmii2_pin_mux[] = { + {OFFSET(gpmc_a0), MODE(2)}, /* RGMII1_TCTL */ + {OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ + {OFFSET(gpmc_a2), MODE(2)}, /* RGMII1_TD3 */ + {OFFSET(gpmc_a3), MODE(2)}, /* RGMII1_TD2 */ + {OFFSET(gpmc_a4), MODE(2)}, /* RGMII1_TD1 */ + {OFFSET(gpmc_a5), MODE(2)}, /* RGMII1_TD0 */ + {OFFSET(gpmc_a6), MODE(2)}, /* RGMII1_TCLK */ + {OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ + {OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ + {OFFSET(gpmc_a9), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ + {OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ + {OFFSET(gpmc_a11), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_uart1_pin_mux(void) +{ + configure_module_pin_mux(uart1_pin_mux); +} + +void enable_uart2_pin_mux(void) +{ + configure_module_pin_mux(uart2_pin_mux); +} + +void enable_uart3_pin_mux(void) +{ + configure_module_pin_mux(uart3_pin_mux); +} + +void enable_uart4_pin_mux(void) +{ + configure_module_pin_mux(uart4_pin_mux); +} + +void enable_uart5_pin_mux(void) +{ + configure_module_pin_mux(uart5_pin_mux); +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_i2c1_pin_mux(void) +{ + configure_module_pin_mux(i2c1_pin_mux); +} + +void enable_board_pin_mux() +{ + /* Baltos */ + configure_module_pin_mux(i2c1_pin_mux); + configure_module_pin_mux(gpio0_7_pin_mux); + configure_module_pin_mux(rgmii2_pin_mux); + configure_module_pin_mux(rmii1_pin_mux); + configure_module_pin_mux(mmc0_pin_mux); + +#if defined(CONFIG_NAND) + configure_module_pin_mux(nand_pin_mux); +#endif +} diff --git a/board/vscom/baltos/u-boot.lds b/board/vscom/baltos/u-boot.lds new file mode 100644 index 000000000000..315ba5b99a72 --- /dev/null +++ b/board/vscom/baltos/u-boot.lds @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.__image_copy_start) + *(.vectors) + CPUDIR/start.o (.text*) + board/vscom/baltos/built-in.o (.text*) + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + + . = .; + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + + .image_copy_end : + { + *(.__image_copy_end) + } + + .rel_dyn_start : + { + *(.__rel_dyn_start) + } + + .rel.dyn : { + *(.rel*) + } + + .rel_dyn_end : + { + *(.__rel_dyn_end) + } + + .hash : { *(.hash*) } + + .end : + { + *(.__end) + } + + _image_binary_end = .; + + /* + * Deprecated: this MMU section is used by pxa at present but + * should not be used by new boards/CPUs. + */ + . = ALIGN(4096); + .mmutable : { + *(.mmutable) + } + +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + __bss_base = .; + } + + .bss __bss_base (OVERLAY) : { + *(.bss*) + . = ALIGN(4); + __bss_limit = .; + } + + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); + } + + .dynsym _image_binary_end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .gnu.hash : { *(.gnu.hash) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } +} diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig new file mode 100644 index 000000000000..679b04f1984c --- /dev/null +++ b/configs/am335x_baltos_defconfig @@ -0,0 +1,7 @@ +CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SYS_EXTRA_OPTIONS="NAND" +CONFIG_CONS_INDEX=1 +CONFIG_ARM=y +CONFIG_TARGET_AM335X_BALTOS=y diff --git a/include/configs/baltos.h b/include/configs/baltos.h new file mode 100644 index 000000000000..512facf20752 --- /dev/null +++ b/include/configs/baltos.h @@ -0,0 +1,346 @@ +/* + * am335x_evm.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __CONFIG_BALTOS_H +#define __CONFIG_BALTOS_H + +#define CONFIG_CMD_FAT +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_NFS + +#include <configs/ti_am335x_common.h> + +#define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */ +#define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM +#define CONFIG_BOARD_LATE_INIT + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +/* Custom script for NOR */ +#define CONFIG_SYS_LDSCRIPT "board/vscom/baltos/u-boot.lds" + +/* Always 128 KiB env size */ +#define CONFIG_ENV_SIZE (128 << 10) + +/* Enhance our eMMC support / experience. */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART + +/* FIT support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ +#define CONFIG_OF_BOARD_SETUP + +/* UBI Support */ +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS + +/* I2C configuration */ +#undef CONFIG_SYS_OMAP24_I2C_SPEED +#define CONFIG_SYS_OMAP24_I2C_SPEED 10000 + +#ifdef CONFIG_NAND +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000 +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS 0x00080000 /* os parameters */ +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif +#define NANDARGS \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "${mtdparts} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "nandroot=ubi0:rootfs rw ubi.mtd=5\0" \ + "nandrootfstype=ubifs rootwait=1\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "setenv loadaddr 0x84000000; " \ + "ubi part UBI; " \ + "ubifsmount ubi0:kernel; " \ + "ubifsload $loadaddr kernel-fit.itb;" \ + "ubifsumount; " \ + "bootm ${loadaddr}#conf${board_name}\0" +#else +#define NANDARGS "" +#endif + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + "boot_fdt=try\0" \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "fdtfile=undefined\0" \ + "console=ttyO0,115200n8\0" \ + "partitions=" \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \ + "optargs=\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 ro\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "rootpath=/export/rootfs\0" \ + "nfsopts=nolock\0" \ + "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \ + "::off\0" \ + "ramroot=/dev/ram0 rw\0" \ + "ramrootfstype=ext2\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "${mtdparts} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "spiroot=/dev/mtdblock4 rw\0" \ + "spirootfstype=jffs2\0" \ + "spisrcaddr=0xe0000\0" \ + "spiimgsize=0x362000\0" \ + "spibusno=0\0" \ + "spiargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${spiroot} " \ + "rootfstype=${spirootfstype}\0" \ + "netargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=/dev/nfs " \ + "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ + "ip=dhcp\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ + "ramargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${ramroot} " \ + "rootfstype=${ramrootfstype}\0" \ + "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ + "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "mmcloados=run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdtaddr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "mmcboot=mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loadimage; then " \ + "run mmcloados;" \ + "fi;" \ + "fi;\0" \ + "spiboot=echo Booting from spi ...; " \ + "run spiargs; " \ + "sf probe ${spibusno}:0; " \ + "sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; " \ + "bootz ${loadaddr}\0" \ + "netboot=echo Booting from network ...; " \ + "setenv autoload no; " \ + "dhcp; " \ + "tftp ${loadaddr} ${bootfile}; " \ + "tftp ${fdtaddr} ${fdtfile}; " \ + "run netargs; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ + "ramboot=echo Booting from ramdisk ...; " \ + "run ramargs; " \ + "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \ + "findfdt=setenv fdtfile am335x-baltos.dtb\0" \ + NANDARGS + /*DFUARGS*/ +#endif + +#define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ + "run mmcboot;" \ + "setenv mmcdev 1; " \ + "setenv bootpart 1:2; " \ + "run mmcboot;" \ + "run nandboot;" + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_ENV_IS_IN_FAT +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_DEVICE_AND_PART "0:1" +#define FAT_ENV_FILE "uboot.env" +#define CONFIG_FAT_WRITE + +#define CONFIG_CMD_EEPROM +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_MULTI_EEPROMS + +/* PMIC support */ +#define CONFIG_POWER_TPS65910 + +/* SPL */ +#ifndef CONFIG_NOR_BOOT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT + +/* Bootcount using the RTC block */ +#define CONFIG_BOOTCOUNT_LIMIT +#define CONFIG_BOOTCOUNT_AM33XX + +/* USB gadget RNDIS */ +/*#define CONFIG_SPL_MUSB_NEW_SUPPORT*/ + +/* General network SPL, both CPSW and USB gadget RNDIS */ +/*#define CONFIG_SPL_NET_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"*/ + +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" + +#ifdef CONFIG_NAND +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_NAND_OMAP_ELM +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#endif +#endif + +/* + * USB configuration. We enable MUSB support, both for host and for + * gadget. We set USB0 as peripheral and USB1 as host, based on the + * board schematic and physical port wired to each. Then for host we + * add mass storage support and for gadget we add both RNDIS ethernet + * and DFU. + */ +#define CONFIG_USB_MUSB_DSPS +#define CONFIG_ARCH_MISC_INIT +#define CONFIG_MUSB_GADGET +#define CONFIG_MUSB_PIO_ONLY +#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT +#define CONFIG_USB_GADGET +#define CONFIG_USBDOWNLOAD_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_MUSB_HOST +#define CONFIG_AM335X_USB0 +#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL +#define CONFIG_AM335X_USB1 +#define CONFIG_AM335X_USB1_MODE MUSB_HOST + +#ifdef CONFIG_MUSB_HOST +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#endif + +#ifdef CONFIG_MUSB_GADGET +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_RNDIS +#define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00" + +/* USB TI's IDs */ +#define CONFIG_G_DNL_VENDOR_NUM 0x0403 +#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00 +#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments" +#endif /* CONFIG_MUSB_GADGET */ + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT) +/* disable host part of MUSB in SPL */ +#undef CONFIG_MUSB_HOST +/* disable EFI partitions and partition UUID support */ +#undef CONFIG_PARTITION_UUIDS +#undef CONFIG_EFI_PARTITION +/* + * Disable CPSW SPL support so we fit within the 101KiB limit. + */ +#undef CONFIG_SPL_ETH_SUPPORT +#endif + +/* Network. */ +#define CONFIG_PHY_GIGE +#define CONFIG_PHYLIB +#define CONFIG_PHY_ADDR 0 +#define CONFIG_PHY_SMSC +#define CONFIG_MII +#define CONFIG_CMD_MII +#define CONFIG_PHY_ATHEROS + +/* NAND support */ +#ifdef CONFIG_NAND +#define CONFIG_CMD_NAND +#define GPMC_NAND_ECC_LP_x8_LAYOUT 1 +#if !defined(CONFIG_SPI_BOOT) && !defined(CONFIG_NOR_BOOT) +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \ + "128k(SPL.backup1)," \ + "128k(SPL.backup2)," \ + "128k(SPL.backup3)," \ + "1920k(u-boot)," \ + "-(UBI)" +#endif +#endif + +#endif /* ! __CONFIG_BALTOS_H */ -- 2.4.0.rc3

3 2

[U-Boot] [PATCH 0/1] Add Toby-Churchill SL50 board support
by Enric Balletbo i Serra 27 May '15

27 May '15

This patch series adds support for SL50 board based on TI AM335x SoC. Best regards, Enric Balletbo i Serra (1): board: Add Toby-Churchill SL50 board support. arch/arm/Kconfig | 6 + board/tcl/sl50/Kconfig | 34 ++++ board/tcl/sl50/MAINTAINERS | 6 + board/tcl/sl50/Makefile | 13 ++ board/tcl/sl50/board.c | 387 ++++++++++++++++++++++++++++++++++++++++++ board/tcl/sl50/board.h | 22 +++ board/tcl/sl50/mux.c | 161 ++++++++++++++++++ configs/am335x_sl50_defconfig | 7 + include/configs/am335x_sl50.h | 141 +++++++++++++++ 9 files changed, 777 insertions(+) create mode 100644 board/tcl/sl50/Kconfig create mode 100644 board/tcl/sl50/MAINTAINERS create mode 100644 board/tcl/sl50/Makefile create mode 100644 board/tcl/sl50/board.c create mode 100644 board/tcl/sl50/board.h create mode 100644 board/tcl/sl50/mux.c create mode 100644 configs/am335x_sl50_defconfig create mode 100644 include/configs/am335x_sl50.h -- 2.1.0

2 2

[U-Boot] soft-i2c and i2c-gpio issues with at91
by Matt Wood 27 May '15

27 May '15

Hi all, I am trying to get a bitbanged i2c port working with u-boot on an Atmel SAMA5D3 platform. I have added DT bindings to support the I2C drivers however when I try to select the bus on the u-boot command line I consistently get an error in gpio-uclass: _gpio_request_by_name_nodev: uclass_get_device_by_of_offset failed _gpio_request_by_name_nodev: Node 'soft-i2c@1', property 'gpios', failed to request GPIO index 0: -19 Each driver always fails at the get_dev_by_offset routine. I suspect some issue with the way the GPIO is defined or is not setup correctly. Has anyone seen this or have any advice on where to look? This is the relevant part of the device tree: aliases { i2c0 = "/soft-i2c@1"; }; soft-i2c@1 { #address-cells = <1>; #size-cells = <0>; /* compatible = "soft-i2c"; */ compatible = "i2c-gpio"; /* clock-frequency = <100000>; */ /* pinctrl-names = "default"; pinctrl-0 = <&pinctrl_soft_i2c>; */ /* Define the proper GPIO pins */ /* clock-pin = <&pioA 31 0>; data-pin = <&pioA 30 0>; */ gpios = <&pioA 30 0 /* SDA */ &pioA 31 0>; /* SCL */ i2c-gpio,sda-open-drain; i2c-gpio,scl-open-drain; i2c-gpio,delay-us =<3>; }; }; Thanks, Matt.

4 8

[U-Boot] [PATCH 5/6] x86: qemu: Create i440fx and q35 board configuration and device tree
by Bin Meng 27 May '15

27 May '15

Although the two qemu-x86 targets (i440fx and q35) share a lot in common, they still have something that cannot easily handled in one place (like different configurations, different properties in the device tree). Split to create two dedicated board configuration and device tree files and make the i440fx be the default build target. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/dts/Makefile | 3 +- arch/x86/dts/qemu-x86_i440fx.dts | 34 +++++++++++++++ arch/x86/dts/{qemu-x86.dts => qemu-x86_q35.dts} | 2 +- board/coreboot/coreboot/Kconfig | 4 +- board/emulation/qemu-x86/Kconfig | 19 +++++++-- configs/qemu-x86_defconfig | 1 - doc/README.x86 | 13 +++++- include/configs/{qemu-x86.h => qemu-x86_i440fx.h} | 20 ++------- include/configs/qemu-x86_q35.h | 52 +++++++++++++++++++++++ 9 files changed, 122 insertions(+), 26 deletions(-) create mode 100644 arch/x86/dts/qemu-x86_i440fx.dts rename arch/x86/dts/{qemu-x86.dts => qemu-x86_q35.dts} (95%) rename include/configs/{qemu-x86.h => qemu-x86_i440fx.h} (78%) create mode 100644 include/configs/qemu-x86_q35.h diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index ca2eab3..f86514c 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -3,7 +3,8 @@ dtb-y += chromebook_link.dtb \ crownbay.dtb \ galileo.dtb \ minnowmax.dtb \ - qemu-x86.dtb + qemu-x86_i440fx.dtb \ + qemu-x86_q35.dtb targets += $(dtb-y) diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts new file mode 100644 index 0000000..4cf843b --- /dev/null +++ b/arch/x86/dts/qemu-x86_i440fx.dts @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +/include/ "skeleton.dtsi" +/include/ "serial.dtsi" + +/ { + model = "QEMU x86 (I440FX)"; + compatible = "qemu,x86"; + + config { + silent_console = <0>; + }; + + chosen { + stdout-path = "/serial"; + }; + + pci { + compatible = "pci-x86"; + #address-cells = <3>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000 + 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + }; + +}; diff --git a/arch/x86/dts/qemu-x86.dts b/arch/x86/dts/qemu-x86_q35.dts similarity index 95% rename from arch/x86/dts/qemu-x86.dts rename to arch/x86/dts/qemu-x86_q35.dts index f1291b5..6c89283 100644 --- a/arch/x86/dts/qemu-x86.dts +++ b/arch/x86/dts/qemu-x86_q35.dts @@ -10,7 +10,7 @@ /include/ "serial.dtsi" / { - model = "QEMU x86"; + model = "QEMU x86 (Q35)"; compatible = "qemu,x86"; config { diff --git a/board/coreboot/coreboot/Kconfig b/board/coreboot/coreboot/Kconfig index 69e3437..2157c1b 100644 --- a/board/coreboot/coreboot/Kconfig +++ b/board/coreboot/coreboot/Kconfig @@ -16,14 +16,14 @@ comment "coreboot-specific options" config SYS_CONFIG_NAME string "Board configuration file" - default "qemu-x86" + default "qemu-x86_i440fx" help This option selects the board configuration file in include/configs/ directory to be used to build U-Boot for coreboot. config DEFAULT_DEVICE_TREE string "Board Device Tree Source (dts) file" - default "qemu-x86" + default "qemu-x86_i440fx" help This option selects the board Device Tree Source (dts) file in arch/x86/dts/ directory to be used to build U-Boot for coreboot. diff --git a/board/emulation/qemu-x86/Kconfig b/board/emulation/qemu-x86/Kconfig index e777ef4..fbf9018 100644 --- a/board/emulation/qemu-x86/Kconfig +++ b/board/emulation/qemu-x86/Kconfig @@ -9,9 +9,6 @@ config SYS_VENDOR config SYS_SOC default "qemu" -config SYS_CONFIG_NAME - default "qemu-x86" - config SYS_TEXT_BASE default 0xfff00000 @@ -21,4 +18,20 @@ config BOARD_SPECIFIC_OPTIONS # dummy select QEMU select BOARD_ROMSIZE_KB_1024 +comment "qemu-specific options" + +config SYS_CONFIG_NAME + string "Board configuration file" + default "qemu-x86_i440fx" + help + This option selects the board configuration file in include/configs/ + directory to be used to build U-Boot for qemu-x86. + +config DEFAULT_DEVICE_TREE + string "Board Device Tree Source (dts) file" + default "qemu-x86_i440fx" + help + This option selects the board Device Tree Source (dts) file in + arch/x86/dts/ directory to be used to build U-Boot for qemu-x86. + endif diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index 198ab97..a894db6 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -3,7 +3,6 @@ CONFIG_VENDOR_EMULATION=y CONFIG_TARGET_QEMU_X86=y CONFIG_OF_CONTROL=y CONFIG_OF_SEPARATE=y -CONFIG_DEFAULT_DEVICE_TREE="qemu-x86" CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_111=y diff --git a/doc/README.x86 b/doc/README.x86 index 0726205..82b773c 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -39,8 +39,8 @@ configuration during the 'make menuconfig' process. x86 architecture ---> ... - (qemu-x86) Board configuration file - (qemu-x86) Board Device Tree Source (dts) file + (qemu-x86_i440fx) Board configuration file + (qemu-x86_i440fx) Board Device Tree Source (dts) file (0x01920000) Board specific Cache-As-RAM (CAR) address (0x4000) Board specific Cache-As-RAM (CAR) size @@ -186,6 +186,15 @@ To build u-boot.rom for QEMU x86 targets, just simply run $ make qemu-x86_defconfig $ make all +Note this default configuration will build a U-Boot for the QEMU x86 i440FX +board. To build a U-Boot against QEMU x86 Q35 board, you can change the build +configuration during the 'make menuconfig' process like below: + +x86 architecture ---> + ... + (qemu-x86_q35) Board configuration file + (qemu-x86_q35) Board Device Tree Source (dts) file + Test with coreboot ------------------ For testing U-Boot as the coreboot payload, there are things that need be paid diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86_i440fx.h similarity index 78% rename from include/configs/qemu-x86.h rename to include/configs/qemu-x86_i440fx.h index d01936b..53d917d 100644 --- a/include/configs/qemu-x86.h +++ b/include/configs/qemu-x86_i440fx.h @@ -37,16 +37,11 @@ "stdout=serial,vga\0" \ "stderr=serial,vga\0" -/* - * ATA/SATA support for QEMU x86 targets - * - Only legacy IDE controller is supported for QEMU '-M pc' target - * - AHCI controller is supported for QEMU '-M q35' target - * - * Default configuraion is to support the QEMU default x86 target - * Undefine CONFIG_CMD_IDE to support q35 target - */ +/* QEMU i440fx target does not have any AHCI controller */ +#undef CONFIG_SCSI_AHCI +#undef CONFIG_CMD_SCSI + #define CONFIG_CMD_IDE -#ifdef CONFIG_CMD_IDE #define CONFIG_SYS_IDE_MAXBUS 2 #define CONFIG_SYS_IDE_MAXDEVICE 4 #define CONFIG_SYS_ATA_BASE_ADDR 0 @@ -57,13 +52,6 @@ #define CONFIG_SYS_ATA_IDE1_OFFSET 0x170 #define CONFIG_ATAPI -#undef CONFIG_SCSI_AHCI -#undef CONFIG_CMD_SCSI -#else -#define CONFIG_SCSI_DEV_LIST \ - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_AHCI} -#endif - /* GPIO is not supported */ #undef CONFIG_INTEL_ICH6_GPIO #undef CONFIG_CMD_GPIO diff --git a/include/configs/qemu-x86_q35.h b/include/configs/qemu-x86_q35.h new file mode 100644 index 0000000..ef81ad3 --- /dev/null +++ b/include/configs/qemu-x86_q35.h @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/x86-common.h> + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) + +#define CONFIG_X86_SERIAL + +#define CONFIG_PCI_MEM_BUS 0xc0000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_PREF_BUS 0xd0000000 +#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS +#define CONFIG_PCI_PREF_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x2000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0xe000 + +#define CONFIG_PCI_CONFIG_HOST_BRIDGE +#define CONFIG_PCI_PNP +#define CONFIG_E1000 + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga\0" \ + "stdout=serial,vga\0" \ + "stderr=serial,vga\0" + +#define CONFIG_SCSI_DEV_LIST \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_AHCI} + +/* GPIO is not supported */ +#undef CONFIG_INTEL_ICH6_GPIO +#undef CONFIG_CMD_GPIO + +/* SPI is not supported */ +#undef CONFIG_ICH_SPI +#undef CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_IS_NOWHERE + +#endif /* __CONFIG_H */ -- 1.8.2.1

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[U-Boot] pull request: u-boot-uniphier/misc
by Masahiro Yamada 27 May '15

27 May '15

Hi Tom, Here is a new tool that helps us move CONFIG options easily. The following changes since commit 9bea236b3402a262772b66d055ec6431cbd3ba87: Merge branch 'master' of git://www.denx.de/git/u-boot-imx (2015-05-26 10:38:01 -0400) are available in the git repository at: git://git.denx.de/u-boot-uniphier.git misc for you to fetch changes up to 2e2ce6c0c8d3d0d2a86d2464d201aecd9aef693d: moveconfig: Print status about the processed defconfigs (2015-05-27 08:39:16 +0900) ---------------------------------------------------------------- Joe Hershberger (9): moveconfig: Always run savedefconfig on the moved config moveconfig: Ignore duplicate configs when moving moveconfig: Add a parameter to accept a list to build moveconfig: Add a switch to only cleanup headers moveconfig: Cleanup headers in arch and board moveconfig: Output a list of failed boards moveconfig: Print a message for missing compiler moveconfig: Add a switch to enable printing errors moveconfig: Print status about the processed defconfigs Masahiro Yamada (1): tools: moveconfig: a tool to move CONFIGs from headers to defconfigs scripts/Makefile.autoconf | 3 +- tools/moveconfig.py | 918 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 920 insertions(+), 1 deletion(-) create mode 100755 tools/moveconfig.py -- Best Regards Masahiro Yamada

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