April 2015 - U-Boot

[U-Boot] [PATCH] arm: ls102xa: Adjust the load address of U-Boot for NOR boot
by Alison Wang 22 May '15

22 May '15

The original load address of U-Boot is 0x67f80000. The address space of NOR flash is 0x60000000 to 0x67ffffff. It will cause the size of u-boot couldn't be larger than 512K. As more features are supported in u-boot, the size of u-boot is larger than 512K. To fix this issue, the load address of U-Boot for NOR boot is adjusted to 0x60100000. In RCW, the PBI command needs to change as follows: .pbi -write 0xee0200, 0x67f80000 +write 0xee0200, 0x60100000 .end Signed-off-by: Alison Wang <alison.wang(a)freescale.com> --- include/configs/ls1021aqds.h | 2 +- include/configs/ls1021atwr.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 5de416d..e0cebf1 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -124,7 +124,7 @@ unsigned long get_board_ddr_clk(void); #endif #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0x67f80000 +#define CONFIG_SYS_TEXT_BASE 0x60100000 #endif #define CONFIG_NR_DRAM_BANKS 1 diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index a13876b..89891ac 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -73,7 +73,7 @@ #endif #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0x67f80000 +#define CONFIG_SYS_TEXT_BASE 0x60100000 #endif #define CONFIG_NR_DRAM_BANKS 1 -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 1/3 v1] arm: ls102xa: Enable CONFIG_DEFAULT_DEVICE_TREE to defconfig for ls1021a
by Haikun Wang 20 May '15

20 May '15

Define CONFIG_DEFAULT_DEVICE_TREE for ls1021a series boards. Signed-off-by: Haikun Wang <Haikun.Wang(a)freescale.com> --- configs/ls1021aqds_ddr4_nor_defconfig | 1 + configs/ls1021aqds_nand_defconfig | 1 + configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021aqds_nor_defconfig | 1 + configs/ls1021aqds_nor_lpuart_defconfig | 1 + configs/ls1021aqds_qspi_defconfig | 1 + configs/ls1021aqds_sdcard_defconfig | 1 + configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_nor_defconfig | 1 + configs/ls1021atwr_nor_lpuart_defconfig | 1 + configs/ls1021atwr_qspi_defconfig | 1 + configs/ls1021atwr_sdcard_defconfig | 1 + 12 files changed, 12 insertions(+) diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index 3c57481..d896027 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -1,3 +1,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds" diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index 3cd33fa..743e3c0 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -2,3 +2,4 @@ CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT" CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds" diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index 2b47995..c5eb90a 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -1,3 +1,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds" diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index 9e42d61..bd65322 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -1,2 +1,3 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds" diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig index a59f59e..0d90ab9 100644 --- a/configs/ls1021aqds_nor_lpuart_defconfig +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -1,3 +1,4 @@ CONFIG_SYS_EXTRA_OPTIONS="LPUART" CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds" diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index 91c1125..5c79198 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -1,3 +1,4 @@ CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds" diff --git a/configs/ls1021aqds_sdcard_defconfig b/configs/ls1021aqds_sdcard_defconfig index 910aa67..1c4a646 100644 --- a/configs/ls1021aqds_sdcard_defconfig +++ b/configs/ls1021aqds_sdcard_defconfig @@ -2,3 +2,4 @@ CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds" diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index eeeb0d5..dedd832 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -1,3 +1,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_ARM=y CONFIG_TARGET_LS1021ATWR=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr" diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index 5f465d3..8903ab6 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -1,2 +1,3 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021ATWR=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr" diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index 7c80041..9721183 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -1,3 +1,4 @@ CONFIG_SYS_EXTRA_OPTIONS="LPUART" CONFIG_ARM=y CONFIG_TARGET_LS1021ATWR=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr" diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index c9715a4..ced7371 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -1,3 +1,4 @@ CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" CONFIG_ARM=y CONFIG_TARGET_LS1021ATWR=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr" diff --git a/configs/ls1021atwr_sdcard_defconfig b/configs/ls1021atwr_sdcard_defconfig index 3390eac..c3e0db9 100644 --- a/configs/ls1021atwr_sdcard_defconfig +++ b/configs/ls1021atwr_sdcard_defconfig @@ -2,3 +2,4 @@ CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" CONFIG_ARM=y CONFIG_TARGET_LS1021ATWR=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr" -- 2.1.0.27.g96db324

2 1

[U-Boot] [PATCH 0/20] tegra: Expand Nyan-big support
by Simon Glass 20 May '15

20 May '15

This series expands Nyan-big support: - Enable Chrome OS EC, so that the keyboard works - Add some extra clock and pre-kernel init required for reliable operation - Add Chrome OS environment variables, including 'run nvboot' to allow booting Chrome OS more easily Still missing are audio and USB. Doug Anderson (1): Add Chrome OS config header Simon Glass (19): dm: spi: Avoid setting the speed with every transfer cros_ec: Show the protocol version in the debug message cros_ec: Handle the single duplex requirement in cros_ec tegra: Provide more accurate microsecond time tegra: cros_ec: Add tegra support for Chrome OS EC tegra: spi: Drop the claim_bus() method to correct delays dm: tegra: cros_ec: Enable Chrome OS EC on Nyan-big dm: gpio: Add an implementation for gpio_get_number() tegra: spi: Support slow SPI rates tegra: clock: Support enabling external clocks tegra: clock: Adjust PLL access to avoid a warning tegra: Introduce SRAM repair on tegra124 tegra: Add missing tegra124 peripherals tegra: Increase maximum arguments to 32 tegra: lcd: Tidy up clock init tegra: Allow board-specific init tegra: nyan-big: Add additional clock and kernel init tegra: config: Allow Chrome OS environment settings to be included tegra: config: nyan-big: Add options required by Chrome OS boot arch/arm/cpu/tegra-common/Makefile | 1 + arch/arm/cpu/tegra-common/clock.c | 24 +- arch/arm/cpu/tegra-common/powergate.c | 20 +- arch/arm/cpu/tegra-common/timer.c | 87 ++++ arch/arm/cpu/tegra124-common/clock.c | 2 +- arch/arm/dts/tegra124-nyan-big.dts | 6 +- arch/arm/include/asm/arch-tegra/clock.h | 8 + arch/arm/include/asm/arch-tegra/sys_proto.h | 7 + arch/arm/include/asm/arch-tegra124/clock-tables.h | 12 +- arch/arm/include/asm/arch-tegra124/flow.h | 12 + board/nvidia/common/board.c | 8 +- board/nvidia/nyan-big/nyan-big.c | 76 ++++ configs/nyan-big_defconfig | 5 + drivers/gpio/gpio-uclass.c | 12 + drivers/misc/cros_ec.c | 3 +- drivers/misc/cros_ec_spi.c | 23 +- drivers/spi/spi-uclass.c | 9 +- drivers/spi/tegra114_spi.c | 51 +-- drivers/video/tegra124/tegra124-lcd.c | 4 +- include/configs/chromeos.h | 464 ++++++++++++++++++++++ include/configs/nyan-big.h | 8 + include/configs/tegra-common-post.h | 15 +- include/configs/tegra-common.h | 2 +- include/spi.h | 3 + 24 files changed, 804 insertions(+), 58 deletions(-) create mode 100644 arch/arm/cpu/tegra-common/timer.c create mode 100644 include/configs/chromeos.h -- 2.2.0.rc0.207.ga3a616c

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[U-Boot] Add spi nand support in u-boot
by Peter Pan 潘栋 (peterpandong) 20 May '15

20 May '15

Hi All, I’d like to add spi nand support in u-boot. But I don’t know where should the spi nand drivers put in and how to define the architecture. I find that currently spi_flash in u-boot means spi nor flash. Should I create a struct spi_nand_flash or make spi_flash compatible? Thanks Peter Pan

2 2

[U-Boot] sunxi: Initial A80 support
by Hans de Goede 19 May '15

19 May '15

Hi Ian, ChenYu, I'm very happy to present this patch series which adds initial A80 support, with this series a u-boot.bin can be build which can then be fel booted using Allwinners boot0 fel binary, and then can load linux from a sdcard using a standard extlinux.conf setup. Next step getting RSB going and finding out how the 2 pmics are hooked up, and then slowly work towards getting SPL going. Ian, as always, can you please review these patches ? ChenYu, if you want to play with this, it is probably easiest to use my sunxi-wip branch. Regards, Hans

3 35

[U-Boot] [PATCH 3/3] x86: quark: Implement PIRQ routing
by Bin Meng 19 May '15

19 May '15

Intel Quark SoC has the same interrupt routing mechanism as the Queensbay platform, only the difference is that PCI devices' INTA/B/C/D are harcoded and cannot be changed freely. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/cpu/quark/Makefile | 2 +- arch/x86/cpu/quark/irq.c | 173 +++++++++++++++++++++++++++++++ arch/x86/cpu/quark/quark.c | 8 ++ arch/x86/include/asm/arch-quark/device.h | 70 ++++++++++--- arch/x86/include/asm/arch-quark/irq.h | 55 ++++++++++ arch/x86/include/asm/arch-quark/quark.h | 15 +++ configs/galileo_defconfig | 1 + include/configs/galileo.h | 1 + 8 files changed, 309 insertions(+), 16 deletions(-) create mode 100644 arch/x86/cpu/quark/irq.c create mode 100644 arch/x86/include/asm/arch-quark/irq.h diff --git a/arch/x86/cpu/quark/Makefile b/arch/x86/cpu/quark/Makefile index e87b424..1e37802 100644 --- a/arch/x86/cpu/quark/Makefile +++ b/arch/x86/cpu/quark/Makefile @@ -4,6 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += car.o dram.o msg_port.o quark.o +obj-y += car.o dram.o irq.o msg_port.o quark.o obj-y += mrc.o mrc_util.o hte.o smc.o obj-$(CONFIG_PCI) += pci.o diff --git a/arch/x86/cpu/quark/irq.c b/arch/x86/cpu/quark/irq.c new file mode 100644 index 0000000..d6edd0c --- /dev/null +++ b/arch/x86/cpu/quark/irq.c @@ -0,0 +1,173 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <malloc.h> +#include <asm/io.h> +#include <asm/pci.h> +#include <asm/post.h> +#include <asm/processor.h> +#include <asm/pirq_routing.h> +#include <asm/arch/device.h> +#include <asm/arch/quark.h> +#include <asm/arch/irq.h> + +static struct irq_routing_table *pirq_routing_table; + +bool pirq_check_irq_routed(int link, u8 irq) +{ + u8 pirq; + + pirq = x86_pci_read_config8(QUARK_LEGACY_BRIDGE, LINK_N2V(link)); + pirq &= 0xf; + + /* IRQ# 0/1/2/8/13 are reserved */ + if (pirq < 3 || pirq == 8 || pirq == 13) + return false; + + return pirq == irq ? true : false; +} + +int pirq_translate_link(int link) +{ + return LINK_V2N(link); +} + +void pirq_assign_irq(int link, u8 irq) +{ + /* IRQ# 0/1/2/8/13 are reserved */ + if (irq < 3 || irq == 8 || irq == 13) + return; + + x86_pci_write_config8(QUARK_LEGACY_BRIDGE, LINK_N2V(link), irq); +} + +static inline void fill_irq_info(struct irq_info **slotp, int *entries, u8 bus, + u8 device, u8 func, u8 pin, u8 pirq) +{ + struct irq_info *slot = *slotp; + + slot->bus = bus; + slot->devfn = (device << 3) | func; + slot->irq[pin - 1].link = LINK_N2V(pirq); + slot->irq[pin - 1].bitmap = PIRQ_BITMAP; + (*entries)++; + (*slotp)++; +} + +__weak int board_fill_irq_info(struct irq_info *slot) +{ + return 0; +} + +static int create_pirq_routing_table(void) +{ + struct irq_routing_table *rt; + struct irq_info *slot; + int irq_entries = 0; + + rt = malloc(sizeof(struct irq_routing_table)); + if (!rt) + return -ENOMEM; + memset((char *)rt, 0, sizeof(struct irq_routing_table)); + + /* Populate the PIRQ table fields */ + rt->signature = PIRQ_SIGNATURE; + rt->version = PIRQ_VERSION; + rt->rtr_bus = 0; + rt->rtr_devfn = (QUARK_LGC_BRIDGE_DEV << 3) | QUARK_LGC_BRIDGE_FUNC; + rt->rtr_vendor = PCI_VENDOR_ID_INTEL; + rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31; + + slot = rt->slots; + + /* Now fill in the irq_info entries in the PIRQ table */ + fill_irq_info(&slot, &irq_entries, 0, QUARK_DEV_20, + QUARK_MMC_SDIO_FUNC, INTA, PIRQE); + fill_irq_info(&slot, &irq_entries, 0, QUARK_DEV_20, + QUARK_UART0_FUNC, INTB, PIRQF); + fill_irq_info(&slot, &irq_entries, 0, QUARK_DEV_20, + QUARK_USB_DEVICE_FUNC, INTC, PIRQG); + fill_irq_info(&slot, &irq_entries, 0, QUARK_DEV_20, + QUARK_USB_EHCI_FUNC, INTD, PIRQH); + fill_irq_info(&slot, &irq_entries, 0, QUARK_DEV_20, + QUARK_USB_OHCI_FUNC, INTD, PIRQH); + fill_irq_info(&slot, &irq_entries, 0, QUARK_DEV_20, + QUARK_UART1_FUNC, INTB, PIRQF); + fill_irq_info(&slot, &irq_entries, 0, QUARK_DEV_20, + QUARK_EMAC0_FUNC, INTC, PIRQG); + fill_irq_info(&slot, &irq_entries, 0, QUARK_DEV_20, + QUARK_EMAC1_FUNC, INTC, PIRQG); + + fill_irq_info(&slot, &irq_entries, 0, QUARK_DEV_21, + QUARK_SPI0_FUNC, INTA, PIRQE); + fill_irq_info(&slot, &irq_entries, 0, QUARK_DEV_21, + QUARK_SPI1_FUNC, INTA, PIRQE); + fill_irq_info(&slot, &irq_entries, 0, QUARK_DEV_21, + QUARK_I2C_GPIO_FUNC, INTC, PIRQG); + + /* + * TODO: + * + * For some unknown reason, the PCI enumeration process hangs + * when it scans to the PCIe root port 0 (D23:F0) & 1 (D23:F1). + * + * For now we just skip these two devices, and this needs to + * be revisited later. + */ +#ifdef TODO + fill_irq_info(&slot, &irq_entries, 0, QUARK_DEV_23, + QUARK_PCIE0_FUNC, INTA, PIRQA); + fill_irq_info(&slot, &irq_entries, 0, QUARK_DEV_23, + QUARK_PCIE1_FUNC, INTA, PIRQA); +#endif + + /* Call board-specific routine to fill in add-in card's irq info */ + irq_entries += board_fill_irq_info(slot); + + rt->size = irq_entries * sizeof(struct irq_info) + 32; + + pirq_routing_table = rt; + + return 0; +} + +void pirq_init(void) +{ + struct quark_rcba *rcba; + u32 base; + + base = x86_pci_read_config32(QUARK_LEGACY_BRIDGE, LB_RCBA); + base &= ~MEM_BAR_EN; + rcba = (struct quark_rcba *)base; + + /* + * Route Quark PCI device interrupt pin to PIRQ + * + * Route device#23's INTA/B/C/D to PIRQA/B/C/D + * Route device#20,21's INTA/B/C/D to PIRQE/F/G/H + */ + writew(PIRQC, &rcba->rmu_ir); + writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12), + &rcba->d23_ir); + writew(PIRQD, &rcba->core_ir); + writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12), + &rcba->d20d21_ir); + + if (create_pirq_routing_table()) { + debug("Failed to create pirq routing table\n"); + } else { + /* Route PIRQ */ + pirq_route_irqs(pirq_routing_table->slots, + get_irq_slot_count(pirq_routing_table)); + } +} + +u32 write_pirq_routing_table(u32 addr) +{ + return copy_pirq_routing_table(addr, pirq_routing_table); +} diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index 4ffa437..7a8f936 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -13,6 +13,7 @@ #include <asm/post.h> #include <asm/processor.h> #include <asm/arch/device.h> +#include <asm/arch/irq.h> #include <asm/arch/msg_port.h> #include <asm/arch/quark.h> @@ -147,3 +148,10 @@ int cpu_eth_init(bd_t *bis) else return 0; } + +int arch_misc_init(void) +{ + pirq_init(); + + return 0; +} diff --git a/arch/x86/include/asm/arch-quark/device.h b/arch/x86/include/asm/arch-quark/device.h index 4af3ded..7882f33 100644 --- a/arch/x86/include/asm/arch-quark/device.h +++ b/arch/x86/include/asm/arch-quark/device.h @@ -9,20 +9,60 @@ #include <pci.h> -#define QUARK_HOST_BRIDGE PCI_BDF(0, 0, 0) -#define QUARK_MMC_SDIO PCI_BDF(0, 20, 0) -#define QUARK_UART0 PCI_BDF(0, 20, 1) -#define QUARK_USB_DEVICE PCI_BDF(0, 20, 2) -#define QUARK_USB_EHCI PCI_BDF(0, 20, 3) -#define QUARK_USB_OHCI PCI_BDF(0, 20, 4) -#define QUARK_UART1 PCI_BDF(0, 20, 5) -#define QUARK_EMAC0 PCI_BDF(0, 20, 6) -#define QUARK_EMAC1 PCI_BDF(0, 20, 7) -#define QUARK_SPI0 PCI_BDF(0, 21, 0) -#define QUARK_SPI1 PCI_BDF(0, 21, 1) -#define QUARK_I2C_GPIO PCI_BDF(0, 21, 2) -#define QUARK_PCIE0 PCI_BDF(0, 23, 0) -#define QUARK_PCIE1 PCI_BDF(0, 23, 1) -#define QUARK_LEGACY_BRIDGE PCI_BDF(0, 31, 0) +#define QUARK_HOST_BRIDGE_DEV 0 +#define QUARK_HOST_BRIDGE_FUNC 0 + +#define QUARK_DEV_20 20 +#define QUARK_MMC_SDIO_FUNC 0 +#define QUARK_UART0_FUNC 1 +#define QUARK_USB_DEVICE_FUNC 2 +#define QUARK_USB_EHCI_FUNC 3 +#define QUARK_USB_OHCI_FUNC 4 +#define QUARK_UART1_FUNC 5 +#define QUARK_EMAC0_FUNC 6 +#define QUARK_EMAC1_FUNC 7 + +#define QUARK_DEV_21 21 +#define QUARK_SPI0_FUNC 0 +#define QUARK_SPI1_FUNC 1 +#define QUARK_I2C_GPIO_FUNC 2 + +#define QUARK_DEV_23 23 +#define QUARK_PCIE0_FUNC 0 +#define QUARK_PCIE1_FUNC 1 + +#define QUARK_LGC_BRIDGE_DEV 31 +#define QUARK_LGC_BRIDGE_FUNC 0 + +#define QUARK_HOST_BRIDGE \ + PCI_BDF(0, QUARK_HOST_BRIDGE_DEV, QUARK_HOST_BRIDGE_FUNC) +#define QUARK_MMC_SDIO \ + PCI_BDF(0, QUARK_DEV_20, QUARK_MMC_SDIO_FUNC) +#define QUARK_UART0 \ + PCI_BDF(0, QUARK_DEV_20, QUARK_UART0_FUNC) +#define QUARK_USB_DEVICE \ + PCI_BDF(0, QUARK_DEV_20, QUARK_USB_DEVICE_FUNC) +#define QUARK_USB_EHCI \ + PCI_BDF(0, QUARK_DEV_20, QUARK_USB_EHCI_FUNC) +#define QUARK_USB_OHCI \ + PCI_BDF(0, QUARK_DEV_20, QUARK_USB_OHCI_FUNC) +#define QUARK_UART1 \ + PCI_BDF(0, QUARK_DEV_20, QUARK_UART1_FUNC) +#define QUARK_EMAC0 \ + PCI_BDF(0, QUARK_DEV_20, QUARK_EMAC0_FUNC) +#define QUARK_EMAC1 \ + PCI_BDF(0, QUARK_DEV_20, QUARK_EMAC1_FUNC) +#define QUARK_SPI0 \ + PCI_BDF(0, QUARK_DEV_21, QUARK_SPI0_FUNC) +#define QUARK_SPI1 \ + PCI_BDF(0, QUARK_DEV_21, QUARK_SPI1_FUNC) +#define QUARK_I2C_GPIO \ + PCI_BDF(0, QUARK_DEV_21, QUARK_I2C_GPIO_FUNC) +#define QUARK_PCIE0 \ + PCI_BDF(0, QUARK_DEV_23, QUARK_PCIE0_FUNC) +#define QUARK_PCIE1 \ + PCI_BDF(0, QUARK_DEV_23, QUARK_PCIE1_FUNC) +#define QUARK_LEGACY_BRIDGE \ + PCI_BDF(0, QUARK_LGC_BRIDGE_DEV, QUARK_LGC_BRIDGE_FUNC) #endif /* _QUARK_DEVICE_H_ */ diff --git a/arch/x86/include/asm/arch-quark/irq.h b/arch/x86/include/asm/arch-quark/irq.h new file mode 100644 index 0000000..f69fb8c --- /dev/null +++ b/arch/x86/include/asm/arch-quark/irq.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ARCH_IRQ_H_ +#define _ARCH_IRQ_H_ + +enum pci_int_pin { + INTX, + INTA, + INTB, + INTC, + INTD +}; + +enum pirq_pin { + PIRQA, + PIRQB, + PIRQC, + PIRQD, + PIRQE, + PIRQF, + PIRQG, + PIRQH +}; + +/* PIRQ link number and value conversion */ +#define LINK_V2N(link) (link - 0x60) +#define LINK_N2V(link) (link + 0x60) + +#define PIRQ_BITMAP 0xdef8 + +struct irq_info; + +/** + * board_fill_irq_info() - Board-specific irq_info fill routine + * + * This fills the irq_info table for any board-specific add-in cards. + * + * @slot: pointer to the struct irq_info that is to be filled in + * @return: number of entries were written to the struct irq_info + */ +int board_fill_irq_info(struct irq_info *slot); + +/** + * pirq_init() - Initialize platform PIRQ routing + * + * This initializes the PIRQ routing on the platform and configures all PCI + * devices' interrupt line register to a working IRQ number on the 8259 PIC. + */ +void pirq_init(void); + +#endif /* _ARCH_IRQ_H_ */ diff --git a/arch/x86/include/asm/arch-quark/quark.h b/arch/x86/include/asm/arch-quark/quark.h index 6dd02fd..c997928 100644 --- a/arch/x86/include/asm/arch-quark/quark.h +++ b/arch/x86/include/asm/arch-quark/quark.h @@ -76,4 +76,19 @@ #define LB_BC 0xd8 #define LB_RCBA 0xf0 +#ifndef __ASSEMBLY__ + +/* Root Complex Register Block */ +struct quark_rcba { + u32 rctl; + u32 esd; + u32 rsvd1[3150]; + u16 rmu_ir; + u16 d23_ir; + u16 core_ir; + u16 d20d21_ir; +}; + +#endif /* __ASSEMBLY__ */ + #endif /* _QUARK_H_ */ diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig index 9b0f969..0c77278 100644 --- a/configs/galileo_defconfig +++ b/configs/galileo_defconfig @@ -7,3 +7,4 @@ CONFIG_DEFAULT_DEVICE_TREE="galileo" CONFIG_ETH_DESIGNWARE=y CONFIG_NETDEVICES=y CONFIG_NET=y +CONFIG_GENERATE_PIRQ_TABLE=y diff --git a/include/configs/galileo.h b/include/configs/galileo.h index 9b0b650..961d087 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -15,6 +15,7 @@ #define CONFIG_SYS_MONITOR_LEN (1 << 20) #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_ARCH_MISC_INIT #define CONFIG_NR_DRAM_BANKS 1 -- 1.8.2.1

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[U-Boot] [PATCH 0/5] nand: sunxi: Add SPL support for booting from NAND.
by Daniel Kochmański 19 May '15

19 May '15

This patchset adds minimal SPL driver for reading from A20 nand partitions utilizing DMA controller. It supports randomization and syndrome partitions. Since BROM reads second syndrome partition, if first SPL checksum doesn't match, additional U-Boot offset may be provided to load backup U-boot from second block of second page. To simplify loading many files (devicetree, kernel, sourcable boot script) additional parameter is added, which allows preloading multiboot image into memory directly from SPL. Additionally conveniance function a20_nandread has been added, which utilizes SPL driver on normal U-Boot. Best regards, Daniel Kochmański Daniel Kochmański (5): nand: sunxi: change BLOCK_SIZE in mksunxiboot to match NAND block size nand: sunxi: Add support for booting from internal NAND memory nand: sunxi: Add secondary U-Boot offset on second syndrome partition nand: sunxi: Add multiimage preload option nand: sunxi: And a20_nandread command utilizing spl nand read driver README | 10 ++ arch/arm/cpu/armv7/sunxi/board.c | 12 ++- board/sunxi/Kconfig | 12 +++ board/sunxi/Makefile | 1 + board/sunxi/nand.c | 219 +++++++++++++++++++++++++++++++++++++++ common/Kconfig | 7 ++ common/Makefile | 1 + common/cmd_a20_nandread.c | 27 +++++ common/spl/spl_nand.c | 51 +++++++-- include/configs/sunxi-common.h | 12 +++ tools/mksunxiboot.c | 2 +- 11 files changed, 344 insertions(+), 10 deletions(-) create mode 100644 board/sunxi/nand.c create mode 100644 common/cmd_a20_nandread.c -- 2.3.6

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[U-Boot] [PATCH v2 0/3] ARM: zynq: include ps7_init_gpl.c/h of Zed, MicroZed, ZC702, ZC706
by Masahiro Yamada 18 May '15

18 May '15

Masahiro Yamada (3): ARM: zynq: drop legacy ps7_init.c/h support ARM: zynq: use separate configuration for ZC702 and ZC706 ARM: zynq: add default ps7_init_gpl.c/h for Zed, MicroZed, ZC70x arch/arm/cpu/armv7/zynq/Kconfig | 19 +- arch/arm/cpu/armv7/zynq/spl.c | 2 +- board/xilinx/zynq/Makefile | 20 +- .../zynq/MicroZed_hw_platform/ps7_init_gpl.c | 12978 ++++++++++++++++++ .../zynq/MicroZed_hw_platform/ps7_init_gpl.h | 130 + board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.c | 13311 +++++++++++++++++++ board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.h | 130 + board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.c | 13218 ++++++++++++++++++ board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.h | 130 + .../zynq/{ => custom_hw_platform}/.gitignore | 1 - board/xilinx/zynq/legacy.c | 2 - board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.c | 12876 ++++++++++++++++++ board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.h | 130 + .../{zynq_zc70x_defconfig => zynq_zc702_defconfig} | 2 +- configs/zynq_zc706_defconfig | 11 + doc/README.zynq | 15 +- 16 files changed, 52952 insertions(+), 23 deletions(-) create mode 100644 board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.c create mode 100644 board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.h create mode 100644 board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.c create mode 100644 board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.h create mode 100644 board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.c create mode 100644 board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.h rename board/xilinx/zynq/{ => custom_hw_platform}/.gitignore (56%) delete mode 100644 board/xilinx/zynq/legacy.c create mode 100644 board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.c create mode 100644 board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.h rename configs/{zynq_zc70x_defconfig => zynq_zc702_defconfig} (88%) create mode 100644 configs/zynq_zc706_defconfig -- 1.9.1

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[U-Boot] [PATCH] mx6: Set shared override bit in PL310 AUX_CTRL register
by Fabio Estevam 15 May '15

15 May '15

From: Fabio Estevam <fabio.estevam(a)freescale.com> Having bit 22 cleared in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. This was inspired by a patch from Catalin Marinas [1] and also from recent discussions in the linux-arm-kernel list [2] where Russell King and Rob Herring suggested that bootloaders should initialize the cache. [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2010-November/031810.… [2] https://lkml.org/lkml/2015/2/20/199 Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- arch/arm/cpu/armv7/mx6/soc.c | 8 ++++++++ arch/arm/include/asm/pl310.h | 2 ++ 2 files changed, 10 insertions(+) diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index ef02972..5aab305 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -506,6 +506,14 @@ void v7_outer_cache_enable(void) struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; unsigned int val; + + /* + * Set bit 22 in the auxiliary control register. If this bit + * is cleared, PL310 treats Normal Shared Non-cacheable + * accesses as Cacheable no-allocate. + */ + setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE); + #if defined CONFIG_MX6SL struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; val = readl(&iomux->gpr[11]); diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h index ddc245b..de7650e 100644 --- a/arch/arm/include/asm/pl310.h +++ b/arch/arm/include/asm/pl310.h @@ -16,6 +16,8 @@ #define L2X0_STNDBY_MODE_EN (1 << 0) #define L2X0_CTRL_EN 1 +#define L310_SHARED_ATT_OVERRIDE_ENABLE (1 << 22) + struct pl310_regs { u32 pl310_cache_id; u32 pl310_cache_type; -- 1.9.1

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[U-Boot] [patch] socfpga: move configuration options to config file
by Pavel Machek 15 May '15

15 May '15

Setting configuration options in header file leads to incosistency between .config user sees, and .config he has. What is worse, a lot of compile warnings is presented for any such config option user sets in .config. Signed-off-by: Pavel Machek <pavel(a)denx.de> diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 0ebfbfc..762b937 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -6,3 +6,19 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk" CONFIG_DM=y CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_DFU=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MII=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_CMD_SETEXPR=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 2e3a8b6..171ddf4 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -18,24 +18,6 @@ #define CONFIG_FAT_WRITE #define CONFIG_HW_WATCHDOG -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BOOTZ -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DFU -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EXT4 -#define CONFIG_CMD_EXT4_WRITE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_FPGA -#define CONFIG_CMD_FS_GENERIC -#define CONFIG_CMD_GREPENV -#define CONFIG_CMD_MII -#define CONFIG_CMD_MMC -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_SETEXPR -#define CONFIG_CMD_USB -#define CONFIG_CMD_USB_MASS_STORAGE #define CONFIG_REGEX /* Enable regular expression support */ -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

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