April 2015 - U-Boot

[U-Boot] [PATCH v2 4/4] x86: queensbay: Implement PIRQ routing
by Bin Meng 25 Apr '15

25 Apr '15

Implement Intel Queensbay platform-specific PIRQ routing support. The chipset PIRQ routing setup is called in the arch_misc_init(). Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- Changes in v2: - Correct a typo in the commit message - Use a local variable in fill_irq_info() - Print a debug message if creating pirq table fails - Use a C structure for RCBA register access arch/x86/cpu/queensbay/Makefile | 2 +- arch/x86/cpu/queensbay/irq.c | 242 +++++++++++++++++++++++++++ arch/x86/cpu/queensbay/tnc.c | 10 +- arch/x86/include/asm/arch-queensbay/device.h | 94 +++++++++++ arch/x86/include/asm/arch-queensbay/irq.h | 55 ++++++ arch/x86/include/asm/arch-queensbay/tnc.h | 39 ++++- arch/x86/include/asm/u-boot-x86.h | 2 + configs/crownbay_defconfig | 1 + include/configs/crownbay.h | 1 + 9 files changed, 442 insertions(+), 4 deletions(-) create mode 100644 arch/x86/cpu/queensbay/irq.c create mode 100644 arch/x86/include/asm/arch-queensbay/device.h create mode 100644 arch/x86/include/asm/arch-queensbay/irq.h diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile index d8761fd..4599a48 100644 --- a/arch/x86/cpu/queensbay/Makefile +++ b/arch/x86/cpu/queensbay/Makefile @@ -5,5 +5,5 @@ # obj-y += fsp_configs.o -obj-y += tnc.o topcliff.o +obj-y += irq.o tnc.o topcliff.o obj-$(CONFIG_PCI) += tnc_pci.o diff --git a/arch/x86/cpu/queensbay/irq.c b/arch/x86/cpu/queensbay/irq.c new file mode 100644 index 0000000..faf9515 --- /dev/null +++ b/arch/x86/cpu/queensbay/irq.c @@ -0,0 +1,242 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <malloc.h> +#include <asm/io.h> +#include <asm/pci.h> +#include <asm/post.h> +#include <asm/processor.h> +#include <asm/pirq_routing.h> +#include <asm/arch/device.h> +#include <asm/arch/tnc.h> +#include <asm/arch/irq.h> + +static struct irq_routing_table *pirq_routing_table; + +bool pirq_check_irq_routed(int link, u8 irq) +{ + u8 pirq; + + pirq = x86_pci_read_config8(TNC_LPC, LINK_N2V(link)); + pirq &= 0xf; + + /* IRQ# 0/1/2/8/13 are reserved */ + if (pirq < 3 || pirq == 8 || pirq == 13) + return false; + + return pirq == irq ? true : false; +} + +int pirq_translate_link(int link) +{ + return LINK_V2N(link); +} + +void pirq_assign_irq(int link, u8 irq) +{ + /* IRQ# 0/1/2/8/13 are reserved */ + if (irq < 3 || irq == 8 || irq == 13) + return; + + x86_pci_write_config8(TNC_LPC, LINK_N2V(link), irq); +} + +static inline void fill_irq_info(struct irq_info **slotp, int *entries, u8 bus, + u8 device, u8 func, u8 pin, u8 pirq) +{ + struct irq_info *slot = *slotp; + + slot->bus = bus; + slot->devfn = (device << 3) | func; + slot->irq[pin - 1].link = LINK_N2V(pirq); + slot->irq[pin - 1].bitmap = PIRQ_BITMAP; + (*entries)++; + (*slotp)++; +} + +/* PCIe port downstream INTx swizzle */ +static inline u8 pin_swizzle(u8 pin, int port) +{ + return (pin + port) % 4; +} + +__weak int board_fill_irq_info(struct irq_info *slot) +{ + return 0; +} + +static int create_pirq_routing_table(void) +{ + struct irq_routing_table *rt; + struct irq_info *slot; + int irq_entries = 0; + pci_dev_t tcf_bdf; + u8 tcf_bus, bus; + int i; + + rt = malloc(sizeof(struct irq_routing_table)); + if (!rt) + return -ENOMEM; + memset((char *)rt, 0, sizeof(struct irq_routing_table)); + + /* Populate the PIRQ table fields */ + rt->signature = PIRQ_SIGNATURE; + rt->version = PIRQ_VERSION; + rt->rtr_bus = 0; + rt->rtr_devfn = (TNC_LPC_DEV << 3) | TNC_LPC_FUNC; + rt->rtr_vendor = PCI_VENDOR_ID_INTEL; + rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31; + + slot = rt->slots; + + /* + * Now fill in the irq_info entries in the PIRQ table + * + * We start from internal TunnelCreek PCI devices first, then + * followed by all the 4 PCIe ports downstream devices, including + * the Queensbay platform Topcliff chipset devices. + */ + fill_irq_info(&slot, &irq_entries, 0, TNC_IGD_DEV, + TNC_IGD_FUNC, INTA, PIRQE); + fill_irq_info(&slot, &irq_entries, 0, TNC_SDVO_DEV, + TNC_SDVO_FUNC, INTA, PIRQF); + fill_irq_info(&slot, &irq_entries, 0, TNC_HDA_DEV, + TNC_HDA_FUNC, INTA, PIRQG); + fill_irq_info(&slot, &irq_entries, 0, TNC_PCIE0_DEV, + TNC_PCIE0_FUNC, INTA, PIRQE); + fill_irq_info(&slot, &irq_entries, 0, TNC_PCIE1_DEV, + TNC_PCIE1_FUNC, INTA, PIRQF); + fill_irq_info(&slot, &irq_entries, 0, TNC_PCIE2_DEV, + TNC_PCIE2_FUNC, INTA, PIRQG); + fill_irq_info(&slot, &irq_entries, 0, TNC_PCIE3_DEV, + TNC_PCIE3_FUNC, INTA, PIRQH); + + /* Check which PCIe port the Topcliff chipset is connected to */ + tcf_bdf = pci_find_device(PCI_VENDOR_ID_INTEL, 0x8800, 0); + tcf_bus = PCI_BUS(tcf_bdf); + for (i = 0; i < 4; i++) { + bus = x86_pci_read_config8(PCI_BDF(0, TNC_PCIE0_DEV + i, 0), + PCI_SECONDARY_BUS); + if (bus == tcf_bus) + break; + } + + /* Fill in the Topcliff chipset devices' irq info */ + if (i < 4) { + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_PCIE_PORT_DEV, + TCF_PCIE_PORT_FUNC, INTA, pin_swizzle(PIRQA, i)); + + tcf_bus++; + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_0, + TCF_GBE_FUNC, INTA, pin_swizzle(PIRQA, i)); + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_0, + TCF_GPIO_FUNC, INTA, pin_swizzle(PIRQA, i)); + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2, + TCF_USB1_OHCI0_FUNC, INTB, pin_swizzle(PIRQB, i)); + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2, + TCF_USB1_OHCI1_FUNC, INTB, pin_swizzle(PIRQB, i)); + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2, + TCF_USB1_OHCI2_FUNC, INTB, pin_swizzle(PIRQB, i)); + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2, + TCF_USB1_EHCI_FUNC, INTB, pin_swizzle(PIRQB, i)); + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2, + TCF_USB_DEVICE_FUNC, INTB, pin_swizzle(PIRQB, i)); + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_4, + TCF_SDIO0_FUNC, INTC, pin_swizzle(PIRQC, i)); + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_4, + TCF_SDIO1_FUNC, INTC, pin_swizzle(PIRQC, i)); + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_6, + TCF_SATA_FUNC, INTD, pin_swizzle(PIRQD, i)); + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_8, + TCF_USB2_OHCI0_FUNC, INTA, pin_swizzle(PIRQA, i)); + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_8, + TCF_USB2_OHCI1_FUNC, INTA, pin_swizzle(PIRQA, i)); + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_8, + TCF_USB2_OHCI2_FUNC, INTA, pin_swizzle(PIRQA, i)); + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_8, + TCF_USB2_EHCI_FUNC, INTA, pin_swizzle(PIRQA, i)); + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10, + TCF_DMA1_FUNC, INTB, pin_swizzle(PIRQB, i)); + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10, + TCF_UART0_FUNC, INTB, pin_swizzle(PIRQB, i)); + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10, + TCF_UART1_FUNC, INTB, pin_swizzle(PIRQB, i)); + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10, + TCF_UART2_FUNC, INTB, pin_swizzle(PIRQB, i)); + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10, + TCF_UART3_FUNC, INTB, pin_swizzle(PIRQB, i)); + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12, + TCF_DMA2_FUNC, INTC, pin_swizzle(PIRQC, i)); + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12, + TCF_SPI_FUNC, INTC, pin_swizzle(PIRQC, i)); + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12, + TCF_I2C_FUNC, INTC, pin_swizzle(PIRQC, i)); + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12, + TCF_CAN_FUNC, INTC, pin_swizzle(PIRQC, i)); + fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12, + TCF_1588_FUNC, INTC, pin_swizzle(PIRQC, i)); + } + + /* Call board-specific routine to fill in add-in card's irq info */ + irq_entries += board_fill_irq_info(slot); + + rt->size = irq_entries * sizeof(struct irq_info) + 32; + + pirq_routing_table = rt; + + return 0; +} + +void pirq_init(void) +{ + struct tnc_rcba *rcba; + u32 base; + + base = x86_pci_read_config32(TNC_LPC, LPC_RCBA); + base &= ~MEM_BAR_EN; + rcba = (struct tnc_rcba *)base; + + /* Make sure all internal PCI devices are using INTA */ + writel(INTA, &rcba->d02ip); + writel(INTA, &rcba->d03ip); + writel(INTA, &rcba->d27ip); + writel(INTA, &rcba->d31ip); + writel(INTA, &rcba->d23ip); + writel(INTA, &rcba->d24ip); + writel(INTA, &rcba->d25ip); + writel(INTA, &rcba->d26ip); + + /* + * Route TunnelCreek PCI device interrupt pin to PIRQ + * + * Since PCIe downstream ports received INTx are routed to PIRQ + * A/B/C/D directly and not configurable, we route internal PCI + * device's INTx to PIRQ E/F/G/H. + */ + writew(PIRQE, &rcba->d02ir); + writew(PIRQF, &rcba->d03ir); + writew(PIRQG, &rcba->d27ir); + writew(PIRQH, &rcba->d31ir); + writew(PIRQE, &rcba->d23ir); + writew(PIRQF, &rcba->d24ir); + writew(PIRQG, &rcba->d25ir); + writew(PIRQH, &rcba->d26ir); + + if (create_pirq_routing_table()) { + debug("Failed to create pirq routing table\n"); + } else { + /* Route PIRQ */ + pirq_route_irqs(pirq_routing_table->slots, + get_irq_slot_count(pirq_routing_table)); + } +} + +u32 write_pirq_routing_table(u32 addr) +{ + return copy_pirq_routing_table(addr, pirq_routing_table); +} diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c index f756a0d..b46a7e9 100644 --- a/arch/x86/cpu/queensbay/tnc.c +++ b/arch/x86/cpu/queensbay/tnc.c @@ -8,7 +8,8 @@ #include <asm/io.h> #include <asm/pci.h> #include <asm/post.h> -#include <asm/arch/tnc.h> +#include <asm/arch/device.h> +#include <asm/arch/irq.h> #include <asm/fsp/fsp_support.h> #include <asm/processor.h> @@ -43,3 +44,10 @@ int arch_cpu_init(void) return 0; } + +int arch_misc_init(void) +{ + pirq_init(); + + return 0; +} diff --git a/arch/x86/include/asm/arch-queensbay/device.h b/arch/x86/include/asm/arch-queensbay/device.h new file mode 100644 index 0000000..953b48f --- /dev/null +++ b/arch/x86/include/asm/arch-queensbay/device.h @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _QUEENSBAY_DEVICE_H_ +#define _QUEENSBAY_DEVICE_H_ + +#include <pci.h> + +/* TunnelCreek PCI Devices */ +#define TNC_HOST_BRIDGE_DEV 0 +#define TNC_HOST_BRIDGE_FUNC 0 +#define TNC_IGD_DEV 2 +#define TNC_IGD_FUNC 0 +#define TNC_SDVO_DEV 3 +#define TNC_SDVO_FUNC 0 +#define TNC_PCIE0_DEV 23 +#define TNC_PCIE0_FUNC 0 +#define TNC_PCIE1_DEV 24 +#define TNC_PCIE1_FUNC 0 +#define TNC_PCIE2_DEV 25 +#define TNC_PCIE2_FUNC 0 +#define TNC_PCIE3_DEV 26 +#define TNC_PCIE3_FUNC 0 +#define TNC_HDA_DEV 27 +#define TNC_HDA_FUNC 0 +#define TNC_LPC_DEV 31 +#define TNC_LPC_FUNC 0 + +#define TNC_HOST_BRIDGE \ + PCI_BDF(0, TNC_HOST_BRIDGE_DEV, TNC_HOST_BRIDGE_FUNC) +#define TNC_IGD \ + PCI_BDF(0, TNC_IGD_DEV, TNC_IGD_FUNC) +#define TNC_SDVO \ + PCI_BDF(0, TNC_SDVO_DEV, TNC_SDVO_FUNC) +#define TNC_PCIE0 \ + PCI_BDF(0, TNC_PCIE0_DEV, TNC_PCIE0_FUNC) +#define TNC_PCIE1 \ + PCI_BDF(0, TNC_PCIE1_DEV, TNC_PCIE1_FUNC) +#define TNC_PCIE2 \ + PCI_BDF(0, TNC_PCIE2_DEV, TNC_PCIE2_FUNC) +#define TNC_PCIE3 \ + PCI_BDF(0, TNC_PCIE3_DEV, TNC_PCIE3_FUNC) +#define TNC_HDA \ + PCI_BDF(0, TNC_HDA_DEV, TNC_HDA_FUNC) +#define TNC_LPC \ + PCI_BDF(0, TNC_LPC_DEV, TNC_LPC_FUNC) + +/* Topcliff IOH PCI Devices */ +#define TCF_PCIE_PORT_DEV 0 +#define TCF_PCIE_PORT_FUNC 0 + +#define TCF_DEV_0 0 +#define TCF_PKT_HUB_FUNC 0 +#define TCF_GBE_FUNC 1 +#define TCF_GPIO_FUNC 2 + +#define TCF_DEV_2 2 +#define TCF_USB1_OHCI0_FUNC 0 +#define TCF_USB1_OHCI1_FUNC 1 +#define TCF_USB1_OHCI2_FUNC 2 +#define TCF_USB1_EHCI_FUNC 3 +#define TCF_USB_DEVICE_FUNC 4 + +#define TCF_DEV_4 4 +#define TCF_SDIO0_FUNC 0 +#define TCF_SDIO1_FUNC 1 + +#define TCF_DEV_6 6 +#define TCF_SATA_FUNC 0 + +#define TCF_DEV_8 8 +#define TCF_USB2_OHCI0_FUNC 0 +#define TCF_USB2_OHCI1_FUNC 1 +#define TCF_USB2_OHCI2_FUNC 2 +#define TCF_USB2_EHCI_FUNC 3 + +#define TCF_DEV_10 10 +#define TCF_DMA1_FUNC 0 +#define TCF_UART0_FUNC 1 +#define TCF_UART1_FUNC 2 +#define TCF_UART2_FUNC 3 +#define TCF_UART3_FUNC 4 + +#define TCF_DEV_12 12 +#define TCF_DMA2_FUNC 0 +#define TCF_SPI_FUNC 1 +#define TCF_I2C_FUNC 2 +#define TCF_CAN_FUNC 3 +#define TCF_1588_FUNC 4 + +#endif /* _QUEENSBAY_DEVICE_H_ */ diff --git a/arch/x86/include/asm/arch-queensbay/irq.h b/arch/x86/include/asm/arch-queensbay/irq.h new file mode 100644 index 0000000..e7f8616 --- /dev/null +++ b/arch/x86/include/asm/arch-queensbay/irq.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ARCH_IRQ_H_ +#define _ARCH_IRQ_H_ + +enum pci_int_pin { + INTX, + INTA, + INTB, + INTC, + INTD +}; + +enum pirq_pin { + PIRQA, + PIRQB, + PIRQC, + PIRQD, + PIRQE, + PIRQF, + PIRQG, + PIRQH +}; + +/* PIRQ link number and value conversion */ +#define LINK_V2N(link) (link - 0x60) +#define LINK_N2V(link) (link + 0x60) + +#define PIRQ_BITMAP 0xdee0 + +struct irq_info; + +/** + * board_fill_irq_info() - Board-specific irq_info fill routine + * + * This fills the irq_info table for any board-specific add-in cards. + * + * @slot: pointer to the struct irq_info that is to be filled in + * @return: number of entries were written to the struct irq_info + */ +int board_fill_irq_info(struct irq_info *slot); + +/** + * pirq_init() - Initialize platform PIRQ routing + * + * This initializes the PIRQ routing on the platform and configures all PCI + * devices' interrupt line register to a working IRQ number on the 8259 PIC. + */ +void pirq_init(void); + +#endif /* _ARCH_IRQ_H_ */ diff --git a/arch/x86/include/asm/arch-queensbay/tnc.h b/arch/x86/include/asm/arch-queensbay/tnc.h index 10ea51d..ad9a6c4 100644 --- a/arch/x86/include/asm/arch-queensbay/tnc.h +++ b/arch/x86/include/asm/arch-queensbay/tnc.h @@ -7,8 +7,43 @@ #ifndef _X86_ARCH_TNC_H_ #define _X86_ARCH_TNC_H_ -#include <pci.h> +/* Memory BAR Enable */ +#define MEM_BAR_EN 0x00000001 -#define TNC_LPC PCI_BDF(0, 31, 0) +/* LPC PCI Configuration Registers */ +#define LPC_RCBA 0xf0 + +/* Root Complex Register Block */ +struct tnc_rcba { + u32 rctl; + u32 esd; + u32 rsvd1[2]; + u32 hdd; + u32 rsvd2; + u32 hdba; + u32 rsvd3[3129]; + u32 d31ip; + u32 rsvd4[3]; + u32 d27ip; + u32 rsvd5; + u32 d02ip; + u32 rsvd6; + u32 d26ip; + u32 d25ip; + u32 d24ip; + u32 d23ip; + u32 d03ip; + u32 rsvd7[3]; + u16 d31ir; + u16 rsvd8[3]; + u16 d27ir; + u16 d26ir; + u16 d25ir; + u16 d24ir; + u16 d23ir; + u16 rsvd9[7]; + u16 d02ir; + u16 d03ir; +}; #endif /* _X86_ARCH_TNC_H_ */ diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index c743efd..122e054 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -53,6 +53,8 @@ int video_bios_init(void); void board_init_f_r_trampoline(ulong) __attribute__ ((noreturn)); void board_init_f_r(void) __attribute__ ((noreturn)); +int arch_misc_init(void); + /* Read the time stamp counter */ static inline __attribute__((no_instrument_function)) uint64_t rdtsc(void) { diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index ce90553..47763f9 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -4,3 +4,4 @@ CONFIG_TARGET_CROWNBAY=y CONFIG_OF_CONTROL=y CONFIG_OF_SEPARATE=y CONFIG_DEFAULT_DEVICE_TREE="crownbay" +CONFIG_GENERATE_PIRQ_TABLE=y diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index 42042d1..4fef433 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -15,6 +15,7 @@ #define CONFIG_SYS_MONITOR_LEN (1 << 20) #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_ARCH_MISC_INIT #define CONFIG_NR_DRAM_BANKS 1 -- 1.8.2.1

2 2

[U-Boot] [PATCH v2 3/4] x86: Support platform PIRQ routing
by Bin Meng 25 Apr '15

25 Apr '15

On x86 boards, platform chipset receives up to four different interrupt signals from PCI devices (INTA/B/C/D), which in turn will be routed to chipset internal PIRQ lines then routed to 8259 PIC finally if configuring the whole system to work under the so-called PIC mode (in contrast to symmetric IO mode which uses IOAPIC). We add two major APIs to aid this, one for routing PIRQ and the other one for generating a PIRQ routing table. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> Acked-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: None arch/x86/Kconfig | 31 ++++++++ arch/x86/include/asm/pirq_routing.h | 139 ++++++++++++++++++++++++++++++++++++ arch/x86/lib/Makefile | 1 + arch/x86/lib/pirq_routing.c | 129 +++++++++++++++++++++++++++++++++ 4 files changed, 300 insertions(+) create mode 100644 arch/x86/include/asm/pirq_routing.h create mode 100644 arch/x86/lib/pirq_routing.c diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 3f1401a..aaceaef 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -442,6 +442,37 @@ config TSC_FREQ_IN_MHZ help The running frequency in MHz of Time-Stamp Counter (TSC). +menu "System tables" + +config GENERATE_PIRQ_TABLE + bool "Generate a PIRQ table" + default n + help + Generate a PIRQ routing table for this board. The PIRQ routing table + is generated by U-Boot in the system memory from 0xf0000 to 0xfffff + at every 16-byte boundary with a PCI IRQ routing signature ("$PIR"). + It specifies the interrupt router information as well how all the PCI + devices' interrupt pins are wired to PIRQs. + +endmenu + +config MAX_PIRQ_LINKS + int + default 8 + help + This variable specifies the number of PIRQ interrupt links which are + routable. On most older chipsets, this is 4, PIRQA through PIRQD. + Some newer chipsets offer more than four links, commonly up to PIRQH. + +config IRQ_SLOT_COUNT + int + default 128 + help + U-Boot can support up to 254 IRQ slot info in the PIRQ routing table + which in turns forms a table of exact 4KiB. The default value 128 + should be enough for most boards. If this does not fit your board, + change it according to your needs. + source "board/coreboot/coreboot/Kconfig" source "board/google/chromebook_link/Kconfig" diff --git a/arch/x86/include/asm/pirq_routing.h b/arch/x86/include/asm/pirq_routing.h new file mode 100644 index 0000000..ddc08e1 --- /dev/null +++ b/arch/x86/include/asm/pirq_routing.h @@ -0,0 +1,139 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn(a)gmail.com> + * + * Ported from coreboot src/arch/x86/include/arch/pirq_routing.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PIRQ_ROUTING_H_ +#define _PIRQ_ROUTING_H_ + +/* + * This is the maximum number on interrupt entries that a PCI device may have. + * This is NOT the number of slots or devices in the system + * This is NOT the number of entries in the PIRQ table + * + * This tells us that in the PIRQ table, we are going to have 4 link-bitmap + * entries per PCI device which is fixed at 4: INTA, INTB, INTC, and INTD. + * + * CAUTION: If you change this, PIRQ routing will not work correctly. + */ +#define MAX_INTX_ENTRIES 4 + +#define PIRQ_SIGNATURE \ + (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24)) +#define PIRQ_VERSION 0x0100 + +struct __packed irq_info { + u8 bus; /* Bus number */ + u8 devfn; /* Device and function number */ + struct __packed { + u8 link; /* IRQ line ID, 0=not routed */ + u16 bitmap; /* Available IRQs */ + } irq[MAX_INTX_ENTRIES]; + u8 slot; /* Slot number, 0=onboard */ + u8 rfu; +}; + +struct __packed irq_routing_table { + u32 signature; /* PIRQ_SIGNATURE */ + u16 version; /* PIRQ_VERSION */ + u16 size; /* Table size in bytes */ + u8 rtr_bus; /* busno of the interrupt router */ + u8 rtr_devfn; /* devfn of the interrupt router */ + u16 exclusive_irqs; /* IRQs devoted exclusively to PCI usage */ + u16 rtr_vendor; /* Vendor ID of the interrupt router */ + u16 rtr_device; /* Device ID of the interrupt router */ + u32 miniport_data; + u8 rfu[11]; + u8 checksum; /* Modulo 256 checksum must give zero */ + struct irq_info slots[CONFIG_IRQ_SLOT_COUNT]; +}; + +/** + * get_irq_slot_count() - Get the number of entries in the irq_info table + * + * This calculates the number of entries for the irq_info table. + * + * @rt: pointer to the base address of the struct irq_info + * @return: number of entries + */ +static inline int get_irq_slot_count(struct irq_routing_table *rt) +{ + return (rt->size - 32) / sizeof(struct irq_info); +} + +/** + * pirq_check_irq_routed() - Check whether an IRQ is routed to 8259 PIC + * + * This function checks whether an IRQ is routed to 8259 PIC for a given link. + * + * Note: this function should be provided by the platform codes, as the + * implementation of interrupt router may be different. + * + * @link: link number which represents a PIRQ + * @irq: the 8259 IRQ number + * @return: true if the irq is already routed to 8259 for a given link, + * false elsewise + */ +bool pirq_check_irq_routed(int link, u8 irq); + +/** + * pirq_translate_link() - Translate a link value + * + * This function translates a platform-specific link value to a link number. + * On Intel platforms, the link value is normally a offset into the PCI + * configuration space into the legacy bridge. + * + * Note: this function should be provided by the platform codes, as the + * implementation of interrupt router may be different. + * + * @link: platform-specific link value + * @return: link number which represents a PIRQ + */ +int pirq_translate_link(int link); + +/** + * pirq_assign_irq() - Assign an IRQ to a PIRQ link + * + * This function assigns the IRQ to a PIRQ link so that the PIRQ is routed to + * the 8259 PIC. + * + * Note: this function should be provided by the platform codes, as the + * implementation of interrupt router may be different. + * + * @link: link number which represents a PIRQ + * @irq: IRQ to which the PIRQ is routed + */ +void pirq_assign_irq(int link, u8 irq); + +/** + * pirq_route_irqs() - Route PIRQs to 8259 PIC + * + * This function configures all PCI devices' interrupt pins and maps them to + * PIRQs and finally 8259 PIC. The routed irq number is written to interrupt + * line register in the configuration space of the PCI device for OS to use. + * The configuration source is taken from a struct irq_info table, the format + * of which is defined in PIRQ routing table spec and PCI BIOS spec. + * + * @irq: pointer to the base address of the struct irq_info + * @num: number of entries in the struct irq_info + */ +void pirq_route_irqs(struct irq_info *irq, int num); + +/** + * copy_pirq_routing_table() - Copy a PIRQ routing table + * + * This helper function copies the given PIRQ routing table to a given address. + * Before copying, it does several sanity tests against the PIRQ routing table. + * It also fixes up the table checksum and align the given address to a 16 byte + * boundary to meet the PIRQ routing table spec requirements. + * + * @addr: address to store the copied PIRQ routing table + * @rt: pointer to the PIRQ routing table to copy from + * @return: end address of the copied PIRQ routing table + */ +u32 copy_pirq_routing_table(u32 addr, struct irq_routing_table *rt); + +#endif /* _PIRQ_ROUTING_H_ */ diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 0de0d89..0178fe1 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -22,6 +22,7 @@ ifndef CONFIG_DM_PCI obj-$(CONFIG_PCI) += pci_type1.o endif obj-y += pch-uclass.o +obj-y += pirq_routing.o obj-y += relocate.o obj-y += physmem.o obj-$(CONFIG_X86_RAMTEST) += ramtest.o diff --git a/arch/x86/lib/pirq_routing.c b/arch/x86/lib/pirq_routing.c new file mode 100644 index 0000000..5a2591a --- /dev/null +++ b/arch/x86/lib/pirq_routing.c @@ -0,0 +1,129 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn(a)gmail.com> + * + * Part of this file is ported from coreboot src/arch/x86/boot/pirq_routing.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <pci.h> +#include <asm/pci.h> +#include <asm/pirq_routing.h> +#include <asm/tables.h> + +static bool irq_already_routed[16]; + +static u8 pirq_get_next_free_irq(u8 *pirq, u16 bitmap) +{ + int i, link; + u8 irq = 0; + + /* IRQ sharing starts from IRQ#3 */ + for (i = 3; i < 16; i++) { + /* Can we assign this IRQ? */ + if (!((bitmap >> i) & 1)) + continue; + + /* We can, now let's assume we can use this IRQ */ + irq = i; + + /* Have we already routed it? */ + if (irq_already_routed[irq]) + continue; + + for (link = 0; link < CONFIG_MAX_PIRQ_LINKS; link++) { + if (pirq_check_irq_routed(link, irq)) { + irq_already_routed[irq] = true; + break; + } + } + + /* If it's not yet routed, use it */ + if (!irq_already_routed[irq]) { + irq_already_routed[irq] = true; + break; + } + + /* But if it was already routed, try the next one */ + } + + /* Now we get our IRQ */ + return irq; +} + +void pirq_route_irqs(struct irq_info *irq, int num) +{ + unsigned char irq_slot[MAX_INTX_ENTRIES]; + unsigned char pirq[CONFIG_MAX_PIRQ_LINKS]; + int i, intx; + + memset(pirq, 0, CONFIG_MAX_PIRQ_LINKS); + + /* Set PCI IRQs */ + for (i = 0; i < num; i++) { + debug("PIRQ Entry %d Dev: %d.%x.%d\n", i, + irq->bus, irq->devfn >> 3, irq->devfn & 7); + + for (intx = 0; intx < MAX_INTX_ENTRIES; intx++) { + int link = irq->irq[intx].link; + int bitmap = irq->irq[intx].bitmap; + int irq = 0; + + debug("INT%c link: %x bitmap: %x ", + 'A' + intx, link, bitmap); + + if (!bitmap || !link) { + debug("not routed\n"); + irq_slot[intx] = irq; + continue; + } + + /* translate link value to link number */ + link = pirq_translate_link(link); + + /* yet not routed */ + if (!pirq[link]) { + irq = pirq_get_next_free_irq(pirq, bitmap); + pirq[link] = irq; + } else { + irq = pirq[link]; + } + + debug("IRQ: %d\n", irq); + irq_slot[intx] = irq; + + /* Assign IRQ in the interrupt router */ + pirq_assign_irq(link, irq); + } + + /* Bus, device, slots IRQs for {A,B,C,D} */ + pci_assign_irqs(irq->bus, irq->devfn >> 3, irq->devfn & 7, + irq_slot); + + irq++; + } + + for (i = 0; i < CONFIG_MAX_PIRQ_LINKS; i++) + debug("PIRQ%c: %d\n", 'A' + i, pirq[i]); +} + +u32 copy_pirq_routing_table(u32 addr, struct irq_routing_table *rt) +{ + if (rt->signature != PIRQ_SIGNATURE || rt->version != PIRQ_VERSION || + rt->size % 16) { + debug("Interrupt Routing Table not valid\n"); + return addr; + } + + /* Fix up the table checksum */ + rt->checksum = table_compute_checksum(rt, rt->size); + + /* Align the table to be 16 byte aligned */ + addr = ALIGN(addr, 16); + + debug("Copying Interrupt Routing Table to 0x%x\n", addr); + memcpy((void *)addr, rt, rt->size); + + return addr + rt->size; +} -- 1.8.2.1

2 1

[U-Boot] [PATCH v2 2/4] x86: Write configuration tables in last_stage_init()
by Bin Meng 25 Apr '15

25 Apr '15

We can write the configuration table in last_stage_init() for all x86 boards, but not with coreboot since coreboot already has them. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> Acked-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: None arch/x86/cpu/cpu.c | 10 +++++++++ arch/x86/include/asm/tables.h | 49 +++++++++++++++++++++++++++++++++++++++++++ arch/x86/lib/Makefile | 1 + arch/x86/lib/tables.c | 30 ++++++++++++++++++++++++++ include/configs/x86-common.h | 1 + 5 files changed, 91 insertions(+) create mode 100644 arch/x86/include/asm/tables.h create mode 100644 arch/x86/lib/tables.c diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index a9ca50b..c9614f1 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -29,6 +29,7 @@ #include <asm/processor.h> #include <asm/processor-flags.h> #include <asm/interrupt.h> +#include <asm/tables.h> #include <linux/compiler.h> DECLARE_GLOBAL_DATA_PTR; @@ -593,3 +594,12 @@ void show_boot_progress(int val) #endif outb(val, POST_PORT); } + +#ifndef CONFIG_SYS_COREBOOT +int last_stage_init(void) +{ + write_tables(); + + return 0; +} +#endif diff --git a/arch/x86/include/asm/tables.h b/arch/x86/include/asm/tables.h new file mode 100644 index 0000000..8146ba3 --- /dev/null +++ b/arch/x86/include/asm/tables.h @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _X86_TABLES_H_ +#define _X86_TABLES_H_ + +/* + * All x86 tables happen to like the address range from 0xf0000 to 0x100000. + * We use 0xf0000 as the starting address to store those tables, including + * PIRQ routing table, Multi-Processor table and ACPI table. + */ +#define ROM_TABLE_ADDR 0xf0000 + +/** + * table_compute_checksum() - Compute a table checksum + * + * This computes an 8-bit checksum for the configuration table. + * All bytes in the configuration table, including checksum itself and + * reserved bytes must add up to zero. + * + * @v: configuration table base address + * @len: configuration table size + * @return: the 8-bit checksum + */ +u8 table_compute_checksum(void *v, int len); + +/** + * write_tables() - Write x86 configuration tables + * + * This writes x86 configuration tables, including PIRQ routing table, + * Multi-Processor table and ACPI table. Whether a specific type of + * configuration table is written is controlled by a Kconfig option. + */ +void write_tables(void); + +/** + * write_pirq_routing_table() - Write PIRQ routing table + * + * This writes PIRQ routing table at a given address. + * + * @start: start address to write PIRQ routing table + * @return: end address of PIRQ routing table + */ +u32 write_pirq_routing_table(u32 start); + +#endif /* _X86_TABLES_H_ */ diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index e49de05..0de0d89 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -26,6 +26,7 @@ obj-y += relocate.o obj-y += physmem.o obj-$(CONFIG_X86_RAMTEST) += ramtest.o obj-y += string.o +obj-y += tables.o obj-$(CONFIG_SYS_X86_TSC_TIMER) += tsc_timer.o obj-$(CONFIG_CMD_ZBOOT) += zimage.o obj-$(CONFIG_HAVE_FSP) += fsp/ diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c new file mode 100644 index 0000000..b390a4b --- /dev/null +++ b/arch/x86/lib/tables.c @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/tables.h> + +u8 table_compute_checksum(void *v, int len) +{ + u8 *bytes = v; + u8 checksum = 0; + int i; + + for (i = 0; i < len; i++) + checksum -= bytes[i]; + + return checksum; +} + +void write_tables(void) +{ + u32 __maybe_unused rom_table_end = ROM_TABLE_ADDR; + +#if CONFIG_GENERATE_PIRQ_TABLE + rom_table_end = write_pirq_routing_table(rom_table_end); + rom_table_end = ALIGN(rom_table_end, 1024); +#endif +} diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 07a5aca..3e21e09 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -20,6 +20,7 @@ #define CONFIG_PHYSMEM #define CONFIG_DISPLAY_BOARDINFO_LATE #define CONFIG_DISPLAY_CPUINFO +#define CONFIG_LAST_STAGE_INIT #define CONFIG_LMB #define CONFIG_OF_LIBFDT -- 1.8.2.1

2 1

[U-Boot] [PATCH v2 1/4] x86: Add a function to assign IRQ numbers to PCI device
by Bin Meng 25 Apr '15

25 Apr '15

Add a function to assign an IRQ number to PCI device's interrupt line register in its configuration space, so that the PCI device can have its interrupt working under PIC mode after OS boots up. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> Acked-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: None arch/x86/cpu/pci.c | 21 +++++++++++++++++++++ arch/x86/include/asm/pci.h | 14 ++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c index e23b233..c209f15 100644 --- a/arch/x86/cpu/pci.c +++ b/arch/x86/cpu/pci.c @@ -151,3 +151,24 @@ int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, return 0; } + +void pci_assign_irqs(int bus, int device, int func, u8 irq[4]) +{ + pci_dev_t bdf; + u8 pin, line; + + bdf = PCI_BDF(bus, device, func); + + pin = x86_pci_read_config8(bdf, PCI_INTERRUPT_PIN); + + /* PCI spec says all values except 1..4 are reserved */ + if ((pin < 1) || (pin > 4)) + return; + + line = irq[pin - 1]; + + debug("Assigning IRQ %d to PCI device %d.%x.%d (INT%c)\n", + line, bus, device, func, 'A' + pin - 1); + + x86_pci_write_config8(bdf, PCI_INTERRUPT_LINE, line); +} diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index a1969ed..56eaa25 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -64,6 +64,20 @@ int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset, int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, ulong value, enum pci_size_t size); +/** + * Assign IRQ number to a PCI device + * + * This function assigns IRQ for a PCI device. If the device does not exist + * or does not require interrupts then this function has no effect. + * + * @bus: PCI bus number + * @device: PCI device number + * @func: PCI function number + * @irq: An array of IRQ numbers that are assigned to INTA through + * INTD of this PCI device. + */ +void pci_assign_irqs(int bus, int device, int func, u8 irq[4]); + #endif /* __ASSEMBLY__ */ #endif /* _PCI_I386_H_ */ -- 1.8.2.1

2 1

[U-Boot] [PATCH 2/2] x86: Install a default e820 table in the __weak install_e820_map()
by Bin Meng 25 Apr '15

25 Apr '15

Create a default e820 table with 3 entries which is enough to boot a Linux kernel. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/lib/zimage.c | 29 ++++++++++++++++++++++------- 1 file changed, 22 insertions(+), 7 deletions(-) diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index 566b048..c3f8a73 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -25,6 +25,8 @@ #endif #include <linux/compiler.h> +DECLARE_GLOBAL_DATA_PTR; + /* * Memory lay-out: * @@ -40,16 +42,29 @@ #define COMMAND_LINE_SIZE 2048 -unsigned generic_install_e820_map(unsigned max_entries, - struct e820entry *entries) +/* + * Install a default e820 table with 3 entries as follows: + * + * 0x000000-0x0a0000 Useable RAM + * 0x0a0000-0x100000 Reserved for ISA + * 0x100000-gd->ram_size Useable RAM + */ +__weak unsigned install_e820_map(unsigned max_entries, + struct e820entry *entries) { - return 0; + entries[0].addr = 0; + entries[0].size = ISA_START_ADDRESS; + entries[0].type = E820_RAM; + entries[1].addr = ISA_START_ADDRESS; + entries[1].size = ISA_END_ADDRESS - ISA_START_ADDRESS; + entries[1].type = E820_RESERVED; + entries[2].addr = ISA_END_ADDRESS; + entries[2].size = gd->ram_size - ISA_END_ADDRESS; + entries[2].type = E820_RAM; + + return 3; } -unsigned install_e820_map(unsigned max_entries, - struct e820entry *entries) - __attribute__((weak, alias("generic_install_e820_map"))); - static void build_command_line(char *command_line, int auto_boot) { char *env_command_line; -- 1.8.2.1

2 4

[U-Boot] [PATCH 1/2] x86: Clean up arch/x86/include/asm/e820.h
by Bin Meng 25 Apr '15

25 Apr '15

There are lots of unused codes defined in e820.h, clean it up. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/include/asm/e820.h | 133 +------------------------------------------- 1 file changed, 2 insertions(+), 131 deletions(-) diff --git a/arch/x86/include/asm/e820.h b/arch/x86/include/asm/e820.h index d155ce9..21bc633 100644 --- a/arch/x86/include/asm/e820.h +++ b/arch/x86/include/asm/e820.h @@ -1,43 +1,7 @@ #ifndef _ASM_X86_E820_H #define _ASM_X86_E820_H -#define E820MAP 0x2d0 /* our map */ -#define E820MAX 128 /* number of entries in E820MAP */ -/* - * Legacy E820 BIOS limits us to 128 (E820MAX) nodes due to the - * constrained space in the zeropage. If we have more nodes than - * that, and if we've booted off EFI firmware, then the EFI tables - * passed us from the EFI firmware can list more nodes. Size our - * internal memory map tables to have room for these additional - * nodes, based on up to three entries per node for which the - * kernel was built: MAX_NUMNODES == (1 << CONFIG_NODES_SHIFT), - * plus E820MAX, allowing space for the possible duplicate E820 - * entries that might need room in the same arrays, prior to the - * call to sanitize_e820_map() to remove duplicates. The allowance - * of three memory map entries per node is "enough" entries for - * the initial hardware platform motivating this mechanism to make - * use of additional EFI map entries. Future platforms may want - * to allow more than three entries per node or otherwise refine - * this size. - */ - -/* - * Odd: 'make headers_check' complains about numa.h if I try - * to collapse the next two #ifdef lines to a single line: - * #if defined(__KERNEL__) && defined(CONFIG_EFI) - */ -#ifdef __KERNEL__ -#ifdef CONFIG_EFI -#include <linux/numa.h> -#define E820_X_MAX (E820MAX + 3 * MAX_NUMNODES) -#else /* ! CONFIG_EFI */ -#define E820_X_MAX E820MAX -#endif -#else /* ! __KERNEL__ */ -#define E820_X_MAX E820MAX -#endif - -#define E820NR 0x1e8 /* # entries in E820MAP */ +#define E820MAX 128 /* number of entries in E820MAP */ #define E820_RAM 1 #define E820_RESERVED 2 @@ -45,111 +9,18 @@ #define E820_NVS 4 #define E820_UNUSABLE 5 -/* reserved RAM used by kernel itself */ -#define E820_RESERVED_KERN 128 - #ifndef __ASSEMBLY__ #include <linux/types.h> + struct e820entry { __u64 addr; /* start of memory segment */ __u64 size; /* size of memory segment */ __u32 type; /* type of memory segment */ } __attribute__((packed)); -struct e820map { - __u32 nr_map; - struct e820entry map[E820_X_MAX]; -}; - #define ISA_START_ADDRESS 0xa0000 #define ISA_END_ADDRESS 0x100000 -#define BIOS_BEGIN 0x000a0000 -#define BIOS_END 0x00100000 - -#ifdef __KERNEL__ -/* see comment in arch/x86/kernel/e820.c */ -extern struct e820map e820; -extern struct e820map e820_saved; - -extern unsigned long pci_mem_start; -extern int e820_any_mapped(u64 start, u64 end, unsigned type); -extern int e820_all_mapped(u64 start, u64 end, unsigned type); -extern void e820_add_region(u64 start, u64 size, int type); -extern void e820_print_map(char *who); -extern int -sanitize_e820_map(struct e820entry *biosmap, int max_nr_map, u32 *pnr_map); -extern u64 e820_update_range(u64 start, u64 size, unsigned old_type, - unsigned new_type); -extern u64 e820_remove_range(u64 start, u64 size, unsigned old_type, - int checktype); -extern void update_e820(void); -extern void e820_setup_gap(void); -extern int e820_search_gap(unsigned long *gapstart, unsigned long *gapsize, - unsigned long start_addr, unsigned long long end_addr); -struct setup_data; -extern void parse_e820_ext(struct setup_data *data, unsigned long pa_data); - -#if defined(CONFIG_X86_64) || \ - (defined(CONFIG_X86_32) && defined(CONFIG_HIBERNATION)) -extern void e820_mark_nosave_regions(unsigned long limit_pfn); -#else -static inline void e820_mark_nosave_regions(unsigned long limit_pfn) -{ -} -#endif - -#ifdef CONFIG_MEMTEST -extern void early_memtest(unsigned long start, unsigned long end); -#else -static inline void early_memtest(unsigned long start, unsigned long end) -{ -} -#endif - -extern unsigned long end_user_pfn; - -extern u64 find_e820_area(u64 start, u64 end, u64 size, u64 align); -extern u64 find_e820_area_size(u64 start, u64 *sizep, u64 align); -extern void reserve_early(u64 start, u64 end, char *name); -extern void reserve_early_overlap_ok(u64 start, u64 end, char *name); -extern void free_early(u64 start, u64 end); -extern void early_res_to_bootmem(u64 start, u64 end); -extern u64 early_reserve_e820(u64 startt, u64 sizet, u64 align); - -extern unsigned long e820_end_of_ram_pfn(void); -extern unsigned long e820_end_of_low_ram_pfn(void); -extern int e820_find_active_region(const struct e820entry *ei, - unsigned long start_pfn, - unsigned long last_pfn, - unsigned long *ei_startpfn, - unsigned long *ei_endpfn); -extern void e820_register_active_regions(int nid, unsigned long start_pfn, - unsigned long end_pfn); -extern u64 e820_hole_size(u64 start, u64 end); -extern void finish_e820_parsing(void); -extern void e820_reserve_resources(void); -extern void e820_reserve_resources_late(void); -extern void setup_memory_map(void); -extern char *default_machine_specific_memory_setup(void); - -/* - * Returns true iff the specified range [s,e) is completely contained inside - * the ISA region. - */ -/* -static inline bool is_ISA_range(u64 s, u64 e) -{ - return s >= ISA_START_ADDRESS && e <= ISA_END_ADDRESS; -} -*/ -#endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ -#ifdef __KERNEL__ -/* #include <linux/ioport.h> */ - -#define HIGH_MEMORY (1024*1024) -#endif /* __KERNEL__ */ - #endif /* _ASM_X86_E820_H */ -- 1.8.2.1

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[U-Boot] Test
by Hannes Petermaier 25 Apr '15

25 Apr '15

Hi all, since midnight i didn't receive anything from the mailinglist ... is there something wrong with it ? or is my mail-provider defective? best regards, HAnnes

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[U-Boot] [PATCH] stm32f4: add serial print port
by kunhuahuang 25 Apr '15

25 Apr '15

This patch add the stm32F4 board's serial ports support. User can use it easily. The user only need to edit the number of the usart. This patch also fix the serial print out. Signed-off-by: kunhuahuang <huangkunhua(a)gmail.com> --- arch/arm/include/asm/arch-stm32f4/gpio.h | 32 ++++++++++ board/st/stm32f429-discovery/stm32f429-discovery.c | 16 ++--- drivers/serial/serial_stm32.c | 69 ++++++++++++++++++---- include/configs/stm32f429-discovery.h | 10 +++- 4 files changed, 105 insertions(+), 22 deletions(-) diff --git a/arch/arm/include/asm/arch-stm32f4/gpio.h b/arch/arm/include/asm/arch-stm32f4/gpio.h index 7cd866e..dd33b96 100644 --- a/arch/arm/include/asm/arch-stm32f4/gpio.h +++ b/arch/arm/include/asm/arch-stm32f4/gpio.h @@ -11,6 +11,38 @@ #ifndef _STM32_GPIO_H_ #define _STM32_GPIO_H_ +#if (CONFIG_STM32_USART == 1) +#define STM32_GPIO_PORT_X STM32_GPIO_PORT_A +#define STM32_GPIO_PIN_TX STM32_GPIO_PIN_9 +#define STM32_GPIO_PIN_RX STM32_GPIO_PIN_10 +#define STM32_GPIO_USART STM32_GPIO_AF7 + +#elif (CONFIG_STM32_USART == 2) +#define STM32_GPIO_PORT_X STM32_GPIO_PORT_D +#define STM32_GPIO_PIN_TX STM32_GPIO_PIN_5 +#define STM32_GPIO_PIN_RX STM32_GPIO_PIN_6 +#define STM32_GPIO_USART STM32_GPIO_AF7 + +#elif (CONFIG_STM32_USART == 3) +#define STM32_GPIO_PORT_X STM32_GPIO_PORT_C +#define STM32_GPIO_PIN_TX STM32_GPIO_PIN_10 +#define STM32_GPIO_PIN_RX STM32_GPIO_PIN_11 +#define STM32_GPIO_USART STM32_GPIO_AF7 + +#elif (CONFIG_STM32_USART == 6) +#define STM32_GPIO_PORT_X STM32_GPIO_PORT_G +#define STM32_GPIO_PIN_TX STM32_GPIO_PIN_14 +#define STM32_GPIO_PIN_RX STM32_GPIO_PIN_9 +#define STM32_GPIO_USART STM32_GPIO_AF8 + +#else +#define STM32_GPIO_PORT_X STM32_GPIO_PORT_A +#define STM32_GPIO_PIN_TX STM32_GPIO_PIN_9 +#define STM32_GPIO_PIN_RX STM32_GPIO_PIN_10 +#define STM32_GPIO_USART STM32_GPIO_AF7 + +#endif + enum stm32_gpio_port { STM32_GPIO_PORT_A = 0, STM32_GPIO_PORT_B, diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c index 2c4830f..2dd5d93 100644 --- a/board/st/stm32f429-discovery/stm32f429-discovery.c +++ b/board/st/stm32f429-discovery/stm32f429-discovery.c @@ -33,21 +33,21 @@ const struct stm32_gpio_ctl gpio_ctl_usart = { .otype = STM32_GPIO_OTYPE_PP, .speed = STM32_GPIO_SPEED_50M, .pupd = STM32_GPIO_PUPD_UP, - .af = STM32_GPIO_AF7 + .af = STM32_GPIO_USART }; -static const struct stm32_gpio_dsc usart1_gpio[] = { - {STM32_GPIO_PORT_A, STM32_GPIO_PIN_9}, /* TX */ - {STM32_GPIO_PORT_A, STM32_GPIO_PIN_10}, /* RX */ +static const struct stm32_gpio_dsc usart_gpio[] = { + {STM32_GPIO_PORT_X, STM32_GPIO_PIN_TX}, /* TX */ + {STM32_GPIO_PORT_X, STM32_GPIO_PIN_RX}, /* RX */ }; -int uart1_setup_gpio(void) +int uart_setup_gpio(void) { int i; int rv = 0; - for (i = 0; i < ARRAY_SIZE(usart1_gpio); i++) { - rv = stm32_gpio_config(&usart1_gpio[i], &gpio_ctl_usart); + for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) { + rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart); if (rv) goto out; } @@ -272,7 +272,7 @@ int board_early_init_f(void) { int res; - res = uart1_setup_gpio(); + res = uart_setup_gpio(); if (res) return res; diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c index 3c80096..37663d6 100644 --- a/drivers/serial/serial_stm32.c +++ b/drivers/serial/serial_stm32.c @@ -10,11 +10,34 @@ #include <serial.h> #include <asm/arch/stm32.h> +/* + * Set up the usart port + */ +#if (CONFIG_STM32_USART >=1) && (CONFIG_STM32_USART <= 6) +#define USART_PORT (CONFIG_STM32_USART - 1) +#else +#define USART_PORT 0 +#endif +/* + * Set up the usart base address + * + * --STM32_USARTD_BASE means default setting + */ #define STM32_USART1_BASE (STM32_APB2PERIPH_BASE + 0x1000) -#define RCC_APB2ENR_USART1EN (1 << 4) - -#define USART_BASE STM32_USART1_BASE -#define RCC_USART_ENABLE RCC_APB2ENR_USART1EN +#define STM32_USART2_BASE (STM32_APB1PERIPH_BASE + 0x4400) +#define STM32_USART3_BASE (STM32_APB1PERIPH_BASE + 0x4800) +#define STM32_USART6_BASE (STM32_APB2PERIPH_BASE + 0x1400) +#define STM32_USARTD_BASE STM32_USART1_BASE +/* + * RCC USART specific definitions + * + * --RCC_ENR_USARTDEN means default setting + */ +#define RCC_ENR_USART1EN (1 << 4) +#define RCC_ENR_USART2EN (1 << 17) +#define RCC_ENR_USART3EN (1 << 18) +#define RCC_ENR_USART6EN (1 << 5) +#define RCC_ENR_USARTDEN RCC_ENR_USART1EN struct stm32_serial { u32 sr; @@ -39,6 +62,24 @@ struct stm32_serial { DECLARE_GLOBAL_DATA_PTR; +static const unsigned long usart_base[] = { + STM32_USART1_BASE, + STM32_USART2_BASE, + STM32_USART3_BASE, + STM32_USARTD_BASE, + STM32_USARTD_BASE, + STM32_USART6_BASE +}; + +static const unsigned long rcc_enr_en[] = { + RCC_ENR_USART1EN, + RCC_ENR_USART2EN, + RCC_ENR_USART3EN, + RCC_ENR_USARTDEN, + RCC_ENR_USARTDEN, + RCC_ENR_USART6EN +}; + static void stm32_serial_setbrg(void) { serial_init(); @@ -46,14 +87,14 @@ static void stm32_serial_setbrg(void) static int stm32_serial_init(void) { - struct stm32_serial *usart = (struct stm32_serial *)USART_BASE; + struct stm32_serial *usart = (struct stm32_serial *)usart_base[USART_PORT]; u32 clock, int_div, frac_div, tmp; - if ((USART_BASE & STM32_BUS_MASK) == STM32_APB1PERIPH_BASE) { - setbits_le32(&STM32_RCC->apb1enr, RCC_USART_ENABLE); + if ((usart_base[USART_PORT] & STM32_BUS_MASK) == STM32_APB1PERIPH_BASE) { + setbits_le32(&STM32_RCC->apb1enr, rcc_enr_en[USART_PORT]); clock = clock_get(CLOCK_APB1); - } else if ((USART_BASE & STM32_BUS_MASK) == STM32_APB2PERIPH_BASE) { - setbits_le32(&STM32_RCC->apb2enr, RCC_USART_ENABLE); + } else if ((usart_base[USART_PORT] & STM32_BUS_MASK) == STM32_APB2PERIPH_BASE) { + setbits_le32(&STM32_RCC->apb2enr, rcc_enr_en[USART_PORT]); clock = clock_get(CLOCK_APB2); } else { return -1; @@ -72,7 +113,7 @@ static int stm32_serial_init(void) static int stm32_serial_getc(void) { - struct stm32_serial *usart = (struct stm32_serial *)USART_BASE; + struct stm32_serial *usart = (struct stm32_serial *)usart_base[USART_PORT]; while ((readl(&usart->sr) & USART_SR_FLAG_RXNE) == 0) ; return readl(&usart->dr); @@ -80,7 +121,11 @@ static int stm32_serial_getc(void) static void stm32_serial_putc(const char c) { - struct stm32_serial *usart = (struct stm32_serial *)USART_BASE; + struct stm32_serial *usart = (struct stm32_serial *)usart_base[USART_PORT]; + + if(c == '\n') + stm32_serial_putc('\r'); + while ((readl(&usart->sr) & USART_SR_FLAG_TXE) == 0) ; writel(c, &usart->dr); @@ -88,7 +133,7 @@ static void stm32_serial_putc(const char c) static int stm32_serial_tstc(void) { - struct stm32_serial *usart = (struct stm32_serial *)USART_BASE; + struct stm32_serial *usart = (struct stm32_serial *)usart_base[USART_PORT]; u8 ret; ret = readl(&usart->sr) & USART_SR_FLAG_RXNE; diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h index 7f569fd..84cc19d 100644 --- a/include/configs/stm32f429-discovery.h +++ b/include/configs/stm32f429-discovery.h @@ -50,8 +50,14 @@ #define CONFIG_STM32_GPIO #define CONFIG_STM32_SERIAL - -#define CONFIG_STM32_USART1 +/* + * Configuration of the USART + * 1: TX:PA9 PX:PA10 + * 2: TX:PD5 RX:PD6 + * 3: TX:PC10 RX:PC11 + * 6: TX:PC6 RX:PC7 + */ +#define CONFIG_STM32_USART 1 #define CONFIG_STM32_HSE_HZ 8000000 -- 1.9.1

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[U-Boot] Question about the hard-coded baud_divisor in debug_uart_init
by Axel Lin 25 Apr '15

25 Apr '15

Hi Simon, Any reason that now using hard-coded "baud_divisor = 13;" in debug_uart_init()? (The change is introduced by commit dd0b0122bac serial: ns16550: Add an option to specify the debug UART register shift) Regards, Axel

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[U-Boot] [PATCH 2/2] x86: crownbay: Update dts for SST SPI flash
by Bin Meng 25 Apr '15

25 Apr '15

Use SST SPI flash compatible string "spi-flash-sst" so that the write op is really working. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/dts/crownbay.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts index fbdeade..a15d8ca 100644 --- a/arch/x86/dts/crownbay.dts +++ b/arch/x86/dts/crownbay.dts @@ -53,7 +53,7 @@ compatible = "intel,ich-spi"; spi-flash@0 { reg = <0>; - compatible = "sst,25vf016b", "spi-flash"; + compatible = "sst,25vf016b", "spi-flash-sst"; memory-map = <0xffe00000 0x00200000>; }; }; -- 1.8.2.1

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