March 2015 - U-Boot

Re: [U-Boot] [PATCH 14/28] drivers/fsl-mc: Changed MC firmware loading for new boot architecture
by Kim Phillips 27 Mar '15

27 Mar '15

On Tue, 24 Mar 2015 21:32:56 -0500 Stuart Yoder <b08248(a)gmail.com> wrote: > Kim, why is this being taken off-list? Adding it back. Also, please don't top-post. > I think it is premature to start focusing on saving single digit > milliseconds in u-boot. The 35 second boot time you are seeing on > some ls2085 boards is due to the fact that the MC was running with > it's CPU caches off until a few weeks ago. DDR is still running at > the slowest speed, which will affect the MC's performance. It's still > early in hardware bringup and things are not even stable yet. > > I'm still convinced that the MC itself probably has significant > performance work. > > The 1ms delay used polling for MC to boot has nothing to do with DPL > size. DPL processing is a separate, later initialization step. We're > just waiting for the MC to initialize here. The MC boot time > shouldn't vary. My visual reading watching things boot is that the MC > boot takes a few hundred milliseconds. I don't see what's wrong with > a 1 ms polling delay here. > > On a system with the MC running with caches on, u-boot took 20 seconds > to boot. The MC took about 5 seconds of that, most of that in DPL > processing. > > We would welcome help analyzing u-boot boot time and where the time is > going. But, seriously, saving 1 ms is not going to help at all. I did a quick experiment and saved ~50ms when setting both udelays down to 50, which, sure, isn't a big deal given it's out of the order of 10sec, but it's something, and, like I said, development time for our users can be seriously helped if MC initialization were omitted from the main u-boot boot sequence, and occurred only when necessary, i.e., when users want to use one of the DP net interfaces. Most of the time when we boot today, we don't use DP net interfaces, so MC init - with or without DPL processing - is just a waste of our time! Thanks, Kim > Thanks, > Stuart > > > > On Tue, Mar 24, 2015 at 10:35 AM, Kim Phillips > <kim.phillips(a)freescale.com> wrote: > > On Tue, 24 Mar 2015 10:14:39 -0500 > > Rivera Jose-B46482 <German.Rivera(a)freescale.com> wrote: > > > >> > From: Kim Phillips [mailto:kim.phillips@freescale.com] > >> > Sent: Monday, March 23, 2015 5:06 PM > >> > > >> > On Mon, 23 Mar 2015 16:15:56 -0500 > >> > Rivera Jose-B46482 <German.Rivera(a)freescale.com> wrote: > >> > > >> > > > From: Kim Phillips [mailto:kim.phillips@freescale.com] > >> > > > Sent: Monday, March 23, 2015 3:34 PM > >> > > > > >> > > > On Mon, 23 Mar 2015 15:06:11 -0500 > >> > > > Rivera Jose-B46482 <German.Rivera(a)freescale.com> wrote: > >> > > > > >> > > > > > From: Kim Phillips [mailto:kim.phillips@freescale.com] > >> > > > > > Sent: Thursday, March 19, 2015 12:53 PM > >> > > > > > > >> > > > > > On Thu, 19 Mar 2015 09:45:45 -0700 York Sun > >> > > > > > <yorksun(a)freescale.com> wrote: > >> > > > > > > >> > > > > > > From: "J. German Rivera" <German.Rivera(a)freescale.com> > >> > > > > > > > >> > > > > > > Changed MC firmware loading to comply with the new MC boot > >> > > > > > architecture. > >> > > > > > > Flush D-cache hierarchy after loading MC images. Add > >> > > > > > > environment variables "mcboottimeout" for MC boot timeout in > >> > > > > > > milliseconds, "mcmemsize" for MC DRAM block size. Check MC > >> > > > > > > boot status before calling flib functions. > >> > > > > > > >> > > > > > Can we just assign actual and/or optimal values for > >> > 'mcboottimeout' > >> > > > > > and 'mcmemsize' instead of making them environment variables? > >> > > > > > > >> > > > > Having environment variables gives us the flexibility if these > >> > > > > values need to be changed for a given customer configuration. The > >> > > > > actual > >> > > > > >> > > > what defines a 'customer configuration,' and how does that manifest > >> > > > itself at u-boot boot time? > >> > > A DPL (data path layout - a device-tree-like structure describing The > >> > > DPAA2 objects created at boot time and their connections) > >> > > > >> > > > Is it the amount of time it takes to load (and execute?) firmare? > >> > > Yes, bigger DPLs take longer to process by the MC. > >> > > > >> > > > Why isn't customer-specific firmware being loaded via linux? All > >> > > > u-boot needs is basic networking, pretty static > >> > > > setup: fixed numbers for both memsize & timeout. > >> > > This is not customer-specific firmware. What is customer-specific is > >> > just the DPL. > >> > > In order to have networking in u-boot, we need to load the MC firmware > >> > > in u-boot, For cases in which the target system has only DPAA2-based > >> > network interfaces. > >> > > >> > ok, for that case, when time comes for u-boot to do some DPAA2 networking > >> > arrives (i.e., we shouldn't have to be loading firmware at board boot- > >> > time), then we should load a minimal DPL for the number of singular, non- > >> > virtual/switch, etc., interfaces for that board just to tftp: this > >> > shouldn't be a big DPL at all, and its time complexity is fixed. > >> > > >> It is up to the customer to decide what kind of DPL they want to have. > > > > true, but in this case the 'customer' is the average upstream u-boot > > user, presumably whose DPL is the simplest ethernet use-case for > > tftp'ing kernels. > > > >> > > > > boot time of the MC and the amount of memory needed by the MC is > >> > > > > dependent on how big/complex is the DPL used. Also, the memory > >> > > > > needed by the MC needs to account for how much memory is needed > >> > > > > for AIOP programs, which may depend on how big/complex they are. > >> > > > > >> > > > ok, that helps (modulo not knowing what 'DPL' is), but still, the > >> > > > massive customer configurations should be being loaded via linux' > >> > > > firmware loading infrastructure: u-boot should be using a static > >> > > > image for u-boot's needs. > >> > > > > >> > > > > > > +static int wait_for_mc(bool booting_mc, u32 *final_reg_gsr) { > >> > > > > > > + u32 reg_gsr; > >> > > > > > > + u32 mc_fw_boot_status; > >> > > > > > > + unsigned long timeout_ms = get_mc_boot_timeout_ms(); > >> > > > > > > + struct mc_ccsr_registers __iomem *mc_ccsr_regs = > >> > > > > > > +MC_CCSR_BASE_ADDR; > >> > > > > > > + > >> > > > > > > + dmb(); > >> > > > > > > + debug("Polling mc_ccsr_regs->reg_gsr ...\n"); > >> > > > > > > + assert(timeout_ms > 0); > >> > > > > > > + for (;;) { > >> > > > > > > + udelay(1000); /* throttle polling */ > >> > > > > > > >> > > > > > does this really need to be a whole 1ms? > >> > > > > > >> > > > > It is unlikely that the MC fw will boot in less than 1 ms. > >> > > > > >> > > > is wait_for_mc() only called for the boot command, or all commands? > >> > > >> > I see: there's a udelay(500) in mc_send_command(), which is too high, > >> > too, IMO, but I'm not that familiar with the h/w: How long does the > >> > shortest command take? > > > > Can you answer this? > > > >> > > > > So, checking more frequently than 1 ms is not necessary. > >> > > > > >> > > > yes it is, because e.g., if it takes 1.1ms we will have wasted 0.9ms > >> > > > on this. > >> > > > > >> > > How significant is to save 0.9ms of the whole boot time? > >> > > >> > Why waste 0.9ms of boot time when there's no need? It already takes the > >> > boards *way* too long to boot, and now I'm understanding > >> > mc_send_command's delay should probably be adjusted, too. > >> > > >> I have not heard any complain about RDB/QDS boards taking too long to boot > >> Due to this "wasteds 0.9ms". > > > > I'm complaining now :) > > > > And it's not just about this singleton constant; it's about the > > general approach to not optimizing the code, vis-a-vis the > > mc_send_command() delay I bring up above. > > > >> Can you support your statement about LS2 RDB/QDS boards taking too long to boot > >> with actual numbers? Otherwise, I will not make any change. > > > > A board takes anywhere from 17 to 35 seconds to boot, and, from the > > prompts, a lot - if not most - of this time is spent during MC > > processing. If we take boot time down to say half of that, that > > would work miracles in how we spend our development time on them. > > > >> > > As the comment in the code says, the intent was to throttle down the > >> > > polling, to reduce traffic on the system bus due to polling. This > >> > > traffic competes with the MC itself accessing the system bus, as it > >> > > boots. Having the polling traffic get in the way of the MC traffic may > >> > > increase the MC boot time. Too small delay between polls may cause the > >> > > MC boot time to increase more than the .9ms you are concerned of > >> > wasting in the delay. > >> > > > >> > > What value would you suggest to use for the delay instead 1000ms? > >> > > >> > I don't know MC h/w: what's the shortest boot time given a standard > >> > simple "DPL"?: A small fraction of that. > >> > > >> I will not make any change at this time as there is no evidence that > >> this optimization is actually needed. > > > > this kind of attitude leaves a lot to be desired...:( > > > > Kim > > _______________________________________________ > > U-Boot mailing list > > U-Boot(a)lists.denx.de > > http://lists.denx.de/mailman/listinfo/u-boot

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[U-Boot] [PATCH] ARM: HYP/non-sec: relocation before enable secondary cores
by Peng Fan 27 Mar '15

27 Mar '15

If CONFIG_ARMV7_PSCI is not defined and CONFIG_ARMV7_SECURE_BASE is defined, smp_kicl_all_cpus may enable secondary cores and runs into secure_ram_addr( _smp_pen), before code is relocated to secure ram. So need relocation to secure ram before enable secondary cores. Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> --- arch/arm/cpu/armv7/virt-v7.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c index b69fd37..4cb8806 100644 --- a/arch/arm/cpu/armv7/virt-v7.c +++ b/arch/arm/cpu/armv7/virt-v7.c @@ -112,13 +112,20 @@ int armv7_init_nonsec(void) for (i = 1; i <= itlinesnr; i++) writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i); + /* + * Relocate secure section before any cpu runs in secure ram. + * smp_kick_all_cpus may enable other cores and runs into secure + * ram, so need to relocate secure section before enabling other + * cores. + */ + relocate_secure_section(); + #ifndef CONFIG_ARMV7_PSCI smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1); smp_kick_all_cpus(); #endif /* call the non-sec switching code on this CPU also */ - relocate_secure_section(); secure_ram_addr(_nonsec_init)(); return 0; } -- 1.8.4

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[U-Boot] [PATCH] ARMv8: bug fix of mmu setup and code optimization
by fenghua＠phytium.com.cn 27 Mar '15

27 Mar '15

From: David Feng <fenghua(a)phytium.com.cn> 1. Fix a bug of mmu_setup that variable i and j should be type long instead of int. 2. Give mmu_setup weak attribute so that other implementation can redfine it. 3. A more common set_pgtable_section(). 4. Give device memory PXN and UXN attribute. CPU may speculatively prefetch instructions from device memory, but the IO subsystem of some implementation may not support this operation. The two attributes prevent this behavior. Signed-off-by: David Feng <fenghua(a)phytium.com.cn> --- arch/arm/cpu/armv8/cache_v8.c | 73 +++++++++++++++++++++++------------- arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 22 +++++------ arch/arm/include/asm/armv8/mmu.h | 71 +++++++++++++++++++---------------- 3 files changed, 95 insertions(+), 71 deletions(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index e4415e8..023dd23 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -22,55 +22,74 @@ __weak void outer_cache_flush_range(unsigned long start, unsigned long end) {} __weak void outer_cache_inval_range(unsigned long start, unsigned long end) {} #ifndef CONFIG_SYS_DCACHE_OFF -void set_pgtable_section(u64 *page_table, u64 index, u64 section, - u64 memory_type) -{ - u64 value; - value = section | PMD_TYPE_SECT | PMD_SECT_AF; - value |= PMD_ATTRINDX(memory_type); - page_table[index] = value; +/* 42 bits virtual address */ +#define VA_BITS (42) + +/* 42 bits physical address */ +#define TCR_EL1_IPS_BITS TCR_EL1_IPS_BITS_42 +#define TCR_EL2_IPS_BITS TCR_EL2_IPS_BITS_42 +#define TCR_EL3_IPS_BITS TCR_EL3_IPS_BITS_42 + +/* PTWs cacheable, inner/outer WBWA and inner-shareable */ +#define TCR_FLAGS (TCR_TG0_64K | \ + TCR_SHARED_INNER | \ + TCR_ORGN_WBWA | \ + TCR_IRGN_WBWA | \ + TCR_T0SZ(VA_BITS)) + +void set_pgtable_section(u64 *page_table, u64 index, u64 output_address, + u64 memory_type, u64 extra_flags) +{ + page_table[index] = output_address | PMD_TYPE_SECT | PMD_SECT_AF | + PMD_SECT_SHARED_INNER | PMD_ATTRINDX(memory_type) | + extra_flags; } /* to activate the MMU we need to set up virtual memory */ -static void mmu_setup(void) +void __weak mmu_setup(void) { - int i, j, el; + int el; + u64 i, j, tcr; bd_t *bd = gd->bd; u64 *page_table = (u64 *)gd->arch.tlb_addr; /* Setup an identity-mapping for all spaces */ for (i = 0; i < (PGTABLE_SIZE >> 3); i++) { set_pgtable_section(page_table, i, i << SECTION_SHIFT, - MT_DEVICE_NGNRNE); + MT_DEVICE_NGNRNE, + PMD_SECT_PXN | PMD_SECT_UXN); + } - /* Setup an identity-mapping for all RAM space */ + /* + * Setup an identity-mapping for all RAM space. + * The secure or non-secure memory access make sense + * when u-boot running at el3 and is mostly implementation + * specific. + */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - ulong start = bd->bi_dram[i].start; - ulong end = bd->bi_dram[i].start + bd->bi_dram[i].size; + u64 start = bd->bi_dram[i].start; + u64 end = bd->bi_dram[i].start + bd->bi_dram[i].size; for (j = start >> SECTION_SHIFT; j < end >> SECTION_SHIFT; j++) { set_pgtable_section(page_table, j, j << SECTION_SHIFT, - MT_NORMAL); + MT_NORMAL, PMD_SECT_NS); } } /* load TTBR0 */ + tcr = TCR_FLAGS; el = current_el(); - if (el == 1) { - set_ttbr_tcr_mair(el, gd->arch.tlb_addr, - TCR_FLAGS | TCR_EL1_IPS_BITS, - MEMORY_ATTRIBUTES); - } else if (el == 2) { - set_ttbr_tcr_mair(el, gd->arch.tlb_addr, - TCR_FLAGS | TCR_EL2_IPS_BITS, - MEMORY_ATTRIBUTES); - } else { - set_ttbr_tcr_mair(el, gd->arch.tlb_addr, - TCR_FLAGS | TCR_EL3_IPS_BITS, - MEMORY_ATTRIBUTES); - } + if (el == 1) + tcr |= TCR_EL1_IPS_BITS; + else if (el == 2) + tcr |= TCR_EL2_IPS_BITS; + else + tcr |= TCR_EL3_IPS_BITS; + + set_ttbr_tcr_mair(el, gd->arch.tlb_addr, tcr, MEMORY_ATTRIBUTES); + /* enable the mmu */ set_sctlr(get_sctlr() | CR_M); } diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index 1f36f7e..bcd2cf2 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -82,11 +82,11 @@ static inline void early_mmu_setup(void) section_l2 = 0; for (i = 0; i < 512; i++) { set_pgtable_section(level1_table_0, i, section_l1t0, - MT_DEVICE_NGNRNE); + MT_DEVICE_NGNRNE, 0); set_pgtable_section(level1_table_1, i, section_l1t1, - MT_NORMAL); + MT_NORMAL, 0); set_pgtable_section(level2_table, i, section_l2, - MT_DEVICE_NGNRNE); + MT_DEVICE_NGNRNE, 0); section_l1t0 += BLOCK_SIZE_L1; section_l1t1 += BLOCK_SIZE_L1; section_l2 += BLOCK_SIZE_L2; @@ -108,13 +108,13 @@ static inline void early_mmu_setup(void) set_pgtable_section(level2_table, CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2, CONFIG_SYS_FSL_OCRAM_BASE, - MT_NORMAL); + MT_NORMAL, 0); for (i = CONFIG_SYS_IFC_BASE >> SECTION_SHIFT_L2; i < (CONFIG_SYS_IFC_BASE + CONFIG_SYS_IFC_SIZE) >> SECTION_SHIFT_L2; i++) { section_l2 = i << SECTION_SHIFT_L2; set_pgtable_section(level2_table, i, - section_l2, MT_NORMAL); + section_l2, MT_NORMAL, 0); } el = current_el(); @@ -154,11 +154,11 @@ static inline void final_mmu_setup(void) section_l2 = 0; for (i = 0; i < 512; i++) { set_pgtable_section(level1_table_0, i, section_l1t0, - MT_DEVICE_NGNRNE); + MT_DEVICE_NGNRNE, 0); set_pgtable_section(level1_table_1, i, section_l1t1, - MT_NORMAL); + MT_NORMAL, 0); set_pgtable_section(level2_table_0, i, section_l2, - MT_DEVICE_NGNRNE); + MT_DEVICE_NGNRNE, 0); section_l1t0 += BLOCK_SIZE_L1; section_l1t1 += BLOCK_SIZE_L1; section_l2 += BLOCK_SIZE_L2; @@ -177,7 +177,7 @@ static inline void final_mmu_setup(void) set_pgtable_section(level2_table_0, CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2, CONFIG_SYS_FSL_OCRAM_BASE, - MT_NORMAL); + MT_NORMAL, 0); /* * Fill in other part of tables if cache is needed @@ -190,7 +190,7 @@ static inline void final_mmu_setup(void) section_l2 = section_base; for (i = 0; i < 512; i++) { set_pgtable_section(level2_table_1, i, section_l2, - MT_DEVICE_NGNRNE); + MT_DEVICE_NGNRNE, 0); section_l2 += BLOCK_SIZE_L2; } tbl_base = FINAL_QBMAN_CACHED_MEM & (BLOCK_SIZE_L1 - 1); @@ -200,7 +200,7 @@ static inline void final_mmu_setup(void) i < tbl_limit >> SECTION_SHIFT_L2; i++) { section_l2 = section_base + (i << SECTION_SHIFT_L2); set_pgtable_section(level2_table_1, i, - section_l2, MT_NORMAL); + section_l2, MT_NORMAL, 0); } /* flush new MMU table */ diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 4b7b67b..2ae5ab6 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -16,27 +16,6 @@ #define UL(x) _AC(x, UL) -/***************************************************************/ -/* - * The following definitions are related each other, shoud be - * calculated specifically. - */ -#define VA_BITS (42) /* 42 bits virtual address */ - -/* PAGE_SHIFT determines the page size */ -#undef PAGE_SIZE -#define PAGE_SHIFT 16 -#define PAGE_SIZE (1 << PAGE_SHIFT) -#define PAGE_MASK (~(PAGE_SIZE-1)) - -/* - * section address mask and size definitions. - */ -#define SECTION_SHIFT 29 -#define SECTION_SIZE (UL(1) << SECTION_SHIFT) -#define SECTION_MASK (~(SECTION_SIZE-1)) -/***************************************************************/ - /* * Memory types */ @@ -65,7 +44,10 @@ /* * Section */ -#define PMD_SECT_S (3 << 8) +#define PMD_SECT_NS (1 << 5) +#define PMD_SECT_SHARED_NON (0 << 8) +#define PMD_SECT_SHARED_OUTER (2 << 8) +#define PMD_SECT_SHARED_INNER (3 << 8) #define PMD_SECT_AF (1 << 10) #define PMD_SECT_NG (1 << 11) #define PMD_SECT_PXN (UL(1) << 53) @@ -97,20 +79,42 @@ #define TCR_TG0_4K (0 << 14) #define TCR_TG0_64K (1 << 14) #define TCR_TG0_16K (2 << 14) -#define TCR_EL1_IPS_BITS (UL(3) << 32) /* 42 bits physical address */ -#define TCR_EL2_IPS_BITS (3 << 16) /* 42 bits physical address */ -#define TCR_EL3_IPS_BITS (3 << 16) /* 42 bits physical address */ +#define TCR_EL1_IPS_BITS_32 (UL(0) << 32) /* 32 bits physical address */ +#define TCR_EL1_IPS_BITS_36 (UL(1) << 32) /* 36 bits physical address */ +#define TCR_EL1_IPS_BITS_40 (UL(2) << 32) /* 40 bits physical address */ +#define TCR_EL1_IPS_BITS_42 (UL(3) << 32) /* 42 bits physical address */ +#define TCR_EL1_IPS_BITS_44 (UL(4) << 32) /* 44 bits physical address */ +#define TCR_EL1_IPS_BITS_48 (UL(5) << 32) /* 48 bits physical address */ +#define TCR_EL2_IPS_BITS_32 (0 << 16) /* 32 bits physical address */ +#define TCR_EL2_IPS_BITS_36 (1 << 16) /* 36 bits physical address */ +#define TCR_EL2_IPS_BITS_40 (2 << 16) /* 40 bits physical address */ +#define TCR_EL2_IPS_BITS_42 (3 << 16) /* 42 bits physical address */ +#define TCR_EL2_IPS_BITS_44 (4 << 16) /* 44 bits physical address */ +#define TCR_EL2_IPS_BITS_48 (5 << 16) /* 48 bits physical address */ +#define TCR_EL3_IPS_BITS_32 TCR_EL2_IPS_BITS_32 +#define TCR_EL3_IPS_BITS_36 TCR_EL2_IPS_BITS_36 +#define TCR_EL3_IPS_BITS_40 TCR_EL2_IPS_BITS_40 +#define TCR_EL3_IPS_BITS_42 TCR_EL2_IPS_BITS_42 +#define TCR_EL3_IPS_BITS_44 TCR_EL2_IPS_BITS_44 +#define TCR_EL3_IPS_BITS_48 TCR_EL2_IPS_BITS_48 -/* PTWs cacheable, inner/outer WBWA and non-shareable */ -#define TCR_FLAGS (TCR_TG0_64K | \ - TCR_SHARED_NON | \ - TCR_ORGN_WBWA | \ - TCR_IRGN_WBWA | \ - TCR_T0SZ(VA_BITS)) +/***************************************************************/ +/* PAGE_SHIFT determines the page size */ +#undef PAGE_SIZE +#define PAGE_SHIFT 16 +#define PAGE_SIZE (1 << PAGE_SHIFT) +#define PAGE_MASK (~(PAGE_SIZE-1)) + +/* Section address mask and size definitions */ +#define SECTION_SHIFT 29 +#define SECTION_SIZE (UL(1) << SECTION_SHIFT) +#define SECTION_MASK (~(SECTION_SIZE-1)) +/***************************************************************/ #ifndef __ASSEMBLY__ -void set_pgtable_section(u64 *page_table, u64 index, - u64 section, u64 memory_type); +void set_pgtable_section(u64 *page_table, u64 index, u64 output_address, + u64 memory_type, u64 extra_flags); + static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) { asm volatile("dsb sy"); @@ -132,4 +136,5 @@ static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) asm volatile("isb"); } #endif + #endif /* _ASM_ARMV8_MMU_H_ */ -- 1.7.9.5

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[U-Boot] Please pull u-boot-sunxi master
by Hans de Goede 27 Mar '15

27 Mar '15

Hi Tom, Please pull u-boot-sunxi/master into master for a small 2 bugfixes for v2015.04: The following changes since commit f643d9294f45487f22e8f33d6572530f17eff4e9: config_distro_bootcmd.h: Prefer booting from bootable paritions (2015-03-25 12:15:18 -0400) are available in the git repository at: http://git.denx.de/u-boot-sunxi.git master for you to fetch changes up to 99deda1dff206d679fcc87949b7151df0d47ea73: sunxi: axp209: fix incorrect limits on ldo3 (2015-03-26 13:17:46 +0100) ---------------------------------------------------------------- Iain Paton (1): sunxi: axp209: fix incorrect limits on ldo3 Ian Campbell (1): sunxi: set GMAC TX delay = 0x1 on Cubietruck. configs/Cubietruck_defconfig | 1 + drivers/power/axp209.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) Regards, Hans

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[U-Boot] Please pull u-boot-dm
by Simon Glass 27 Mar '15

27 Mar '15

Hi Tom, The following changes since commit b81bdf62e0cf9b5c64d30284d01658a851f142f7: bav335x: Update defconfigs and fix typo in EEPROM config format (2015-03-24 10:56:35 -0400) are available in the git repository at: http://git.denx.de/u-boot-dm.git for you to fetch changes up to 891ee87e2b4586012ce5bacd9149177f61de4ad5: dm: serial: remove bogus include <ns16550.h> (2015-03-25 16:33:27 -0600) ---------------------------------------------------------------- Masahiro Yamada (1): dm: serial: remove bogus include <ns16550.h> drivers/serial/serial-uclass.c | 2 -- 1 file changed, 2 deletions(-) Regards, Simon

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[U-Boot] Please pull u-boot-x86.git
by Simon Glass 27 Mar '15

27 Mar '15

Hi Tom, These are improvements to a new board and some code clean-ups that I requested, so I think it is probably reasonable to take these now. The following changes since commit b81bdf62e0cf9b5c64d30284d01658a851f142f7: bav335x: Update defconfigs and fix typo in EEPROM config format (2015-03-24 10:56:35 -0400) are available in the git repository at: http://git.denx.de/u-boot-x86.git for you to fetch changes up to 6f1eba49a558421e3fcb06ab0addc12b9a3804c6: x86: Add ramboot and nfsboot commands in x86-common.h (2015-03-24 21:22:38 -0600) ---------------------------------------------------------------- Bin Meng (11): x86: quark: MRC codes clean up fdtdec: Improve fdtdec_get_pci_bdf() documentation x86: Add queensbay fsp patch information in README.x86 x86: quark: Enable on-chip ethernet controllers net: Add ethernet FCS length macro in net.h net: Update README.drivers.eth to mention latest APIs net: Add Intel Topcliff GMAC driver x86: crownbay: Enable Intel Topcliff GMAC support x86: crownbay: Enable saving environment in SPI flash x86: galileo: Enable saving environment in SPI flash x86: Add ramboot and nfsboot commands in x86-common.h Tom Rini (1): arch/x86/cpu/quark/mrc.c: Switch to U_BOOT_DATE / U_BOOT_TIME arch/x86/cpu/quark/hte.c | 74 ++++---- arch/x86/cpu/quark/hte.h | 4 +- arch/x86/cpu/quark/mrc.c | 15 +- arch/x86/cpu/quark/mrc_util.c | 326 ++++++++++++++++---------------- arch/x86/cpu/quark/mrc_util.h | 34 ---- arch/x86/cpu/quark/quark.c | 19 ++ arch/x86/cpu/quark/smc.c | 1205 ++++++++++++++++++++++++++++++++++++++++++++++++++++------------------------------------------------------------------- arch/x86/cpu/quark/smc.h | 349 ++++++++++++++++++++++------------- doc/README.drivers.eth | 51 +++-- doc/README.x86 | 7 + drivers/net/Makefile | 1 + drivers/net/e1000.h | 7 +- drivers/net/pch_gbe.c | 466 ++++++++++++++++++++++++++++++++++++++++++++++ drivers/net/pch_gbe.h | 300 ++++++++++++++++++++++++++++++ drivers/usb/gadget/ether.c | 1 - drivers/usb/gadget/rndis.c | 1 - include/configs/crownbay.h | 12 ++ include/configs/galileo.h | 13 ++ include/configs/x86-common.h | 31 +++- include/fdtdec.h | 5 +- include/net.h | 2 + include/netdev.h | 4 + include/usb_ether.h | 1 - 23 files changed, 1852 insertions(+), 1076 deletions(-) create mode 100644 drivers/net/pch_gbe.c create mode 100644 drivers/net/pch_gbe.h Regards, Simon

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[U-Boot] Adding support for red pitaya zynq board; is zynq working?
by Jeremy Herbert 27 Mar '15

27 Mar '15

Hi all, I just tried to build the latest master mainline u-boot for a xilinx zynq 7010 board called the red pitaya. I'm not affiliated at all with the board, just trying to use it with a recent version of u-boot (and linux). Unfortunately it gets stuck in a reset loop (I wasn't able to nail down why, but it was definitely something in u-boot). However, I was able to successfully build u-boot using the xilinx fork here: https://github.com/Xilinx/u-boot-xlnx and have it work fine. I've attached the patch I made to add minimal support for the red pitaya (SD boot only, no ethernet as it uses an unsupported lantiq chipset). It is the policy of the xilinx u-boot fork that board support should be pushed straight upstream, but I'm not sure if this is the right place seeing as the upstream version doesn't currently work. Could someone please give me some advice on what to do with this patch? Thanks, Jeremy

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[U-Boot] serial atag tag in devicetree ?
by Hans de Goede 27 Mar '15

27 Mar '15

Hi All, I'm sending this mail because Paul Kocialkowski (in the Cc) has submitted a patch for upstream u-boot to set the serial atag tag from u-boot for Allwinner SoCs, using the SoCs SID, which is a 128 bit register containing a unique number for each SoC. In some cases a manufacturer may want to override this with its own serial from say an eeprom, as such it is desirable to communicate the serial from u-boot to the kernel rather then reproducing the sid reading code in the kernel. For old atag using kernels there is an atag for this, and the contents of this tag will show up in /proc/cpuinfo, currently there is no equivalent for this in devicetree. I'm a bit reluctant to merge Paul's patch into u-boot because of this as it will enable a feature on older kernels while leaving the upstream kernel without it. So I was wondering how to deal with this in devicetree, at least one board in u-boot already sets a devicetree property for this: board/gateworks/gw_ventana/gw_ventana.c 1202: * serial# env var 1207: char *serial = getenv("serial#"); 1432: setenv("serial#", str); 1512: fdt_setprop(blob, 0, "system-serial", getenv("serial#"), 1513: strlen(getenv("serial#")) + 1); Which sets a system-serial property in the root node, so at the same level where we also have the model string this seems to make sense to me. So do we want to add a devicetree binding for system serials, and if we do should we make it a string like above, or should we make it an 64 bit integer like the atag? If we make it a string we can store longer serials, but how should we deal with those wrt /proc/cpuinfo? Only show the first 64 bits ? Regards, Hans

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[U-Boot] [PATCH 3/3 v1] arm: ls102xa: Enable Driver Model SPI for ls1021atwr
by Haikun Wang 27 Mar '15

27 Mar '15

From: Haikun Wang <Haikun.Wang(a)freescale.com> Enable Driver Model SPI for ls1021atwr board. DSPI and QSPI are compatible under Driver Model SPI. Signed-off-by: Haikun Wang <Haikun.Wang(a)freescale.com> --- include/configs/ls1021atwr.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 0a0bb5f..6aeecda 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -235,9 +235,18 @@ #define FSL_QSPI_FLASH_SIZE (1 << 24) #define FSL_QSPI_FLASH_NUM 2 +#define CONFIG_SPI_FLASH_STMICRO +#endif + +/* DM SPI */ +#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE +#define CONFIG_DM +#define CONFIG_DM_SPI #define CONFIG_CMD_SF +#define CONFIG_DM_SPI_FLASH #define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_STMICRO #endif /* -- 1.9.1

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[U-Boot] [PATCH 2/3 v1] arm: ls102xa: Enable Driver Model SPI for ls1021aqds
by Haikun Wang 27 Mar '15

27 Mar '15

From: Haikun Wang <Haikun.Wang(a)freescale.com> Enable Driver Model SPI for ls1021aqds board. DSPI and QSPI are compatible under Driver Model SPI. Signed-off-by: Haikun Wang <Haikun.Wang(a)freescale.com> --- include/configs/ls1021aqds.h | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 3c66f87..8adb709 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -415,10 +415,22 @@ unsigned long get_board_ddr_clk(void); #define QSPI0_AMBA_BASE 0x40000000 #define FSL_QSPI_FLASH_SIZE (1 << 24) #define FSL_QSPI_FLASH_NUM 2 +#define CONFIG_SPI_FLASH_SPANSION +#endif +/* DSPI */ +#define CONFIG_FSL_DSPI +#define CONFIG_SPI_FLASH_ATMEL + +/* DM SPI */ +#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE +#define CONFIG_DM +#define CONFIG_DM_SPI #define CONFIG_CMD_SF +#define CONFIG_DM_SPI_FLASH #define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_SPANSION #endif /* -- 1.9.1

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