December 2015 - U-Boot

[U-Boot] [PATCH] arm: socfpga: arria10: add additional i2c nodes for Arria10
by dinguyen＠opensource.altera.com 02 Dec '15

02 Dec '15

From: Dinh Nguyen <dinguyen(a)opensource.altera.com> Add remaining 3 I2C base addresses for the Arria10. Signed-off-by: Dinh Nguyen <dinguyen(a)opensource.altera.com> --- arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h index a7056d4..8653dd5 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h @@ -29,6 +29,10 @@ #define SOCFPGA_MPUL2_ADDRESS 0xfffff000 #define SOCFPGA_I2C0_ADDRESS 0xffc02200 #define SOCFPGA_I2C1_ADDRESS 0xffc02300 +#define SOCFPGA_I2C2_ADDRESS 0xffc02400 +#define SOCFPGA_I2C3_ADDRESS 0xffc02500 +#define SOCFPGA_I2C4_ADDRESS 0xffc02600 + #define SOCFPGA_ECC_OCRAM_ADDRESS 0xff8c3000 #define SOCFPGA_UART0_ADDRESS 0xffc02000 -- 2.6.2

4 3

[U-Boot] [PATCH 2/2] Remove fdtfile list from Raspberry Pi
by Marco Schuster 02 Dec '15

02 Dec '15

As pass-through of the processed FDT is working now, there is no need for the RPi u-boot any more to load fdt files. This patch removes the fdtfile list and the setter for the env variable "fdtfile". This also removes the naming inconsistencies between the fdtfile names in u-boot and the fdtfile names in the official Raspberry Pi Firmware repository. --- board/raspberrypi/rpi/rpi.c | 36 ------------------------------------ 1 file changed, 36 deletions(-) diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index d8d0fbb..adba458 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -77,108 +77,84 @@ struct msg_get_clock_rate { /* See comments in mbox.h for data source */ static const struct { const char *name; - const char *fdtfile; bool has_onboard_eth; } models[] = { [0] = { "Unknown model", -#ifdef CONFIG_BCM2836 - "bcm2836-rpi-other.dtb", -#else - "bcm2835-rpi-other.dtb", -#endif false, }, #ifdef CONFIG_BCM2836 [BCM2836_BOARD_REV_2_B] = { "2 Model B", - "bcm2836-rpi-2-b.dtb", true, }, #else [BCM2835_BOARD_REV_B_I2C0_2] = { "Model B (no P5)", - "bcm2835-rpi-b-i2c0.dtb", true, }, [BCM2835_BOARD_REV_B_I2C0_3] = { "Model B (no P5)", - "bcm2835-rpi-b-i2c0.dtb", true, }, [BCM2835_BOARD_REV_B_I2C1_4] = { "Model B", - "bcm2835-rpi-b.dtb", true, }, [BCM2835_BOARD_REV_B_I2C1_5] = { "Model B", - "bcm2835-rpi-b.dtb", true, }, [BCM2835_BOARD_REV_B_I2C1_6] = { "Model B", - "bcm2835-rpi-b.dtb", true, }, [BCM2835_BOARD_REV_A_7] = { "Model A", - "bcm2835-rpi-a.dtb", false, }, [BCM2835_BOARD_REV_A_8] = { "Model A", - "bcm2835-rpi-a.dtb", false, }, [BCM2835_BOARD_REV_A_9] = { "Model A", - "bcm2835-rpi-a.dtb", false, }, [BCM2835_BOARD_REV_B_REV2_d] = { "Model B rev2", - "bcm2835-rpi-b-rev2.dtb", true, }, [BCM2835_BOARD_REV_B_REV2_e] = { "Model B rev2", - "bcm2835-rpi-b-rev2.dtb", true, }, [BCM2835_BOARD_REV_B_REV2_f] = { "Model B rev2", - "bcm2835-rpi-b-rev2.dtb", true, }, [BCM2835_BOARD_REV_B_PLUS] = { "Model B+", - "bcm2835-rpi-b-plus.dtb", true, }, [BCM2835_BOARD_REV_CM] = { "Compute Module", - "bcm2835-rpi-cm.dtb", false, }, [BCM2835_BOARD_REV_A_PLUS] = { "Model A+", - "bcm2835-rpi-a-plus.dtb", false, }, [BCM2835_BOARD_REV_B_PLUS_13] = { "Model B+", - "bcm2835-rpi-b-plus.dtb", true, }, [BCM2835_BOARD_REV_CM_14] = { "Compute Module", - "bcm2835-rpi-cm.dtb", false, }, [BCM2835_BOARD_REV_A_PLUS_15] = { "Model A+", - "bcm2835-rpi-a-plus.dtb", false, }, #endif @@ -205,17 +181,6 @@ int dram_init(void) return 0; } -static void set_fdtfile(void) -{ - const char *fdtfile; - - if (getenv("fdtfile")) - return; - - fdtfile = models[rpi_board_rev].fdtfile; - setenv("fdtfile", fdtfile); -} - static void set_usbethaddr(void) { ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_mac_address, msg, 1); @@ -254,7 +219,6 @@ static void set_board_info(void) int misc_init_r(void) { - set_fdtfile(); set_usbethaddr(); #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG set_board_info(); -- 2.6.2

2 1

[U-Boot] [PATCH v4] arm: Add sata support on Layerscape ARMv8 board
by Yuantian.Tang＠freescale.com 02 Dec '15

02 Dec '15

From: Tang Yuantian <Yuantian.Tang(a)freescale.com> Freescale ARM-based Layerscape contains a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds SATA feature on ls2080aqds, ls2080ardb and ls1043aqds boards. Signed-off-by: Tang Yuantian <Yuantian.Tang(a)freescale.com> --- v4: - rebase to lastest git tree - add another ARMv8 platform which is ls1043aqds v3: - rename ls2085a to ls2080a - rebase to the latest git tree - replace the magic number with micro variable v2: - rebase to the latest git tree arch/arm/cpu/armv8/fsl-layerscape/soc.c | 43 +++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 18 ++++++++++ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 31 ++++++++++++++++ include/configs/ls1043aqds.h | 17 +++++++++ 4 files changed, 109 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 8896b70..574ffc4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -6,6 +6,8 @@ #include <common.h> #include <fsl_ifc.h> +#include <ahci.h> +#include <scsi.h> #include <asm/arch/soc.h> #include <asm/io.h> #include <asm/global_data.h> @@ -120,7 +122,44 @@ void fsl_lsch3_early_init_f(void) erratum_a009203(); } +#ifdef CONFIG_SCSI_AHCI_PLAT +int sata_init(void) +{ + struct ccsr_ahci __iomem *ccsr_ahci; + + ccsr_ahci = (void *)CONFIG_SYS_SATA2; + out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); + out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); + + ccsr_ahci = (void *)CONFIG_SYS_SATA1; + out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); + out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); + + ahci_init((void __iomem *)CONFIG_SYS_SATA1); + scsi_scan(0); + + return 0; +} +#endif + #elif defined(CONFIG_LS1043A) +#ifdef CONFIG_SCSI_AHCI_PLAT +int sata_init(void) +{ + struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA; + + out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); + out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG); + out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG); + out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); + + ahci_init((void __iomem *)CONFIG_SYS_SATA); + scsi_scan(0); + + return 0; +} +#endif + void fsl_lsch2_early_init_f(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; @@ -141,6 +180,10 @@ void fsl_lsch2_early_init_f(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { +#ifdef CONFIG_SCSI_AHCI_PLAT + sata_init(); +#endif + return 0; } #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index b5a2d28..be3acc3 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -54,6 +54,24 @@ #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN +/* SATA */ +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_CMD_SCSI +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + 0x02200000) +#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + 0x02210000) + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0x06000000 #define GICR_BASE 0x06100000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 504c1f9..83186d6 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -51,6 +51,37 @@ struct cpu_type { #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) +/* ahci port register default value */ +#define AHCI_PORT_PHY_1_CFG 0xa003fffe +#define AHCI_PORT_PHY_2_CFG 0x28184d1f +#define AHCI_PORT_PHY_3_CFG 0x0e081509 +#define AHCI_PORT_TRANS_CFG 0x08000025 + +/* AHCI (sata) register map */ +struct ccsr_ahci { + u32 res1[0xa4/4]; /* 0x0 - 0xa4 */ + u32 pcfg; /* port config */ + u32 ppcfg; /* port phy1 config */ + u32 pp2c; /* port phy2 config */ + u32 pp3c; /* port phy3 config */ + u32 pp4c; /* port phy4 config */ + u32 pp5c; /* port phy5 config */ + u32 axicc; /* AXI cache control */ + u32 paxic; /* port AXI config */ + u32 axipc; /* AXI PROT control */ + u32 ptc; /* port Trans Config */ + u32 pts; /* port Trans Status */ + u32 plc; /* port link config */ + u32 plc1; /* port link config1 */ + u32 plc2; /* port link config2 */ + u32 pls; /* port link status */ + u32 pls1; /* port link status1 */ + u32 pcmdc; /* port CMD config */ + u32 ppcs; /* port phy control status */ + u32 pberr; /* port 0/1 BIST error */ + u32 cmds; /* port 0/1 CMD status error */ +}; + #ifdef CONFIG_FSL_LSCH3 void fsl_lsch3_early_init_f(void); #elif defined(CONFIG_FSL_LSCH2) diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 4aeb238..bd7af00 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -88,6 +88,23 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg #endif +/* SATA */ +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_CMD_SCSI +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_SYS_SATA (CONFIG_SYS_IMMR + 0x02200000) + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + /* * IFC Definitions */ -- 2.1.0.27.g96db324

4 11

[U-Boot] U-boot broken on e500v2 soc
by York Sun 02 Dec '15

02 Dec '15

Valentin, Can you refresh my memory why you needed this commitac337168ad81a18e768e5e3cfff8d229adeb2b25 (patch http://patchwork.ozlabs.org/patch/455439)? Today I bisect an issue back to this commit. Scott, Can you help to examine this u-boot commit? Before this commit, 512x/5xxx/83xx/85xx do nothing on function invalidate_dcache_range() and flush_dcache_range(). With this patch, I found e500v2 is broken on Intel e1000 card when testing v2016-rc1. I didn't catch this issue when testing this patch. I wonder if this code is not safe for e500v2, or because the cache line size should be determined by reading L1CFG0. Why didn't we see any issue with Linux with the same code. Log for testing on e500v2 P1023RDB U-Boot 2016.01-rc1-00115-g2b24e09 (Nov 20 2015 - 22:01:56 -0800) CPU0: P1023E, Version: 1.1, (0x80fe0011) Core: e500, Version: 5.1, (0x80212151) Clock Configuration: CPU0:500 MHz, CPU1:500 MHz, CCB:333.333 MHz, DDR:333.333 MHz (666.667 MT/s data rate) (Asynchronous), LBC:41.667 MHz FMAN1: 333.333 MHz QMAN: 0 MHz L1: D-cache 32 KiB enabled I-cache 32 KiB enabled Board: P1023 RDB I2C: ready DRAM: DIMM 0: is not a DDR3 SPD. SPD error on controller 0! Trying fallback to raw timing calculation Detected UDIMM Fixed DDR on board 512 MiB (DDR3, 32-bit, CL=5, ECC off) Flash: 64 MiB L2: 256 KiB enabled NAND: 128 MiB EEPROM: CRC mismatch (a7fdad5b != ffffffff) PCIe1: Root Complex of Slot 1, no link, regs @ 0xff60a000 PCIe1: Bus 00 - 00 PCIe2: Root Complex of Slot 2, x1 gen1, regs @ 0xff609000 02:00.0 - 8086:107d - Network controller PCIe2: Bus 01 - 02 PCIe3: Root Complex of Slot 3, x1 gen1, regs @ 0xff60b000 04:00.0 - 168c:0030 - Network controller PCIe3: Bus 03 - 04 In: serial Out: serial Err: serial Net: Fman1: Uploading microcode version 160.0.18 e1000: 00:15:17:8e:7b:8d FM1@DTSEC1, FM1@DTSEC2, e1000#0 [PRIME] Warning: e1000#0 MAC addresses don't match: Address in SROM is 00:15:17:8e:7b:8d Address in environment is 00:e0:0c:00:06:02 => ping $serverip Using e1000#0 device Bad trap at PC: 1ffc6f10, SR: 6049434, vector=e00 NIP: 1FFC6F10 XER: 00000000 LR: 1FEF0B6C REGS: 1f8eda70 TRAP: 0e00 DAR: 20000000 MSR: 06049434 EE: 1 PR: 0 FP: 0 ME: 1 IR/DR: 11 GPR00: 1FF457D4 1F8EDB60 1F8EDF14 20000000 00020000 0000001F 00000000 1F8EDAB8 GPR08: A0003818 00004000 00000003 1F8EDB80 1FF457D4 EC662032 1FFC8D50 1FFC6F24 GPR16: 1FFB0074 1FFB005C 1FF59701 1FF5971F 1FF49C37 1FFB0068 00000000 1FFC6F10 GPR24: 1FFB00CC 1FF48D60 00000000 1F8F3D70 1FFC5600 00400000 1FF5C610 00400000 Call backtrace: 1FF2F350 1FF457D4 1FF06888 1FF13AF8 1FEFA180 1FEFA7FC 1FEF9A90 1FEFA124 1FEFA7FC 1FEFAA1C 1FF12B54 1FEFB140 1FF3AA7C 1FEFB454 1FEF0F4C Exception in kernel pc 1ffc6f10 signal 0 ### ERROR ### Please RESET the board ### P1022DS log U-Boot 2016.01-rc1-00115-g2b24e09 (Nov 20 2015 - 22:17:10 -0800) CPU0: P1022E, Version: 1.0, (0x80ee0010) Core: e500, Version: 5.0, (0x80211050) Clock Configuration: CPU0:999.990 MHz, CPU1:999.990 MHz, CCB:499.995 MHz, DDR:333.330 MHz (666.660 MT/s data rate) (Asynchronous), LBC:31.250 MHz L1: D-cache 32 KiB enabled I-cache 32 KiB enabled Board: P1022DS Sys ID: 0x19, Sys Ver: 0x03, FPGA Ver: 0x09, vBank: 0 I2C: ready SPI: ready DRAM: Detected RDIMM 18JSF51272PDZ1G4D1 Detected 4 GiB of memory This U-Boot only supports < 4G of DDR You could rebuild it with CONFIG_PHYS_64BIT 2 GiB (DDR3, 64-bit, CL=5, ECC off) Flash: 128 MiB L2: 256 KiB enabled NAND: 1024 MiB MMC: FSL_SDHC: 0 EEPROM: NXID v0 PCIe1: Root Complex of Slot 1, no link, regs @ 0xffe0a000 PCIe1: Bus 00 - 00 PCIe2: Root Complex of Slot 3, x1 gen1, regs @ 0xffe09000 02:00.0 - 8086:10b9 - Network controller PCIe2: Bus 01 - 02 PCIe3: Root Complex of Slot 2, no link, regs @ 0xffe0b000 PCIe3: Bus 03 - 03 In: serial Out: serial Err: serial Net: e1000: 00:15:17:0b:8c:74 eTSEC1, eTSEC2, e1000#0 [PRIME] Hit any key to stop autoboot: 0 => ping $serverip Using e1000#0 device pci_bus_to_hose() failed pci_hose_phys_to_bus: invalid hose pci_bus_to_hose() failed pci_hose_phys_to_bus: invalid hose Abort

3 4

[U-Boot] [PATCH v2 0/3] spl: mmc: Fix warning and unify spl_mmc_find_device()
by Simon Glass 02 Dec '15

02 Dec '15

This little series fixes a compiler warning in SPL MMC which affects Rockchip. It also joins up the spl_mmc_find_device() function again. I feel that splitting the function was the wrong approach as discussed here: https://patchwork.ozlabs.org/patch/537276/ The first patch fixes the warning. The other two are suggested improvements but are separate from that problem. Changes in v2: - Fix the warning in the commit message (it was the wrong one) Simon Glass (3): spl: mmc: Fix compiler warning with CONFIG_DM_MMC spl: mmc: Rename 'mmc' variable to 'mmcp' spl: mmc: Unify non/driver model spl_mmc_find_device() common/spl/spl_mmc.c | 44 +++++++++++--------------------------------- 1 file changed, 11 insertions(+), 33 deletions(-) -- 2.6.0.rc2.230.g3dd15c0

1 3

[U-Boot] [RFC] arm: socfpga: introduce SOCFPGA_GEN5 or SOCFPGA_GEN10
by dinguyen＠opensource.altera.com 02 Dec '15

02 Dec '15

From: Dinh Nguyen <dinguyen(a)opensource.altera.com> Define SOCFPGA_GEN5 which applies to Arria5/Cyclone5 hardware, and SOCFPGA_GEN10 for Arria10 hardware. This would allow us to use the shorten define in the rest of code. Signed-off-by: Dinh Nguyen <dinguyen(a)opensource.altera.com> --- include/configs/socfpga_common.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 3374683..8fc5666 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -6,6 +6,11 @@ #ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ #define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA5) || defined(CONFIG_TARGET_SOCFPGA_CYCLONE5) +#define SOCFPGA_GEN5 +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#define SOCFPGA_GEN10 +#endif /* Virtual target or real hardware */ #undef CONFIG_SOCFPGA_VIRTUAL_TARGET -- 2.6.2

3 3

[U-Boot] Please pull u-boot-rockchip
by Simon Glass 02 Dec '15

02 Dec '15

Hi Tom, (This comes after the u-boot-dm request) This includes a few fixes and support for the Rockchip RK3036. The following changes since commit 3ba5f74a541f77bfb6904e684e2cf0bfad005106: dm: pci: Disable PCI compatibility functions by default (2015-12-01 06:26:38 -0700) are available in the git repository at: git://git.denx.de/u-boot-rockchip.git for you to fetch changes up to 00ea76e8004e8582798123f3698f91b32514810f: rockchip: Explicitly set CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN (2015-12-01 08:07:22 -0700) ---------------------------------------------------------------- Ariel D'Alessandro (1): rockchip: move SYS_MALLOC_SIMPLE to mach-rockchip Kconfig Jeffy Chen (2): rockchip: Add max spl size & spl header configs rockchip: Add support for rk's second level loader Sjoerd Simons (4): rockchip: Also load the initrd below 512M rockchip: firefly: Save the environment on SD card Revert "rockchip: Reconfigure the malloc based to point to system memory" rockchip: Explicitly set CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN huang lin (21): rockchip: add timer driver rockchip: move SYS_MALLOC_F_LEN to rk3288 own Kconfig rockchip: rename board-spl.c to rk3288-board-spl.c rockchip: add config decide whether to build common.c dm: core: Add SPL Kconfig for REGMAP and SYSCON rockchip: serial driver support rk3036 rockchip: Bring in RK3036 device tree file includes and bindings rockchip: rk3036: Add clock driver rockchip: rk3036: Add header files for GRF rockchip: rk3036: Add Soc reset driver rockchip: rk3036: Add a simple syscon driver rockchip: rk3036: Add pinctrl driver mmc: dw_mmc: move data transfer as a separate function mmc: dw_mmc: support fifo mode in dwc mmc driver rockchip: mmc: use non-removable property to distinguish emmc and sdcard register rockchip: mmc: get the fifo mode and fifo depth property from dts rockchip: add early uart driver rockchip: add rk3036 sdram driver rockchip: rk3036: Add core Soc start-up code rockchip: Add basic support for evb-rk3036 board rockchip: doc: show packet rk3036 uboot image arch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3036-sdk.dts | 46 ++++ arch/arm/dts/rk3036.dtsi | 428 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 168 ++++++++++++ arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 493 +++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-rockchip/sdram_rk3036.h | 341 +++++++++++++++++++++++ arch/arm/include/asm/arch-rockchip/timer.h | 22 ++ arch/arm/include/asm/arch-rockchip/uart.h | 44 +++ arch/arm/mach-rockchip/Kconfig | 29 +- arch/arm/mach-rockchip/Makefile | 10 +- arch/arm/mach-rockchip/board.c | 1 + arch/arm/mach-rockchip/rk3036-board-spl.c | 55 ++++ arch/arm/mach-rockchip/rk3036/Kconfig | 23 ++ arch/arm/mach-rockchip/rk3036/Makefile | 13 + arch/arm/mach-rockchip/rk3036/reset_rk3036.c | 45 ++++ arch/arm/mach-rockchip/rk3036/save_boot_param.S | 32 +++ arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 764 ++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/rk3036/syscon_rk3036.c | 21 ++ arch/arm/mach-rockchip/{board-spl.c => rk3288-board-spl.c} | 28 +- arch/arm/mach-rockchip/rk3288/Kconfig | 9 + arch/arm/mach-rockchip/rk_early_print.c | 63 +++++ arch/arm/mach-rockchip/rk_timer.c | 48 ++++ board/evb_rk3036/evb_rk3036/Kconfig | 15 ++ board/evb_rk3036/evb_rk3036/MAINTAINERS | 0 board/evb_rk3036/evb_rk3036/Makefile | 7 + board/evb_rk3036/evb_rk3036/evb_rk3036.c | 49 ++++ configs/chromebook_jerry_defconfig | 3 + configs/evb-rk3036_defconfig | 26 ++ configs/firefly-rk3288_defconfig | 3 + configs/sandbox_defconfig | 2 + doc/README.rockchip | 11 + drivers/clk/Makefile | 1 + drivers/clk/clk_rk3036.c | 414 ++++++++++++++++++++++++++++ drivers/core/Kconfig | 19 ++ drivers/core/Makefile | 4 +- drivers/mmc/dw_mmc.c | 140 +++++++--- drivers/mmc/rockchip_dw_mmc.c | 26 +- drivers/pinctrl/Kconfig | 9 + drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl_rk3036.c | 276 +++++++++++++++++++ drivers/serial/ns16550.c | 1 + include/configs/chromebook_jerry.h | 1 + include/configs/evb_rk3036.h | 12 + include/configs/firefly-rk3288.h | 8 + include/configs/rk3036_common.h | 99 +++++++ include/configs/rk3288_common.h | 12 +- include/dt-bindings/clock/rk3036-cru.h | 186 +++++++++++++ include/dwmmc.h | 5 + tools/Makefile | 8 +- tools/rkcommon.c | 26 +- tools/rkcommon.h | 4 +- tools/rkimage.c | 2 +- tools/rksd.c | 6 +- tools/rkspi.c | 6 +- 54 files changed, 3955 insertions(+), 113 deletions(-) create mode 100644 arch/arm/dts/rk3036-sdk.dts create mode 100644 arch/arm/dts/rk3036.dtsi create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3036.h create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3036.h create mode 100644 arch/arm/include/asm/arch-rockchip/sdram_rk3036.h create mode 100644 arch/arm/include/asm/arch-rockchip/timer.h create mode 100644 arch/arm/include/asm/arch-rockchip/uart.h create mode 100644 arch/arm/mach-rockchip/rk3036-board-spl.c create mode 100644 arch/arm/mach-rockchip/rk3036/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3036/Makefile create mode 100644 arch/arm/mach-rockchip/rk3036/reset_rk3036.c create mode 100644 arch/arm/mach-rockchip/rk3036/save_boot_param.S create mode 100644 arch/arm/mach-rockchip/rk3036/sdram_rk3036.c create mode 100644 arch/arm/mach-rockchip/rk3036/syscon_rk3036.c rename arch/arm/mach-rockchip/{board-spl.c => rk3288-board-spl.c} (90%) create mode 100644 arch/arm/mach-rockchip/rk_early_print.c create mode 100644 arch/arm/mach-rockchip/rk_timer.c create mode 100644 board/evb_rk3036/evb_rk3036/Kconfig create mode 100644 board/evb_rk3036/evb_rk3036/MAINTAINERS create mode 100644 board/evb_rk3036/evb_rk3036/Makefile create mode 100644 board/evb_rk3036/evb_rk3036/evb_rk3036.c create mode 100644 configs/evb-rk3036_defconfig create mode 100644 drivers/clk/clk_rk3036.c create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3036.c create mode 100644 include/configs/evb_rk3036.h create mode 100644 include/configs/rk3036_common.h create mode 100644 include/dt-bindings/clock/rk3036-cru.h Regards, Simon

2 1

[U-Boot] Please pull u-boot-dm
by Simon Glass 02 Dec '15

02 Dec '15

Hi Tom, This includes conversion of x86 to use the timer uclass and moving Tegra to driver model for PCI. The following changes since commit 4a421a67b6f36678bfd27b7fedc0de35faf94c76: Merge branch 'master' of git://git.denx.de/u-boot-atmel (2015-11-30 18:13:10 -0500) are available in the git repository at: git://git.denx.de/u-boot-dm.git for you to fetch changes up to 3ba5f74a541f77bfb6904e684e2cf0bfad005106: dm: pci: Disable PCI compatibility functions by default (2015-12-01 06:26:38 -0700) ---------------------------------------------------------------- Bin Meng (11): dm: timer: Fix several nits dm: timer: Implement pre_probe() timer: altera: Remove the codes to get clock frequency timer: sandbox: Use device tree to pass the clock frequency dm: timer: Support 64-bit counter x86: Remove MIN_PORT80_KCLOCKS_DELAY x86: tsc: Use notrace from <linux/compiler.h> x86: tsc: Add driver model timer support x86: Convert to use driver model timer x86: tsc: Remove legacy timer codes x86: tsc: Move tsc_timer.c to drivers/timer Simon Glass (22): dm: timer: Avoid using timer before it is ready dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig dm: pci: Avoid a driver model build error with CONFIG_CMD_PCI_ENUM dm: pci: Set up the SDRAM mapping correctly dm: pci: Support decoding ranges with duplicate entries dm: pci: Add functions to emulate 8- and 16-bit access dm: pci: Add a function to get the controller for a bus dm: pci: Add a function to find the regions for a PCI bus dm: tegra: pci: Convert tegra boards to driver model for PCI pci: Use a common return in command processing pci: Use a separate variable for the bus number pci: Refactor the pciinfo() function dm: pci: Add a comment about how to find struct pci_controller dm: pci: Rename pci_auto.c to pci_auto_old.c dm: pci: Move common auto-config functions to a common file dm: pci: Reorder functions in cmd_pci.c pci: Tidy up function comments in cmd_pci.c pci: Use common functions to read/write config pci: Use a separate 'dev' variable for the PCI device pci: Move PCI header output code into its own function dm: pci: Convert 'pci' command to driver model dm: pci: Disable PCI compatibility functions by default Stephen Warren (1): ARM: tegra: refactor common Kconfig options arch/arm/mach-tegra/Kconfig | 40 +++-- arch/arm/mach-tegra/board2.c | 4 + arch/sandbox/dts/sandbox.dts | 1 + arch/x86/Kconfig | 23 +-- arch/x86/cpu/baytrail/valleyview.c | 3 - arch/x86/cpu/coreboot/timestamp.c | 22 --- arch/x86/cpu/cpu.c | 18 -- arch/x86/cpu/efi/efi.c | 4 - arch/x86/cpu/ivybridge/cpu.c | 1 - arch/x86/cpu/qemu/Kconfig | 1 - arch/x86/cpu/qemu/qemu.c | 3 - arch/x86/cpu/quark/Kconfig | 5 - arch/x86/cpu/quark/quark.c | 3 - arch/x86/cpu/queensbay/tnc.c | 3 - arch/x86/dts/bayleybay.dts | 1 + arch/x86/dts/broadwell_som-6896.dts | 1 + arch/x86/dts/chromebook_link.dts | 1 + arch/x86/dts/chromebox_panther.dts | 1 + arch/x86/dts/crownbay.dts | 1 + arch/x86/dts/efi.dts | 5 + arch/x86/dts/galileo.dts | 5 + arch/x86/dts/minnowmax.dts | 1 + arch/x86/dts/qemu-x86_i440fx.dts | 5 + arch/x86/dts/qemu-x86_q35.dts | 5 + arch/x86/dts/tsc_timer.dtsi | 6 + arch/x86/include/asm/global_data.h | 3 - arch/x86/lib/Makefile | 1 - common/board_r.c | 10 +- common/cmd_pci.c | 635 +++++++++++++++++++++++++++++++++++++++++++------------------------ configs/apalis_t30_defconfig | 1 + configs/bayleybay_defconfig | 1 + configs/beaver_defconfig | 4 + configs/cardhu_defconfig | 4 + configs/chromebook_link_defconfig | 1 + configs/chromebox_panther_defconfig | 1 + configs/coreboot-x86_defconfig | 2 +- configs/crownbay_defconfig | 1 + configs/efi-x86_defconfig | 3 +- configs/galileo_defconfig | 1 + configs/jetson-tk1_defconfig | 4 + configs/minnowmax_defconfig | 1 + configs/p2371-2180_defconfig | 1 + configs/qemu-x86_defconfig | 1 + configs/sandbox_defconfig | 1 + configs/trimslice_defconfig | 4 + drivers/pci/Kconfig | 19 ++ drivers/pci/Makefile | 5 +- drivers/pci/pci-uclass.c | 105 ++++++++++- drivers/pci/pci_auto_common.c | 128 ++++++++++++++ drivers/pci/{pci_auto.c => pci_auto_old.c} | 116 ------------- drivers/pci/pci_tegra.c | 477 +++++++++++++++++--------------------------------- drivers/timer/Kconfig | 19 +- drivers/timer/Makefile | 1 + drivers/timer/altera_timer.c | 10 +- drivers/timer/sandbox_timer.c | 6 +- drivers/timer/timer-uclass.c | 30 +++- {arch/x86/lib => drivers/timer}/tsc_timer.c | 104 ++++++----- include/common.h | 1 - include/configs/apalis_t30.h | 2 - include/configs/beaver.h | 2 - include/configs/cardhu.h | 2 - include/configs/jetson-tk1.h | 2 - include/configs/p2371-2180.h | 2 - include/configs/trimslice.h | 2 - include/configs/x86-common.h | 2 - include/fdtdec.h | 4 - include/pci.h | 83 ++++++++- include/timer.h | 25 ++- lib/fdtdec.c | 4 - lib/time.c | 9 +- 70 files changed, 1111 insertions(+), 892 deletions(-) create mode 100644 arch/x86/dts/tsc_timer.dtsi create mode 100644 drivers/pci/pci_auto_common.c rename drivers/pci/{pci_auto.c => pci_auto_old.c} (81%) rename {arch/x86/lib => drivers/timer}/tsc_timer.c (87%) Regards, Simon

2 1

[U-Boot] [PATCH v2] net: gem: Enable CTRL+C in wait_for_bit
by Michal Simek 01 Dec '15

01 Dec '15

Enable to break waiting loop at any time. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- Changes in v2: - Change return value to EINTR - Add missing header for ctrlc drivers/net/zynq_gem.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 858093f0d7e2..81bd8b94901b 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -13,6 +13,7 @@ #include <net.h> #include <netdev.h> #include <config.h> +#include <console.h> #include <fdtdec.h> #include <libfdt.h> #include <malloc.h> @@ -447,6 +448,11 @@ static int wait_for_bit(const char *func, u32 *reg, const u32 mask, if (get_timer(start) > timeout) break; + if (ctrlc()) { + puts("Abort\n"); + return -EINTR; + } + udelay(1); } -- 1.9.1

2 1

[U-Boot] [PATCH v3] usb: add support for generic EHCI devices
by Alexey Brodkin 01 Dec '15

01 Dec '15

From: Alexey Brodkin <Alexey.Brodkin(a)synopsys.com> This driver is meant to be used with any EHCI-compatible host controller in case if there's no need for platform-specific glue such as setup of controller or PHY's power mode via GPIOs etc. Signed-off-by: Alexey Brodkin <abrodkin(a)synopsys.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> Reviewed-by: Marek Vasut <marex(a)denx.de> Cc: Stephen Warren <swarren(a)nvidia.com> --- Changes compared to v2: * Driver is disabled by default now * Use uintptr_t instead of uint32_t for "struct ehci_hcor" address calculation Changes compared to v1: * Updated commit message with removal of Synopsys board mention * Cleaned-up ehci_usb_remove() drivers/usb/host/Kconfig | 7 ++++++ drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-generic.c | 51 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 59 insertions(+) create mode 100644 drivers/usb/host/ehci-generic.c diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 2a2bffe..6bb9caa 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -73,4 +73,11 @@ config USB_EHCI_UNIPHIER ---help--- Enables support for the on-chip EHCI controller on UniPhier SoCs. +config USB_EHCI_GENERIC + bool "Support for generic EHCI USB controller" + depends on OF_CONTROL + default n + ---help--- + Enables support for generic EHCI controller. + endif diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index f70f38c..b9b4471 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -32,6 +32,7 @@ else obj-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o endif obj-$(CONFIG_USB_EHCI_FARADAY) += ehci-faraday.o +obj-$(CONFIG_USB_EHCI_GENERIC) += ehci-generic.o obj-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o obj-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o obj-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c new file mode 100644 index 0000000..22e1ad0 --- /dev/null +++ b/drivers/usb/host/ehci-generic.c @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2015 Alexey Brodkin <abrodkin(a)synopsys.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include "ehci.h" + +/* + * Even though here we don't explicitly use "struct ehci_ctrl" + * ehci_register() expects it to be the first thing that resides in + * device's private data. + */ +struct generic_ehci { + struct ehci_ctrl ctrl; +}; + +static int ehci_usb_probe(struct udevice *dev) +{ + struct ehci_hccr *hccr = (struct ehci_hccr *)dev_get_addr(dev); + struct ehci_hcor *hcor; + + hcor = (struct ehci_hcor *)((uintptr_t)hccr + + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + + return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST); +} + +static int ehci_usb_remove(struct udevice *dev) +{ + return ehci_deregister(dev); +} + +static const struct udevice_id ehci_usb_ids[] = { + { .compatible = "generic-ehci" }, + { } +}; + +U_BOOT_DRIVER(usb_ehci) = { + .name = "ehci_generic", + .id = UCLASS_USB, + .of_match = ehci_usb_ids, + .probe = ehci_usb_probe, + .remove = ehci_usb_remove, + .ops = &ehci_usb_ops, + .priv_auto_alloc_size = sizeof(struct generic_ehci), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; + -- 2.5.0

3 7