December 2015 - U-Boot

[U-Boot] [PATCH v3 10/10] mvebu: ds414: Implement Synology specific command set
by Phil Sutter 13 Jan '16

13 Jan '16

Synology keeps per item configuration in a dedicated 'partition' in SPI flash, namely the one named 'vendor' in DTS file. It contains the two NICs MAC addresses as well as the item's serial number. I didn't find a way to have this information extracted automatically, therefore implemented 'syno populate_env' command which extracts the three values and puts them into environment. To make things permanent though, one has to 'saveenv'. Another command is 'syno clk_gate', which allows to change the clock gating which is done in DS414 board file. Signed-off-by: Phil Sutter <phil(a)nwl.cc> --- board/Synology/common/Makefile | 7 ++ board/Synology/common/cmd_syno.c | 227 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 234 insertions(+) create mode 100644 board/Synology/common/Makefile create mode 100644 board/Synology/common/cmd_syno.c diff --git a/board/Synology/common/Makefile b/board/Synology/common/Makefile new file mode 100644 index 0000000..e66aeb8 --- /dev/null +++ b/board/Synology/common/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2015 Phil Sutter <phil(a)nwl.cc> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := cmd_syno.o diff --git a/board/Synology/common/cmd_syno.c b/board/Synology/common/cmd_syno.c new file mode 100644 index 0000000..4a1918d --- /dev/null +++ b/board/Synology/common/cmd_syno.c @@ -0,0 +1,227 @@ +/* + * Commands to deal with Synology specifics. + * + * Copyright (C) 2015 Phil Sutter <phil(a)nwl.cc> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <div64.h> +#include <spi.h> +#include <spi_flash.h> +#include <linux/mtd/mtd.h> + +#include <asm/io.h> +#include "../drivers/ddr/marvell/axp/ddr3_init.h" + +#define ETH_ALEN 6 +#define ETHADDR_MAX 4 +#define SYNO_SN_TAG "SN=" +#define SYNO_CHKSUM_TAG "CHK=" + + +static int do_syno_populate(int argc, char * const argv[]) +{ + unsigned int bus = CONFIG_SF_DEFAULT_BUS; + unsigned int cs = CONFIG_SF_DEFAULT_CS; + unsigned int speed = CONFIG_SF_DEFAULT_SPEED; + unsigned int mode = CONFIG_SF_DEFAULT_MODE; + struct spi_flash *flash; + unsigned long addr = 0x80000; /* XXX: parameterize this? */ + loff_t offset = 0x007d0000; + loff_t len = 0x00010000; + char *buf, *bufp; + char var[128]; + char val[128]; + int ret, n; + + /* XXX: arg parsing to select flash here? */ + + flash = spi_flash_probe(bus, cs, speed, mode); + if (!flash) { + printf("Failed to initialize SPI flash at %u:%u\n", bus, cs); + return 1; + } + + buf = map_physmem(addr, len, MAP_WRBACK); + if (!buf) { + puts("Failed to map physical memory\n"); + return 1; + } + + ret = spi_flash_read(flash, offset, len, buf); + if (ret) { + puts("Failed to read from SPI flash\n"); + goto out_unmap; + } + + for (n = 0; n < ETHADDR_MAX; n++) { + char ethaddr[ETH_ALEN]; + int i, sum = 0; + unsigned char csum = 0; + + for (i = 0, bufp = buf + n * 7; i < ETH_ALEN; i++) { + sum += bufp[i]; + csum += bufp[i]; + ethaddr[i] = bufp[i]; + } + if (!sum) /* MAC address empty */ + continue; + if (csum != bufp[i]) { /* seventh byte is checksum value */ + printf("Invalid MAC address for interface %d!\n", n); + continue; + } + if (n == 0) + sprintf(var, "ethaddr"); + else + sprintf(var, "eth%daddr", n); + snprintf(val, sizeof(val) - 1, + "%02x:%02x:%02x:%02x:%02x:%02x", + ethaddr[0], ethaddr[1], ethaddr[2], + ethaddr[3], ethaddr[4], ethaddr[5]); + printf("parsed %s = %s\n", var, val); + setenv(var, val); + } + if (!strncmp(buf + 32, SYNO_SN_TAG, strlen(SYNO_SN_TAG))) { + char *snp, *csump; + int csum = 0; + unsigned long c; + + snp = bufp = buf + 32 + strlen(SYNO_SN_TAG); + for (n = 0; bufp[n] && bufp[n] != ','; n++) + csum += bufp[n]; + bufp[n] = '\0'; + + /* should come right after, but you never know */ + bufp = strstr(bufp + n + 1, SYNO_CHKSUM_TAG); + if (!bufp) { + printf("Serial number checksum tag missing!\n"); + goto out_unmap; + } + + csump = bufp += strlen(SYNO_CHKSUM_TAG); + for (n = 0; bufp[n] && bufp[n] != ','; n++) + ; + bufp[n] = '\0'; + + if (strict_strtoul(csump, 10, &c) || c != csum) { + puts("Invalid serial number found!\n"); + ret = 1; + goto out_unmap; + } + printf("parsed SN = %s\n", snp); + setenv("SN", snp); + } else { /* old style format */ + unsigned char csum = 0; + + for (n = 0, bufp = buf + 32; n < 10; n++) + csum += bufp[n]; + + if (csum != bufp[n]) { + puts("Invalid serial number found!\n"); + ret = 1; + goto out_unmap; + } + bufp[n] = '\0'; + printf("parsed SN = %s\n", buf + 32); + setenv("SN", buf + 32); + } +out_unmap: + unmap_physmem(buf, len); + return ret; +} + +/* map bit position to function in POWER_MNG_CTRL_REG */ +static const char * const pwr_mng_bit_func[] = { + "audio", + "ge3", "ge2", "ge1", "ge0", + "pcie00", "pcie01", "pcie02", "pcie03", + "pcie10", "pcie11", "pcie12", "pcie13", + "bp", + "sata0_link", "sata0_core", + "lcd", + "sdio", + "usb0", "usb1", "usb2", + "idma", "xor0", "crypto", + NULL, + "tdm", + "pcie20", "pcie30", + "xor1", + "sata1_link", "sata1_core", + NULL, +}; + +static int do_syno_clk_gate(int argc, char * const argv[]) +{ + u32 pwr_mng_ctrl_reg = reg_read(POWER_MNG_CTRL_REG); + const char *func, *state; + int i, val; + + if (argc < 2) + return -1; + + if (!strcmp(argv[1], "get")) { + puts("Clock Gating:\n"); + for (i = 0; i < 32; i++) { + func = pwr_mng_bit_func[i]; + if (!func) + continue; + state = pwr_mng_ctrl_reg & (1 << i) ? "ON" : "OFF"; + printf("%s:\t\t%s\n", func, state); + } + return 0; + } + if (argc < 4) + return -1; + if (!strcmp(argv[1], "set")) { + func = argv[2]; + state = argv[3]; + for (i = 0; i < 32; i++) { + if (!pwr_mng_bit_func[i]) + continue; + if (!strcmp(func, pwr_mng_bit_func[i])) + break; + } + if (i == 32) { + printf("Error: name '%s' not known\n", func); + return -1; + } + val = state[0] != '0'; + pwr_mng_ctrl_reg |= (val << i); + pwr_mng_ctrl_reg &= ~(!val << i); + reg_write(POWER_MNG_CTRL_REG, pwr_mng_ctrl_reg); + } + return 0; +} + +static int do_syno(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + const char *cmd; + int ret; + + if (argc < 2) + goto usage; + + cmd = argv[1]; + --argc; + ++argv; + + if (!strcmp(cmd, "populate_env")) + ret = do_syno_populate(argc, argv); + else if (!strcmp(cmd, "clk_gate")) + ret = do_syno_clk_gate(argc, argv); + + if (ret != -1) + return ret; +usage: + return CMD_RET_USAGE; +} + +U_BOOT_CMD( + syno, 5, 1, do_syno, + "Synology specific commands", + "populate_env - Read vendor data from SPI flash into environment\n" + "clk_gate (get|set name 1|0) - Manage clock gating\n" +); -- 2.5.3

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[U-Boot] [PATCH v3 08/10] mvebu: Add rudimental MV78230 support
by Phil Sutter 13 Jan '16

13 Jan '16

This adds basic support for Marvell's MV78230 SoC which belongs to the Armada XP series. Signed-off-by: Phil Sutter <phil(a)nwl.cc> --- arch/arm/mach-mvebu/cpu.c | 16 +++++++++++----- arch/arm/mach-mvebu/include/mach/soc.h | 1 + arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c | 6 +++++- 3 files changed, 17 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 6ea558c..5c62fd5 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -49,13 +49,16 @@ int mvebu_soc_family(void) { u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; - if ((devid == SOC_MV78260_ID) || (devid == SOC_MV78460_ID)) + switch (devid) { + case SOC_MV78230_ID: + case SOC_MV78260_ID: + case SOC_MV78460_ID: return MVEBU_SOC_AXP; - - if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID || - devid == SOC_88F6828_ID) + case SOC_88F6810_ID: + case SOC_88F6820_ID: + case SOC_88F6828_ID: return MVEBU_SOC_A38X; - + } return MVEBU_SOC_UNKNOWN; } @@ -153,6 +156,9 @@ int print_cpuinfo(void) puts("SoC: "); switch (devid) { + case SOC_MV78230_ID: + puts("MV78230-"); + break; case SOC_MV78260_ID: puts("MV78260-"); break; diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 9eaf0db..6b12a92 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -11,6 +11,7 @@ #ifndef _MVEBU_SOC_H #define _MVEBU_SOC_H +#define SOC_MV78230_ID 0x7823 #define SOC_MV78260_ID 0x7826 #define SOC_MV78460_ID 0x7846 #define SOC_88F6810_ID 0x6810 diff --git a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c index 633b899..afc0cef 100644 --- a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c +++ b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c @@ -199,7 +199,9 @@ u16 ctrl_model_get(void) * SoC version can't be autodetected. So we need to rely on a define * from the config system here. */ -#ifdef CONFIG_MV78260 +#if defined(CONFIG_MV78230) + return MV_78230_DEV_ID; +#elif defined(CONFIG_MV78260) return MV_78260_DEV_ID; #else return MV_78460_DEV_ID; @@ -217,6 +219,8 @@ u32 get_line_cfg(u32 line_num, MV_BIN_SERDES_CFG *info) static int serdes_max_lines_get(void) { switch (ctrl_model_get()) { + case MV_78230_DEV_ID: + return 7; case MV_78260_DEV_ID: return 12; case MV_78460_DEV_ID: -- 2.5.3

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[U-Boot] [PATCH v3 07/10] mvebu: axp: Rename MV_DDR_32BIT to CONFIG_DDR_32BIT
by Phil Sutter 13 Jan '16

13 Jan '16

This should make it clear that this symbol is meant to be defined by board headers. Signed-off-by: Phil Sutter <phil(a)nwl.cc> --- drivers/ddr/marvell/axp/ddr3_axp_config.h | 2 +- drivers/ddr/marvell/axp/ddr3_axp_mc_static.h | 20 ++++++++++---------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/ddr/marvell/axp/ddr3_axp_config.h b/drivers/ddr/marvell/axp/ddr3_axp_config.h index 25c34fb..8549fe8 100644 --- a/drivers/ddr/marvell/axp/ddr3_axp_config.h +++ b/drivers/ddr/marvell/axp/ddr3_axp_config.h @@ -51,7 +51,7 @@ #define DRAM_ECC 0 #endif -#ifdef MV_DDR_32BIT +#ifdef CONFIG_DDR_32BIT #define BUS_WIDTH 32 #else #define BUS_WIDTH 64 diff --git a/drivers/ddr/marvell/axp/ddr3_axp_mc_static.h b/drivers/ddr/marvell/axp/ddr3_axp_mc_static.h index 2c0e9075..71794ad 100644 --- a/drivers/ddr/marvell/axp/ddr3_axp_mc_static.h +++ b/drivers/ddr/marvell/axp/ddr3_axp_mc_static.h @@ -8,9 +8,9 @@ #define __AXP_MC_STATIC_H MV_DRAM_MC_INIT ddr3_A0_db_667[MV_MAX_DDR3_STATIC_SIZE] = { -#ifdef MV_DDR_32BIT +#ifdef CONFIG_DDR_32BIT {0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */ -#else /*MV_DDR_64BIT */ +#else /*CONFIG_DDR_64BIT */ {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */ #endif {0x00001404, 0x3630b800}, /*Dunit Control Low Register */ @@ -66,9 +66,9 @@ MV_DRAM_MC_INIT ddr3_A0_db_667[MV_MAX_DDR3_STATIC_SIZE] = { }; MV_DRAM_MC_INIT ddr3_A0_AMC_667[MV_MAX_DDR3_STATIC_SIZE] = { -#ifdef MV_DDR_32BIT +#ifdef CONFIG_DDR_32BIT {0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */ -#else /*MV_DDR_64BIT */ +#else /*CONFIG_DDR_64BIT */ {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */ #endif {0x00001404, 0x3630b800}, /*Dunit Control Low Register */ @@ -124,9 +124,9 @@ MV_DRAM_MC_INIT ddr3_A0_AMC_667[MV_MAX_DDR3_STATIC_SIZE] = { }; MV_DRAM_MC_INIT ddr3_A0_db_400[MV_MAX_DDR3_STATIC_SIZE] = { -#ifdef MV_DDR_32BIT +#ifdef CONFIG_DDR_32BIT {0x00001400, 0x73004C30}, /*DDR SDRAM Configuration Register */ -#else /* MV_DDR_64BIT */ +#else /* CONFIG_DDR_64BIT */ {0x00001400, 0x7300CC30}, /*DDR SDRAM Configuration Register */ #endif {0x00001404, 0x3630B840}, /*Dunit Control Low Register */ @@ -176,9 +176,9 @@ MV_DRAM_MC_INIT ddr3_A0_db_400[MV_MAX_DDR3_STATIC_SIZE] = { }; MV_DRAM_MC_INIT ddr3_Z1_db_600[MV_MAX_DDR3_STATIC_SIZE] = { -#ifdef MV_DDR_32BIT +#ifdef CONFIG_DDR_32BIT {0x00001400, 0x73014A28}, /*DDR SDRAM Configuration Register */ -#else /*MV_DDR_64BIT */ +#else /*CONFIG_DDR_64BIT */ {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */ #endif {0x00001404, 0x3630B040}, /*Dunit Control Low Register */ @@ -233,9 +233,9 @@ MV_DRAM_MC_INIT ddr3_Z1_db_600[MV_MAX_DDR3_STATIC_SIZE] = { }; MV_DRAM_MC_INIT ddr3_Z1_db_300[MV_MAX_DDR3_STATIC_SIZE] = { -#ifdef MV_DDR_32BIT +#ifdef CONFIG_DDR_32BIT {0x00001400, 0x73004C30}, /*DDR SDRAM Configuration Register */ -#else /*MV_DDR_64BIT */ +#else /*CONFIG_DDR_64BIT */ {0x00001400, 0x7300CC30}, /*DDR SDRAM Configuration Register */ /*{0x00001400, 0x7304CC30}, *//*DDR SDRAM Configuration Register */ #endif -- 2.5.3

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[U-Boot] [PATCH v3 06/10] mvebu: Introduce kconfig symbols for SoC variants
by Phil Sutter 13 Jan '16

13 Jan '16

This patch adds intermediate kconfig symbols which select their SoC family. Boards then select them instead of the family symbol directly. Signed-off-by: Phil Sutter <phil(a)nwl.cc> --- arch/arm/mach-mvebu/Kconfig | 24 ++++++++++++++++++++---- include/configs/clearfog.h | 1 - include/configs/db-88f6820-gp.h | 1 - 3 files changed, 20 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index d96b2ae..a39f900 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -6,25 +6,41 @@ config ARMADA_38X config ARMADA_XP bool +config MV78230 + bool + select ARMADA_XP + +config MV78260 + bool + select ARMADA_XP + +config MV78460 + bool + select ARMADA_XP + +config DB_88F6820_GP + bool + select ARMADA_38X + choice prompt "Marvell MVEBU (Armada XP/38x) board select" optional config TARGET_CLEARFOG bool "Support ClearFog" - select ARMADA_38X + select DB_88F6820_GP config TARGET_DB_88F6820_GP bool "Support DB-88F6820-GP" - select ARMADA_38X + select DB_88F6820_GP config TARGET_DB_MV784MP_GP bool "Support db-mv784mp-gp" - select ARMADA_XP + select MV78460 config TARGET_MAXBCM bool "Support maxbcm" - select ARMADA_XP + select MV78460 endchoice diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h index 6c5356b..f0de827 100644 --- a/include/configs/clearfog.h +++ b/include/configs/clearfog.h @@ -10,7 +10,6 @@ /* * High Level Configuration Options (easy to change) */ -#define CONFIG_DB_88F6820_GP /* Board target name for DDR training */ #define CONFIG_DISPLAY_BOARDINFO_LATE diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index 03a3d31..ef14132 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -10,7 +10,6 @@ /* * High Level Configuration Options (easy to change) */ -#define CONFIG_DB_88F6820_GP /* Board target name for DDR training */ #define CONFIG_DISPLAY_BOARDINFO_LATE -- 2.5.3

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[U-Boot] [PATCH v3 05/10] mvebu: axp: refactor board_sat_r_get() and caller
by Phil Sutter 13 Jan '16

13 Jan '16

Instead of calling board_sat_r_get() only for those boards providing the satr11 value via I2C, call it for all boards and return static values for those not using I2C. In addition to that, make this a weak function to allow for board code to override it. Signed-off-by: Phil Sutter <phil(a)nwl.cc> --- .../arm/mach-mvebu/serdes/axp/high_speed_env_lib.c | 46 +++++++--------------- 1 file changed, 15 insertions(+), 31 deletions(-) diff --git a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c index bfa7f13..633b899 100644 --- a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c +++ b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c @@ -75,16 +75,24 @@ static u32 board_id_get(void) #endif } -static u8 board_sat_r_get(u8 dev_num, u8 reg) +__weak u8 board_sat_r_get(u8 dev_num, u8 reg) { u8 data; u8 *dev; u32 board_id = board_id_get(); int ret; - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - switch (board_id) { + case DB_78X60_AMC_ID: + case DB_78X60_PCAC_REV2_ID: + case RD_78460_CUSTOMER_ID: + case RD_78460_SERVER_ID: + case RD_78460_SERVER_REV2_ID: + case DB_78X60_PCAC_ID: + return (0x1 << 1) | 1; + case FPGA_88F78XX0_ID: + case RD_78460_NAS_ID: + return (0x0 << 1) | 1; case DB_784MP_GP_ID: dev = rd78460gp_twsi_dev; @@ -94,15 +102,12 @@ static u8 board_sat_r_get(u8 dev_num, u8 reg) dev = db88f78xx0rev2_twsi_dev; break; - case DB_78X60_PCAC_ID: - case FPGA_88F78XX0_ID: - case DB_78X60_PCAC_REV2_ID: - case RD_78460_SERVER_REV2_ID: default: return 0; } /* Read MPP module ID */ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); ret = i2c_read(dev[dev_num], 0, 1, (u8 *)&data, 1); if (ret) return MV_ERROR; @@ -240,7 +245,6 @@ int serdes_phy_config(void) u8 device_rev; u32 rx_high_imp_mode; u16 ctrl_mode; - u32 board_id = board_id_get(); u32 pex_if; u32 pex_if_num; @@ -251,29 +255,9 @@ int serdes_phy_config(void) if (max_serdes_lines == 0) return MV_OK; - switch (board_id) { - case DB_78X60_AMC_ID: - case DB_78X60_PCAC_REV2_ID: - case RD_78460_CUSTOMER_ID: - case RD_78460_SERVER_ID: - case RD_78460_SERVER_REV2_ID: - case DB_78X60_PCAC_ID: - satr11 = (0x1 << 1) | 1; - break; - case FPGA_88F78XX0_ID: - case RD_78460_NAS_ID: - satr11 = (0x0 << 1) | 1; - break; - case DB_88F78XX0_BP_REV2_ID: - case DB_784MP_GP_ID: - case DB_88F78XX0_BP_ID: - satr11 = board_sat_r_get(1, 1); - if ((u8) MV_ERROR == (u8) satr11) - return MV_ERROR; - break; - default: - satr11 = 0; - } + satr11 = board_sat_r_get(1, 1); + if ((u8) MV_ERROR == (u8) satr11) + return MV_ERROR; board_modules_scan(); memset(addr, 0, sizeof(addr)); -- 2.5.3

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[U-Boot] [PATCH v3 04/10] drivers/pci/pci_mvebu: Fix for boards with X4 lanes
by Phil Sutter 13 Jan '16

13 Jan '16

Armada XP has support for X4 lanes, boards specify this in their serdes_cfg. During PEX init in high_speed_env_lib.c, the configuration is stored in GEN_PURP_RES_2_REG. When enumerating PEX, subsequent interfaces of an X4 lane must be skipped. Otherwise the enumeration hangs up the board. The way this is implemented here is not exactly beautiful, but it mimics how Marvell's BSP does it. Alternatively we could get the information using board_serdes_cfg_get(), but that won't lead to clean code, either. Signed-off-by: Phil Sutter <phil(a)nwl.cc> --- arch/arm/mach-mvebu/include/mach/soc.h | 2 ++ drivers/pci/pci_mvebu.c | 14 ++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 5d4ad30..9eaf0db 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -96,4 +96,6 @@ #define MVCPU_WIN_ENABLE CPU_WIN_ENABLE #define MVCPU_WIN_DISABLE CPU_WIN_DISABLE +#define COMPHY_REFCLK_ALIGNMENT (MVEBU_REGISTER(0x182f8)) + #endif /* _MVEBU_SOC_H */ diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index fd2744d..4eedfe1 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -155,6 +155,14 @@ static void mvebu_get_port_lane(struct mvebu_pcie *pcie, int pex_idx, } #endif +static int mvebu_pex_unit_is_x4(int pex_idx) +{ + int pex_unit = pex_idx < 9 ? pex_idx >> 2 : 3; + u32 mask = (0x0f << (pex_unit * 8)); + + return (readl(COMPHY_REFCLK_ALIGNMENT) & mask) == mask; +} + static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie) { u32 val; @@ -419,5 +427,11 @@ void pci_init_board(void) writel(0, pcie->base + PCIE_BAR_HI_OFF(0)); bus = hose->last_busno + 1; + + /* need to skip more for X4 links, otherwise scan will hang */ + if (mvebu_soc_family() == MVEBU_SOC_AXP) { + if (mvebu_pex_unit_is_x4(i)) + i += 3; + } } } -- 2.5.3

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[U-Boot] [PATCH v3 03/10] axp: Fix debugging support in DDR3 write leveling
by Phil Sutter 13 Jan '16

13 Jan '16

If MV_DEBUG_WL is defined, DEBUG_WL_S and DEBUG_WL_D macros are missing. In addition to that, get rid of debug output printing non-existent counter variable. Signed-off-by: Phil Sutter <phil(a)nwl.cc> --- drivers/ddr/marvell/axp/ddr3_write_leveling.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/ddr/marvell/axp/ddr3_write_leveling.c b/drivers/ddr/marvell/axp/ddr3_write_leveling.c index df3a3df..da384f3 100644 --- a/drivers/ddr/marvell/axp/ddr3_write_leveling.c +++ b/drivers/ddr/marvell/axp/ddr3_write_leveling.c @@ -22,6 +22,8 @@ DEBUG_WL_FULL_S(s); DEBUG_WL_FULL_D(d, l); DEBUG_WL_FULL_S("\n") #ifdef MV_DEBUG_WL +#define DEBUG_WL_S(s) puts(s) +#define DEBUG_WL_D(d, l) printf("%x", d) #define DEBUG_RL_S(s) \ debug_cond(ddr3_get_log_level() >= MV_LOG_LEVEL_2, "%s", s) #define DEBUG_RL_D(d, l) \ @@ -1229,8 +1231,6 @@ static int ddr3_write_leveling_single_cs(u32 cs, u32 freq, int ratio_2to1, DEBUG_WL_FULL_D((u32) phase, 1); DEBUG_WL_FULL_S(", Delay = "); DEBUG_WL_FULL_D((u32) delay, 1); - DEBUG_WL_FULL_S(", Counter = "); - DEBUG_WL_FULL_D((u32) i, 1); DEBUG_WL_FULL_S("\n"); /* Drive DQS high for one cycle - All data PUPs */ -- 2.5.3

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[U-Boot] [PATCH v3 02/10] README: Review the u-boot porting guide list
by Phil Sutter 13 Jan '16

13 Jan '16

* There is no boards.cfg anymore, so drop (1). * Creating flash.c and u-boot.lds seems not mandatory as well. * Adjusting the enumerators for the above implicitly fixed for double items numbered (3). Signed-off-by: Phil Sutter <phil(a)nwl.cc> --- README | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/README b/README index 4fee706..dcc9478 100644 --- a/README +++ b/README @@ -5153,14 +5153,11 @@ If the system board that you have is not listed, then you will need to port U-Boot to your hardware platform. To do this, follow these steps: -1. Add a new configuration option for your board to the toplevel - "boards.cfg" file, using the existing entries as examples. - Follow the instructions there to keep the boards in order. -2. Create a new directory to hold your board specific code. Add any +1. Create a new directory to hold your board specific code. Add any files you need. In your board directory, you will need at least - the "Makefile", a "<board>.c", "flash.c" and "u-boot.lds". -3. Create a new configuration file "include/configs/<board>.h" for - your board + the "Makefile" and a "<board>.c". +2. Create a new configuration file "include/configs/<board>.h" for + your board. 3. If you're porting U-Boot to a new CPU, then also create a new directory to hold your CPU specific code. Add any files you need. 4. Run "make <board>_defconfig" with your new name. -- 2.5.3

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[U-Boot] [PATCH v3 01/10] drivers/pci: Fix for debug builds without CONFIG_PCI_ENUM_ONLY
by Phil Sutter 13 Jan '16

13 Jan '16

The debug printing references bar_res, which exists only if CONFIG_PCI_ENUM_ONLY is not defined. Therefore move it into the ifdef'd area. Signed-off-by: Phil Sutter <phil(a)nwl.cc> --- drivers/pci/pci_auto_old.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/pci_auto_old.c b/drivers/pci/pci_auto_old.c index 932eab8..8f17779 100644 --- a/drivers/pci/pci_auto_old.c +++ b/drivers/pci/pci_auto_old.c @@ -98,11 +98,11 @@ void pciauto_setup_device(struct pci_controller *hose, bar_res = prefetch; else bar_res = mem; -#endif debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ", bar_nr, bar_res == prefetch ? "Prf" : "Mem", (unsigned long long)bar_size); +#endif } #ifndef CONFIG_PCI_ENUM_ONLY -- 2.5.3

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[U-Boot] U-Boot Rockchip dwc_hcd question for low-speed devices
by Josh Sanford 13 Jan '16

13 Jan '16

All, I am trying to use USB within U-Boot on a Firefly RK3288 (Rockchip) board, and I am able to enumerate high-speed devices, but not full-speed or low-speed devices. I know that the devices are functional, because they work on the same physical hardware when I boot into Linux. Note that I'm using "U-Boot 2014.10-RK3288-02". As an aside, the built-in "USB 2.0 Hub [MTT]" hub never generates a USB_PORT_STAT_C_CONNECTION for me, even though USB_PORT_STAT_CONNECTION goes high immediately after powering on, so I forcibly assert USB_PORT_STAT_C_CONNECTION to allow the rest of the tree to enumerate. High-speed devices can be nested as deeply as I wish and still show up properly, but I can't get low-speed devices (i.e. a keyboard) to work in any hub port, including any of the ports directly on the board. All attempts to read from my low-speed devices return all zeros. When I dig a little deeper, I find myself in int dwc_wait_for_complete(struct usb_device *dev, uint32_t channel_num, uint32_t *hcStat, uint32_t *errCnt) {}. On the second iteration through the goto loop, hcintn.b.chhltd and hcintn.b.xacterr are both asserted, but hcintn.b.ack, hcintn.b.nak, and hcintn.b.nyet are not, and errCnt is only 1, so the code sets *hcStat = HCSTAT_REINIT and returns. I do notice that dwc_hcd.c seems not to have any code to support split transactions (or perhaps I simply haven't seen it yet). If true, I wonder whether this code is actually expected to support full-speed and low-speed devices. Do you have any thoughts on the matter? I wish I were more of a USB expert, but I'm regrettably quite a novice. Regards, Josh

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