November 2015 - U-Boot

[U-Boot] [PATCH] Re-enable setexpr on Raspberry Pi
by Marco Schuster 14 Jan '16

14 Jan '16

This patch re-enables the setexpr command, I don't really understand why it got excluded in the first place. setexpr can be used e.g. to implement failed-boot-counters and failovers to rescue firmware. Signed-off-by: Marco Schuster <m.schuster91(a)googlemail.com> --- configs/rpi_2_defconfig | 1 - configs/rpi_defconfig | 1 - 2 files changed, 2 deletions(-) diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig index 5c9e69a..bd81ee6 100644 --- a/configs/rpi_2_defconfig +++ b/configs/rpi_2_defconfig @@ -6,5 +6,4 @@ CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_CMD_GPIO=y -# CONFIG_CMD_SETEXPR is not set CONFIG_PHYS_TO_BUS=y diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig index b8b267f..5d27909 100644 --- a/configs/rpi_defconfig +++ b/configs/rpi_defconfig @@ -6,5 +6,4 @@ CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_CMD_GPIO=y -# CONFIG_CMD_SETEXPR is not set CONFIG_PHYS_TO_BUS=y -- 2.6.2

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[U-Boot] [PATCH 0/4 v4] arm: socfpga: Add Cadence QSPI support
by Stefan Roese 14 Jan '16

14 Jan '16

Hi! So this is my 4th posting regarding the Candence SPI driver on SoCFPGA. Again, SPI NOR flash is working. At least on SoCrates and on another custom SoCFPGA based board. The main change in this version is, that the Cadence driver now is a driver model (DM) based driver. And this needs the DT support which I posted just before. One of the reasons to enable DT support in SoCFPGA is, that I need to support multiple different SPI controllers for this platform. This is the QSPI Cadence controller and the Designware SPI master controller. Both are implemented in the SoCFPGA. And enabling both controllers is only possible by using the new driver model (DM). The DM SPI code only supports DT based probing. So it was easier to move SoCFPGA to DT than to add the (deprecated) platform-data based probing to the DM SPI suport. Note that I have patches to support the Designware SPI master controller also via DM in the queue. I'll post them shortly. Thanks, Stefan Cc: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)altera.com> Cc: Vince Bridgers <vbridger(a)altera.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Pavel Machek <pavel(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki(a)gmail.com>

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[U-Boot] 2TB disks
by Stefan Monnier 13 Jan '16

13 Jan '16

I just bumped into a problem where U-Boot refused to boot from my disk's second partition because the sector number is "negative". More specifically, my disk drive is 2TB, which means that the number of 512B blocks fits into an unsigned 32bit int but not into a signed 32bit int. U-boot's "scsi part" displays the size (in blocks) correctly, but the size of the first partition (which is around 1.8TB) is printed as a negative number, and so is the start sector of the second partition. This was tested on a BananaPi using v2015-07. Stefan

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[U-Boot] Fix wrap around bug in MBR sector counts
by Stefan Monnier 12 Jan '16

12 Jan '16

I just bumped into a problem where U-Boot refused to boot from my disk's second partition because the sector number is "negative". More specifically, my disk drive is 2TB, which means that the number of 512B blocks fits into an unsigned 32bit int but not into a signed 32bit int. U-boot's "scsi part" displays the size (in blocks) correctly, but the size of the first partition (which is around 1.8TB) is printed as a negative number, and so is the start sector of the second partition. This was tested on a BananaPi using v2015-07.

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[U-Boot] [PATCH] fdt: fix address cell count checking in fdt_translate_address()
by Przemyslaw Marczak 12 Jan '16

12 Jan '16

Commit: dm: core: Enable optional use of fdt_translate_address() Enables use of this function as default, but after this it's not possible to get dev address for the case in which: '#size-cells == 0' This causes errors when getting address for some GPIOs, for which the '#size-cells' is set to 0. Example error: '__of_translate_address: Bad cell count for gpx0' Allowing for that case by modifying the macro 'OF_CHECK_COUNTS', (called from )__of_translate_address(), fixes the issue. Now, this macro doesn't check, that '#size-cells' is greater than 0. This is possible from the specification point of view, but I'm not sure that it doesn't introduce a regression for other configs. Please test and share the results. Tested-on: Odroid U3, Odroid X2, Odroid XU3, Sandbox. Signed-off-by: Przemyslaw Marczak <p.marczak(a)samsung.com> Cc: Masahiro Yamada <yamada.masahiro(a)socionext.com> Cc: Lukasz Majewski <l.majewski(a)samsung.com> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> Cc: Stefan Roese <sr(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> Cc: Bin Meng <bmeng.cn(a)gmail.com> Cc: Marek Vasut <marex(a)denx.de> --- common/fdt_support.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/common/fdt_support.c b/common/fdt_support.c index f86365e..5f808cc 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -946,8 +946,7 @@ void fdt_del_node_and_alias(void *blob, const char *alias) /* Max address size we deal with */ #define OF_MAX_ADDR_CELLS 4 #define OF_BAD_ADDR ((u64)-1) -#define OF_CHECK_COUNTS(na, ns) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS && \ - (ns) > 0) +#define OF_CHECK_COUNTS(na) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS) /* Debug utility */ #ifdef DEBUG @@ -1115,7 +1114,7 @@ static u64 __of_translate_address(void *blob, int node_offset, const fdt32_t *in /* Cound address cells & copy address locally */ bus->count_cells(blob, parent, &na, &ns); - if (!OF_CHECK_COUNTS(na, ns)) { + if (!OF_CHECK_COUNTS(na)) { printf("%s: Bad cell count for %s\n", __FUNCTION__, fdt_get_name(blob, node_offset, NULL)); goto bail; @@ -1142,7 +1141,7 @@ static u64 __of_translate_address(void *blob, int node_offset, const fdt32_t *in /* Get new parent bus and counts */ pbus = &of_busses[0]; pbus->count_cells(blob, parent, &pna, &pns); - if (!OF_CHECK_COUNTS(pna, pns)) { + if (!OF_CHECK_COUNTS(pna)) { printf("%s: Bad cell count for %s\n", __FUNCTION__, fdt_get_name(blob, node_offset, NULL)); break; -- 1.9.1

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[U-Boot] [PATCH 1/3] usb: host: ehci-vf: Remove hardcoded USB host client configuration
by Sanchayan Maity 08 Jan '16

08 Jan '16

The current ehci-vf USB driver for Vybrid hardcodes the USB host and client functionality. Remove this. Reported-by: Santhosh Kumar Janardhanam <santhosh.kj(a)hcl.com> Signed-off-by: Sanchayan Maity <maitysanchayan(a)gmail.com> --- drivers/usb/host/ehci-vf.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/usb/host/ehci-vf.c b/drivers/usb/host/ehci-vf.c index 98e0fc6..351e0fb 100644 --- a/drivers/usb/host/ehci-vf.c +++ b/drivers/usb/host/ehci-vf.c @@ -134,11 +134,6 @@ int ehci_hcd_init(int index, enum usb_init_type init, if (index >= ARRAY_SIZE(nc_reg_bases)) return -EINVAL; - if (init == USB_INIT_DEVICE && index == 1) - return -ENODEV; - if (init == USB_INIT_HOST && index == 0) - return -ENODEV; - ehci = (struct usb_ehci *)nc_reg_bases[index]; /* Do board specific initialisation */ -- 2.6.2

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[U-Boot] [PATCH] powerpc, mpc5xxx: fix missing bootflag init
by Heiko Schocher 08 Jan '16

08 Jan '16

since: commit: f05ad9ba "Add a way to skip relocation" tqm5200s board fails to boot. Reason is that board_init_f has a function parameter bootflag, which is not setup in in arch/powerpc/cpu/mpc5xxx/start.S _start So board_init_f gets a undefined bootflag, currently the gd pointer address. Unfortunately this address sets the GD_FLG_SKIP_RELOC bit, so u-boot code gets not relocated and u-boot does not boot ... Init bootflag with 0, and tqm5200 boots fine again. Signed-off-by: Heiko Schocher <hs(a)denx.de> --- I added a nightly build to: http://xeidos.ddns.net/buildbot/waterfall http://xeidos.ddns.net/buildbot/builders/tqm5200s_ml_ub What does this nightly build: - checkout current u-boot mainline code - compile u-boot for tqm5200s board - install u-boot image on the board with bdi - run the image, and look if u-boot boots ToDo: - add more tbot [1] tests for this board Currently failing, as this patch is not in mainline, but it should go to green, if this patch is applied, cross your fingers ;-) [1] https://github.com/hsdenx/tbot arch/powerpc/cpu/mpc5xxx/start.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/powerpc/cpu/mpc5xxx/start.S b/arch/powerpc/cpu/mpc5xxx/start.S index 94eb0d3..54793f0 100644 --- a/arch/powerpc/cpu/mpc5xxx/start.S +++ b/arch/powerpc/cpu/mpc5xxx/start.S @@ -91,6 +91,7 @@ _start: li r5,GD_SIZE /* parameter 3: count */ bl memset + li r3, 0 /* parameter 1: bootflag */ bl board_init_f /* run 1st part of board init code (in Flash)*/ /* NOTREACHED - board_init_f() does not return */ #else @@ -169,6 +170,7 @@ lowboot_reentry: /* r3: IMMR */ bl cpu_init_f /* run low-level CPU init code (in Flash)*/ + li r3, 0 /* parameter 1: bootflag */ bl board_init_f /* run 1st part of board init code (in Flash)*/ /* NOTREACHED - board_init_f() does not return */ -- 2.1.0

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[U-Boot] [PATCH 00/10] Add support for Rockchip RK3288 Ethernet
by Sjoerd Simons 08 Jan '16

08 Jan '16

This series adds support for the GMAC Ethernet interface on RK3288 SoCs. To add support I've taken a slightly different approach then some of the other boards with a designware IP block, by creating a new driver to take care of the platfrom glue which subclasses the main designware driver instead of adding the compatibility string the designware driver directly and doing the SoC specific setup in the board files. This seems quite a bit more elegant in a device model based world. As the pinctrl and clock drivers are quite simple at the moment (hardcoded settings rather then retrieved from device-tree) the pinctrl and clock settings added in this series assume the setup for the ethernet interface used is for Firefly and Radxa Rock 2. Specifically It assumes the gmac is driven by an external clock, GPIO4B0 is the phy reset and the phy interface mode is RGMII. I've only tested this series on a Radxa Rock 2 board, it would be great if someone could test this on other boards with the designware IP especially for those with the reset GPIO in devicetree (e.g. some of the Allwinner boards). Sjoerd Simons (10): rockchip: rk3288: Add pinctrl support for the gmac ethernet interface rockchip: rk3288: Add clock support for the gmac ethernet interface net: designware: support phy reset device-tree bindings net: designware: Export various functions/struct to allow subclassing net: designware: Add a post-started hook net: gmac_rk3288: Add RK3288 GMAC driver rockchip: rk3288-firefly: Add gmac definition rockchip: firefly: Enable networking support rockchip: Add PXE and DHCP to the default boot targets rockchip: Drop Ethernet from the TODO arch/arm/dts/rk3288-firefly.dtsi | 16 ++ arch/arm/include/asm/arch-rockchip/cru_rk3288.h | 17 ++ arch/arm/include/asm/arch-rockchip/grf_rk3288.h | 228 ++++++++++++++++++++++++ arch/arm/include/asm/arch-rockchip/periph.h | 1 + configs/firefly-rk3288_defconfig | 5 + doc/README.rockchip | 1 - drivers/clk/clk_rk3288.c | 16 ++ drivers/net/Kconfig | 7 + drivers/net/Makefile | 1 + drivers/net/designware.c | 91 ++++++++-- drivers/net/designware.h | 19 ++ drivers/net/gmac_rk3288.c | 140 +++++++++++++++ drivers/pinctrl/rockchip/pinctrl_rk3288.c | 102 +++++++++++ include/configs/firefly-rk3288.h | 3 + include/configs/rk3288_common.h | 4 +- 15 files changed, 639 insertions(+), 12 deletions(-) create mode 100644 drivers/net/gmac_rk3288.c -- 2.5.3

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[U-Boot] [PATCH] cmd_pci: Check for VendorID earlier
by Fabio Estevam 06 Jan '16

06 Jan '16

From: Fabio Estevam <fabio.estevam(a)freescale.com> Since commit ff3e077bd2 ("dm: pci: Add a uclass for PCI") the following error message is seen: => pci 0 Scanning PCI devices on bus 0 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 00.01.00 0x16c3 0xabcd Bridge device 0x04 Cannot read bus configuration: -1 => pci 1 Scanning PCI devices on bus 1 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 01.00.00 0x8086 0x08b1 Network controller 0x80 Cannot read bus configuration: -1 When we are done scanning the PCI devices pci_read_config_word() will return -1 and VendorID will contain 0xFFFF. The original code would exit the 'for' loop in this condition. Keep the same original behaviour by first testing the VendorID value and then checking and propagating the pci_read_config_word() error afterwards. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- common/cmd_pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/cmd_pci.c b/common/cmd_pci.c index dcecef8..92dc643 100644 --- a/common/cmd_pci.c +++ b/common/cmd_pci.c @@ -77,10 +77,10 @@ void pciinfo(int BusNum, int ShortPCIListing) ret = pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID); - if (ret) - goto error; if ((VendorID == 0xFFFF) || (VendorID == 0x0000)) continue; + if (ret) + goto error; if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType); -- 1.9.1

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[U-Boot] [PATCH 1/2] nios2: rename board nios2-generic to 3c120_devboard
by Thomas Chou 06 Jan '16

06 Jan '16

Rename board nios2-generic to 3c120_devboard. Since nios2 is converted to driver model and device tree control of u-boot, the nios2-generic board directory is removed. We can rename the board back to a real board name. Now the boards maintained in u-boot mainline are the same as Linux kernel, namely 3c120 and 10m50. Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- configs/3c120_defconfig | 27 ++++++++++ configs/nios2-generic_defconfig | 27 ---------- doc/README.nios2 | 8 +-- include/configs/3c120_devboard.h | 107 +++++++++++++++++++++++++++++++++++++++ include/configs/nios2-generic.h | 107 --------------------------------------- 5 files changed, 138 insertions(+), 138 deletions(-) create mode 100644 configs/3c120_defconfig delete mode 100644 configs/nios2-generic_defconfig create mode 100644 include/configs/3c120_devboard.h delete mode 100644 include/configs/nios2-generic.h diff --git a/configs/3c120_defconfig b/configs/3c120_defconfig new file mode 100644 index 0000000..736119e --- /dev/null +++ b/configs/3c120_defconfig @@ -0,0 +1,27 @@ +CONFIG_NIOS2=y +CONFIG_SYS_CONFIG_NAME="3c120_devboard" +CONFIG_DM_SERIAL=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="3c120_devboard" +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_ITEST is not set +CONFIG_CMD_DHCP=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_ALTERA_PIO=y +CONFIG_MISC=y +CONFIG_ALTERA_SYSID=y +CONFIG_MTD=y +CONFIG_CFI_FLASH=y +CONFIG_DM_ETH=y +CONFIG_ALTERA_TSE=y +CONFIG_ALTERA_JTAG_UART=y +CONFIG_ALTERA_JTAG_UART_BYPASS=y +CONFIG_TIMER=y +CONFIG_ALTERA_TIMER=y diff --git a/configs/nios2-generic_defconfig b/configs/nios2-generic_defconfig deleted file mode 100644 index 0a6de6f..0000000 --- a/configs/nios2-generic_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -CONFIG_NIOS2=y -CONFIG_SYS_CONFIG_NAME="nios2-generic" -CONFIG_DM_SERIAL=y -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="3c120_devboard" -CONFIG_HUSH_PARSER=y -CONFIG_CMD_CPU=y -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_ITEST is not set -CONFIG_CMD_DHCP=y -# CONFIG_CMD_NFS is not set -CONFIG_CMD_PING=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_ALTERA_PIO=y -CONFIG_MISC=y -CONFIG_ALTERA_SYSID=y -CONFIG_MTD=y -CONFIG_CFI_FLASH=y -CONFIG_DM_ETH=y -CONFIG_ALTERA_TSE=y -CONFIG_ALTERA_JTAG_UART=y -CONFIG_ALTERA_JTAG_UART_BYPASS=y -CONFIG_TIMER=y -CONFIG_ALTERA_TIMER=y diff --git a/doc/README.nios2 b/doc/README.nios2 index 2dab7d1..a33c4e8 100644 --- a/doc/README.nios2 +++ b/doc/README.nios2 @@ -45,9 +45,9 @@ the sequence of these devices, like this, }; Next, you will need a default config file. You may start with -nios2-generic_defconfig, modify the options and save it. +3c120_defconfig, modify the options and save it. -$ make nios2-generic_defconfig +$ make 3c120_defconfig $ make menuconfig $ make savedefconfig $ cp defconfig configs/mysystem_defconfig @@ -72,9 +72,9 @@ copies all the u-boot-dtb.bin, not just u-boot.bin. binary. This is handy for development, eg, using gdb or nios2-download. The last thing, legacy board header file describes those config options -not covered in Kconfig yet. You may copy it from nios2-generic.h. +not covered in Kconfig yet. You may copy it from 3c120_devboard.h. -$ cp include/configs/nios2-generic.h include/configs/mysystem.h +$ cp include/configs/3c120_devboard.h include/configs/mysystem.h Please change the SDRAM base and size to match your board. The base should be cached virtual address, for Nios II with MMU it is 0xCxxx_xxxx diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h new file mode 100644 index 0000000..856c836 --- /dev/null +++ b/include/configs/3c120_devboard.h @@ -0,0 +1,107 @@ +/* + * (C) Copyright 2005, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt(a)psyent.com> + * (C) Copyright 2010, Thomas Chou <thomas(a)wytron.com.tw> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * BOARD/CPU + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO_LATE + +/* + * SERIAL + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_CONSOLE_INFO_QUIET /* Suppress console info */ + +/* + * CFI Flash + */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 +#define CONFIG_SYS_MAX_FLASH_SECT 512 + +/* + * NET options + */ +#define CONFIG_SYS_RX_ETH_BUFFER 0 +#define CONFIG_CMD_MII +#define CONFIG_PHY_GIGE +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#define CONFIG_PHY_MARVELL + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * FDT options + */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_LMB + +/* + * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above + * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the + * reset address, no? This will keep the environment in user region + * of flash. NOTE: the monitor length must be multiple of sector size + * (which is common practice). + */ +#define CONFIG_ENV_IS_IN_FLASH + +#define CONFIG_ENV_SIZE 0x20000 /* 128k, 1 sector */ +#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ +#define CONFIG_ENV_ADDR 0xe2840000 + +/* + * MEMORY ORGANIZATION + * -Monitor at top of sdram. + * -The heap is placed below the monitor + * -The stack is placed below the heap (&grows down). + */ +#define CONFIG_SYS_SDRAM_BASE 0xD0000000 +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256k */ +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_SDRAM_SIZE - \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_MALLOC_LEN 0x20000 + +/* + * MISC + */ +#define CONFIG_SYS_LONGHELP /* Provide extended help */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */ +#define CONFIG_SYS_MAXARGS 16 /* Max command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Bootarg buf size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + \ + 16) /* Print buf size */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MONITOR_BASE - \ + CONFIG_ENV_SIZE - \ + CONFIG_SYS_MALLOC_LEN - \ + 0x10000) +#define CONFIG_CMDLINE_EDITING +#define CONFIG_CMD_GPIO + +#endif /* __CONFIG_H */ diff --git a/include/configs/nios2-generic.h b/include/configs/nios2-generic.h deleted file mode 100644 index 856c836..0000000 --- a/include/configs/nios2-generic.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * (C) Copyright 2005, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt(a)psyent.com> - * (C) Copyright 2010, Thomas Chou <thomas(a)wytron.com.tw> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * BOARD/CPU - */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO_LATE - -/* - * SERIAL - */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_CONSOLE_INFO_QUIET /* Suppress console info */ - -/* - * CFI Flash - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -/* - * NET options - */ -#define CONFIG_SYS_RX_ETH_BUFFER 0 -#define CONFIG_CMD_MII -#define CONFIG_PHY_GIGE -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -#define CONFIG_PHY_MARVELL - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * FDT options - */ -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP -#define CONFIG_LMB - -/* - * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above - * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the - * reset address, no? This will keep the environment in user region - * of flash. NOTE: the monitor length must be multiple of sector size - * (which is common practice). - */ -#define CONFIG_ENV_IS_IN_FLASH - -#define CONFIG_ENV_SIZE 0x20000 /* 128k, 1 sector */ -#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ -#define CONFIG_ENV_ADDR 0xe2840000 - -/* - * MEMORY ORGANIZATION - * -Monitor at top of sdram. - * -The heap is placed below the monitor - * -The stack is placed below the heap (&grows down). - */ -#define CONFIG_SYS_SDRAM_BASE 0xD0000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256k */ -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_SDRAM_SIZE - \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_MALLOC_LEN 0x20000 - -/* - * MISC - */ -#define CONFIG_SYS_LONGHELP /* Provide extended help */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */ -#define CONFIG_SYS_MAXARGS 16 /* Max command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Bootarg buf size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + \ - 16) /* Print buf size */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MONITOR_BASE - \ - CONFIG_ENV_SIZE - \ - CONFIG_SYS_MALLOC_LEN - \ - 0x10000) -#define CONFIG_CMDLINE_EDITING -#define CONFIG_CMD_GPIO - -#endif /* __CONFIG_H */ -- 2.5.0

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