November 2015 - U-Boot

[U-Boot] Adding support for SPI-attached MR25H256 MRAM with Device Tree
by Simon Falsig 15 Feb '16

15 Feb '16

I have a custom board based on a TI AM3356 processor (quite similar to a BeagleBone) with an Everspin MR25H256 MRAM attached to the SPI bus, currently using U-Boot 2015.10 to boot a 3.18.9-rt5 Linux kernel. I'd like to use this MRAM to store the MAC address for one of the Ethernet interfaces, but I'm having a bit of trouble getting started on how support for this should be added. I can access the MRAM just fine from Linux (using the m25p80 driver and the MTD framework), so with the appropriate drivers compiled into the kernel, Linux picks the chip up without any issue by simply adding the following to the device tree: mram: m25p80@0 { #address-cells = <1>; #size-cells = <1>; compatible = "mr25h256"; reg = <0>; spi-max-frequency = <40000000>; status = "okay"; }; I'd like U-Boot to do something similar, but there are a few issues: 1. The chip is not JEDEC compatible, so it cannot be probed like the other chips currently listed in drivers/mtd/spi/sf_params.c 2. Since it's an MRAM, it doesn't need to be erased before being written - Linux has a flag for this, but it doesn't seem as if U-Boot has anything similar. (Not that I need this currently though, as I only need to be able to read the chip for now - but it'd be nice to have, and others might be able to use it too.) I've tried having a look at doc/driver-model/spi-howto.txt, hoping that this would have up-to-date information on how to implement/modify a SPI driver, but when I for instance look at spi_setup_slave_fdt(), which seems to be one of the necessary functions, I can only find it implemented in drivers/spi/spi-uclass.c, with a comment saying that it is only for compatibility, and that it is to be removed?... If anyone can help me with a few hints on how to get started adding support for this chip, it'd be much appreciated! Thanks in advance and best regards, Simon Falsig simon(a)newtec.dk

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[U-Boot] [PATCH] openrisc: updating build tools naming convention
by Guillaume REMBERT 13 Feb '16

13 Feb '16

Dear u-boot community, I just made a small change on the openrisc-generic platform configuration to take in account the new naming convention (or1k instead of or32, so the build process gets fine). Could you take care to review and approve the following patch, please? Kind regards, -- ____________________________________________ Guillaume REMBERT Phone/Fax: 0033 9 72 32 55 76 Mobile: 0033 6 83 27 98 19 E-Mail: guillaume.rembert(a)euryecetelecom.com ____________________________________________ On Earth and Space... EURYECE TELECOM ... where failure is not an option http://www.euryecetelecom.com __________________________________ 51d13f5355943e14db4b95a7f8ae4cd87eba1fe1 arch/openrisc/config.mk | 2 +- arch/openrisc/cpu/u-boot.lds | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/openrisc/config.mk b/arch/openrisc/config.mk index cd95f24..bfdb71f 100644 --- a/arch/openrisc/config.mk +++ b/arch/openrisc/config.mk @@ -6,7 +6,7 @@ # ifeq ($(CROSS_COMPILE),) -CROSS_COMPILE := or32-elf- +CROSS_COMPILE := or1k-elf- endif # r10 used for global object pointer, already set in OR32 GCC but just to be diff --git a/arch/openrisc/cpu/u-boot.lds b/arch/openrisc/cpu/u-boot.lds index d9bb7b7..854088b 100644 --- a/arch/openrisc/cpu/u-boot.lds +++ b/arch/openrisc/cpu/u-boot.lds @@ -1,5 +1,5 @@ #include <config.h> -OUTPUT_ARCH(or32) +OUTPUT_ARCH(or1k) __DYNAMIC = 0; MEMORY

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[U-Boot] [PATCH v3 1/2] zynqmp: nand: Add Nand driver support for zynqmp
by Siva Durga Prasad Paladugu 13 Feb '16

13 Feb '16

Add nand driver support for zynqmp. The Nand controller used in ZynqMP is Arasan Nand Flash controller. Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> --- Changes from v2: - Moved config NAND_ARASAN to driver/mtd/nand/Kconfig as per review comment Changes from v1: - Newly added in series --- arch/arm/include/asm/arch-zynqmp/hardware.h | 2 ++ configs/xilinx_zynqmp_ep_defconfig | 1 + drivers/mtd/nand/Kconfig | 7 +++++++ include/configs/xilinx_zynqmp.h | 9 +++++++++ 4 files changed, 19 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index 0f03c24..3c9f08c 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -25,6 +25,8 @@ #define ZYNQ_SDHCI_BASEADDR0 0xFF160000 #define ZYNQ_SDHCI_BASEADDR1 0xFF170000 +#define ARASAN_NAND_BASEADDR 0xFF100000 + #define ZYNQMP_SATA_BASEADDR 0xFD0C0000 #define ZYNQMP_USB0_XHCI_BASEADDR 0xFE200000 diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig index 79304c1..43a24a7 100644 --- a/configs/xilinx_zynqmp_ep_defconfig +++ b/configs/xilinx_zynqmp_ep_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQMP=y CONFIG_ZYNQMP_USB=y +CONFIG_NAND_ARASAN=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108" CONFIG_SYS_PROMPT="ZynqMP> " diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 9a74064..6e35213 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -71,6 +71,13 @@ config NAND_SUNXI Enable support for NAND. This option allows SPL to read from sunxi NAND using DMA transfers. +config NAND_ARASAN + bool "Configure Arasan Nand" + help + This enables Nand driver support for Arasan nand flash + controller. This uses the hardware ECC for read and + write operations. + comment "Generic NAND options" # Enhance depends when converting drivers to Kconfig which use this config diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 36c1100..1f17adb 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -101,6 +101,15 @@ # define CONFIG_CMD_EXT4_WRITE #endif +#ifdef CONFIG_NAND_ARASAN +# define CONFIG_CMD_NAND +# define CONFIG_CMD_NAND_LOCK_UNLOCK +# define CONFIG_SYS_MAX_NAND_DEVICE 1 +# define CONFIG_SYS_NAND_SELF_INIT +# define CONFIG_SYS_NAND_ONFI_DETECTION +# define CONFIG_MTD_DEVICE +#endif + /* Miscellaneous configurable options */ #define CONFIG_SYS_LOAD_ADDR 0x8000000 -- 1.7.1

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[U-Boot] [PATCH] x86: Clean up SPI flash drivers in defconfig
by Bin Meng 12 Feb '16

12 Feb '16

Every board has one dedicated type of SPI flash, hence it is unnecessary to include multiple SPI flash drivers. For QEMU and coreboot (default build of coreboot is also QEMU), SPI flash is not supported. Remove those SPI flash drivers. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- configs/bayleybay_defconfig | 2 -- configs/chromebook_link_defconfig | 2 -- configs/chromebox_panther_defconfig | 2 -- configs/coreboot-x86_defconfig | 4 ---- configs/crownbay_defconfig | 3 --- configs/galileo_defconfig | 2 -- configs/minnowmax_defconfig | 3 --- configs/qemu-x86_defconfig | 4 ---- 8 files changed, 22 deletions(-) diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig index 0a5a56f..c1ed990 100644 --- a/configs/bayleybay_defconfig +++ b/configs/bayleybay_defconfig @@ -21,8 +21,6 @@ CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_CONTROL=y CONFIG_CPU=y CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y CONFIG_E1000=y diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index ac64877..26b1d13 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -21,8 +21,6 @@ CONFIG_CMD_CROS_EC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_LPC=y CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index 0f3a9af..7fb25b4 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -20,8 +20,6 @@ CONFIG_CMD_CROS_EC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_LPC=y CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot-x86_defconfig index 8903cdd..96b6d0d 100644 --- a/configs/coreboot-x86_defconfig +++ b/configs/coreboot-x86_defconfig @@ -12,10 +12,6 @@ CONFIG_CMD_BOOTSTAGE=y CONFIG_CMD_TPM=y CONFIG_CMD_TPM_TEST=y CONFIG_OF_CONTROL=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y CONFIG_E1000=y CONFIG_DM_PCI=y diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index f4592c5..c96e800 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -19,10 +19,7 @@ CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_CONTROL=y CONFIG_CPU=y CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y CONFIG_E1000=y CONFIG_PCH_GBE=y diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig index 3612350..0dfc5f2 100644 --- a/configs/galileo_defconfig +++ b/configs/galileo_defconfig @@ -15,8 +15,6 @@ CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index 37c07c1..44fb426 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -20,10 +20,7 @@ CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_CONTROL=y CONFIG_CPU=y CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index ebdb892..6cd6bfb 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -14,10 +14,6 @@ CONFIG_BOOTSTAGE_REPORT=y CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_CONTROL=y CONFIG_CPU=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y CONFIG_E1000=y CONFIG_DM_PCI=y -- 1.8.2.1

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[U-Boot] [PATCH v2 00/26] dm: Conversion of code to the new driver model PCI API
by Simon Glass 12 Feb '16

12 Feb '16

PCI devices should be accessed just by their device pointer (which is struct udevice *). At present the hose (PCI controller) is often passed along with a pci_dev_t (bus/device/function) value. With driver model this is not necessary but most PCI code has not been converted over to use this new API yet. This series converts over various drivers with the goal of moving both Tegra and x86 to use PCI fully for driver model. In addition, both move to use driver model for Ethernet, which on x86 is related. The process is not complete with this series. Remaining are the Intel E1000 Ethernet driver and various x86-specific things like ICH SPI. Changes in v2: - Add a new pci_internal.h header file for internal PCI functions - Add missing code in dm_pci_phys_to_bus() - Drop non-DM PCI code - Drop unnecessary and confusing '#ifdef CONFIG_DM_ETH' in rtl8169_eth_probe() - Drop unnecessary comment at the top of pci_auto.c - Fix the indentation of the 'bar' for() loop - Fix use of 'pdev' instead of 'dev' - Get the vendor from the PCI parent platdata - Move the functions into pci_common.c so they can be used by old code - Put this code behind CONFIG_DM_PCI to avoid PowerPC build errors - Rename _dm_pci_hose_bus_to_phys() to _dm_pci_bus_to_phys() - Rename pci_run_vga_bios() to dm_pci_run_vga_bios() - Require driver model with pci_rom.c - Reword the commit message for clarity - Use dev_get_parent_platdata() instead of re-reading values from the device - Use dm_pci_get_bdf() - Use pci_bus_find_bdf() - Use u32 instead of uint32_t - Use uintptr_t to cast the hcor address Simon Glass (26): dm: pci: Mark legacy files as such dm: pci: Add a dm_ prefix to pci_get_bdf() dm: pci: Add a dm_ prefix to pci_bus_find_bdf() dm: pci: Use driver model PCI API in auto-config dm: pci: Add a driver-model version of pci_find_device() dm: pci: scsi: Use driver-model PCI API dm: pci: Add a driver-model version of pci_find_class() dm: pci: Add a function to read a PCI BAR dm: serial: Convert ns16550 driver to use driver model PCI API dm: x86: ivybridge: Convert graphics init to use DM PCI API dm: Convert bios_interrupts to use DM PCI API dm: pci: video: Convert video and pci_rom to use DM PCI API dm: x86: pci: Adjust bios_run_on_x86() to use the DM PCI API dm: pci: Drop the old version of pci_find_device/s() dm: pci: Drop the old version of pci_find_class() dm: tegra: net: Convert tegra boards to driver model for Ethernet dm: test: Convert PCI tests to use the DM PCI API dm: pci: Add driver model API functions for address mapping dm: net: Convert rtl8169 to use DM PCI API dm: pci: Switch to DM API for PCI address mapping dm: ahci: Convert to use new DM PCI API dm: usb: Convert echi-pci to use new DM PCI API dm: Convert PCI MMC over to use DM PCI API pci: Tidy up comments in pci_bind_bus_devices() dm: net: usb: Refactor mcs7830 driver ready for DM conversion dm: net: usb: Convert mcs7830 driver to support driver model arch/arm/mach-tegra/Kconfig | 1 + arch/x86/cpu/baytrail/valleyview.c | 4 +- arch/x86/cpu/ivybridge/bd82x6x.c | 6 +- arch/x86/cpu/ivybridge/gma.c | 15 +- arch/x86/cpu/quark/quark.c | 4 +- arch/x86/cpu/queensbay/topcliff.c | 4 +- arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 3 +- arch/x86/lib/bios.c | 3 +- arch/x86/lib/bios_interrupts.c | 36 ++- board/compulab/trimslice/trimslice.c | 8 - board/nvidia/cardhu/cardhu.c | 6 - board/nvidia/jetson-tk1/jetson-tk1.c | 6 - board/nvidia/p2371-2180/p2371-2180.c | 6 - board/toradex/apalis_t30/apalis_t30.c | 6 - common/cmd_pci.c | 2 +- common/cmd_scsi.c | 14 +- drivers/block/ahci.c | 70 ++++- drivers/mmc/pci_mmc.c | 15 +- drivers/net/designware.c | 2 +- drivers/net/e1000.c | 4 +- drivers/net/pch_gbe.c | 2 +- drivers/net/rtl8169.c | 84 ++++-- drivers/pci/Makefile | 7 +- drivers/pci/pci-uclass.c | 240 ++++++++++++++-- drivers/pci/pci.c | 5 +- drivers/pci/pci_auto.c | 386 ++++++++++++++++++++++++++ drivers/pci/pci_auto_old.c | 54 +--- drivers/pci/pci_common.c | 86 +++--- drivers/pci/pci_compat.c | 2 +- drivers/pci/pci_internal.h | 50 ++++ drivers/pci/pci_rom.c | 47 ++-- drivers/serial/ns16550.c | 5 +- drivers/usb/eth/mcs7830.c | 370 ++++++++++++++++-------- drivers/usb/host/ehci-pci.c | 51 +++- drivers/video/vesa_fb.c | 10 +- include/ahci.h | 4 + include/bios_emul.h | 2 +- include/fdtdec.h | 23 +- include/mmc.h | 6 +- include/pci.h | 102 ++++++- include/pci_rom.h | 6 +- lib/fdtdec.c | 57 +--- test/dm/pci.c | 15 +- 43 files changed, 1349 insertions(+), 480 deletions(-) create mode 100644 drivers/pci/pci_auto.c create mode 100644 drivers/pci/pci_internal.h -- 2.6.0.rc2.230.g3dd15c0

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[U-Boot] [PATCH 0/2] atmel_nand: add sama5d2 chip support, which support up to 32bit pmecc
by Josh Wu 02 Feb '16

02 Feb '16

This patch set will enable sama5d2 chip pmecc support, it includes: 1. update the pmecc registers and pmecc error location registers map. 2. add 32bit ecc support. Josh Wu (2): atmel_nand_ecc: update pmecc registers according to sama5d2 chip atmel_nand: Add 32 bit ecc support for sama5d2 chip drivers/mtd/nand/atmel_nand.c | 10 +++++++++- drivers/mtd/nand/atmel_nand_ecc.h | 36 ++++++++++++++++++++++++++++++++---- 2 files changed, 41 insertions(+), 5 deletions(-) -- 1.9.1

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[U-Boot] [PATCH] patman: fix series-notes handling for buildman
by Albert ARIBAUD 02 Feb '16

02 Feb '16

A patman series with a 'Series-notes' section causes buildman to crash with: self.series.notes += self.section TypeError: cannot concatenate 'str' and 'list' objects Fix by initializing series.notes as a one-element array rathen than a scalar. Signed-off-by: Albert ARIBAUD <albert.u.boot(a)aribaud.net> --- tools/patman/series.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/patman/series.py b/tools/patman/series.py index 3399f2c..e8aad59 100644 --- a/tools/patman/series.py +++ b/tools/patman/series.py @@ -69,7 +69,7 @@ class Series(dict): # Otherwise just set the value elif name in valid_series: - self[name] = value + self[name] = [value] else: raise ValueError("In %s: line '%s': Unknown 'Series-%s': valid " "options are %s" % (commit.hash, line, name, -- 2.5.0

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[U-Boot] How to access GP partitions from uboot (2015.04)
by harsha kiran 29 Jan '16

29 Jan '16

Hi! I have created 4 hw GP partitions on the eMMC (GP1,2,3,4) and formatted with ext4 fs. I have to read the contents of these partitions from the uboot but i am not finding them in the mmc part command. I can see them in the mmc info... U-Boot# mmc info Device: OMAP SD/MMC Manufacturer ID: fe OEM: 14e Name: MMC16 Tran Speed: 52000000 Rd Block Len: 512 MMC version 4.4.1 High Capacity: Yes Capacity: 13.5 GiB Bus Width: 8-bit Erase Group Size: 8 MiB HC WP Group Size: 16 MiB User Capacity: 13.5 GiB Boot Capacity: 16 MiB ENH RPMB Capacity: 128 KiB ENH GP1 Capacity: 256 MiB GP2 Capacity: 400 MiB GP3 Capacity: 256 MiB GP4 Capacity: 256 MiB But when i do mmc part i only see the user data partition information..i dont see the gp partition information U-Boot# mmc part Partition Map for MMC device 1 -- Partition Type: DOS Part Start Sector Num Sectors UUID Type 1 16 31280 00000000-01 0e Boot 2 31296 28181952 00000000-02 83 Do i have to enable any thing in the config to see them? Thanks, Harsha -- View this message in context: http://u-boot.10912.n7.nabble.com/How-to-access-GP-partitions-from-uboot-20… Sent from the U-Boot mailing list archive at Nabble.com.

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[U-Boot] [PATCH v4] mmc: socfpga_dw_mmc: Enable calibration for drvsel and smplsel
by Chin Liang See 27 Jan '16

27 Jan '16

Enable SDMMC calibration to determine the best setting for drvsel and smplsel. Calibration will be triggered if the drvsel and smplsel node are not available in DTS. Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: Pavel Machek <pavel(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> Cc: Pantelis Antoniou <pantelis.antoniou(a)konsulko.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> --- Changes for v4 - Calibration only run if node not in DTS Changes for v3 - Remove the && ok as its redundant Changes for v2 - Using standard error return macro - Split to small function to avoid deep identation - Fix coding standard --- drivers/mmc/socfpga_dw_mmc.c | 208 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 205 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index 2bd0ebd..a8e2660 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -13,6 +13,7 @@ #include <asm/arch/dwmmc.h> #include <asm/arch/clock_manager.h> #include <asm/arch/system_manager.h> +#include "mmc_private.h" static const struct socfpga_clock_manager *clock_manager_base = (void *)SOCFPGA_CLKMGR_ADDRESS; @@ -25,7 +26,144 @@ struct dwmci_socfpga_priv_data { unsigned int smplsel; }; -static void socfpga_dwmci_clksel(struct dwmci_host *host) +/* + * rows and columns of calibration rectange. The values are based on the value + * range of drvsel and smplsel register in system manager. Note drvsel 0 is + * unusable as it has meta-stability issue. + */ +#define SOCFPGA_SD_DRVSEL 7 +#define SOCFPGA_SD_SMPLSEL 8 + +static int socfpga_dwmci_find_row_col_fit_rectangle(unsigned rect_width, + unsigned rect_height, + unsigned char cal_results[SOCFPGA_SD_DRVSEL][SOCFPGA_SD_SMPLSEL], + unsigned int *cal_row, unsigned int *cal_col) +{ + unsigned char start_row, start_col; + + /* Find the row and column where the candidate fits */ + for (start_col = 0; start_col < (SOCFPGA_SD_SMPLSEL - rect_width + 1); + start_col++) { + for (start_row = 0; + start_row < (SOCFPGA_SD_DRVSEL - rect_height + 1); + start_row++) { + unsigned ok = 1; + unsigned add_col, add_row; + + /* Determine if the rectangle fits here */ + for (add_col = 0; (add_col < rect_width); add_col++) { + for (add_row = 0; add_row < rect_height; + add_row++) { + if (!cal_results[start_row + add_row] + [start_col + add_col]) { + ok = 0; + break; + } + } + } + + /* + * Return 'middle' of rectangle in case of + * success + */ + if (ok) { + if (rect_width > 1) + rect_width--; + + if (rect_height > 1) + rect_height--; + + *cal_row = start_row + (rect_height / 2); + *cal_col = start_col + (rect_width / 2); + + return 0; + } + } + } + return -EINVAL; +} + +/* + * This function determines the largest rectangle filled with 1's and returns + * the middle. This functon can be optimized, for example using the algorithm + * from http://www.drdobbs.com/database/the-maximal-rectangle-problem/184410529 + * It currently takes less than 1ms, while creating the input data takes ~5ms + * so there is not a real need to optimize it. + */ +static int socfpga_dwmci_find_calibration_point( + unsigned char cal_results[SOCFPGA_SD_DRVSEL][SOCFPGA_SD_SMPLSEL], + unsigned int sum, unsigned int *cal_row, unsigned int *cal_col) +{ + /* Structure containing a rectangle candidate */ + struct rect_cand_t { + unsigned char height; + unsigned char width; + unsigned short area; + }; + + /* Array with the rectangle candidates */ + struct rect_cand_t rect_cands[SOCFPGA_SD_DRVSEL * SOCFPGA_SD_SMPLSEL]; + struct rect_cand_t tmp; + unsigned char cr_rect_cand = 0; + unsigned char height, width, k; + + /* No solution if all combinations fail */ + if (sum == 0) + return -EINVAL; + + /* Simple solution if all combinations pass */ + if (sum == (SOCFPGA_SD_DRVSEL * SOCFPGA_SD_SMPLSEL)) { + *cal_row = (SOCFPGA_SD_DRVSEL - 1) / 2; + *cal_col = (SOCFPGA_SD_SMPLSEL - 1) / 2; + return 0; + } + + /* + * Create list of all possible sub-rectangles, in descending area + * order + */ + for (height = SOCFPGA_SD_DRVSEL; height >= 1; height--) { + for (width = SOCFPGA_SD_SMPLSEL; width >= 1; width--) { + /* Add a new rectangle candidate */ + rect_cands[cr_rect_cand].height = height; + rect_cands[cr_rect_cand].width = width; + rect_cands[cr_rect_cand].area = height * width; + cr_rect_cand++; + + /* First candidate it always in the right position */ + if (cr_rect_cand == 1) + continue; + + /* + * Put the candidate in right location to maintain + * descending order + */ + for (k = cr_rect_cand - 1; k > 1; k--) { + if (rect_cands[k-1].area < rect_cands[k].area) { + tmp = rect_cands[k-1]; + rect_cands[k-1] = rect_cands[k]; + rect_cands[k] = tmp; + } else { + break; + } + } + } + } + + /* Try to fit the rectangle candidates, in descending area order */ + for (k = 0; k < SOCFPGA_SD_DRVSEL * SOCFPGA_SD_SMPLSEL; k++) { + if (!socfpga_dwmci_find_row_col_fit_rectangle( + rect_cands[k].width, + rect_cands[k].height, + cal_results, cal_row, cal_col)) + return 0; + } + + /* We could not fit any rectangle - return failure */ + return -EINVAL; +} + +static void socfpga_dwmci_set_clksel(struct dwmci_host *host) { struct dwmci_socfpga_priv_data *priv = host->priv; @@ -46,6 +184,70 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host) CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); } +/* + * This function calibrates the drvsel and smplsel by trying all possible + * values and selecting the best combnation + */ +void socfpga_dwmci_calibrate(struct dwmci_host *host) +{ + int err = 0; + unsigned char cal_results[SOCFPGA_SD_DRVSEL][SOCFPGA_SD_SMPLSEL]; + unsigned int sum = 0; + unsigned int row, col; + + struct mmc *mmc = host->mmc; + struct dwmci_socfpga_priv_data *priv = host->priv; + + printf("%s: Calibration started.\n", __func__); + + for (row = 0; row < SOCFPGA_SD_DRVSEL; row++) { + for (col = 0; col < SOCFPGA_SD_SMPLSEL; col++) { + priv->drvsel = row + 1; + priv->smplsel = col; + socfpga_dwmci_set_clksel(host); + cal_results[row][col] = !(mmc_set_blocklen(mmc, + mmc->read_bl_len)); + sum += cal_results[row][col]; + } + } + +#if DEBUG + debug("%s: Calibration raw data:\n", __func__); + for (row = 0; row < SOCFPGA_SD_DRVSEL; row++) { + debug("\t"); + for (col = 0; col < SOCFPGA_SD_SMPLSEL; col++) + debug("%d ", cal_results[row][col]); + debug("\n"); + } +#endif + + err = socfpga_dwmci_find_calibration_point(cal_results, sum, + &priv->drvsel, + &priv->smplsel); + + if (err) { + printf("%s: Calibration failed.\n", __func__); + hang(); + } else + printf("%s: Calibration passed: drvsel = %d " + "smplsel = %d.\n", __func__, priv->drvsel, priv->smplsel); + + socfpga_dwmci_set_clksel(host); + + /* re-write in case accidentally overwrite with junk */ + mmc_set_blocklen(mmc, mmc->read_bl_len); +} + +static void socfpga_dwmci_clksel(struct dwmci_host *host) +{ + struct dwmci_socfpga_priv_data *priv = host->priv; + + if (priv->drvsel == 0xf || priv->smplsel == 0xf) + socfpga_dwmci_calibrate(host); + else + socfpga_dwmci_set_clksel(host); +} + static int socfpga_dwmci_of_probe(const void *blob, int node, const int idx) { /* FIXME: probe from DT eventually too/ */ @@ -102,8 +304,8 @@ static int socfpga_dwmci_of_probe(const void *blob, int node, const int idx) host->bus_hz = clk; host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2); - priv->drvsel = fdtdec_get_uint(blob, node, "drvsel", 3); - priv->smplsel = fdtdec_get_uint(blob, node, "smplsel", 0); + priv->drvsel = fdtdec_get_uint(blob, node, "drvsel", 0xf); + priv->smplsel = fdtdec_get_uint(blob, node, "smplsel", 0xf); host->priv = priv; return add_dwmci(host, host->bus_hz, 400000); -- 2.2.0

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[U-Boot] [PATCH v2] mmc: atmel: Properly fix clock configuration
by Gregory CLEMENT 27 Jan '16

27 Jan '16

Timing issue occurs on eMMC not only when modifying the frequency but also for all the switch command(CMD6). According to the MMC spec waiting 8 clocks after a switch command would be the thing to do. This patch allows fixing CPU hang observed when trying to changing the bus width on a eMMC on SAMA5D4. Signed-off-by: Gregory CLEMENT <gregory.clement(a)free-electrons.com> Tested-by: Marek Vasut <marex(a)denx.de> # on DENX MA5D4EV --- drivers/mmc/gen_atmel_mci.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c index da870c6..f090b27 100644 --- a/drivers/mmc/gen_atmel_mci.c +++ b/drivers/mmc/gen_atmel_mci.c @@ -36,6 +36,7 @@ struct atmel_mci_priv { struct mmc_config cfg; struct atmel_mci *mci; unsigned int initialized:1; + unsigned int curr_clk; }; /* Read Atmel MCI IP version */ @@ -91,7 +92,10 @@ static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen) } } - + if (version >= 0x500) + priv->curr_clk = bus_hz / (clkdiv * 2 + clkodd + 2); + else + priv->curr_clk = (bus_hz / (clkdiv + 1)) / 2; blklen &= 0xfffc; mr = MMCI_BF(CLKDIV, clkdiv); @@ -118,8 +122,6 @@ static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen) if (mmc->card_caps & mmc->cfg->host_caps & MMC_MODE_HS) writel(MMCI_BIT(HSMODE), &mci->cfg); - udelay(50); - priv->initialized = 1; } @@ -323,6 +325,13 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) } } + /* + * After the switch command, wait for 8 clocks before the next + * command + */ + if (cmd->cmdidx == MMC_CMD_SWITCH) + udelay(8*1000000/ priv->curr_clk); /* 8 clk in us */ + return 0; } -- 2.5.0

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