October 2015 - U-Boot

[U-Boot] [PATCH] FSL SPI read fix.
by Dale Smith 14 Dec '15

14 Dec '15

The fsl spi engine is non functional when reading from a device. This patch fixes it. Note that none of the other spi interfaces parse through the datastream looking for 0x0b bytes. -Dale diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index a1ebd33..737719b 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -291,17 +291,10 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, debug("***spi_xfer:...%08x readed\n", tmpdin); } } - if (data_in) { - memcpy(data_in, buffer + 2 * cmd_len, tran_len); - if (*buffer == 0x0b) { - data_in += tran_len; - data_len -= tran_len; - *(int *)buffer += tran_len; - } - } spi_cs_deactivate(slave); } - + if (data_in) + memcpy(data_in, buffer + rx_offset, len); free(buffer); return 0; }

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Re: [U-Boot] [linux-sunxi] Mainline U-Boot, EHCI, usbkbd not working (workaround)
by B.R. Oake 13 Dec '15

13 Dec '15

(This started on the linux-sunxi mailing list but will hopefully be of interest on the U-Boot list) On 04/01/15 13:45, Lars Doelle wrote: > while testing with mainline u-boot, I came over the > problem, that the USB keyboard is not recognized. > > The device is an A20-OLinuXIno-LIME2. I used the > current A20-OLinuXino-Lime2_defconfig for building. > > In my understanding, the issue should be reproducible > with all devices having an EHCI root hub. > > --- > sun7i# usb reset > (Re)start USB... > USB0: USB EHCI 1.00 > scanning bus 0 for devices... cannot reset port 1!? > 1 USB Device(s) found > USB1: USB EHCI 1.00 > scanning bus 1 for devices... 1 USB Device(s) found > scanning usb for storage devices... 0 Storage Device(s) found > sun7i# usb tree > USB device tree: > 1 Hub (480 Mb/s, 0mA) > u-boot EHCI Host Controller > > 2 Hub (480 Mb/s, 0mA) > u-boot EHCI Host Controller > --- > > As a workaround, i plugged an USB hub in between: > [...] I also have this problem. I've tried three different USB keyboards on an A20-Olinuxino-Micro and a Banana Pi, and I always get that error "cannot reset port N!?" where N is whichever USB socket I've plugged it into, and U-Boot cannot see the keyboard. Once Linux has loaded, the keyboard works without any trouble. Can anyone suggest what is causing this? Thank you, B.R. Oake.

5 7

[U-Boot] [PATCH] arm: socfpga: Fix cache configuration
by Stefan Roese 09 Dec '15

09 Dec '15

By not defining CONFIG_SYS_ARM_CACHE_WRITEALLOC, the WRITEBACK cache policy is selected. This leads to much better performance on the SoCFPGA. A quick network test shows this: Without this patch: => tftp 100000 big-40mb Speed: 1000, full duplex Using dwmac.ff702000 device TFTP from server 192.168.1.54; our IP address is 192.168.1.252 Filename 'big-40mb'. Load address: 0x100000 Loading: ################################################################# ################################################################# ################################################################# ################################################################# ########################## 2.5 MiB/s With this patch: => tftp 100000 big-40mb Speed: 1000, full duplex Using dwmac.ff702000 device TFTP from server 192.168.1.54; our IP address is 192.168.1.252 Filename 'big-40mb'. Load address: 0x100000 Loading: ################################################################# ################################################################# ################################################################# ################################################################# ########################## 7.6 MiB/s A performance improvement of factor ~3. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Chin Liang See <clsee(a)altera.com> Cc: Pavel Machek <pavel(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> --- include/configs/socfpga_common.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 38ae763..a2811ba 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -73,7 +73,6 @@ /* * Cache */ -#define CONFIG_SYS_ARM_CACHE_WRITEALLOC #define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS -- 2.5.2

4 27

[U-Boot] [PATCH] usb: udc: Fix warnings on 64-bit builds
by Michal Simek 09 Dec '15

09 Dec '15

Cast u32 bit value to 64bit before recasting to 64bit pointer to avoid pointer from integer cast size mismatch warnings. Warning log: +../drivers/usb/gadget/udc/udc-core.c: In function ‘usb_gadget_unmap_request’: +../drivers/usb/gadget/udc/udc-core.c:68:19: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/usb/gadget/udc/udc-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/gadget/udc/udc-core.c b/drivers/usb/gadget/udc/udc-core.c index 875e998a82e3..326757b547fa 100644 --- a/drivers/usb/gadget/udc/udc-core.c +++ b/drivers/usb/gadget/udc/udc-core.c @@ -65,7 +65,7 @@ void usb_gadget_unmap_request(struct usb_gadget *gadget, if (req->length == 0) return; - dma_unmap_single((void *)req->dma, req->length, + dma_unmap_single((void *)(uintptr_t)req->dma, req->length, is_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE); } EXPORT_SYMBOL_GPL(usb_gadget_unmap_request); -- 2.5.0

3 6

[U-Boot] [PATCH] imx: mx7: enable CONFIG_FSL_CLK
by Peng Fan 07 Dec '15

07 Dec '15

This commit "677f970bc62a661690b3431543d5a5d5e682ba70" introduce a new macro "CONFIG_FSL_CLK" that get_clocks() should not be limited by ESDHC. But that patch missed to enable it for i.MX7. THis patch enables CONFIG_FSL_CLK to let get_clocks work. Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> Cc: Adrian Alonso <aalonso(a)freescale.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Fabio Estevam <fabio.estevam(a)freescale.com> --- include/configs/mx7_common.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index 04468b9..4fb2a2b 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -36,6 +36,8 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_FSL_CLK + #define CONFIG_LOADADDR 0x80800000 #define CONFIG_SYS_TEXT_BASE 0x87800000 -- 1.8.4

2 1

[U-Boot] [PATCH] dm: implement a cfi flash uclass
by Thomas Chou 07 Dec '15

07 Dec '15

Implement a cfi flash uclass to work with drivers/mtd/cfi-flash.c. The flash base address is extracted from device tree, and passed to cfi_flash_bank_addr(). Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- common/board_r.c | 3 ++ drivers/mtd/Kconfig | 11 +++++++ drivers/mtd/Makefile | 1 + drivers/mtd/cfi-flash-uclass.c | 70 ++++++++++++++++++++++++++++++++++++++++++ drivers/mtd/cfi_flash.c | 19 ++++++++++++ include/cfi-flash.h | 27 ++++++++++++++++ include/dm/uclass-id.h | 1 + 7 files changed, 132 insertions(+) create mode 100644 drivers/mtd/cfi-flash-uclass.c create mode 100644 include/cfi-flash.h diff --git a/common/board_r.c b/common/board_r.c index aaf390e..86b606d 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -38,6 +38,7 @@ #include <miiphy.h> #endif #include <mmc.h> +#include <mtd/cfi_flash.h> #include <nand.h> #include <onenand_uboot.h> #include <scsi.h> @@ -348,6 +349,8 @@ static int initr_flash(void) /* update start of FLASH memory */ #ifdef CONFIG_SYS_FLASH_BASE bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; +#else + bd->bi_flashstart = cfi_flash_bank_addr(0); #endif /* size of FLASH memory (final value) */ bd->bi_flashsize = flash_size; diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index 59278d1..4b52894 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -1,3 +1,14 @@ +menu "CFI Flash Support" + +config DM_CFI_FLASH + bool "Enable Driver Model for CFI Flash drivers" + depends on DM + help + Enable driver model for CFI flash access. It uses the same API as + drivers/mtd/cfi_flash.c. But now implemented by the uclass. + +endmenu + source "drivers/mtd/nand/Kconfig" source "drivers/mtd/spi/Kconfig" diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index a623f4c..d86e2c2 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -11,6 +11,7 @@ endif obj-$(CONFIG_MTD_PARTITIONS) += mtdpart.o obj-$(CONFIG_MTD_CONCAT) += mtdconcat.o obj-$(CONFIG_HAS_DATAFLASH) += at45.o +obj-$(CONFIG_DM_CFI_FLASH) += cfi-flash-uclass.o obj-$(CONFIG_FLASH_CFI_DRIVER) += cfi_flash.o obj-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o obj-$(CONFIG_HAS_DATAFLASH) += dataflash.o diff --git a/drivers/mtd/cfi-flash-uclass.c b/drivers/mtd/cfi-flash-uclass.c new file mode 100644 index 0000000..1db7e2f --- /dev/null +++ b/drivers/mtd/cfi-flash-uclass.c @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2015 Thomas Chou <thomas(a)wytron.com.tw> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <fdtdec.h> +#include <cfi-flash.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Implement a cfi flash uclass to work with drivers/mtd/cfi-flash.c. + */ + +phys_addr_t cfi_flash_get_base(struct udevice *dev) +{ + struct cfi_flash_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + return uc_priv->base; +} + +UCLASS_DRIVER(cfi_flash) = { + .id = UCLASS_CFI_FLASH, + .name = "cfi_flash", + .per_device_auto_alloc_size = sizeof(struct cfi_flash_dev_priv), +}; + +struct cfi_flash_platdata { + phys_addr_t base; +}; + +static int cfi_flash_probe(struct udevice *dev) +{ + struct cfi_flash_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct cfi_flash_platdata *plat = dev->platdata; + + uc_priv->base = plat->base; + + return 0; +} + +static int cfi_flash_ofdata_to_platdata(struct udevice *dev) +{ + struct cfi_flash_platdata *plat = dev_get_platdata(dev); + fdt_size_t size; + + fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size); + plat->base = (phys_addr_t)ioremap(dev_get_addr(dev), size); + + return 0; +} + +static const struct udevice_id cfi_flash_ids[] = { + { .compatible = "cfi-flash", }, + { } +}; + +U_BOOT_DRIVER(cfi_flash) = { + .name = "cfi_flash", + .id = UCLASS_CFI_FLASH, + .of_match = cfi_flash_ids, + .ofdata_to_platdata = cfi_flash_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct cfi_flash_platdata), + .probe = cfi_flash_probe, +}; diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 50983b8..6ec0877 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -18,6 +18,9 @@ /* #define DEBUG */ #include <common.h> +#include <dm.h> +#include <errno.h> +#include <cfi-flash.h> #include <asm/processor.h> #include <asm/io.h> #include <asm/byteorder.h> @@ -87,10 +90,26 @@ static u16 cfi_flash_config_reg(int i) int cfi_flash_num_flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT; #endif +#ifdef CONFIG_DM_CFI_FLASH +phys_addr_t cfi_flash_bank_addr(int i) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device(UCLASS_CFI_FLASH, i, &dev); + if (ret) + return ret; + if (!dev) + return -ENODEV; + + return cfi_flash_get_base(dev); +} +#else __weak phys_addr_t cfi_flash_bank_addr(int i) { return ((phys_addr_t [])CONFIG_SYS_FLASH_BANKS_LIST)[i]; } +#endif __weak unsigned long cfi_flash_bank_size(int i) { diff --git a/include/cfi-flash.h b/include/cfi-flash.h new file mode 100644 index 0000000..0064cba --- /dev/null +++ b/include/cfi-flash.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2015 Thomas Chou <thomas(a)wytron.com.tw> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DM_CFI_FLASH_H_ +#define _DM_CFI_FLASH_H_ + +/* + * Get the cfi flash base address + * + * @dev: The cfi flash device + * @return: the cfi flash base address + */ +phys_addr_t cfi_flash_get_base(struct udevice *dev); + +/* + * struct cfi_flash_dev_priv - information about a device used by the uclass + * + * @base: the cfi flash base address + */ +struct cfi_flash_dev_priv { + phys_addr_t base; +}; + +#endif /* _DM_CFI_FLASH_H_ */ diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index a6982ab..09e370c 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -25,6 +25,7 @@ enum uclass_id { UCLASS_SIMPLE_BUS, /* bus with child devices */ /* U-Boot uclasses start here - in alphabetical order */ + UCLASS_CFI_FLASH, /* cfi flash */ UCLASS_CLK, /* Clock source, e.g. used by peripherals */ UCLASS_CPU, /* CPU, typically part of an SoC */ UCLASS_CROS_EC, /* Chrome OS EC */ -- 2.1.4

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[U-Boot] [PATCH] dm: core: Enable optional use of fdt_translate_address()
by Stefan Roese 04 Dec '15

04 Dec '15

The current "simple" address translation simple_bus_translate() is not working on some platforms (e.g. MVEBU). As here more complex "ranges" properties are used in many nodes (multiple tuples etc). This patch enables the optional use of the common fdt_translate_address() function which handles this translation correctly. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> Cc: Bin Meng <bmeng.cn(a)gmail.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- drivers/core/Kconfig | 30 ++++++++++++++++++++++++++++++ drivers/core/device.c | 8 +++++++- 2 files changed, 37 insertions(+), 1 deletion(-) diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index 41f4e69..15681df 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -120,4 +120,34 @@ config SPL_SIMPLE_BUS Supports the 'simple-bus' driver, which is used on some systems in SPL. +config OF_TRANSLATE + bool "Translate addresses using fdt_translate_address" + depends on DM && OF_CONTROL + default y + help + If this option is enabled, the reg property will be translated + using the fdt_translate_address() function. This is necessary + on some platforms (e.g. MVEBU) using complex "ranges" + properties in many nodes. As this translation is not handled + correctly in the default simple_bus_translate() function. + + If this option is not enabled, simple_bus_translate() will be + used for the address translation. This function is faster and + smaller in size than fdt_translate_address(). + +config SPL_OF_TRANSLATE + bool "Translate addresses using fdt_translate_address" + depends on SPL_DM && SPL_OF_CONTROL + default n + help + If this option is enabled, the reg property will be translated + using the fdt_translate_address() function. This is necessary + on some platforms (e.g. MVEBU) using complex "ranges" + properties in many nodes. As this translation is not handled + correctly in the default simple_bus_translate() function. + + If this option is not enabled, simple_bus_translate() will be + used for the address translation. This function is faster and + smaller in size than fdt_translate_address(). + endmenu diff --git a/drivers/core/device.c b/drivers/core/device.c index a6cd936..0cf73cf 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -11,6 +11,7 @@ #include <common.h> #include <fdtdec.h> +#include <fdt_support.h> #include <malloc.h> #include <dm/device.h> #include <dm/device-internal.h> @@ -580,7 +581,12 @@ fdt_addr_t dev_get_addr(struct udevice *dev) fdt_addr_t addr; addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg"); - if (CONFIG_IS_ENABLED(SIMPLE_BUS) && addr != FDT_ADDR_T_NONE) { + if (CONFIG_IS_ENABLED(OF_TRANSLATE)) { + const fdt32_t *reg = fdt_getprop(gd->fdt_blob, dev->of_offset, + "reg", NULL); + addr = fdt_translate_address((void *)gd->fdt_blob, + dev->of_offset, reg); + } else if (CONFIG_IS_ENABLED(SIMPLE_BUS) && addr != FDT_ADDR_T_NONE) { if (device_get_uclass_id(dev->parent) == UCLASS_SIMPLE_BUS) addr = simple_bus_translate(dev->parent, addr); } -- 2.5.1

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[U-Boot] [PATCH v3] arm: ls2080a: Add sata support on qds and rdb board
by Tang Yuantian 01 Dec '15

01 Dec '15

Freescale ARM-based Layerscape LS2080A contain a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds SATA feature on ls2080aqds and ls2080ardb boards. Signed-off-by: Tang Yuantian <Yuantian.Tang(a)freescale.com> --- depends on patches: http://patchwork.ozlabs.org/patch/530576/ armv8: LS2080A: Rename LS2085A to reflect LS2080A http://patchwork.ozlabs.org/patch/530575/ armv8: ls2085a: Add support of LS2085A SoC v3: - rename ls2085a to ls2080a - rebase to the latest git tree - replace the magic number with micro variable v2: - rebase to the latest git tree arch/arm/cpu/armv8/fsl-lsch3/soc.c | 36 +++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-lsch3/config.h | 20 +++++++++++++ arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 25 ++++++++++++++++ arch/arm/include/asm/arch-fsl-lsch3/soc.h | 3 ++ board/freescale/ls2080aqds/ls2080aqds.c | 11 +++++++ board/freescale/ls2080ardb/ls2080ardb.c | 11 +++++++ 6 files changed, 106 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c b/arch/arm/cpu/armv8/fsl-lsch3/soc.c index 2538001..4f9489e 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/soc.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/soc.c @@ -11,6 +11,9 @@ #include <asm/arch-fsl-lsch3/soc.h> #include <asm/io.h> #include <asm/global_data.h> +#include <asm/arch-fsl-lsch3/immap_lsch3.h> +#include <ahci.h> +#include <scsi.h> DECLARE_GLOBAL_DATA_PTR; @@ -78,6 +81,39 @@ void fsl_lsch3_early_init_f(void) erratum_a009203(); } +#ifdef CONFIG_SCSI_AHCI_PLAT +int ls2080a_sata_init(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_ahci __iomem *ahci_base; + u32 cfg; + int rc = -1; + + ahci_base = (void __iomem *)CONFIG_SYS_SATA2; + out_le32(&ahci_base->ppcfg, AHCI_PORT_PHY_1_CFG); + + ahci_base = (void __iomem *)CONFIG_SYS_SATA1; + out_le32(&ahci_base->ppcfg, AHCI_PORT_PHY_1_CFG); + + cfg = in_le32(&gur->rcwsr[28]) & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; + cfg >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; + + if ((cfg != 0x41) && (cfg != 0x42) && (cfg != 0x43) && + (cfg != 0x44) && (cfg != 0x49) && (cfg != 0x4A)) { + printf("SATA disabled: serdes protocol doesn't support\n"); + return rc; + } + + rc = ahci_init((void __iomem *)CONFIG_SYS_SATA1); + if (rc) + return rc; + + scsi_scan(0); + + return 0; +} +#endif + #ifdef CONFIG_SPL_BUILD void board_init_f(ulong dummy) { diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 0733852..1616bea 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -68,6 +68,26 @@ #define CONFIG_SYS_LS2080A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) #define CONFIG_SYS_LS2080A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) +/* SATA */ +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_CMD_SCSI +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + 0x02200000) +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + 0x02210000) + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + /* TZ Protection Controller Definitions */ #define TZPC_BASE 0x02200000 #define TZPCR0SIZE_BASE (TZPC_BASE) diff --git a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h index 941f99a..ce04018 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h @@ -182,4 +182,29 @@ struct ccsr_reset { u32 ip_rev1; /* 0xbf8 */ u32 ip_rev2; /* 0xbfc */ }; + +/* AHCI (sata) register map */ +struct ccsr_ahci { + u32 res1[0xa4/4]; /* 0x0 - 0xa4 */ + u32 pcfg; /* port config */ + u32 ppcfg; /* port phy1 config */ + u32 pp2c; /* port phy2 config */ + u32 pp3c; /* port phy3 config */ + u32 pp4c; /* port phy4 config */ + u32 pp5c; /* port phy5 config */ + u32 axicc; /* AXI cache control */ + u32 paxic; /* port AXI config */ + u32 axipc; /* AXI PROT control */ + u32 ptc; /* port Trans Config */ + u32 pts; /* port Trans Status */ + u32 plc; /* port link config */ + u32 plc1; /* port link config1 */ + u32 plc2; /* port link config2 */ + u32 pls; /* port link status */ + u32 pls1; /* port link status1 */ + u32 pcmdc; /* port CMD config */ + u32 ppcs; /* port phy control status */ + u32 pberr; /* port 0/1 BIST error */ + u32 cmds; /* port 0/1 CMD status error */ +}; #endif /* __ARCH_FSL_LSCH3_IMMAP_H */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/soc.h b/arch/arm/include/asm/arch-fsl-lsch3/soc.h index 9a29272..1963842 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/soc.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/soc.h @@ -23,6 +23,9 @@ struct cpu_type { #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) +#define AHCI_PORT_PHY_1_CFG 0xa003fffe + +int ls2080a_sata_init(void); void fsl_lsch3_early_init_f(void); void cpu_name(char *name); diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 8f114a5..f20bf81 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -188,6 +188,17 @@ int config_board_mux(int ctrl_type) return 0; } +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_SCSI_AHCI_PLAT + ls2080a_sata_init(); +#endif + + return 0; +} +#endif + int board_init(void) { char *env_hwconfig; diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 5451b2e..036860c 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -145,6 +145,17 @@ int config_board_mux(int ctrl_type) return 0; } +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_SCSI_AHCI_PLAT + ls2080a_sata_init(); +#endif + + return 0; +} +#endif + int board_init(void) { char *env_hwconfig; -- 2.1.0.27.g96db324

3 2

[U-Boot] [PATCH v6] arm: atmel: Add SAMA5D2 Xplained board
by Wenyou Yang 30 Nov '15

30 Nov '15

The board supports following features: - Boot media support: SD card/e.MMC/SPI flash, - Support LCD display (optional, disabled by default), - Support ethernet, - Support USB mass storage. Signed-off-by: Wenyou Yang <wenyou.yang(a)atmel.com> --- The patch is based on the following patches sent in mailing list. [PATCH] gpio: atmel: Add the PIO4 driver support [PATCH] arm: at91: Change the Chip ID registers' addresses [PATCH v4] mmc: atmel: Add atmel sdhci support [PATCH v3] arm: at91: clock: Add the generated clock support Changes in v6: 1./ change function invocation due to its declaration change, at91_enable_periph_generated_clk(). Changes in v5: 1./ remove wrong pin config for USB hw init. Changes in v4: 1./ remove __weak attribute for has_lcdc() added in v3. 2./ remove unused goto err_exit. Changes in v3: 1./ change defines-->definitions for more clearly in asm/arch/sama5d2.h. 2./ remove unused cpu_is_sama5d2x() macros. 3./ fix spelling error "adress". 4./ add __weak attribute for has_lcdc(). 5./ remove SPL configs. Changes in v2: 1./ re-order SAMA5D2 statements alphabetically. 2./ remove redundant "Unknown CPU type". 3./ rework sama5d2's macros. 4./ remove some #ifdef before functions. 5./ move CONFIG_CMD_SF to Kconfig. 6./ remove NAND macros from config file. 7./ CONFIG_BOOTCOMMAND for sf uses defines in at91-sama5_common.h. arch/arm/mach-at91/Kconfig | 5 + arch/arm/mach-at91/armv7/Makefile | 1 + arch/arm/mach-at91/armv7/sama5d2_devices.c | 59 +++++ arch/arm/mach-at91/include/mach/at91_pmc.h | 9 +- arch/arm/mach-at91/include/mach/atmel_usba_udc.h | 3 +- arch/arm/mach-at91/include/mach/hardware.h | 2 + arch/arm/mach-at91/include/mach/sama5d2.h | 203 ++++++++++++++++ board/atmel/sama5d2_xplained/Kconfig | 15 ++ board/atmel/sama5d2_xplained/MAINTAINERS | 7 + board/atmel/sama5d2_xplained/Makefile | 8 + board/atmel/sama5d2_xplained/sama5d2_xplained.c | 284 ++++++++++++++++++++++ configs/sama5d2_xplained_mmc_defconfig | 11 + configs/sama5d2_xplained_spiflash_defconfig | 11 + include/configs/sama5d2_xplained.h | 122 ++++++++++ 14 files changed, 734 insertions(+), 6 deletions(-) create mode 100644 arch/arm/mach-at91/armv7/sama5d2_devices.c create mode 100644 arch/arm/mach-at91/include/mach/sama5d2.h create mode 100644 board/atmel/sama5d2_xplained/Kconfig create mode 100644 board/atmel/sama5d2_xplained/MAINTAINERS create mode 100644 board/atmel/sama5d2_xplained/Makefile create mode 100644 board/atmel/sama5d2_xplained/sama5d2_xplained.c create mode 100644 configs/sama5d2_xplained_mmc_defconfig create mode 100644 configs/sama5d2_xplained_spiflash_defconfig create mode 100644 include/configs/sama5d2_xplained.h diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index fdaf328..c333647 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -71,6 +71,10 @@ config TARGET_AT91SAM9X5EK select CPU_ARM926EJS select SUPPORT_SPL +config TARGET_SAMA5D2_XPLAINED + bool "SAMA5D2 Xplained board" + select CPU_V7 + config TARGET_SAMA5D3_XPLAINED bool "SAMA5D3 Xplained board" select CPU_V7 @@ -123,6 +127,7 @@ source "board/atmel/at91sam9m10g45ek/Kconfig" source "board/atmel/at91sam9n12ek/Kconfig" source "board/atmel/at91sam9rlek/Kconfig" source "board/atmel/at91sam9x5ek/Kconfig" +source "board/atmel/sama5d2_xplained/Kconfig" source "board/atmel/sama5d3_xplained/Kconfig" source "board/atmel/sama5d3xek/Kconfig" source "board/atmel/sama5d4_xplained/Kconfig" diff --git a/arch/arm/mach-at91/armv7/Makefile b/arch/arm/mach-at91/armv7/Makefile index f4f35a4..9538bc1 100644 --- a/arch/arm/mach-at91/armv7/Makefile +++ b/arch/arm/mach-at91/armv7/Makefile @@ -8,6 +8,7 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-$(CONFIG_SAMA5D2) += sama5d2_devices.o obj-$(CONFIG_SAMA5D3) += sama5d3_devices.o obj-$(CONFIG_SAMA5D4) += sama5d4_devices.o obj-y += clock.o diff --git a/arch/arm/mach-at91/armv7/sama5d2_devices.c b/arch/arm/mach-at91/armv7/sama5d2_devices.c new file mode 100644 index 0000000..6ebbccf --- /dev/null +++ b/arch/arm/mach-at91/armv7/sama5d2_devices.c @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2015 Atmel Corporation + * Wenyou Yang <wenyou.yang(a)atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/clk.h> +#include <asm/arch/sama5d2.h> + +char *get_cpu_name() +{ + unsigned int extension_id = get_extension_chip_id(); + + if (cpu_is_sama5d2()) { + switch (extension_id) { + case ARCH_EXID_SAMA5D21CU: + return "SAMA5D21"; + case ARCH_EXID_SAMA5D22CU: + return "SAMA5D22-CU"; + case ARCH_EXID_SAMA5D22CN: + return "SAMA5D22-CN"; + case ARCH_EXID_SAMA5D23CU: + return "SAMA5D23-CU"; + case ARCH_EXID_SAMA5D24CX: + return "SAMA5D24-CX"; + case ARCH_EXID_SAMA5D24CU: + return "SAMA5D24-CU"; + case ARCH_EXID_SAMA5D26CU: + return "SAMA5D26-CU"; + case ARCH_EXID_SAMA5D27CU: + return "SAMA5D27-CU"; + case ARCH_EXID_SAMA5D27CN: + return "SAMA5D27-CN"; + case ARCH_EXID_SAMA5D28CU: + return "SAMA5D28-CU"; + case ARCH_EXID_SAMA5D28CN: + return "SAMA5D28-CN"; + default: + ; + } + } + + return "Unknown CPU type"; +} + +#ifdef CONFIG_USB_GADGET_ATMEL_USBA +void at91_udp_hw_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr); + + at91_periph_clk_enable(ATMEL_ID_UDPHS); +} +#endif diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index 8a3fb94..5adaa30 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -78,7 +78,8 @@ typedef struct at91_pmc { #define AT91_PMC_PLLXR_DIV(x) (x & 0xFF) #define AT91_PMC_PLLXR_PLLCOUNT(x) ((x & 0x3F) << 8) #define AT91_PMC_PLLXR_OUT(x) ((x & 0x03) << 14) -#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) +#if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D3) || \ + defined(CONFIG_SAMA5D4) #define AT91_PMC_PLLXR_MUL(x) ((x & 0x7F) << 18) #else #define AT91_PMC_PLLXR_MUL(x) ((x & 0x7FF) << 16) @@ -97,7 +98,8 @@ typedef struct at91_pmc { #define AT91_PMC_MCKR_CSS_PLLB 0x00000003 #define AT91_PMC_MCKR_CSS_MASK 0x00000003 -#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \ +#if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D3) || \ + defined(CONFIG_SAMA5D4) || \ defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12) #define AT91_PMC_MCKR_PRES_1 0x00000000 #define AT91_PMC_MCKR_PRES_2 0x00000010 @@ -127,10 +129,7 @@ typedef struct at91_pmc { #else #define AT91_PMC_MCKR_MDIV_1 0x00000000 #define AT91_PMC_MCKR_MDIV_2 0x00000100 -#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \ - defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12) #define AT91_PMC_MCKR_MDIV_3 0x00000300 -#endif #define AT91_PMC_MCKR_MDIV_4 0x00000200 #define AT91_PMC_MCKR_MDIV_MASK 0x00000300 #endif diff --git a/arch/arm/mach-at91/include/mach/atmel_usba_udc.h b/arch/arm/mach-at91/include/mach/atmel_usba_udc.h index 38b5012..46a329b 100644 --- a/arch/arm/mach-at91/include/mach/atmel_usba_udc.h +++ b/arch/arm/mach-at91/include/mach/atmel_usba_udc.h @@ -31,7 +31,8 @@ static struct usba_ep_data usba_udc_ep[] = { EP("ep5", 5, 1024, 3, 1, 1), EP("ep6", 6, 1024, 3, 1, 1), }; -#elif defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) +#elif defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D3) || \ + defined(CONFIG_SAMA5D4) static struct usba_ep_data usba_udc_ep[] = { EP("ep0", 0, 64, 1, 0, 0), EP("ep1", 1, 1024, 3, 1, 0), diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h index ff6b71b..38abfda 100644 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ b/arch/arm/mach-at91/include/mach/hardware.h @@ -23,6 +23,8 @@ # include <asm/arch/at91sam9g45.h> #elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5) # include <asm/arch/at91sam9x5.h> +#elif defined(CONFIG_SAMA5D2) +# include <asm/arch/sama5d2.h> #elif defined(CONFIG_SAMA5D3) # include <asm/arch/sama5d3.h> #elif defined(CONFIG_SAMA5D4) diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h new file mode 100644 index 0000000..c85571c --- /dev/null +++ b/arch/arm/mach-at91/include/mach/sama5d2.h @@ -0,0 +1,203 @@ +/* + * Chip-specific header file for the SAMA5D2 SoC + * + * Copyright (C) 2015 Atmel + * Wenyou Yang <wenyou.yang(a)atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SAMA5D2_H +#define __SAMA5D2_H + +/* + * definitions to be used in other places + */ +#define CONFIG_AT91FAMILY /* It's a member of AT91 */ + +/* + * Peripheral identifiers/interrupts. + */ +#define ATMEL_ID_FIQ 0 /* FIQ Interrupt ID */ +/* 1 */ +#define ATMEL_ID_ARM 2 /* Performance Monitor Unit */ +#define ATMEL_ID_PIT 3 /* Periodic Interval Timer Interrupt */ +#define ATMEL_ID_WDT 4 /* Watchdog Timer Interrupt */ +#define ATMEL_ID_GMAC 5 /* Ethernet MAC */ +#define ATMEL_ID_XDMAC0 6 /* DMA Controller 0 */ +#define ATMEL_ID_XDMAC1 7 /* DMA Controller 1 */ +#define ATMEL_ID_ICM 8 /* Integrity Check Monitor */ +#define ATMEL_ID_AES 9 /* Advanced Encryption Standard */ +#define ATMEL_ID_AESB 10 /* AES bridge */ +#define ATMEL_ID_TDES 11 /* Triple Data Encryption Standard */ +#define ATMEL_ID_SHA 12 /* SHA Signature */ +#define ATMEL_ID_MPDDRC 13 /* MPDDR Controller */ +#define ATMEL_ID_MATRIX1 14 /* H32MX, 32-bit AHB Matrix */ +#define ATMEL_ID_MATRIX0 15 /* H64MX, 64-bit AHB Matrix */ +#define ATMEL_ID_SECUMOD 16 /* Secure Module */ +#define ATMEL_ID_HSMC 17 /* Multi-bit ECC interrupt */ +#define ATMEL_ID_PIOA 18 /* Parallel I/O Controller A */ +#define ATMEL_ID_FLEXCOM0 19 /* FLEXCOM0 */ +#define ATMEL_ID_FLEXCOM1 20 /* FLEXCOM1 */ +#define ATMEL_ID_FLEXCOM2 21 /* FLEXCOM2 */ +#define ATMEL_ID_FLEXCOM3 22 /* FLEXCOM3 */ +#define ATMEL_ID_FLEXCOM4 23 /* FLEXCOM4 */ +#define ATMEL_ID_UART0 24 /* UART0 */ +#define ATMEL_ID_UART1 25 /* UART1 */ +#define ATMEL_ID_UART2 26 /* UART2 */ +#define ATMEL_ID_UART3 27 /* UART3 */ +#define ATMEL_ID_UART4 28 /* UART4 */ +#define ATMEL_ID_TWIHS0 29 /* Two-wire Interface 0 */ +#define ATMEL_ID_TWIHS1 30 /* Two-wire Interface 1 */ +#define ATMEL_ID_SDMMC0 31 /* Secure Data Memory Card Controller 0 */ +#define ATMEL_ID_SDMMC1 32 /* Secure Data Memory Card Controller 1 */ +#define ATMEL_ID_SPI0 33 /* Serial Peripheral Interface 0 */ +#define ATMEL_ID_SPI1 34 /* Serial Peripheral Interface 1 */ +#define ATMEL_ID_TC0 35 /* Timer Counter 0 (ch.0,1,2) */ +#define ATMEL_ID_TC1 36 /* Timer Counter 1 (ch.3,4,5) */ +/* 37 */ +#define ATMEL_ID_PWM 38 /* PWMController0 (ch. 0,1,2,3) */ +/* 39 */ +#define ATMEL_ID_ADC 40 /* Touch Screen ADC Controller */ +#define ATMEL_ID_UHPHS 41 /* USB Host High Speed */ +#define ATMEL_ID_UDPHS 42 /* USB Device High Speed */ +#define ATMEL_ID_SSC0 43 /* Serial Synchronous Controller 0 */ +#define ATMEL_ID_SSC1 44 /* Serial Synchronous Controller 1 */ +#define ATMEL_ID_LCDC 45 /* LCD Controller */ +#define ATMEL_ID_ISI 46 /* Image Sensor Controller, for A5D2, named after ISC */ +#define ATMEL_ID_TRNG 47 /* True Random Number Generator */ +#define ATMEL_ID_PDMIC 48 /* PDM Interface Controller */ +#define ATMEL_ID_AIC_IRQ 49 /* IRQ Interrupt ID */ +#define ATMEL_ID_SFC 50 /* Fuse Controller */ +#define ATMEL_ID_SECURAM 51 /* Secure RAM */ +#define ATMEL_ID_QSPI0 52 /* QSPI0 */ +#define ATMEL_ID_QSPI1 53 /* QSPI1 */ +#define ATMEL_ID_I2SC0 54 /* Inter-IC Sound Controller 0 */ +#define ATMEL_ID_I2SC1 55 /* Inter-IC Sound Controller 1 */ +#define ATMEL_ID_CAN0_INT0 56 /* MCAN 0 Interrupt0 */ +#define ATMEL_ID_CAN1_INT0 57 /* MCAN 1 Interrupt0 */ +/* 58 */ +#define ATMEL_ID_CLASSD 59 /* Audio Class D Amplifier */ +#define ATMEL_ID_SFR 60 /* Special Function Register */ +#define ATMEL_ID_SAIC 61 /* Secured AIC */ +#define ATMEL_ID_AIC 62 /* Advanced Interrupt Controller */ +#define ATMEL_ID_L2CC 63 /* L2 Cache Controller */ +#define ATMEL_ID_CAN0_INT1 64 /* MCAN 0 Interrupt1 */ +#define ATMEL_ID_CAN1_INT1 65 /* MCAN 1 Interrupt1 */ +#define ATMEL_ID_GMAC_Q1 66 /* GMAC Queue 1 Interrupt */ +#define ATMEL_ID_GMAC_Q2 67 /* GMAC Queue 2 Interrupt */ +#define ATMEL_ID_PIOB 68 /* Parallel I/O Controller B */ +#define ATMEL_ID_PIOC 69 /* Parallel I/O Controller C */ +#define ATMEL_ID_PIOD 70 /* Parallel I/O Controller D */ +#define ATMEL_ID_SDMMC0_TIMER 71 /* Secure Data Memory Card Controller 0 (TIMER) */ +#define ATMEL_ID_SDMMC1_TIMER 72 /* Secure Data Memory Card Controller 1 (TIMER) */ +/* 73 */ +#define ATMEL_ID_SYS 74 /* System Controller Interrupt */ +#define ATMEL_ID_ACC 75 /* Analog Comparator */ +#define ATMEL_ID_RXLP 76 /* UART Low-Power */ +#define ATMEL_ID_SFRBU 77 /* Special Function Register BackUp */ +#define ATMEL_ID_CHIPID 78 /* Chip ID */ + +/* + * User Peripherals physical base addresses. + */ +#define ATMEL_BASE_LCDC 0xf0000000 +#define ATMEL_BASE_XDMAC1 0xf0004000 +#define ATMEL_BASE_MPDDRC 0xf000c000 +#define ATMEL_BASE_XDMAC0 0xf0010000 +#define ATMEL_BASE_PMC 0xf0014000 +#define ATMEL_BASE_QSPI0 0xf0020000 +#define ATMEL_BASE_QSPI1 0xf0024000 +#define ATMEL_BASE_SPI0 0xf8000000 +#define ATMEL_BASE_GMAC 0xf8008000 +#define ATMEL_BASE_TC0 0xf800c000 +#define ATMEL_BASE_TC1 0xf8010000 +#define ATMEL_BASE_HSMC 0xf8014000 +#define ATMEL_BASE_UART0 0xf801c000 +#define ATMEL_BASE_UART1 0xf8020000 +#define ATMEL_BASE_UART2 0xf8024000 +#define ATMEL_BASE_TWI0 0xf8028000 +#define ATMEL_BASE_SYSC 0xf8048000 +#define ATMEL_BASE_SPI1 0xfc000000 +#define ATMEL_BASE_UART3 0xfc008000 +#define ATMEL_BASE_UART4 0xfc00c000 +#define ATMEL_BASE_TWI1 0xfc028000 +#define ATMEL_BASE_UDPHS 0xfc02c000 + +#define ATMEL_BASE_PIOA 0xfc038000 + +#define ATMEL_CHIPID_CIDR 0xfc069000 +#define ATMEL_CHIPID_EXID 0xfc069004 + +/* + * Address Memory Space + */ +#define ATMEL_BASE_DDRCS 0x20000000 +#define ATMEL_BASE_QSPI0_AES_MEM 0x90000000 +#define ATMEL_BASE_QSPI1_AES_MEM 0x98000000 +#define ATMEL_BASE_SDMMC0 0xa0000000 +#define ATMEL_BASE_SDMMC1 0xb0000000 +#define ATMEL_BASE_QSPI0_MEM 0xd0000000 +#define ATMEL_BASE_QSPI1_MEM 0xd8000000 + +/* + * Internal Memories + */ +#define ATMEL_BASE_UDPHS_FIFO 0x00300000 /* USB Device HS controller */ +#define ATMEL_BASE_OHCI 0x00400000 /* USB Host controller (OHCI) */ +#define ATMEL_BASE_EHCI 0x00500000 /* USB Host controller (EHCI) */ + +/* + * SYSC Spawns + */ +#define ATMEL_BASE_RSTC ATMEL_BASE_SYSC +#define ATMEL_BASE_SHDWC (ATMEL_BASE_SYSC + 0x10) +#define ATMEL_BASE_PIT (ATMEL_BASE_SYSC + 0x30) +#define ATMEL_BASE_WDT (ATMEL_BASE_SYSC + 0x40) +#define ATMEL_BASE_SCKC (ATMEL_BASE_SYSC + 0x50) +#define ATMEL_BASE_RTC (ATMEL_BASE_SYSC + 0xb0) + +/* + * Other misc definitions + */ +#define ATMEL_BASE_PMECC (ATMEL_BASE_HSMC + 0x70) +#define ATMEL_BASE_PMERRLOC (ATMEL_BASE_HSMC + 0x500) + +#define ATMEL_BASE_PIOB (ATMEL_BASE_PIOA + 0x40) +#define ATMEL_BASE_PIOC (ATMEL_BASE_PIOB + 0x40) +#define ATMEL_BASE_PIOD (ATMEL_BASE_PIOC + 0x40) + +#define ATMEL_PIO_PORTS 4 +#define CPU_HAS_PCR +#define CPU_HAS_H32MXDIV + +/* SAMA5D2 series chip id definitions */ +#define ARCH_ID_SAMA5D2 0x8a5c08c0 +#define ARCH_EXID_SAMA5D21CU 0x0000005a +#define ARCH_EXID_SAMA5D22CU 0x00000059 +#define ARCH_EXID_SAMA5D22CN 0x00000069 +#define ARCH_EXID_SAMA5D23CU 0x00000058 +#define ARCH_EXID_SAMA5D24CX 0x00000004 +#define ARCH_EXID_SAMA5D24CU 0x00000014 +#define ARCH_EXID_SAMA5D26CU 0x00000012 +#define ARCH_EXID_SAMA5D27CU 0x00000011 +#define ARCH_EXID_SAMA5D27CN 0x00000021 +#define ARCH_EXID_SAMA5D28CU 0x00000010 +#define ARCH_EXID_SAMA5D28CN 0x00000020 + +#define cpu_is_sama5d2() (get_chip_id() == ARCH_ID_SAMA5D2) + +/* PIT Timer(PIT_PIIR) */ +#define CONFIG_SYS_TIMER_COUNTER 0xf804803c + +/* No PMECC Galois table in ROM */ +#define NO_GALOIS_TABLE_IN_ROM + +#ifndef __ASSEMBLY__ +unsigned int get_chip_id(void); +unsigned int get_extension_chip_id(void); +unsigned int has_lcdc(void); +char *get_cpu_name(void); +#endif + +#endif diff --git a/board/atmel/sama5d2_xplained/Kconfig b/board/atmel/sama5d2_xplained/Kconfig new file mode 100644 index 0000000..55712e9 --- /dev/null +++ b/board/atmel/sama5d2_xplained/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAMA5D2_XPLAINED + +config SYS_BOARD + default "sama5d2_xplained" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sama5d2_xplained" + +endif diff --git a/board/atmel/sama5d2_xplained/MAINTAINERS b/board/atmel/sama5d2_xplained/MAINTAINERS new file mode 100644 index 0000000..ff9c86f --- /dev/null +++ b/board/atmel/sama5d2_xplained/MAINTAINERS @@ -0,0 +1,7 @@ +SAMA5D2 XPLAINED BOARD +M: Wenyou Yang <wenyou.yang(a)atmel.com> +S: Maintained +F: board/atmel/sama5d2_xplained/ +F: include/configs/sama5d2_xplained.h +F: configs/sama5d2_xplained_mmc_defconfig +F: configs/sama5d2_xplained_spiflash_defconfig diff --git a/board/atmel/sama5d2_xplained/Makefile b/board/atmel/sama5d2_xplained/Makefile new file mode 100644 index 0000000..420870b --- /dev/null +++ b/board/atmel/sama5d2_xplained/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2015 Atmel Corporation +# Wenyou Yang <wenyou.yang(a)atmel.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += sama5d2_xplained.o diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c new file mode 100644 index 0000000..929a210 --- /dev/null +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -0,0 +1,284 @@ +/* + * Copyright (C) 2015 Atmel Corporation + * Wenyou.Yang <wenyou.yang(a)atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <atmel_hlcdc.h> +#include <lcd.h> +#include <mmc.h> +#include <net.h> +#include <netdev.h> +#include <spi.h> +#include <version.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/atmel_pio4.h> +#include <asm/arch/atmel_usba_udc.h> +#include <asm/arch/atmel_sdhci.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/sama5d2.h> + +DECLARE_GLOBAL_DATA_PTR; + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 0); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1); +} + +static void board_spi0_hw_init(void) +{ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 14, 0); + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 15, 0); + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 16, 0); + + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1); + + at91_periph_clk_enable(ATMEL_ID_SPI0); +} + +static void board_usb_hw_init(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 1); +} + +#ifdef CONFIG_LCD +vidinfo_t panel_info = { + .vl_col = 480, + .vl_row = 272, + .vl_clk = 9000000, + .vl_bpix = LCD_BPP, + .vl_tft = 1, + .vl_hsync_len = 41, + .vl_left_margin = 2, + .vl_right_margin = 2, + .vl_vsync_len = 11, + .vl_upper_margin = 2, + .vl_lower_margin = 2, + .mmio = ATMEL_BASE_LCDC, +}; + +/* No power up/down pin for the LCD pannel */ +void lcd_enable(void) { /* Empty! */ } +void lcd_disable(void) { /* Empty! */ } + +unsigned int has_lcdc(void) +{ + return 1; +} + +static void board_lcd_hw_init(void) +{ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDPWM */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDISP */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDVSYNC */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 31, 0); /* LCDHSYNC */ + atmel_pio4_set_a_periph(AT91_PIO_PORTD, 0, 0); /* LCDPCK */ + atmel_pio4_set_a_periph(AT91_PIO_PORTD, 1, 0); /* LCDDEN */ + + /* LCDDAT0 */ + /* LCDDAT1 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDDAT2 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDDAT3 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDDAT4 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDDAT5 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDDAT6 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDDAT7 */ + + /* LCDDAT8 */ + /* LCDDAT9 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDDAT10 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDDAT11 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDDAT12 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDDAT13 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDDAT14 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDDAT15 */ + + /* LCDD16 */ + /* LCDD17 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDDAT18 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDDAT19 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDAT20 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 25, 0); /* LCDDAT21 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDDAT22 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDDAT23 */ + + at91_periph_clk_enable(ATMEL_ID_LCDC); +} + +#ifdef CONFIG_LCD_INFO +void lcd_show_board_info(void) +{ + ulong dram_size; + int i; + char temp[32]; + + lcd_printf("%s\n", U_BOOT_VERSION); + lcd_printf("2015 ATMEL Corp\n"); + lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), + strmhz(temp, get_cpu_clk_rate())); + + dram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + dram_size += gd->bd->bi_dram[i].size; + + lcd_printf("%ld MB SDRAM\n", dram_size >> 20); +} +#endif /* CONFIG_LCD_INFO */ +#endif /* CONFIG_LCD */ + +static void board_gmac_hw_init(void) +{ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 14, 0); /* GTXCK */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 15, 0); /* GTXEN */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 16, 0); /* GRXDV */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 17, 0); /* GRXER */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 18, 0); /* GRX0 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 19, 0); /* GRX1 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 20, 0); /* GTX0 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 21, 0); /* GTX1 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 22, 0); /* GMDC */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 23, 0); /* GMDIO */ + + at91_periph_clk_enable(ATMEL_ID_GMAC); +} + +static void board_sdhci0_hw_init(void) +{ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0); /* SDMMC0_CK */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0); /* SDMMC0_CMD */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0); /* SDMMC0_DAT0 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0); /* SDMMC0_DAT1 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0); /* SDMMC0_DAT2 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0); /* SDMMC0_DAT3 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 6, 0); /* SDMMC0_DAT4 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 7, 0); /* SDMMC0_DAT5 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 8, 0); /* SDMMC0_DAT6 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 9, 0); /* SDMMC0_DAT7 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 10, 0); /* SDMMC0_RSTN */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SDMMC0_VDDSEL */ + + at91_periph_clk_enable(ATMEL_ID_SDMMC0); + at91_enable_periph_generated_clk(ATMEL_ID_SDMMC0, + GCK_CSS_PLLA_CLK, 1); + +} + +static void board_sdhci1_hw_init(void) +{ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 18, 0); /* SDMMC1_DAT0 */ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 19, 0); /* SDMMC1_DAT1 */ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 20, 0); /* SDMMC1_DAT2 */ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 21, 0); /* SDMMC1_DAT3 */ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 22, 0); /* SDMMC1_CK */ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 27, 0); /* SDMMC1_RSTN */ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 28, 0); /* SDMMC1_CMD */ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 30, 0); /* SDMMC1_CD */ + + at91_periph_clk_enable(ATMEL_ID_SDMMC1); + at91_enable_periph_generated_clk(ATMEL_ID_SDMMC1, + GCK_CSS_PLLA_CLK, 1); +} + +int board_mmc_init(bd_t *bis) +{ +#ifdef CONFIG_ATMEL_SDHCI0 + atmel_sdhci_init((void *)ATMEL_BASE_SDMMC0, ATMEL_ID_SDMMC0); +#endif +#ifdef CONFIG_ATMEL_SDHCI1 + atmel_sdhci_init((void *)ATMEL_BASE_SDMMC1, ATMEL_ID_SDMMC1); +#endif + + return 0; +} + +static void board_uart1_hw_init(void) +{ + atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, 1); /* URXD1 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0); /* UTXD1 */ + + at91_periph_clk_enable(ATMEL_ID_UART1); +} + +int board_early_init_f(void) +{ + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); + at91_periph_clk_enable(ATMEL_ID_PIOD); + + board_uart1_hw_init(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_ATMEL_SPI + board_spi0_hw_init(); +#endif +#ifdef CONFIG_ATMEL_SDHCI +#ifdef CONFIG_ATMEL_SDHCI0 + board_sdhci0_hw_init(); +#endif +#ifdef CONFIG_ATMEL_SDHCI1 + board_sdhci1_hw_init(); +#endif +#endif +#ifdef CONFIG_MACB + board_gmac_hw_init(); +#endif +#ifdef CONFIG_LCD + board_lcd_hw_init(); +#endif +#ifdef CONFIG_CMD_USB + board_usb_hw_init(); +#endif +#ifdef CONFIG_USB_GADGET_ATMEL_USBA + at91_udp_hw_init(); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; + +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00); +#endif + +#ifdef CONFIG_USB_GADGET_ATMEL_USBA + usba_udc_probe(&pdata); +#ifdef CONFIG_USB_ETH_RNDIS + usb_eth_initialize(bis); +#endif +#endif + + return rc; +} diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig new file mode 100644 index 0000000..c1dcbef --- /dev/null +++ b/configs/sama5d2_xplained_mmc_defconfig @@ -0,0 +1,11 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TARGET_SAMA5D2_XPLAINED=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC" +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_SF=y +# CONFIG_CMD_FPGA is not set +CONFIG_SPI_FLASH=y diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig new file mode 100644 index 0000000..0271e8e --- /dev/null +++ b/configs/sama5d2_xplained_spiflash_defconfig @@ -0,0 +1,11 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TARGET_SAMA5D2_XPLAINED=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH" +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_SF=y +# CONFIG_CMD_FPGA is not set +CONFIG_SPI_FLASH=y diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h new file mode 100644 index 0000000..ae5ba3d --- /dev/null +++ b/include/configs/sama5d2_xplained.h @@ -0,0 +1,122 @@ +/* + * Configuration file for the SAMA5D2 Xplained Board. + * + * Copyright (C) 2015 Atmel Corporation + * Wenyou Yang <wenyou.yang(a)atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* No NOR flash, this definition should put before common header */ +#define CONFIG_SYS_NO_FLASH + +#include "at91-sama5_common.h" + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_UART1 +#define CONFIG_USART_ID ATMEL_ID_UART1 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#undef CONFIG_AT91_GPIO +#define CONFIG_ATMEL_PIO4 + +/* SerialFlash */ +#ifdef CONFIG_CMD_SF +#define CONFIG_ATMEL_SPI +#define CONFIG_ATMEL_SPI0 +#define CONFIG_SPI_FLASH_ATMEL +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#endif + +/* NAND flash */ +#undef CONFIG_CMD_NAND + +/* MMC */ +#define CONFIG_CMD_MMC + +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_SDHCI +#define CONFIG_ATMEL_SDHCI +#define CONFIG_ATMEL_SDHCI0 +#define CONFIG_ATMEL_SDHCI1 +#define CONFIG_SUPPORT_EMMC_BOOT +#endif + +/* USB */ +#define CONFIG_CMD_USB + +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_STORAGE +#endif + +/* USB device */ +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_ATMEL_USBA +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_RNDIS +#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D2 XPlained" + +#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Ethernet Hardware */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB_SEARCH_PHY + +/* LCD */ +/* #define CONFIG_LCD */ + +#ifdef CONFIG_LCD +#define LCD_BPP LCD_COLOR16 +#define LCD_OUTPUT_BPP 24 +#define CONFIG_LCD_LOGO +#define CONFIG_LCD_INFO +#define CONFIG_LCD_INFO_BELOW_LOGO +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_ATMEL_HLCD +#define CONFIG_ATMEL_LCD_RGB565 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#endif + +#ifdef CONFIG_SYS_USE_MMC + +/* bootstrap + u-boot + env in sd card */ +#undef FAT_ENV_DEVICE_AND_PART +#undef CONFIG_BOOTCOMMAND + +#define FAT_ENV_DEVICE_AND_PART "1" +#define CONFIG_BOOTCOMMAND "fatload mmc 1:1 0x21000000 at91-sama5d2_xplained.dtb; " \ + "fatload mmc 1:1 0x22000000 zImage; " \ + "bootz 0x22000000 - 0x21000000" +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk root=/dev/mmcblk1p2 rw rootwait" + +#endif + +#endif -- 1.7.9.5

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[U-Boot] [PATCH] arm: ls1021a: Ensure Generic Timer disabled before jumping into the OS
by Alison Wang 30 Nov '15

30 Nov '15

This patch addresses a problem mentioned recently on this mailing list: [1]. In that posting a LS1021 based system was locking up at about 5 minutes after boot,but the problem was mysteriously related to the toolchain used for building u-boot.Debugging the problem reveals a stuck interrupt 29 on the GIC. It appears Freescale's LS1021 support in u-boot erroneously sets the 64-bit ARM generic PL1 physical time CompareValue register to all-ones with a 32-bit value.This causes the timer compare to fire 344 seconds after u-boot configures it.Depending on how fast u-boot gets the kernel booted,this amounts to about 5-minutes of Linux uptime before locking up. Apparently the bug is masked by some toolchains. Perhaps this is explained by default compiler options, word sizes, or binutils versions. To fix the above issue, the generic physical timer is disabled before jumping to the OS. [1] https://lists.yoctoproject.org/pipermail/meta-freescale/2015-June/014400.ht… Signed-off-by: Chris Kilgour <techie(a)whiterocker.com> Signed-off-by: Alison Wang <alison.wang(a)freescale.com> --- arch/arm/cpu/armv7/ls102xa/cpu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index 75f0d8c..298422f 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -346,3 +346,13 @@ void smp_kick_all_cpus(void) out_be32(&gur->brrl, 0x2); } #endif + +void arch_preboot_os(void) +{ + unsigned long ctrl; + + /* Disable PL1 Physical Timer */ + asm("mrc p15, 0, %0, c14, c2, 1" : "=r" (ctrl)); + ctrl &= ~ARCH_TIMER_CTRL_ENABLE; + asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl)); +} -- 2.1.0.27.g96db324

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