October 2015 - U-Boot

[U-Boot] [PATCH V6] sf: Turn SPI flash chip into 3-Byte address mode
by Zhiqiang Hou 27 Jan '16

27 Jan '16

From: Hou Zhiqiang <B48286(a)freescale.com> For more than 16MiB SPI flash chips, there are 3-Byte and 4-Byte address mode, and only the 3-Byte address mode is supported in U-Boot so far. So, reset the SPI flash to 3-Byte address mode in probe to ensure the SPI flash work correctly, because it may has been set to 4-Byte address mode after warm boot. Signed-off-by: Hou Zhiqiang <B48286(a)freescale.com> --- Tested on T1042RDB board. V6: Add the spi_release_bus. V5: 1. Removed #ifdef for STMICRO. 2. Add support for Spansion chips (>16MiB) switch to 3-Byte address mode. V4: Split the the patch to 2 patches for clear FSR and SPI flash address mode. V3: Generate the patch based on the latest tree git://git.denx.de/u-boot.git. V2: Add the operation of enter 3 Byte address mode in probe. V1: Based on git://git.denx.de/u-boot.git. drivers/mtd/spi/sf_internal.h | 7 +++++++ drivers/mtd/spi/sf_ops.c | 40 ++++++++++++++++++++++++++++++++++++++++ drivers/mtd/spi/sf_probe.c | 10 ++++++++++ 3 files changed, 57 insertions(+) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 1de1dac..9519bd8 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -75,6 +75,10 @@ enum { #define CMD_FLAG_STATUS 0x70 #define CMD_CLEAR_FLAG_STATUS 0x50 +/* Used for Micron, Macronix and Winbond flashes */ +#define CMD_ENTER_4B_ADDR 0xB7 +#define CMD_EXIT_4B_ADDR 0xE9 + /* Read commands */ #define CMD_READ_ARRAY_SLOW 0x03 #define CMD_READ_ARRAY_FAST 0x0b @@ -231,6 +235,9 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, size_t len, void *data); +int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash, + int enable, u8 idcode0); + #ifdef CONFIG_SPI_FLASH_MTD int spi_flash_mtd_register(struct spi_flash *flash); void spi_flash_mtd_unregister(void); diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index deebcab..de30c55 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -93,6 +93,46 @@ int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc) } #endif +int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash, + int enable, u8 idcode0) +{ + int ret; + u8 cmd, bar; + bool need_wren = false; + + ret = spi_claim_bus(flash->spi); + if (ret) { + debug("SF: unable to claim SPI bus\n"); + return ret; + } + + switch (idcode0) { + case SPI_FLASH_CFI_MFR_STMICRO: + /* Some Micron need WREN command; all will accept it */ + need_wren = true; + case SPI_FLASH_CFI_MFR_MACRONIX: + case SPI_FLASH_CFI_MFR_WINBOND: + if (need_wren) + spi_flash_cmd_write_enable(flash); + + cmd = enable ? CMD_ENTER_4B_ADDR : CMD_EXIT_4B_ADDR; + ret = spi_flash_cmd(flash->spi, cmd, NULL, 0); + if (need_wren) + spi_flash_cmd_write_disable(flash); + + break; + default: + /* Spansion style */ + bar = enable << 7; + cmd = CMD_BANKADDR_BRWR; + ret = spi_flash_cmd_write(flash->spi, &cmd, 1, &bar, 1); + } + + spi_release_bus(flash->spi); + + return ret; +} + #ifdef CONFIG_SPI_FLASH_BAR static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel) { diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index e0283dc..3b204f8 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -170,6 +170,16 @@ static int spi_flash_validate_params(struct spi_slave *spi, u8 *idcode, flash->page_size <<= flash->shift; flash->sector_size = params->sector_size << flash->shift; flash->size = flash->sector_size * params->nr_sectors << flash->shift; + + /* + * So far, the 4-byte address mode haven't been supported in U-Boot, + * and make sure the chip (> 16MiB) in default 3-byte address mode, + * in case of warm bootup, the chip was set to 4-byte mode in kernel. + */ + if (flash->size > SPI_FLASH_16MB_BOUN) { + if (spi_flash_cmd_4B_addr_switch(flash, false, idcode[0]) < 0) + debug("SF: enter 3B address mode failed\n"); + } #ifdef CONFIG_SF_DUAL_FLASH if (flash->dual_flash & SF_DUAL_STACKED_FLASH) flash->size <<= 1; -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] arm: cache: Implement cache range check for v7
by Marek Vasut 25 Jan '16

25 Jan '16

Add code to aid tracking down cache alignment issues. In case DEBUG is defined in the cache.c, this code will check alignment of each attempt to flush/invalidate data cache and print a warning if the alignment is incorrect. If DEBUG is not defined, this code is optimized out. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> Cc: Tom Rini <trini(a)konsulko.com> --- arch/arm/cpu/armv7/cache_v7.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index e8ee875..84431bb 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -16,6 +16,23 @@ #define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4 #ifndef CONFIG_SYS_DCACHE_OFF +static int check_cache_range(unsigned long start, unsigned long stop) +{ + int ok = 1; + + if (start & (CONFIG_SYS_CACHELINE_SIZE - 1)) + ok = 0; + + if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) + ok = 0; + + if (!ok) + debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n", + start, stop); + + return ok; +} + /* * Write the level and type you want to Cache Size Selection Register(CSSELR) * to get size details from Current Cache Size ID Register(CCSIDR) @@ -257,6 +274,8 @@ void flush_dcache_all(void) */ void invalidate_dcache_range(unsigned long start, unsigned long stop) { + check_cache_range(start, stop); + v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE); v7_outer_cache_inval_range(start, stop); @@ -269,6 +288,8 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop) */ void flush_dcache_range(unsigned long start, unsigned long stop) { + check_cache_range(start, stop); + v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE); v7_outer_cache_flush_range(start, stop); -- 2.1.4

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[U-Boot] [RESEND PATCH v2 0/2] This series adds an ability to use pl01x for early debug output.
by Sergey Temerkhanov 19 Jan '16

19 Jan '16

This is the version 2 of the patch I posted at http://lists.denx.de/pipermail/u-boot/2015-September/227210.html Changes in v2: - Broke down into 2 patches - Minor changes to accomodate Kconfig options - Broke down into 2 patches - Made CONFIG_DEBUG_UART_PL010 and CONFIG_DEBUG_UART_PL011 separate options - Typo fixes Sergey Temerkhanov (2): arm: serial: Add debug UART capability to the pl01x driver arm: serial: Add Kconfig entries to facilitate usage of the pl01x driver for early debug output drivers/serial/Kconfig | 22 ++++++++++++++++++++++ drivers/serial/serial_pl01x.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) -- 2.1.4

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[U-Boot] [PATCH 0/4 v4] arm: socfpga: Add Cadence QSPI support
by Stefan Roese 14 Jan '16

14 Jan '16

Hi! So this is my 4th posting regarding the Candence SPI driver on SoCFPGA. Again, SPI NOR flash is working. At least on SoCrates and on another custom SoCFPGA based board. The main change in this version is, that the Cadence driver now is a driver model (DM) based driver. And this needs the DT support which I posted just before. One of the reasons to enable DT support in SoCFPGA is, that I need to support multiple different SPI controllers for this platform. This is the QSPI Cadence controller and the Designware SPI master controller. Both are implemented in the SoCFPGA. And enabling both controllers is only possible by using the new driver model (DM). The DM SPI code only supports DT based probing. So it was easier to move SoCFPGA to DT than to add the (deprecated) platform-data based probing to the DM SPI suport. Note that I have patches to support the Designware SPI master controller also via DM in the queue. I'll post them shortly. Thanks, Stefan Cc: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)altera.com> Cc: Vince Bridgers <vbridger(a)altera.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Pavel Machek <pavel(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki(a)gmail.com>

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[U-Boot] 2TB disks
by Stefan Monnier 13 Jan '16

13 Jan '16

I just bumped into a problem where U-Boot refused to boot from my disk's second partition because the sector number is "negative". More specifically, my disk drive is 2TB, which means that the number of 512B blocks fits into an unsigned 32bit int but not into a signed 32bit int. U-boot's "scsi part" displays the size (in blocks) correctly, but the size of the first partition (which is around 1.8TB) is printed as a negative number, and so is the start sector of the second partition. This was tested on a BananaPi using v2015-07. Stefan

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[U-Boot] [PATCH] fdt: fix address cell count checking in fdt_translate_address()
by Przemyslaw Marczak 12 Jan '16

12 Jan '16

Commit: dm: core: Enable optional use of fdt_translate_address() Enables use of this function as default, but after this it's not possible to get dev address for the case in which: '#size-cells == 0' This causes errors when getting address for some GPIOs, for which the '#size-cells' is set to 0. Example error: '__of_translate_address: Bad cell count for gpx0' Allowing for that case by modifying the macro 'OF_CHECK_COUNTS', (called from )__of_translate_address(), fixes the issue. Now, this macro doesn't check, that '#size-cells' is greater than 0. This is possible from the specification point of view, but I'm not sure that it doesn't introduce a regression for other configs. Please test and share the results. Tested-on: Odroid U3, Odroid X2, Odroid XU3, Sandbox. Signed-off-by: Przemyslaw Marczak <p.marczak(a)samsung.com> Cc: Masahiro Yamada <yamada.masahiro(a)socionext.com> Cc: Lukasz Majewski <l.majewski(a)samsung.com> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> Cc: Stefan Roese <sr(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> Cc: Bin Meng <bmeng.cn(a)gmail.com> Cc: Marek Vasut <marex(a)denx.de> --- common/fdt_support.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/common/fdt_support.c b/common/fdt_support.c index f86365e..5f808cc 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -946,8 +946,7 @@ void fdt_del_node_and_alias(void *blob, const char *alias) /* Max address size we deal with */ #define OF_MAX_ADDR_CELLS 4 #define OF_BAD_ADDR ((u64)-1) -#define OF_CHECK_COUNTS(na, ns) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS && \ - (ns) > 0) +#define OF_CHECK_COUNTS(na) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS) /* Debug utility */ #ifdef DEBUG @@ -1115,7 +1114,7 @@ static u64 __of_translate_address(void *blob, int node_offset, const fdt32_t *in /* Cound address cells & copy address locally */ bus->count_cells(blob, parent, &na, &ns); - if (!OF_CHECK_COUNTS(na, ns)) { + if (!OF_CHECK_COUNTS(na)) { printf("%s: Bad cell count for %s\n", __FUNCTION__, fdt_get_name(blob, node_offset, NULL)); goto bail; @@ -1142,7 +1141,7 @@ static u64 __of_translate_address(void *blob, int node_offset, const fdt32_t *in /* Get new parent bus and counts */ pbus = &of_busses[0]; pbus->count_cells(blob, parent, &pna, &pns); - if (!OF_CHECK_COUNTS(pna, pns)) { + if (!OF_CHECK_COUNTS(pna)) { printf("%s: Bad cell count for %s\n", __FUNCTION__, fdt_get_name(blob, node_offset, NULL)); break; -- 1.9.1

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[U-Boot] [PATCH 1/3] usb: host: ehci-vf: Remove hardcoded USB host client configuration
by Sanchayan Maity 08 Jan '16

08 Jan '16

The current ehci-vf USB driver for Vybrid hardcodes the USB host and client functionality. Remove this. Reported-by: Santhosh Kumar Janardhanam <santhosh.kj(a)hcl.com> Signed-off-by: Sanchayan Maity <maitysanchayan(a)gmail.com> --- drivers/usb/host/ehci-vf.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/usb/host/ehci-vf.c b/drivers/usb/host/ehci-vf.c index 98e0fc6..351e0fb 100644 --- a/drivers/usb/host/ehci-vf.c +++ b/drivers/usb/host/ehci-vf.c @@ -134,11 +134,6 @@ int ehci_hcd_init(int index, enum usb_init_type init, if (index >= ARRAY_SIZE(nc_reg_bases)) return -EINVAL; - if (init == USB_INIT_DEVICE && index == 1) - return -ENODEV; - if (init == USB_INIT_HOST && index == 0) - return -ENODEV; - ehci = (struct usb_ehci *)nc_reg_bases[index]; /* Do board specific initialisation */ -- 2.6.2

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[U-Boot] [PATCH 00/10] Add support for Rockchip RK3288 Ethernet
by Sjoerd Simons 08 Jan '16

08 Jan '16

This series adds support for the GMAC Ethernet interface on RK3288 SoCs. To add support I've taken a slightly different approach then some of the other boards with a designware IP block, by creating a new driver to take care of the platfrom glue which subclasses the main designware driver instead of adding the compatibility string the designware driver directly and doing the SoC specific setup in the board files. This seems quite a bit more elegant in a device model based world. As the pinctrl and clock drivers are quite simple at the moment (hardcoded settings rather then retrieved from device-tree) the pinctrl and clock settings added in this series assume the setup for the ethernet interface used is for Firefly and Radxa Rock 2. Specifically It assumes the gmac is driven by an external clock, GPIO4B0 is the phy reset and the phy interface mode is RGMII. I've only tested this series on a Radxa Rock 2 board, it would be great if someone could test this on other boards with the designware IP especially for those with the reset GPIO in devicetree (e.g. some of the Allwinner boards). Sjoerd Simons (10): rockchip: rk3288: Add pinctrl support for the gmac ethernet interface rockchip: rk3288: Add clock support for the gmac ethernet interface net: designware: support phy reset device-tree bindings net: designware: Export various functions/struct to allow subclassing net: designware: Add a post-started hook net: gmac_rk3288: Add RK3288 GMAC driver rockchip: rk3288-firefly: Add gmac definition rockchip: firefly: Enable networking support rockchip: Add PXE and DHCP to the default boot targets rockchip: Drop Ethernet from the TODO arch/arm/dts/rk3288-firefly.dtsi | 16 ++ arch/arm/include/asm/arch-rockchip/cru_rk3288.h | 17 ++ arch/arm/include/asm/arch-rockchip/grf_rk3288.h | 228 ++++++++++++++++++++++++ arch/arm/include/asm/arch-rockchip/periph.h | 1 + configs/firefly-rk3288_defconfig | 5 + doc/README.rockchip | 1 - drivers/clk/clk_rk3288.c | 16 ++ drivers/net/Kconfig | 7 + drivers/net/Makefile | 1 + drivers/net/designware.c | 91 ++++++++-- drivers/net/designware.h | 19 ++ drivers/net/gmac_rk3288.c | 140 +++++++++++++++ drivers/pinctrl/rockchip/pinctrl_rk3288.c | 102 +++++++++++ include/configs/firefly-rk3288.h | 3 + include/configs/rk3288_common.h | 4 +- 15 files changed, 639 insertions(+), 12 deletions(-) create mode 100644 drivers/net/gmac_rk3288.c -- 2.5.3

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[U-Boot] [PATCH] cmd_pci: Check for VendorID earlier
by Fabio Estevam 06 Jan '16

06 Jan '16

From: Fabio Estevam <fabio.estevam(a)freescale.com> Since commit ff3e077bd2 ("dm: pci: Add a uclass for PCI") the following error message is seen: => pci 0 Scanning PCI devices on bus 0 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 00.01.00 0x16c3 0xabcd Bridge device 0x04 Cannot read bus configuration: -1 => pci 1 Scanning PCI devices on bus 1 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 01.00.00 0x8086 0x08b1 Network controller 0x80 Cannot read bus configuration: -1 When we are done scanning the PCI devices pci_read_config_word() will return -1 and VendorID will contain 0xFFFF. The original code would exit the 'for' loop in this condition. Keep the same original behaviour by first testing the VendorID value and then checking and propagating the pci_read_config_word() error afterwards. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- common/cmd_pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/cmd_pci.c b/common/cmd_pci.c index dcecef8..92dc643 100644 --- a/common/cmd_pci.c +++ b/common/cmd_pci.c @@ -77,10 +77,10 @@ void pciinfo(int BusNum, int ShortPCIListing) ret = pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID); - if (ret) - goto error; if ((VendorID == 0xFFFF) || (VendorID == 0x0000)) continue; + if (ret) + goto error; if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType); -- 1.9.1

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[U-Boot] [RFC PATCH 1/2] common: Add new clk command
by Michal Simek 05 Jan '16

05 Jan '16

Command provides just dump subcommand for showing clock frequencies in a soc. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- README | 1 + common/Makefile | 1 + common/cmd_clk.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++++ include/clk.h | 6 ++++++ include/config_cmd_all.h | 1 + 5 files changed, 60 insertions(+) create mode 100644 common/cmd_clk.c create mode 100644 include/clk.h diff --git a/README b/README index aea82be..0087649 100644 --- a/README +++ b/README @@ -887,6 +887,7 @@ The following options need to be configured: CONFIG_CMD_BSP * Board specific commands CONFIG_CMD_BOOTD bootd CONFIG_CMD_CACHE * icache, dcache + CONFIG_CMD_CLK * clock command support CONFIG_CMD_CONSOLE coninfo CONFIG_CMD_CRC32 * crc32 CONFIG_CMD_DATE * support for RTC, date/time... diff --git a/common/Makefile b/common/Makefile index d12cba5..a000e7d 100644 --- a/common/Makefile +++ b/common/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_CMD_BOOTLDR) += cmd_bootldr.o obj-$(CONFIG_CMD_BOOTSTAGE) += cmd_bootstage.o obj-$(CONFIG_CMD_CACHE) += cmd_cache.o obj-$(CONFIG_CMD_CBFS) += cmd_cbfs.o +obj-$(CONFIG_CMD_CLK) += cmd_clk.o obj-$(CONFIG_CMD_CONSOLE) += cmd_console.o obj-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o obj-$(CONFIG_DATAFLASH_MMC_SELECT) += cmd_dataflash_mmc_mux.o diff --git a/common/cmd_clk.c b/common/cmd_clk.c new file mode 100644 index 0000000..6d3d46a --- /dev/null +++ b/common/cmd_clk.c @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <command.h> +#include <clk.h> + +int __weak soc_clk_dump(void) +{ + puts("Not implemented\n"); + return 1; +} + +static int do_clk_dump(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + return soc_clk_dump(); +} + +static cmd_tbl_t cmd_clk_sub[] = { + U_BOOT_CMD_MKENT(dump, 1, 1, do_clk_dump, "", ""), +}; + +static int do_clk(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + cmd_tbl_t *c; + + if (argc < 2) + return CMD_RET_USAGE; + + /* Strip off leading 'clk' command argument */ + argc--; + argv++; + + c = find_cmd_tbl(argv[0], &cmd_clk_sub[0], ARRAY_SIZE(cmd_clk_sub)); + + if (c) + return c->cmd(cmdtp, flag, argc, argv); + else + return CMD_RET_USAGE; +} + +#ifdef CONFIG_SYS_LONGHELP +static char clk_help_text[] = + "dump - Print clock frequencies"; +#endif + +U_BOOT_CMD(clk, 2, 1, do_clk, "CLK sub-system", clk_help_text); diff --git a/include/clk.h b/include/clk.h new file mode 100644 index 0000000..df4570c --- /dev/null +++ b/include/clk.h @@ -0,0 +1,6 @@ +#ifndef _CLK_H_ +#define _CLK_H_ + +int soc_clk_dump(void); + +#endif /* _CLK_H_ */ diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index d847069..3e8983f 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -23,6 +23,7 @@ #define CONFIG_CMD_BSP /* Board Specific functions */ #define CONFIG_CMD_CACHE /* icache, dcache */ #define CONFIG_CMD_CDP /* Cisco Discovery Protocol */ +#define CONFIG_CMD_CLK /* Clock support */ #define CONFIG_CMD_CONSOLE /* coninfo */ #define CONFIG_CMD_DATE /* support for RTC, date/time...*/ #define CONFIG_CMD_DHCP /* DHCP Support */ -- 1.8.2.3

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