October 2015 - U-Boot

Re: [U-Boot] u-boot driver model
by Simon Glass 22 Oct '15

22 Oct '15

+U-Boot Hi Marco, On 20 October 2015 at 06:56, Hoefle Marco <Marco.Hoefle(a)nanotronic.ch> wrote: > > Hello Simon, > I read your presentation regarding driver model for u-boot. We want to port our old u-boot for Microblaze to an up to date one. > I am struggling with the device tree -> driver model mapping. > > The problem is identical to the thread here: > http://lists.denx.de/pipermail/u-boot/2015-April/210754.html > Invalid bus 0 (err=-19) > *** Warning - spi_flash_probe() failed, using default environment > > Unfortunately dm tree crashes so it is hard to debug further: > U-Boot> dm tree > Hardware exception at 0x4 address > Return address from exception 0x8 > Illegal op-code exception > Unaligned halfword access > Unaligned load access > Register R0 > ### ERROR ### Please RESET the board ### > > This is the device tree compiled into u-boot: > > U-Boot> bdinfo > DRAM bank = 0x00000000 > -> start = 0x80000000 > -> size = 0x10000000 > flash start = 0x00000000 > flash size = 0x00000000 > flash offset = 0x00000000 > eth0name = Xelite.40e00000 > ethaddr = 00:0A:35:02:C7:19 > current eth = Xelite.40e00000 > ip_addr = 192.168.0.3 > baudrate = 115200 bps > relocaddr = 0x8FF9B000 > reloc off = 0x00F9B000 > fdt_blob = 0x8FEB8A7C > new_fdt = 0x8FEB8A7C > fdt_size = 0x000024A0 > > U-Boot> fdt addr 0x8FEB8A7C > U-Boot> fdt print > / { > #address-cells = <0x00000001>; > #size-cells = <0x00000001>; > aliases { > serial0 = "serial@40600000"; > spi0 = "/axi_quad_spi@44a00000"; > }; > memory { > device_type = "memory"; > reg = <0x80000000 0x10000000>; > }; > axi_quad_spi@44a00000 { > compatible = "xlnx,xps-spi-2.00.a"; > reg = <0x44a00000 0x00010000>; > spi-max-frequency = <0x423a35c7>; > #address-cells = <0x00000001>; > #size-cells = <0x00000000>; > status = "okay"; > is-dual = <0x00000000>; > num-cs = <0x00000001>; > flash@0 { > compatible = "n25q128a11"; > reg = <0x00000000>; > spi-tx-bus-width = <0x00000001>; > spi-rx-bus-width = <0x00000004>; > spi-max-frequency = <0x0d3ed78e>; > #address-cells = <0x00000001>; > #size-cells = <0x00000001>; > partition@qspi-fsbl-uboot { > label = "qspi-fsbl-uboot"; > reg = <0x00000000 0x00100000>; > }; > partition@qspi-linux { > label = "qspi-linux"; > reg = <0x00100000 0x00500000>; > }; > partition@qspi-device-tree { > label = "qspi-device-tree"; > reg = <0x00600000 0x00020000>; > }; > partition@qspi-rootfs { > label = "qspi-rootfs"; > reg = <0x00620000 0x005e0000>; > }; > partition@qspi-bitstream { > label = "qspi-bitstream"; > reg = <0x00c00000 0x00400000>; > }; > }; > }; > }; > > > > Do you have any hint on how to debug this further? Can you try with no SPI and see if you can get 'dm tree' to work? If that doesn't work it isn't worth trying to figure out SPI. I suggest starting with what access is happening in 'dm tree' that causes a problem. You can probably add some debugging to drivers/core/dump.c. > Thanks and best regards, > Marco Regards, Simon

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[U-Boot] [PATCH v5] x86: Add support for Advantech SOM-6896
by George McCollister 22 Oct '15

22 Oct '15

Advantech SOM-6896 is a Broadwell U based COM Express Compact Module Type 6. This patch adds support for it as a coreboot payload. On board SATA and SPI are functional. On board Ethernet isn't functional but since it's optional and ties up a PCIe x4 that is otherwise brought out, this isn't a concern at the moment. USB doesn't work since the xHCI driver appears to be broken. Signed-off-by: George McCollister <george.mccollister(a)gmail.com> Reviewed-by: Bin Meng <bmeng.cn(a)gmail.com> Acked-by: Simon Glass <sjg(a)chromium.org> --- Changes for V2: Changed pci's compatible string to "pci-x86" Changed I/O from base of 0x1000 to base of 0x1900 Changed spi-flash memory-map Changes for V3: Renamed som-6896.dts to broadwell_som-6896.dts Changes for V4: Changed PCI I/O start from 0x1900 to 0x2000 (actually did it this time) Removed whitespace before my name at the top of som-6896.h Changes for V5: Changed 'Added' to 'Add' in the subject arch/x86/dts/Makefile | 3 ++- arch/x86/dts/broadwell_som-6896.dts | 43 +++++++++++++++++++++++++++++++++++++ include/configs/som-6896.h | 38 ++++++++++++++++++++++++++++++++ 3 files changed, 83 insertions(+), 1 deletion(-) create mode 100644 arch/x86/dts/broadwell_som-6896.dts create mode 100644 include/configs/som-6896.h diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 71595c7..83a2b8c 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -6,7 +6,8 @@ dtb-y += bayleybay.dtb \ galileo.dtb \ minnowmax.dtb \ qemu-x86_i440fx.dtb \ - qemu-x86_q35.dtb + qemu-x86_q35.dtb \ + broadwell_som-6896.dtb targets += $(dtb-y) diff --git a/arch/x86/dts/broadwell_som-6896.dts b/arch/x86/dts/broadwell_som-6896.dts new file mode 100644 index 0000000..a6b5d0f --- /dev/null +++ b/arch/x86/dts/broadwell_som-6896.dts @@ -0,0 +1,43 @@ +/dts-v1/; + +/include/ "skeleton.dtsi" +/include/ "serial.dtsi" +/include/ "rtc.dtsi" + +/ { + model = "Advantech SOM-6896"; + compatible = "advantech,som-6896", "intel,broadwell"; + + aliases { + spi0 = "/spi"; + }; + + config { + silent_console = <0>; + }; + + chosen { + stdout-path = "/serial"; + }; + + pci { + compatible = "pci-x86"; + #address-cells = <3>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000 + 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + }; + + spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich-spi"; + spi-flash@0 { + reg = <0>; + compatible = "winbond,w25q128", "spi-flash"; + memory-map = <0xff000000 0x01000000>; + }; + }; +}; diff --git a/include/configs/som-6896.h b/include/configs/som-6896.h new file mode 100644 index 0000000..300e9df --- /dev/null +++ b/include/configs/som-6896.h @@ -0,0 +1,38 @@ +/* + * Configuration settings for the SOM-6896 + * + * Copyright (C) 2015 NovaTech LLC + * George McCollister <george.mccollister(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/x86-common.h> + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R + +#define CONFIG_SCSI_DEV_LIST \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_AHCI} + +#define CONFIG_SYS_EARLY_PCI_INIT +#define CONFIG_PCI_PNP + +#define VIDEO_IO_OFFSET 0 +#define CONFIG_X86EMU_RAW_IO + +#define CONFIG_ARCH_EARLY_INIT_R + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga,usbkbd\0" \ + "stdout=serial,vga\0" \ + "stderr=serial,vga\0" + +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_OFFSET 0x00ff0000 + +#endif /* __CONFIG_H */ -- 2.5.0

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[U-Boot] [PATCH 0/9] x86: Fix up the MRC cache on ivybridge
by Simon Glass 22 Oct '15

22 Oct '15

At present the MRC cache on ivybridge is disabled due to a bug which was unknown. This has now been located and a fix is included in this series. In addition, the RTC functions have a few problems which prevent the checksum from being read correctly. This series fixes these and adds a few other minor improvements. Also included is a modified version of Bin's patch to enable the MRC cache on ivybridge. Bin Meng (1): x86: ivybridge: Enable the MRC cache Simon Glass (8): rtc: mc146818: Add a comment to the #endif rtc: mc146818: Use probe() to set up the device dm: rtc: Correct rtc_read32() return value x86: ivybridge: Use 'ret' instead of 'rcode' x86: ivybridge: Check the RTC return value x86: ivybridge: Use CONFIG_ENABLE_MRC_CACHE option x86: ivybridge: Fix car_uninit() to correctly set run state x86: ivybridge: Measure the MRC code execution time arch/x86/cpu/ivybridge/Kconfig | 6 ------ arch/x86/cpu/ivybridge/car.S | 6 +++--- arch/x86/cpu/ivybridge/sdram.c | 42 +++++++++++++++++++++++------------------- drivers/rtc/mc146818.c | 6 +++--- drivers/rtc/rtc-uclass.c | 2 +- 5 files changed, 30 insertions(+), 32 deletions(-) -- 2.6.0.rc2.230.g3dd15c0

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[U-Boot] [PATCH v2 0/5] x86: Early debug enhancements
by Simon Glass 22 Oct '15

22 Oct '15

This series adds a few more features to the debug UART, making it possible to use it even when the board needs to perform additional init for the UART to work. The debug UART is anabled on link. Some minor PCI tidy-ups are also included. Link currently does not boot due to lack of early malloc() memory. For now just increase the size. Changes in v2: - Adjust all _debug_uart_init() declarations to be static inline - Remove comment block since we now always enable the debug UART - Use a tab after the 'call' instruction Simon Glass (5): debug_uart: Adjust the declaration of debug_uart_init() debug_uart: Support board-specific UART initialisation debug_uart: Add an option to announce the debug UART x86: Init the debug UART if enabled x86: chromebook_link: Enable the debug UART arch/x86/cpu/ivybridge/cpu.c | 7 +++++++ arch/x86/cpu/start.S | 11 +++-------- configs/chromebook_link_defconfig | 4 ++++ drivers/serial/Kconfig | 21 +++++++++++++++++++++ drivers/serial/ns16550.c | 2 +- drivers/serial/serial_efi.c | 2 +- drivers/serial/serial_s5p.c | 2 +- include/debug_uart.h | 30 ++++++++++++++++++++++++++++-- lib/efi/efi_stub.c | 2 +- 9 files changed, 67 insertions(+), 14 deletions(-) -- 2.6.0.rc2.230.g3dd15c0

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[U-Boot] [PATCH 1/6] ARM: tegra: rename dummy XUSB padctl implementation
by Stephen Warren 21 Oct '15

21 Oct '15

From: Stephen Warren <swarren(a)nvidia.com> A future patch will soon move some of the XUSB padctl code into a common file in arch/arm/mach-tegra. Rename the existing dummy XUSB padctl file to avoid conflicting with that, or being confusing. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- arch/arm/mach-tegra/Makefile | 2 +- arch/arm/mach-tegra/{xusb-padctl.c => xusb-padctl-dummy.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename arch/arm/mach-tegra/{xusb-padctl.c => xusb-padctl-dummy.c} (100%) diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 98431a91f875..2be6ef41fff6 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -23,7 +23,7 @@ obj-y += clock.o obj-y += lowlevel_init.o obj-y += pinmux-common.o obj-y += powergate.o -obj-y += xusb-padctl.o +obj-y += xusb-padctl-dummy.o obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o obj-$(CONFIG_TEGRA_GPU) += gpu.o obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o diff --git a/arch/arm/mach-tegra/xusb-padctl.c b/arch/arm/mach-tegra/xusb-padctl-dummy.c similarity index 100% rename from arch/arm/mach-tegra/xusb-padctl.c rename to arch/arm/mach-tegra/xusb-padctl-dummy.c -- 1.9.1

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[U-Boot] [PATCH 1/5] pci: tegra: clip RAM size to 32-bits
by Stephen Warren 21 Oct '15

21 Oct '15

From: Stephen Warren <swarren(a)nvidia.com> Tegra peripherals can generally access a 32-bit physical address space, and I believe this applies to PCIe. Clip the PCI region that refers to DRAM so it fits into 32-bits to avoid issues. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- drivers/pci/pci_tegra.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c index ebb959f1f31f..357e7793b4ff 100644 --- a/drivers/pci/pci_tegra.c +++ b/drivers/pci/pci_tegra.c @@ -997,6 +997,14 @@ static const struct tegra_pcie_soc tegra124_pcie_soc = { static int process_nodes(const void *fdt, int nodes[], unsigned int count) { unsigned int i; + uint64_t dram_end; + uint32_t pci_dram_size; + + /* Clip PCI-accessible DRAM to 32-bits */ + dram_end = ((uint64_t)NV_PA_SDRAM_BASE) + gd->ram_size; + if (dram_end > 0x100000000) + dram_end = 0x100000000; + pci_dram_size = dram_end - NV_PA_SDRAM_BASE; for (i = 0; i < count; i++) { const struct tegra_pcie_soc *soc; @@ -1069,7 +1077,7 @@ static int process_nodes(const void *fdt, int nodes[], unsigned int count) pcie->hose.last_busno = 0; pci_set_region(&pcie->hose.regions[0], NV_PA_SDRAM_BASE, - NV_PA_SDRAM_BASE, gd->ram_size, + NV_PA_SDRAM_BASE, pci_dram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); pci_set_region(&pcie->hose.regions[1], pcie->io.start, -- 1.9.1

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[U-Boot] [PATCH] ARM: tegra210: implement PLLE init procedure from TRM
by Stephen Warren 21 Oct '15

21 Oct '15

From: Stephen Warren <swarren(a)nvidia.com> Implement the procedure that the TRM mandates to initialize PLLREFE and PLLE. This makes the PLL actually lock. Note that this section of the TRM is being cleaned up to remove some confusion. The set of register accesses in this patch should be final, although the step numbers/descriptions might still change. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- arch/arm/mach-tegra/tegra210/clock.c | 179 ++++++++++++++++++++++++++--------- 1 file changed, 132 insertions(+), 47 deletions(-) diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index 6d75d371cb03..df92bdce889e 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -8,6 +8,7 @@ /* Tegra210 Clock control functions */ #include <common.h> +#include <errno.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/sysctr.h> @@ -1030,6 +1031,59 @@ void arch_timer_init(void) debug("%s: TSC CNTCR = 0x%08X\n", __func__, val); } +#define PLLREFE_MISC 0x4c8 +#define PLLREFE_MISC_LOCK BIT(27) +#define PLLREFE_MISC_IDDQ BIT(24) + +#define PLLREFE_BASE 0x4c4 +#define PLLREFE_BASE_BYPASS BIT(31) +#define PLLREFE_BASE_ENABLE BIT(30) +#define PLLREFE_BASE_REF_DIS BIT(29) +#define PLLREFE_BASE_KCP(kcp) (((kcp) & 0x3) << 27) +#define PLLREFE_BASE_KVCO BIT(26) +#define PLLREFE_BASE_DIVP(p) (((p) & 0x1f) << 16) +#define PLLREFE_BASE_DIVN(n) (((n) & 0xff) << 8) +#define PLLREFE_BASE_DIVM(m) (((m) & 0xff) << 0) + +static int tegra_pllref_enable(void) +{ + u32 value; + unsigned long start; + + /* + * This sequence comes from Tegra X1 TRM section "Cold Boot, with no + * Recovery Mode or Boot from USB", sub-section "PLLREFE". + */ + + value = readl(NV_PA_CLK_RST_BASE + PLLREFE_MISC); + value &= ~PLLREFE_MISC_IDDQ; + writel(value, NV_PA_CLK_RST_BASE + PLLREFE_MISC); + + udelay(5); + + value = PLLREFE_BASE_ENABLE | + PLLREFE_BASE_KCP(0) | + PLLREFE_BASE_DIVP(0) | + PLLREFE_BASE_DIVN(0x41) | + PLLREFE_BASE_DIVM(4); + writel(value, NV_PA_CLK_RST_BASE + PLLREFE_BASE); + + debug("waiting for pllrefe lock\n"); + start = get_timer(0); + while (get_timer(start) < 250) { + value = readl(NV_PA_CLK_RST_BASE + PLLREFE_MISC); + if (value & PLLREFE_MISC_LOCK) + break; + } + if (!(value & PLLREFE_MISC_LOCK)) { + debug(" timeout\n"); + return -ETIMEDOUT; + } + debug(" done\n"); + + return 0; +} + #define PLLE_SS_CNTL 0x68 #define PLLE_SS_CNTL_SSCINCINTR(x) (((x) & 0x3f) << 24) #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16) @@ -1041,100 +1095,131 @@ void arch_timer_init(void) #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0) #define PLLE_BASE 0x0e8 -#define PLLE_BASE_ENABLE (1 << 30) -#define PLLE_BASE_LOCK_OVERRIDE (1 << 29) -#define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24) +#define PLLE_BASE_ENABLE (1 << 31) +#define PLLE_BASE_PLDIV_CML(x) (((x) & 0x1f) << 24) #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8) #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) #define PLLE_MISC 0x0ec #define PLLE_MISC_IDDQ_SWCTL (1 << 14) -#define PLLE_MISC_IDDQ_OVERRIDE (1 << 13) -#define PLLE_MISC_LOCK_ENABLE (1 << 9) -#define PLLE_MISC_PTS (1 << 8) -#define PLLE_MISC_VREG_BG_CTRL(x) (((x) & 0x3) << 4) +#define PLLE_MISC_IDDQ_OVERRIDE_VALUE (1 << 13) +#define PLLE_MISC_LOCK (1 << 11) +#define PLLE_MISC_KCP(x) (((x) & 0x3) << 6) #define PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2) +#define PLLE_MISC_KVCO (1 << 0) #define PLLE_AUX 0x48c +#define PLLE_AUX_SS_SEQ_INCLUDE (1 << 31) +#define PLLE_AUX_REF_SEL_PLLREFE (1 << 28) #define PLLE_AUX_SEQ_ENABLE (1 << 24) +#define PLLE_AUX_SS_SWCTL (1 << 6) #define PLLE_AUX_ENABLE_SWCTL (1 << 4) +#define PLLE_AUX_USE_LOCKDET (1 << 3) int tegra_plle_enable(void) { - unsigned int m = 1, n = 200, cpcon = 13; u32 value; + unsigned long start; - value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); - value &= ~PLLE_BASE_LOCK_OVERRIDE; - writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); + /* PLLREF feeds PLLE */ + tegra_pllref_enable(); + + /* + * This sequence comes from Tegra X1 TRM section "Cold Boot, with no + * Recovery Mode or Boot from USB", sub-section "PLLEs". + */ + + /* 1. Select XTAL as the source */ value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX); - value |= PLLE_AUX_ENABLE_SWCTL; - value &= ~PLLE_AUX_SEQ_ENABLE; + value &= ~PLLE_AUX_REF_SEL_PLLREFE; writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX); - udelay(1); - value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); - value |= PLLE_MISC_IDDQ_SWCTL; - value &= ~PLLE_MISC_IDDQ_OVERRIDE; - value |= PLLE_MISC_LOCK_ENABLE; - value |= PLLE_MISC_PTS; - value |= PLLE_MISC_VREG_BG_CTRL(3); - value |= PLLE_MISC_VREG_CTRL(2); + value &= ~PLLE_MISC_IDDQ_OVERRIDE_VALUE; writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); + /* 2. Wait 5 us */ udelay(5); - value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); - value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | - PLLE_SS_CNTL_BYPASS_SS; - writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); + /* + * 3. Program the following registers to generate a low jitter 100MHz + * clock. + */ value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); - value &= ~PLLE_BASE_PLDIV_CML(0xf); + value &= ~PLLE_BASE_PLDIV_CML(0x1f); value &= ~PLLE_BASE_NDIV(0xff); value &= ~PLLE_BASE_MDIV(0xff); - value |= PLLE_BASE_PLDIV_CML(cpcon); - value |= PLLE_BASE_NDIV(n); - value |= PLLE_BASE_MDIV(m); + value |= PLLE_BASE_PLDIV_CML(0xe); + value |= PLLE_BASE_NDIV(0x7d); + value |= PLLE_BASE_MDIV(2); writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); - udelay(1); + value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); + value &= ~PLLE_MISC_KCP(3); + value &= ~PLLE_MISC_VREG_CTRL(3); + value &= ~PLLE_MISC_KVCO; + writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); value |= PLLE_BASE_ENABLE; writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); - /* wait for lock */ - udelay(300); - - value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); - value &= ~PLLE_SS_CNTL_SSCINVERT; - value &= ~PLLE_SS_CNTL_SSCCENTER; - - value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f); - value &= ~PLLE_SS_CNTL_SSCINC(0xff); - value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff); + /* 4. Wait for LOCK */ - value |= PLLE_SS_CNTL_SSCINCINTR(0x20); - value |= PLLE_SS_CNTL_SSCINC(0x01); - value |= PLLE_SS_CNTL_SSCMAX(0x25); + debug("waiting for plle lock\n"); + start = get_timer(0); + while (get_timer(start) < 250) { + value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); + if (value & PLLE_MISC_LOCK) + break; + } + if (!(value & PLLE_MISC_LOCK)) { + debug(" timeout\n"); + return -ETIMEDOUT; + } + debug(" done\n"); - writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); + /* 5. Enable SSA */ value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); - value &= ~PLLE_SS_CNTL_SSCBYP; + value &= ~PLLE_SS_CNTL_SSCINC(0xff); + value |= PLLE_SS_CNTL_SSCINC(1); + value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f); + value |= PLLE_SS_CNTL_SSCINCINTR(0x23); + value &= ~PLLE_SS_CNTL_SSCMAX(0x1fff); + value |= PLLE_SS_CNTL_SSCMAX(0x21); + value &= ~PLLE_SS_CNTL_SSCINVERT; + value &= ~PLLE_SS_CNTL_SSCCENTER; value &= ~PLLE_SS_CNTL_BYPASS_SS; + value &= ~PLLE_SS_CNTL_SSCBYP; writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); - udelay(1); + /* 6. Wait 300 ns */ - value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); + udelay(1); value &= ~PLLE_SS_CNTL_INTERP_RESET; writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); + /* 7. Enable HW power sequencer for PLLE */ + + value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); + value &= ~PLLE_MISC_IDDQ_SWCTL; + writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); + + value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX); + value &= ~PLLE_AUX_SS_SWCTL; + value &= ~PLLE_AUX_ENABLE_SWCTL; + value |= PLLE_AUX_SS_SEQ_INCLUDE; + value |= PLLE_AUX_USE_LOCKDET; + writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX); + + /* 8. Wait 1 us */ + udelay(1); + value |= PLLE_AUX_SEQ_ENABLE; + writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX); return 0; } -- 1.9.1

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[U-Boot] [PATCH v6] x86: Add support for Advantech SOM-6896
by George McCollister 21 Oct '15

21 Oct '15

Advantech SOM-6896 is a Broadwell U based COM Express Compact Module Type 6. This patch adds support for it as a coreboot payload. On board SATA and SPI are functional. On board Ethernet isn't functional but since it's optional and ties up a PCIe x4 that is otherwise brought out, this isn't a concern at the moment. USB doesn't work since the xHCI driver appears to be broken. Signed-off-by: George McCollister <george.mccollister(a)gmail.com> Reviewed-by: Bin Meng <bmeng.cn(a)gmail.com> Reviewed-by: Tom Rini <trini(a)konsulko.com> Acked-by: Simon Glass <sjg(a)chromium.org> --- Changes for V2: Changed pci's compatible string to "pci-x86" Changed I/O from base of 0x1000 to base of 0x1900 Changed spi-flash memory-map Changes for V3: Renamed som-6896.dts to broadwell_som-6896.dts Changes for V4: Changed PCI I/O start from 0x1900 to 0x2000 (actually did it this time) Removed whitespace before my name at the top of som-6896.h Changes for V5: Changed 'Added' to 'Add' in the subject Changes for V6: None arch/x86/dts/Makefile | 3 ++- arch/x86/dts/broadwell_som-6896.dts | 43 +++++++++++++++++++++++++++++++++++++ include/configs/som-6896.h | 38 ++++++++++++++++++++++++++++++++ 3 files changed, 83 insertions(+), 1 deletion(-) create mode 100644 arch/x86/dts/broadwell_som-6896.dts create mode 100644 include/configs/som-6896.h diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 71595c7..83a2b8c 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -6,7 +6,8 @@ dtb-y += bayleybay.dtb \ galileo.dtb \ minnowmax.dtb \ qemu-x86_i440fx.dtb \ - qemu-x86_q35.dtb + qemu-x86_q35.dtb \ + broadwell_som-6896.dtb targets += $(dtb-y) diff --git a/arch/x86/dts/broadwell_som-6896.dts b/arch/x86/dts/broadwell_som-6896.dts new file mode 100644 index 0000000..a6b5d0f --- /dev/null +++ b/arch/x86/dts/broadwell_som-6896.dts @@ -0,0 +1,43 @@ +/dts-v1/; + +/include/ "skeleton.dtsi" +/include/ "serial.dtsi" +/include/ "rtc.dtsi" + +/ { + model = "Advantech SOM-6896"; + compatible = "advantech,som-6896", "intel,broadwell"; + + aliases { + spi0 = "/spi"; + }; + + config { + silent_console = <0>; + }; + + chosen { + stdout-path = "/serial"; + }; + + pci { + compatible = "pci-x86"; + #address-cells = <3>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000 + 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + }; + + spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich-spi"; + spi-flash@0 { + reg = <0>; + compatible = "winbond,w25q128", "spi-flash"; + memory-map = <0xff000000 0x01000000>; + }; + }; +}; diff --git a/include/configs/som-6896.h b/include/configs/som-6896.h new file mode 100644 index 0000000..300e9df --- /dev/null +++ b/include/configs/som-6896.h @@ -0,0 +1,38 @@ +/* + * Configuration settings for the SOM-6896 + * + * Copyright (C) 2015 NovaTech LLC + * George McCollister <george.mccollister(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/x86-common.h> + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R + +#define CONFIG_SCSI_DEV_LIST \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_AHCI} + +#define CONFIG_SYS_EARLY_PCI_INIT +#define CONFIG_PCI_PNP + +#define VIDEO_IO_OFFSET 0 +#define CONFIG_X86EMU_RAW_IO + +#define CONFIG_ARCH_EARLY_INIT_R + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga,usbkbd\0" \ + "stdout=serial,vga\0" \ + "stderr=serial,vga\0" + +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_OFFSET 0x00ff0000 + +#endif /* __CONFIG_H */ -- 2.5.0

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[U-Boot] [PATCH] am43xx_evm: Add DFU support for qspi flash
by Vignesh R 21 Oct '15

21 Oct '15

This adds support to update firmware on qspi flash present on am437x-sk-evm and am43xx-epos-evm via DFU. On device: => setenv dfu_alt_info ${dfu_alt_info_qspi} => dfu 0 sf 0:0 On host: $ sudo dfu-util -l $ sudo dfu-util -D u-boot.img -a u-boot.img Signed-off-by: Vignesh R <vigneshr(a)ti.com> --- Tested on am437x-sk-evm by flashing u-boot.img and zImage. include/configs/am43xx_evm.h | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 67d5c48ddeb6..c37420b79d98 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -165,11 +165,22 @@ "fdt ram 0x80f80000 0x80000;" \ "ramdisk ram 0x81000000 0x4000000\0" +#define CONFIG_DFU_SF +#define DFU_ALT_INFO_QSPI \ + "dfu_alt_info_qspi=" \ + "u-boot.img raw 0x0 0x080000;" \ + "u-boot.backup raw 0x080000 0x080000;" \ + "u-boot-spl-os raw 0x100000 0x010000;" \ + "u-boot-env raw 0x110000 0x010000;" \ + "u-boot-env.backup raw 0x120000 0x010000;" \ + "kernel raw 0x130000 0x800000\0" + #define DFUARGS \ "dfu_bufsiz=0x10000\0" \ DFU_ALT_INFO_MMC \ DFU_ALT_INFO_EMMC \ - DFU_ALT_INFO_RAM + DFU_ALT_INFO_RAM \ + DFU_ALT_INFO_QSPI #else #define DFUARGS #endif -- 2.6.2

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[U-Boot] Relocation issue - need help!
by Wolfgang Denk 21 Oct '15

21 Oct '15

Hi, I'm trying to track down a "syntax error" issue that gets triggered when erasing the U-Boot image in NOR flash. Symptoms look like this: => print update update=protect off 0xfc000000 +${filesize};erase 0xfc000000 +${filesize};cp.b 200000 0xfc000000 ${filesize};protect on 0xfc000000 +${filesize} => run update Un-Protected 2 sectors .. done Erased 2 sectors syntax error Protected 2 sectors => run update syntax error git bisect found commit 199adb6 "common/misc: sparse fixes" as culprit; breaking this down further showed a single line in common/cli_hush.c to trigger the problem. This patch fixes it: --- common/cli_hush.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/cli_hush.c b/common/cli_hush.c index 38da5a0..5bbcfe6 100644 --- a/common/cli_hush.c +++ b/common/cli_hush.c @@ -3127,7 +3127,7 @@ static void mapset(const unsigned char *set, int code) for (s=set; *s; s++) map[*s] = code; } -static void update_ifs_map(void) +void update_ifs_map(void) { /* char *ifs and char map[256] are both globals. */ ifs = (uchar *)getenv("IFS"); -- 1.8.3.1 But I still have bad feelings - symptoms indicate that this is actually a relocation issue, as it only gets triggered when erasing the U-Boot image in NOR flash, so probably there are still pointers to data in NOR being used. This patch here is not suited to fix the original cause of this issue. But then, I do not see where there might be a relocation problem. To be sure I even verified that "ifs" and "map[]" are really in RAM all the time. Has anybody an idea how to further track this down? Or is the patch above actually a real fix? If so, why? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de Old programmers never die, they just branch to a new address.

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