October 2015 - U-Boot

[U-Boot] [PATCH v4 00/24] spi: Use BIT and GENMASK
by Jagan Teki 24 Oct '15

24 Oct '15

This series replaces numerical bit shitfts and mask values with BIT and GENMASK macro's Changes for v4: - Patch split for individual drivers. Changes for v3, v2: - none Jagan Teki (24): spi: zynq_[q]spi: Use BIT macro spi: zynq_[q]spi: Use GENMASK macro spi: altera_spi: Use BIT macro spi: atmel_spi: Use BIT macro spi: bfin_spi6xx: Use BIT macro spi: cadence_qspi_apb: Use BIT macro spi: designware_spi: Use BIT macro spi: exynos_spi: Use BIT macro spi: fsl: Use BIT macro spi: ich: Use BIT macro spi: mpc8xxx_spi: Use BIT macro spi: omap3_spi: Use BIT macro spi: sh_qspi: Use BIT macro spi: tegra: Use BIT macro spi: ti_qspi: Use BIT macro spi: xilinx_spi: Use BIT macro spi: atmel_spi: Use GENMASK spi: cadence_qspi_apb: Use GENMASK spi: designware_spi: Use GENMASK spi: fsl_qspi: Use GENMASK spi: mxs_spi: Use GENMASK spi: omap3_spi: Use GENMASK spi: tegra: Use GENMASK spi: xilinx_spi: Use GENMASK drivers/spi/altera_spi.c | 26 +++++++-------- drivers/spi/atmel_spi.h | 54 +++++++++++++++--------------- drivers/spi/bfin_spi6xx.c | 8 ++--- drivers/spi/cadence_qspi_apb.c | 76 +++++++++++++++++++++--------------------- drivers/spi/designware_spi.c | 16 ++++----- drivers/spi/exynos_spi.c | 4 +-- drivers/spi/fsl_dspi.c | 2 +- drivers/spi/fsl_espi.c | 20 +++++------ drivers/spi/fsl_qspi.c | 6 ++-- drivers/spi/ich.c | 4 +-- drivers/spi/mpc8xxx_spi.c | 2 +- drivers/spi/mxs_spi.c | 2 +- drivers/spi/omap3_spi.h | 64 +++++++++++++++++------------------ drivers/spi/sh_qspi.c | 16 ++++----- drivers/spi/tegra114_spi.c | 76 +++++++++++++++++++++--------------------- drivers/spi/tegra20_sflash.c | 54 +++++++++++++++--------------- drivers/spi/tegra20_slink.c | 62 +++++++++++++++++----------------- drivers/spi/ti_qspi.c | 10 +++--- drivers/spi/xilinx_spi.c | 46 ++++++++++++------------- drivers/spi/zynq_qspi.c | 28 ++++++++-------- drivers/spi/zynq_spi.c | 22 ++++++------ 21 files changed, 299 insertions(+), 299 deletions(-) -- 1.9.1

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[U-Boot] [PATCH] gpio: return success if value is positiv
by Stefan Agner 24 Oct '15

24 Oct '15

Currently we return the GPIO value directly as command exit code. In shell exit codes, 0 means success. Hence if a GPIO is one, we actually return a "failure". Fix this by returning SUCCESS if the value is positive. This allows to implement scripts more naturally e.g.: if gpio input 47; then echo "Pressed"; else echo "Not pressed"; fi Signed-off-by: Stefan Agner <stefan(a)agner.ch> --- Not sure if it is the right thing to do to change that, maybe there are a lot of users which rely on that output already? It just feels a bit more natural to me when using the command in scripts... -- Stefan common/cmd_gpio.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/common/cmd_gpio.c b/common/cmd_gpio.c index 65d6df4..ed735bd 100644 --- a/common/cmd_gpio.c +++ b/common/cmd_gpio.c @@ -208,7 +208,10 @@ static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (ret != -EBUSY) gpio_free(gpio); - return value; + if (value) + return CMD_RET_SUCCESS; + else + return CMD_RET_FAILURE; } U_BOOT_CMD(gpio, 4, 0, do_gpio, -- 2.6.2

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[U-Boot] [PATCH] mtd: pxa3xx_nand: Correct allocation and init bug
by Kevin Smith 23 Oct '15

23 Oct '15

Correct a null pointer dereference in board_nand_init(). Zeroed memory was allocated, then immediately dereferenced, which is a null dereference. The dereference is completely removed, since this pointer is later initialized in alloc_nand_resources. The allocation size is reduced from what was introduced from the Linux kernel, as U-boot uses the statically allocated nand_info instead of needing to dynamically allocate an mtd_info instance. Also, some pointer math was corrected in the initialization of the nand_chip pointer. Signed-off-by: Kevin Smith <kevin.smith(a)elecsyscorp.com> Cc: Stefan Roese <sr(a)denx.de> Cc: Luka Perkov <luka.perkov(a)sartura.hr> Cc: Scott Wood <scottwood(a)freescale.com> --- drivers/mtd/nand/pxa3xx_nand.c | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index 1565a9a..e5ea5c2 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -1486,8 +1486,8 @@ static int alloc_nand_resource(struct pxa3xx_nand_info *info) info->variant = pxa3xx_nand_get_variant(); for (cs = 0; cs < pdata->num_cs; cs++) { mtd = &nand_info[cs]; - chip = (struct nand_chip *)info + - sizeof(struct pxa3xx_nand_host); + chip = (struct nand_chip *) + ((u8 *)&info[1] + sizeof(*host) * cs); host = (struct pxa3xx_nand_host *)chip; info->host[cs] = host; host->mtd = mtd; @@ -1600,19 +1600,12 @@ void board_nand_init(void) struct pxa3xx_nand_host *host; int ret; - info = kzalloc(sizeof(*info) + (sizeof(struct mtd_info) + - sizeof(*host)) * - CONFIG_SYS_MAX_NAND_DEVICE, GFP_KERNEL); + info = kzalloc(sizeof(*info) + + sizeof(*host) * CONFIG_SYS_MAX_NAND_DEVICE, + GFP_KERNEL); if (!info) return; - /* - * If CONFIG_SYS_NAND_SELF_INIT is defined, each driver is responsible - * for instantiating struct nand_chip, while drivers/mtd/nand/nand.c - * still provides a "struct mtd_info nand_info" instance. - */ - info->host[0]->mtd = &nand_info[0]; - ret = pxa3xx_nand_probe(info); if (ret) return; -- 2.4.6

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[U-Boot] [PATCH] spi: Tegra: add device tree binding doc for SPI and QSPI
by Tom Warren 23 Oct '15

23 Oct '15

This patch adds the device tree binding doc for the Tegra114 SPI controller and the Tegra210 QSPI controller. Signed-off-by: Tom Warren <twarren(a)nvidia.com> --- doc/device-tree-bindings/spi/spi-tegra.txt | 47 ++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 doc/device-tree-bindings/spi/spi-tegra.txt diff --git a/doc/device-tree-bindings/spi/spi-tegra.txt b/doc/device-tree-bindings/spi/spi-tegra.txt new file mode 100644 index 0000000..e215efe --- /dev/null +++ b/doc/device-tree-bindings/spi/spi-tegra.txt @@ -0,0 +1,47 @@ +NVIDIA Tegra114 SPI controller. + +Required properties: +- compatible : should be "nvidia,tegra114-spi". +- reg: Should contain SPI registers location and length. +- interrupts: Should contain SPI interrupts. +- clocks : Should contain an entry for SPI clock. + +Recommended properties: +- spi-max-frequency: Definition as per + doc/device-tree-bindings/spi/spi-bus.txt +Example: + +spi@7000d600 { + compatible = "nvidia,tegra114-spi"; + reg = <0x7000d600 0x200>; + interrupts = <0 82 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 44>; + status = "disabled"; + spi-max-frequency = <25000000>; +}; + +NVIDIA Tegra210 QSPI controller. + +Required properties: +- compatible : should be "nvidia,tegra210-qspi". +- reg: Should contain QSPI registers location and length. +- interrupts: Should contain QSPI interrupts. +- clocks : Should contain an entry for QSPI clock. + +Recommended properties: +- spi-max-frequency: Definition as per + doc/device-tree-bindings/spi/spi-bus.txt +Example: + +spi@70410000 { + compatible = "nvidia,tegra210-qspi"; + reg = <0x0 0x70410000 0x0 0x1000>; + interrupts = <0 10 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 211>; + status = "disabled"; + spi-max-frequency = <24000000>; +}; -- 1.8.2.1.610.g562af5b

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[U-Boot] [PATCH v4] Tegra: T210: Add QSPI driver
by Tom Warren 23 Oct '15

23 Oct '15

This is the normal Tegra SPI driver modified to work with the QSPI controller in Tegra210. It does not do 2x/4x transfers or any other QSPI protocol. Signed-off-by: Yen Lin <yelin(a)nvidia.com> Signed-off-by: Tom Warren <twarren(a)nvidia.com> --- Changes in v2: - Drop defconfig and pinmux files, this is a driver-only patch. - If/when pinmux tables have been updated for P2371/P2571, another - patch will be sent to enable the QSPI driver on those boards. Changes in v3: - removed status reg write/clear in claim_bus(), done in xfer() Changes in v4: - added timeout in wait for FIFO flush status in xfer() - used BIT and GENMASK macros throughout - minor changes in copyright message in driver and Kconfig help drivers/spi/Kconfig | 7 + drivers/spi/Makefile | 1 + drivers/spi/tegra210_qspi.c | 408 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 416 insertions(+) create mode 100644 drivers/spi/tegra210_qspi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 2f8cf19..95286da 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -123,6 +123,13 @@ config TEGRA20_SLINK be used to access the SPI NOR flash on platforms embedding this nVidia Tegra20/Tegra30 IP cores. +config TEGRA210_QSPI + bool "nVidia Tegra210 QSPI driver" + help + Enable the Tegra Quad-SPI (QSPI) driver for T210. This driver + be used to access SPI chips on platforms embedding this + NVIDIA Tegra210 IP core. + config XILINX_SPI bool "Xilinx SPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index de241be..209a41e 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_SH_QSPI) += sh_qspi.o obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o +obj-$(CONFIG_TEGRA210_QSPI) += tegra210_qspi.o obj-$(CONFIG_TI_QSPI) += ti_qspi.o obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c new file mode 100644 index 0000000..521f745 --- /dev/null +++ b/drivers/spi/tegra210_qspi.c @@ -0,0 +1,408 @@ +/* + * NVIDIA Tegra210 QSPI controller driver + * + * (C) Copyright 2015 NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch-tegra/clk_rst.h> +#include <spi.h> +#include <fdtdec.h> +#include "tegra_spi.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* COMMAND1 */ +#define QSPI_CMD1_GO BIT(31) +#define QSPI_CMD1_M_S BIT(30) +#define QSPI_CMD1_MODE_MASK GENMASK(1,0) +#define QSPI_CMD1_MODE_SHIFT 28 +#define QSPI_CMD1_CS_SEL_MASK GENMASK(1,0) +#define QSPI_CMD1_CS_SEL_SHIFT 26 +#define QSPI_CMD1_CS_POL_INACTIVE0 BIT(22) +#define QSPI_CMD1_CS_SW_HW BIT(21) +#define QSPI_CMD1_CS_SW_VAL BIT(20) +#define QSPI_CMD1_IDLE_SDA_MASK GENMASK(1,0) +#define QSPI_CMD1_IDLE_SDA_SHIFT 18 +#define QSPI_CMD1_BIDIR BIT(17) +#define QSPI_CMD1_LSBI_FE BIT(16) +#define QSPI_CMD1_LSBY_FE BIT(15) +#define QSPI_CMD1_BOTH_EN_BIT BIT(14) +#define QSPI_CMD1_BOTH_EN_BYTE BIT(13) +#define QSPI_CMD1_RX_EN BIT(12) +#define QSPI_CMD1_TX_EN BIT(11) +#define QSPI_CMD1_PACKED BIT(5) +#define QSPI_CMD1_BITLEN_MASK GENMASK(4,0) +#define QSPI_CMD1_BITLEN_SHIFT 0 + +/* COMMAND2 */ +#define QSPI_CMD2_TX_CLK_TAP_DELAY BIT(6) +#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(11,6) +#define QSPI_CMD2_RX_CLK_TAP_DELAY BIT(0) +#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(5,0) + +/* TRANSFER STATUS */ +#define QSPI_XFER_STS_RDY BIT(30) + +/* FIFO STATUS */ +#define QSPI_FIFO_STS_CS_INACTIVE BIT(31) +#define QSPI_FIFO_STS_FRAME_END BIT(30) +#define QSPI_FIFO_STS_RX_FIFO_FLUSH BIT(15) +#define QSPI_FIFO_STS_TX_FIFO_FLUSH BIT(14) +#define QSPI_FIFO_STS_ERR BIT(8) +#define QSPI_FIFO_STS_TX_FIFO_OVF BIT(7) +#define QSPI_FIFO_STS_TX_FIFO_UNR BIT(6) +#define QSPI_FIFO_STS_RX_FIFO_OVF BIT(5) +#define QSPI_FIFO_STS_RX_FIFO_UNR BIT(4) +#define QSPI_FIFO_STS_TX_FIFO_FULL BIT(3) +#define QSPI_FIFO_STS_TX_FIFO_EMPTY BIT(2) +#define QSPI_FIFO_STS_RX_FIFO_FULL BIT(1) +#define QSPI_FIFO_STS_RX_FIFO_EMPTY BIT(0) + +#define QSPI_TIMEOUT 1000 + +struct qspi_regs { + u32 command1; /* 000:QSPI_COMMAND1 register */ + u32 command2; /* 004:QSPI_COMMAND2 register */ + u32 timing1; /* 008:QSPI_CS_TIM1 register */ + u32 timing2; /* 00c:QSPI_CS_TIM2 register */ + u32 xfer_status;/* 010:QSPI_TRANS_STATUS register */ + u32 fifo_status;/* 014:QSPI_FIFO_STATUS register */ + u32 tx_data; /* 018:QSPI_TX_DATA register */ + u32 rx_data; /* 01c:QSPI_RX_DATA register */ + u32 dma_ctl; /* 020:QSPI_DMA_CTL register */ + u32 dma_blk; /* 024:QSPI_DMA_BLK register */ + u32 rsvd[56]; /* 028-107 reserved */ + u32 tx_fifo; /* 108:QSPI_FIFO1 register */ + u32 rsvd2[31]; /* 10c-187 reserved */ + u32 rx_fifo; /* 188:QSPI_FIFO2 register */ + u32 spare_ctl; /* 18c:QSPI_SPARE_CTRL register */ +}; + +struct tegra210_qspi_priv { + struct qspi_regs *regs; + unsigned int freq; + unsigned int mode; + int periph_id; + int valid; + int last_transaction_us; +}; + +static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus) +{ + struct tegra_spi_platdata *plat = bus->platdata; + const void *blob = gd->fdt_blob; + int node = bus->of_offset; + + plat->base = dev_get_addr(bus); + plat->periph_id = clock_decode_periph_id(blob, node); + + if (plat->periph_id == PERIPH_ID_NONE) { + debug("%s: could not decode periph id %d\n", __func__, + plat->periph_id); + return -FDT_ERR_NOTFOUND; + } + + /* Use 500KHz as a suitable default */ + plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", + 500000); + plat->deactivate_delay_us = fdtdec_get_int(blob, node, + "spi-deactivate-delay", 0); + debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", + __func__, plat->base, plat->periph_id, plat->frequency, + plat->deactivate_delay_us); + + return 0; +} + +static int tegra210_qspi_probe(struct udevice *bus) +{ + struct tegra_spi_platdata *plat = dev_get_platdata(bus); + struct tegra210_qspi_priv *priv = dev_get_priv(bus); + + priv->regs = (struct qspi_regs *)plat->base; + + priv->last_transaction_us = timer_get_us(); + priv->freq = plat->frequency; + priv->periph_id = plat->periph_id; + + return 0; +} + +static int tegra210_qspi_claim_bus(struct udevice *bus) +{ + struct tegra210_qspi_priv *priv = dev_get_priv(bus); + struct qspi_regs *regs = priv->regs; + + /* Change SPI clock to correct frequency, PLLP_OUT0 source */ + clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq); + + debug("%s: FIFO STATUS = %08x\n", __func__, readl(&regs->fifo_status)); + + /* Set master mode and sw controlled CS */ + setbits_le32(&regs->command1, QSPI_CMD1_M_S | QSPI_CMD1_CS_SW_HW | + (priv->mode << QSPI_CMD1_MODE_SHIFT)); + debug("%s: COMMAND1 = %08x\n", __func__, readl(&regs->command1)); + + return 0; +} + +/** + * Activate the CS by driving it LOW + * + * @param slave Pointer to spi_slave to which controller has to + * communicate with + */ +static void spi_cs_activate(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct tegra_spi_platdata *pdata = dev_get_platdata(bus); + struct tegra210_qspi_priv *priv = dev_get_priv(bus); + + /* If it's too soon to do another transaction, wait */ + if (pdata->deactivate_delay_us && + priv->last_transaction_us) { + ulong delay_us; /* The delay completed so far */ + delay_us = timer_get_us() - priv->last_transaction_us; + if (delay_us < pdata->deactivate_delay_us) + udelay(pdata->deactivate_delay_us - delay_us); + } + + clrbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL); +} + +/** + * Deactivate the CS by driving it HIGH + * + * @param slave Pointer to spi_slave to which controller has to + * communicate with + */ +static void spi_cs_deactivate(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct tegra_spi_platdata *pdata = dev_get_platdata(bus); + struct tegra210_qspi_priv *priv = dev_get_priv(bus); + + setbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL); + + /* Remember time of this transaction so we can honour the bus delay */ + if (pdata->deactivate_delay_us) + priv->last_transaction_us = timer_get_us(); + + debug("Deactivate CS, bus '%s'\n", bus->name); +} + +static int tegra210_qspi_xfer(struct udevice *dev, unsigned int bitlen, + const void *data_out, void *data_in, + unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct tegra210_qspi_priv *priv = dev_get_priv(bus); + struct qspi_regs *regs = priv->regs; + u32 reg, tmpdout, tmpdin = 0; + const u8 *dout = data_out; + u8 *din = data_in; + int num_bytes, tm, ret; + + debug("%s: slave %u:%u dout %p din %p bitlen %u\n", + __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen); + if (bitlen % 8) + return -1; + num_bytes = bitlen / 8; + + ret = 0; + + /* clear all error status bits */ + reg = readl(&regs->fifo_status); + writel(reg, &regs->fifo_status); + + /* flush RX/TX FIFOs */ + setbits_le32(&regs->fifo_status, + (QSPI_FIFO_STS_RX_FIFO_FLUSH | + QSPI_FIFO_STS_TX_FIFO_FLUSH)); + + tm = QSPI_TIMEOUT; + while ((tm && readl(&regs->fifo_status) & + (QSPI_FIFO_STS_RX_FIFO_FLUSH | + QSPI_FIFO_STS_TX_FIFO_FLUSH))) { + tm--; + udelay(1); + } + + if (!tm) { + printf("%s: timeout during QSPI FIFO flush!\n", + __func__); + return -1; + } + + /* + * Notes: + * 1. don't set LSBY_FE, so no need to swap bytes from/to TX/RX FIFOs; + * 2. don't set RX_EN and TX_EN yet. + * (SW needs to make sure that while programming the blk_size, + * tx_en and rx_en bits must be zero) + * [TODO] I (Yen Lin) have problems when both RX/TX EN bits are set + * i.e., both dout and din are not NULL. + */ + clrsetbits_le32(&regs->command1, + (QSPI_CMD1_LSBI_FE | QSPI_CMD1_LSBY_FE | + QSPI_CMD1_RX_EN | QSPI_CMD1_TX_EN), + (spi_chip_select(dev) << QSPI_CMD1_CS_SEL_SHIFT)); + + /* set xfer size to 1 block (32 bits) */ + writel(0, &regs->dma_blk); + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(dev); + + /* handle data in 32-bit chunks */ + while (num_bytes > 0) { + int bytes; + + tmpdout = 0; + bytes = (num_bytes > 4) ? 4 : num_bytes; + + if (dout != NULL) { + memcpy((void *)&tmpdout, (void *)dout, bytes); + dout += bytes; + num_bytes -= bytes; + writel(tmpdout, &regs->tx_fifo); + setbits_le32(&regs->command1, QSPI_CMD1_TX_EN); + } + + if (din != NULL) + setbits_le32(&regs->command1, QSPI_CMD1_RX_EN); + + /* clear ready bit */ + setbits_le32(&regs->xfer_status, QSPI_XFER_STS_RDY); + + clrsetbits_le32(&regs->command1, + QSPI_CMD1_BITLEN_MASK << QSPI_CMD1_BITLEN_SHIFT, + (bytes * 8 - 1) << QSPI_CMD1_BITLEN_SHIFT); + /* Need to stabilize other reg bit before GO bit set */ + udelay(2); + setbits_le32(&regs->command1, QSPI_CMD1_GO); + udelay(1); + + /* + * Wait for SPI transmit FIFO to empty, or to time out. + * The RX FIFO status will be read and cleared last + */ + for (tm = 0; tm < QSPI_TIMEOUT; ++tm) { + u32 fifo_status, xfer_status; + + xfer_status = readl(&regs->xfer_status); + if (!(xfer_status & QSPI_XFER_STS_RDY)) + continue; + + fifo_status = readl(&regs->fifo_status); + if (fifo_status & QSPI_FIFO_STS_ERR) { + debug("%s: got a fifo error: ", __func__); + if (fifo_status & QSPI_FIFO_STS_TX_FIFO_OVF) + debug("tx FIFO overflow "); + if (fifo_status & QSPI_FIFO_STS_TX_FIFO_UNR) + debug("tx FIFO underrun "); + if (fifo_status & QSPI_FIFO_STS_RX_FIFO_OVF) + debug("rx FIFO overflow "); + if (fifo_status & QSPI_FIFO_STS_RX_FIFO_UNR) + debug("rx FIFO underrun "); + if (fifo_status & QSPI_FIFO_STS_TX_FIFO_FULL) + debug("tx FIFO full "); + if (fifo_status & QSPI_FIFO_STS_TX_FIFO_EMPTY) + debug("tx FIFO empty "); + if (fifo_status & QSPI_FIFO_STS_RX_FIFO_FULL) + debug("rx FIFO full "); + if (fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY) + debug("rx FIFO empty "); + debug("\n"); + break; + } + + if (!(fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY)) { + tmpdin = readl(&regs->rx_fifo); + if (din != NULL) { + memcpy(din, &tmpdin, bytes); + din += bytes; + num_bytes -= bytes; + } + } + break; + } + + if (tm >= QSPI_TIMEOUT) + ret = tm; + + /* clear ACK RDY, etc. bits */ + writel(readl(&regs->fifo_status), &regs->fifo_status); + } + + if (flags & SPI_XFER_END) + spi_cs_deactivate(dev); + + debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n", + __func__, tmpdin, readl(&regs->fifo_status)); + + if (ret) { + printf("%s: timeout during SPI transfer, tm %d\n", + __func__, ret); + return -1; + } + + return ret; +} + +static int tegra210_qspi_set_speed(struct udevice *bus, uint speed) +{ + struct tegra_spi_platdata *plat = bus->platdata; + struct tegra210_qspi_priv *priv = dev_get_priv(bus); + + if (speed > plat->frequency) + speed = plat->frequency; + priv->freq = speed; + debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq); + + return 0; +} + +static int tegra210_qspi_set_mode(struct udevice *bus, uint mode) +{ + struct tegra210_qspi_priv *priv = dev_get_priv(bus); + + priv->mode = mode; + debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); + + return 0; +} + +static const struct dm_spi_ops tegra210_qspi_ops = { + .claim_bus = tegra210_qspi_claim_bus, + .xfer = tegra210_qspi_xfer, + .set_speed = tegra210_qspi_set_speed, + .set_mode = tegra210_qspi_set_mode, + /* + * cs_info is not needed, since we require all chip selects to be + * in the device tree explicitly + */ +}; + +static const struct udevice_id tegra210_qspi_ids[] = { + { .compatible = "nvidia,tegra210-qspi" }, + { } +}; + +U_BOOT_DRIVER(tegra210_qspi) = { + .name = "tegra210-qspi", + .id = UCLASS_SPI, + .of_match = tegra210_qspi_ids, + .ops = &tegra210_qspi_ops, + .ofdata_to_platdata = tegra210_qspi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata), + .priv_auto_alloc_size = sizeof(struct tegra210_qspi_priv), + .per_child_auto_alloc_size = sizeof(struct spi_slave), + .probe = tegra210_qspi_probe, +}; -- 1.8.2.1.610.g562af5b

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[U-Boot] [PATCH] dm: keystone: serial: Add driver model support
by Lokesh Vutla 23 Oct '15

23 Oct '15

Add driver model support for keystone serial driver. Signed-off-by: Lokesh Vutla <lokeshvutla(a)ti.com> --- drivers/serial/Makefile | 1 + drivers/serial/serial_keystone.c | 48 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) create mode 100644 drivers/serial/serial_keystone.c diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 869ea7b..1818c7c 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_EFI_APP) += serial_efi.o obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o obj-$(CONFIG_MCFUART) += mcfuart.o obj-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o +obj-$(CONFIG_KEYSTONE_SERIAL) += serial_keystone.o obj-$(CONFIG_SYS_NS16550) += ns16550.o obj-$(CONFIG_S5P) += serial_s5p.o obj-$(CONFIG_IMX_SERIAL) += serial_imx.o diff --git a/drivers/serial/serial_keystone.c b/drivers/serial/serial_keystone.c new file mode 100644 index 0000000..7b5ab6c --- /dev/null +++ b/drivers/serial/serial_keystone.c @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015 Texas Instruments, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <ns16550.h> +#include <serial.h> +#include <asm/arch/clock.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if CONFIG_IS_ENABLED(OF_CONTROL) +static const struct udevice_id keystone_serial_ids[] = { + { .compatible = "ti,keystone-uart" }, + { .compatible = "ns16550a" }, + { } +}; + +static int keystone_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct ns16550_platdata *plat = dev_get_platdata(dev); + int ret; + + ret = ns16550_serial_ofdata_to_platdata(dev); + if (ret) + return ret; + plat->clock = CONFIG_SYS_NS16550_CLK; + return 0; +} +#endif + +U_BOOT_DRIVER(serial_keystone_ns16550) = { + .name = "serial_keystone", + .id = UCLASS_SERIAL, +#if CONFIG_IS_ENABLED(OF_CONTROL) + .of_match = of_match_ptr(keystone_serial_ids), + .ofdata_to_platdata = of_match_ptr(keystone_serial_ofdata_to_platdata), + .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), +#endif + .priv_auto_alloc_size = sizeof(struct NS16550), + .probe = ns16550_serial_probe, + .ops = &ns16550_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; -- 2.1.4

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[U-Boot] [PATCH 00/12] SPL mmc refactor and alternate boot device feature
by Nikita Kiryanov 23 Oct '15

23 Oct '15

This series has two parts: patches 1-7 perform refactors aimed at reducing the ifdef complexity of SPL mmc code (and some nand as well). This refactor also addresses a few design issues I noticed while working on the refactor. The rest of the series introduces a new SPL feature that allows board code to define a list of boot devices that SPL will try before failing (instead of the only one device it attempts now). This feature is useful for implementing fallbacks, as well as reacting to bootROM sequences. For example: On CM-FX6, if boot from the alternate boot device (MMC) fails, the bootROM proceeds to try boot from SPI flash. If the SPI flash boot is succesful, SPL will still try to load U-Boot from MMC, instead of from the actual boot device (SPI flash), and probably fail and hang. The alternate boot feature makes it possible for SPL to follow the MMC boot attempt with boot from the SPI flash. The CM-FX6 based miniature PC Utilite depends on this capability for its SPI flash boot to work, since SPI flash boot is only attempted if MMC boot fails. This series was tested on CM-FX6 and compile tested for arm and powerpc. Cc: Igor Grinberg <grinberg(a)compulab.co.il> Cc: Tom Rini <trini(a)konsulko.com> Cc: Pantelis Antoniou <panto(a)antoniou-consulting.com> Nikita Kiryanov (12): spl: nand: remove code duplication spl: mmc: add break statements in spl_mmc_load_image() spl: mmc: refactor device location code to its own function spl: mmc: remove #ifdef CONFIG_SPL_OS_BOOT check spl: mmc: get rid of #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION check spl: mmc: move fs boot into its own function spl: mmc: get rid of emmc boot code duplication spl: change return values of spl_*_load_image() common: spl: move image load to its own function spl: add support for alternative boot device spl: announce boot devices arm: mx6: cm-fx6: define fallback boot devices for spl arch/arm/cpu/armv7/sunxi/board.c | 4 +- arch/arm/include/asm/spl.h | 2 +- board/compulab/cm_fx6/spl.c | 19 +-- common/spl/spl.c | 191 ++++++++++++++++++++++------ common/spl/spl_ext.c | 6 + common/spl/spl_fat.c | 6 + common/spl/spl_mmc.c | 263 +++++++++++++++++++++++---------------- common/spl/spl_nand.c | 47 ++++--- common/spl/spl_net.c | 9 +- common/spl/spl_nor.c | 6 +- common/spl/spl_onenand.c | 4 +- common/spl/spl_sata.c | 11 +- common/spl/spl_usb.c | 17 ++- common/spl/spl_ymodem.c | 5 +- drivers/mtd/spi/spi_spl_load.c | 17 ++- include/configs/cm_fx6.h | 1 - include/spl.h | 18 +-- 17 files changed, 414 insertions(+), 212 deletions(-) -- 1.9.1

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[U-Boot] [PATCH v8 1/4] include: Add log2 and fls64 header fi
by Fabio Estevam 23 Oct '15

23 Oct '15

From: Fabio Estevam <fabio.estevam(a)freescale.com> Use the log2 and fls64 header files directly from the kernel. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- Changes since v7: - None include/asm-generic/bitops/fls64.h | 36 +++++++ include/linux/bitops.h | 9 ++ include/linux/log2.h | 208 +++++++++++++++++++++++++++++++++++++ 3 files changed, 253 insertions(+) create mode 100644 include/asm-generic/bitops/fls64.h create mode 100644 include/linux/log2.h diff --git a/include/asm-generic/bitops/fls64.h b/include/asm-generic/bitops/fls64.h new file mode 100644 index 0000000..86d403f --- /dev/null +++ b/include/asm-generic/bitops/fls64.h @@ -0,0 +1,36 @@ +#ifndef _ASM_GENERIC_BITOPS_FLS64_H_ +#define _ASM_GENERIC_BITOPS_FLS64_H_ + +#include <asm/types.h> + +/** + * fls64 - find last set bit in a 64-bit word + * @x: the word to search + * + * This is defined in a similar way as the libc and compiler builtin + * ffsll, but returns the position of the most significant set bit. + * + * fls64(value) returns 0 if value is 0 or the position of the last + * set bit if value is nonzero. The last (most significant) bit is + * at position 64. + */ +#if BITS_PER_LONG == 32 +static inline int fls64(__u64 x) +{ + __u32 h = x >> 32; + if (h) + return fls(h) + 32; + return fls(x); +} +#elif BITS_PER_LONG == 64 +static inline int fls64(__u64 x) +{ + if (x == 0) + return 0; + return __fls(x) + 1; +} +#else +#error BITS_PER_LONG not 32 or 64 +#endif + +#endif /* _ASM_GENERIC_BITOPS_FLS64_H_ */ diff --git a/include/linux/bitops.h b/include/linux/bitops.h index 7d30ace..647733f 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -129,6 +129,15 @@ static inline unsigned int generic_hweight8(unsigned int w) # define fls generic_fls #endif +#include <asm-generic/bitops/fls64.h> + +static inline unsigned fls_long(unsigned long l) +{ + if (sizeof(l) == 4) + return fls(l); + return fls64(l); +} + /** * __set_bit - Set a bit in memory * @nr: the bit to set diff --git a/include/linux/log2.h b/include/linux/log2.h new file mode 100644 index 0000000..fd7ff3d --- /dev/null +++ b/include/linux/log2.h @@ -0,0 +1,208 @@ +/* Integer base 2 logarithm calculation + * + * Copyright (C) 2006 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells(a)redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#ifndef _LINUX_LOG2_H +#define _LINUX_LOG2_H + +#include <linux/types.h> +#include <linux/bitops.h> + +/* + * deal with unrepresentable constant logarithms + */ +extern __attribute__((const, noreturn)) +int ____ilog2_NaN(void); + +/* + * non-constant log of base 2 calculators + * - the arch may override these in asm/bitops.h if they can be implemented + * more efficiently than using fls() and fls64() + * - the arch is not required to handle n==0 if implementing the fallback + */ +#ifndef CONFIG_ARCH_HAS_ILOG2_U32 +static inline __attribute__((const)) +int __ilog2_u32(u32 n) +{ + return fls(n) - 1; +} +#endif + +#ifndef CONFIG_ARCH_HAS_ILOG2_U64 +static inline __attribute__((const)) +int __ilog2_u64(u64 n) +{ + return fls64(n) - 1; +} +#endif + +/* + * Determine whether some value is a power of two, where zero is + * *not* considered a power of two. + */ + +static inline __attribute__((const)) +bool is_power_of_2(unsigned long n) +{ + return (n != 0 && ((n & (n - 1)) == 0)); +} + +/* + * round up to nearest power of two + */ +static inline __attribute__((const)) +unsigned long __roundup_pow_of_two(unsigned long n) +{ + return 1UL << fls_long(n - 1); +} + +/* + * round down to nearest power of two + */ +static inline __attribute__((const)) +unsigned long __rounddown_pow_of_two(unsigned long n) +{ + return 1UL << (fls_long(n) - 1); +} + +/** + * ilog2 - log of base 2 of 32-bit or a 64-bit unsigned value + * @n - parameter + * + * constant-capable log of base 2 calculation + * - this can be used to initialise global variables from constant data, hence + * the massive ternary operator construction + * + * selects the appropriately-sized optimised version depending on sizeof(n) + */ +#define ilog2(n) \ +( \ + __builtin_constant_p(n) ? ( \ + (n) < 1 ? ____ilog2_NaN() : \ + (n) & (1ULL << 63) ? 63 : \ + (n) & (1ULL << 62) ? 62 : \ + (n) & (1ULL << 61) ? 61 : \ + (n) & (1ULL << 60) ? 60 : \ + (n) & (1ULL << 59) ? 59 : \ + (n) & (1ULL << 58) ? 58 : \ + (n) & (1ULL << 57) ? 57 : \ + (n) & (1ULL << 56) ? 56 : \ + (n) & (1ULL << 55) ? 55 : \ + (n) & (1ULL << 54) ? 54 : \ + (n) & (1ULL << 53) ? 53 : \ + (n) & (1ULL << 52) ? 52 : \ + (n) & (1ULL << 51) ? 51 : \ + (n) & (1ULL << 50) ? 50 : \ + (n) & (1ULL << 49) ? 49 : \ + (n) & (1ULL << 48) ? 48 : \ + (n) & (1ULL << 47) ? 47 : \ + (n) & (1ULL << 46) ? 46 : \ + (n) & (1ULL << 45) ? 45 : \ + (n) & (1ULL << 44) ? 44 : \ + (n) & (1ULL << 43) ? 43 : \ + (n) & (1ULL << 42) ? 42 : \ + (n) & (1ULL << 41) ? 41 : \ + (n) & (1ULL << 40) ? 40 : \ + (n) & (1ULL << 39) ? 39 : \ + (n) & (1ULL << 38) ? 38 : \ + (n) & (1ULL << 37) ? 37 : \ + (n) & (1ULL << 36) ? 36 : \ + (n) & (1ULL << 35) ? 35 : \ + (n) & (1ULL << 34) ? 34 : \ + (n) & (1ULL << 33) ? 33 : \ + (n) & (1ULL << 32) ? 32 : \ + (n) & (1ULL << 31) ? 31 : \ + (n) & (1ULL << 30) ? 30 : \ + (n) & (1ULL << 29) ? 29 : \ + (n) & (1ULL << 28) ? 28 : \ + (n) & (1ULL << 27) ? 27 : \ + (n) & (1ULL << 26) ? 26 : \ + (n) & (1ULL << 25) ? 25 : \ + (n) & (1ULL << 24) ? 24 : \ + (n) & (1ULL << 23) ? 23 : \ + (n) & (1ULL << 22) ? 22 : \ + (n) & (1ULL << 21) ? 21 : \ + (n) & (1ULL << 20) ? 20 : \ + (n) & (1ULL << 19) ? 19 : \ + (n) & (1ULL << 18) ? 18 : \ + (n) & (1ULL << 17) ? 17 : \ + (n) & (1ULL << 16) ? 16 : \ + (n) & (1ULL << 15) ? 15 : \ + (n) & (1ULL << 14) ? 14 : \ + (n) & (1ULL << 13) ? 13 : \ + (n) & (1ULL << 12) ? 12 : \ + (n) & (1ULL << 11) ? 11 : \ + (n) & (1ULL << 10) ? 10 : \ + (n) & (1ULL << 9) ? 9 : \ + (n) & (1ULL << 8) ? 8 : \ + (n) & (1ULL << 7) ? 7 : \ + (n) & (1ULL << 6) ? 6 : \ + (n) & (1ULL << 5) ? 5 : \ + (n) & (1ULL << 4) ? 4 : \ + (n) & (1ULL << 3) ? 3 : \ + (n) & (1ULL << 2) ? 2 : \ + (n) & (1ULL << 1) ? 1 : \ + (n) & (1ULL << 0) ? 0 : \ + ____ilog2_NaN() \ + ) : \ + (sizeof(n) <= 4) ? \ + __ilog2_u32(n) : \ + __ilog2_u64(n) \ + ) + +/** + * roundup_pow_of_two - round the given value up to nearest power of two + * @n - parameter + * + * round the given value up to the nearest power of two + * - the result is undefined when n == 0 + * - this can be used to initialise global variables from constant data + */ +#define roundup_pow_of_two(n) \ +( \ + __builtin_constant_p(n) ? ( \ + (n == 1) ? 1 : \ + (1UL << (ilog2((n) - 1) + 1)) \ + ) : \ + __roundup_pow_of_two(n) \ + ) + +/** + * rounddown_pow_of_two - round the given value down to nearest power of two + * @n - parameter + * + * round the given value down to the nearest power of two + * - the result is undefined when n == 0 + * - this can be used to initialise global variables from constant data + */ +#define rounddown_pow_of_two(n) \ +( \ + __builtin_constant_p(n) ? ( \ + (1UL << ilog2(n))) : \ + __rounddown_pow_of_two(n) \ + ) + +/** + * order_base_2 - calculate the (rounded up) base 2 order of the argument + * @n: parameter + * + * The first few values calculated by this routine: + * ob2(0) = 0 + * ob2(1) = 0 + * ob2(2) = 1 + * ob2(3) = 2 + * ob2(4) = 2 + * ob2(5) = 3 + * ... and so on. + */ + +#define order_base_2(n) ilog2(roundup_pow_of_two(n)) + +#endif /* _LINUX_LOG2_H */ -- 1.9.1

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[U-Boot] [PATCH] fdt_support: Check for bank size before updating memory node
by Lokesh Vutla 23 Oct '15

23 Oct '15

In case if one of the bank that is passed is of size zero, then u-boot will be updating memory node with a bank of size zero. There is not need to update memory node if size is zero, so check for bank size before updating. Signed-off-by: Lokesh Vutla <lokeshvutla(a)ti.com> --- common/fdt_support.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/common/fdt_support.c b/common/fdt_support.c index f86365e..0019eef 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -401,6 +401,9 @@ static int fdt_pack_reg(const void *fdt, void *buf, u64 *address, u64 *size, char *p = buf; for (i = 0; i < n; i++) { + if (size[i] == 0) + continue; + if (address_cells == 2) *(fdt64_t *)p = cpu_to_fdt64(address[i]); else -- 2.1.4

3 3

[U-Boot] Pull request: u-boot-nios/master
by Thomas Chou 23 Oct '15

23 Oct '15

Hi Tom, Please pull, The following changes since commit 9f13b6d147dc74f2400ce18d9d4005ba53f21fd3: ARM: AM335x: mux: change mmc0 cd pinmux from mmc0_sdcd to gpio (2015-10-22 14:44:03 -0400) are available in the git repository at: git://git.denx.de/u-boot-nios.git master for you to fetch changes up to 96fa1e4385bb1b63c58c48d10b552605f47a6f7f: net: convert altera_tse to driver model and phylib (2015-10-23 14:55:48 +0800) ---------------------------------------------------------------- Thomas Chou (42): nios2: move command line configuration to Kconfig nios2: enable CONFIG_NET_RANDOM_ETHADDR nios2: permit device tree control of U-Boot nios2: move altera_pio_init to board_early_init_r nios2: BSS should be cleared only after board_init_f nios2: enlarge the code relocation range nios2: remove gp assignments in link script nios2: define _end in link script nios2: enable device tree control of U-Boot nios2: enable Driver Model nios2: Switch to generic timer nios2: Split timer code into timer.c nios2: zap dly_clks nios2: zap version_string nios2: call board_init_f_mem nios2: enable malloc() pool before relocation nios2: map physical address to uncached virtual address nios2: convert altera_jtag_uart to driver model nios2: convert altera_uart to driver model spi : convert altera_spi to driver model nios2: add clear and set bits macros nios2 : convert altera_pio to driver model nios2: convert nios2 cpu to driver model dm: implement a Timer uclass timer: start a new timer after relocation nios2: convert altera timer to driver model serial: remove altera serial initializations dm: implement a Miscellaneous uclass nios2: convert altera sysid to driver model nios2: remove asm/psr.h nios2: convert do_reset to use dm cpu data nios2: convert ioremap to use dm cpu data nios2: clean up comments style in start.S nios2: zap initdram nios2: set default cache configuration in start.S nios2: convert cache flush to use dm cpu data nios2: convert copy_exception_trampoline to use dm cpu data nios2: convert dma_alloc_coherent to use malloc_cache_aligned nios2: zap nios2-generic board dir nios2: add README.nios2 nios2: fix virt_to_phys for nios2 with MMU net: convert altera_tse to driver model and phylib arch/Kconfig | 4 + arch/nios2/Kconfig | 16 +- arch/nios2/cpu/Makefile | 2 +- arch/nios2/cpu/cpu.c | 128 ++- arch/nios2/cpu/interrupts.c | 144 +-- arch/nios2/cpu/start.S | 186 ++-- arch/nios2/cpu/sysid.c | 46 - arch/nios2/cpu/u-boot.lds | 14 +- arch/nios2/dts/.gitignore | 1 + arch/nios2/dts/3c120_devboard.dts | 201 ++++ arch/nios2/dts/Makefile | 11 + arch/nios2/dts/include/dt-bindings | 1 + arch/nios2/include/asm/cache.h | 13 +- arch/nios2/include/asm/config.h | 2 - arch/nios2/include/asm/dma-mapping.h | 27 +- arch/nios2/include/asm/global_data.h | 9 + arch/nios2/include/asm/gpio.h | 80 +- arch/nios2/include/asm/io.h | 69 +- arch/nios2/include/asm/psr.h | 12 - arch/nios2/include/asm/sections.h | 10 - arch/nios2/include/asm/system.h | 2 + arch/nios2/include/asm/unaligned.h | 5 - arch/nios2/lib/Makefile | 1 - arch/nios2/lib/bootm.c | 6 +- arch/nios2/lib/cache.S | 68 -- arch/nios2/lib/cache.c | 129 +++ arch/nios2/lib/time.c | 22 - board/altera/common/cfide.c | 33 - board/altera/nios2-generic/Kconfig | 12 - board/altera/nios2-generic/MAINTAINERS | 6 - board/altera/nios2-generic/Makefile | 10 - board/altera/nios2-generic/config.mk | 12 - board/altera/nios2-generic/custom_fpga.h | 89 -- board/altera/nios2-generic/nios2-generic.c | 85 -- common/board_r.c | 3 + configs/nios2-generic_defconfig | 19 +- doc/README.nios2 | 95 ++ doc/device-tree-bindings/cpu/nios2.txt | 54 + doc/device-tree-bindings/gpio/altera_pio.txt | 28 + doc/device-tree-bindings/misc/altera_sysid.txt | 4 + doc/device-tree-bindings/net/altera_tse.txt | 112 ++ .../serial/altera_jtaguart.txt | 4 + doc/device-tree-bindings/serial/altera_uart.txt | 7 + doc/device-tree-bindings/spi/spi_altera.txt | 4 + doc/device-tree-bindings/timer/altera_timer.txt | 19 + drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/gpio/Kconfig | 7 + drivers/gpio/altera_pio.c | 316 ++---- drivers/misc/Kconfig | 16 + drivers/misc/Makefile | 2 + drivers/misc/altera_sysid.c | 101 ++ drivers/misc/misc-uclass.c | 51 + drivers/net/Kconfig | 9 + drivers/net/altera_tse.c | 1143 ++++++-------------- drivers/net/altera_tse.h | 277 +---- drivers/serial/Kconfig | 40 + drivers/serial/altera_jtag_uart.c | 171 ++- drivers/serial/altera_uart.c | 198 ++-- drivers/serial/serial.c | 4 - drivers/spi/Kconfig | 8 + drivers/spi/altera_spi.c | 197 ++-- drivers/timer/Kconfig | 19 + drivers/timer/Makefile | 8 + drivers/timer/altera_timer.c | 104 ++ drivers/timer/timer-uclass.c | 42 + include/asm-generic/global_data.h | 3 + include/configs/nios2-generic.h | 73 +- include/dm/uclass-id.h | 2 + include/misc.h | 79 ++ include/serial.h | 2 - include/timer.h | 52 + lib/time.c | 49 + 73 files changed, 2384 insertions(+), 2397 deletions(-) delete mode 100644 arch/nios2/cpu/sysid.c create mode 100644 arch/nios2/dts/.gitignore create mode 100644 arch/nios2/dts/3c120_devboard.dts create mode 100644 arch/nios2/dts/Makefile create mode 120000 arch/nios2/dts/include/dt-bindings delete mode 100644 arch/nios2/include/asm/psr.h delete mode 100644 arch/nios2/lib/cache.S create mode 100644 arch/nios2/lib/cache.c delete mode 100644 arch/nios2/lib/time.c delete mode 100644 board/altera/common/cfide.c delete mode 100644 board/altera/nios2-generic/Kconfig delete mode 100644 board/altera/nios2-generic/MAINTAINERS delete mode 100644 board/altera/nios2-generic/Makefile delete mode 100644 board/altera/nios2-generic/config.mk delete mode 100644 board/altera/nios2-generic/custom_fpga.h delete mode 100644 board/altera/nios2-generic/nios2-generic.c create mode 100644 doc/README.nios2 create mode 100644 doc/device-tree-bindings/cpu/nios2.txt create mode 100644 doc/device-tree-bindings/gpio/altera_pio.txt create mode 100644 doc/device-tree-bindings/misc/altera_sysid.txt create mode 100644 doc/device-tree-bindings/net/altera_tse.txt create mode 100644 doc/device-tree-bindings/serial/altera_jtaguart.txt create mode 100644 doc/device-tree-bindings/serial/altera_uart.txt create mode 100644 doc/device-tree-bindings/spi/spi_altera.txt create mode 100644 doc/device-tree-bindings/timer/altera_timer.txt create mode 100644 drivers/misc/altera_sysid.c create mode 100644 drivers/misc/misc-uclass.c create mode 100644 drivers/timer/Kconfig create mode 100644 drivers/timer/Makefile create mode 100644 drivers/timer/altera_timer.c create mode 100644 drivers/timer/timer-uclass.c create mode 100644 include/misc.h create mode 100644 include/timer.h

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