January 2015 - U-Boot

[U-Boot] Please pull u-boot-x86.git
by Simon Glass 13 Jan '15

13 Jan '15

Hi Tom, The following changes since commit 92fa7f53f1f3f03296f8ffb14bdf1baefab83368: Prepare v2015.01 (2015-01-12 09:39:08 -0500) are available in the git repository at: git://git.denx.de/u-boot-x86.git for you to fetch changes up to c479f96c0e0ceb226a8fb83a7996b78bfdcfd7b2: x86: Remove CONFIG_DISPLAY_CPUINFO in chromebook_link.h (2015-01-12 17:03:47 -0800) ---------------------------------------------------------------- Bin Meng (25): x86: Remove alex.dts in arch/x86/dts x86: Rename coreboot.dsti to serial.dtsi x86: Clean up the board dts files x86: Add missing DECLARE_GLOBAL_DATA_PTR for pci.c x86: Support pci bus scan in the early phase pci: Make pci apis usable before relocation x86: Simplify the fsp hob access functions fdt: Add several apis to decode pci device node serial: ns16550: Support ns16550 compatible pci uart devices x86: Use ePAPR defined properties for x86-uart x86: crownbay: Add pci devices in the dts file x86: fsp: Drop get_hob_type() and get_hob_length() x86: coreboot: Set up timer base correctly x86: Allow a hardcoded TSC frequency provided by Kconfig x86: Move CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig x86: Hide ROM chip size when CONFIG_X86_RESET_VECTOR is not selected x86: coreboot: Make SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE configurable x86: coreboot: Move coreboot-specific defines from coreboot.h to Kconfig x86: Move CONFIG_SYS_CAR_xxx to Kconfig x86: Remove include/configs/coreboot.h x86: Make chromebook_link the default board for coreboot x86: coreboot: Wrap cros_ec initialization x86: coreboot: Configure pci memory regions x86: Update README.x86 for coreboot support x86: Remove CONFIG_DISPLAY_CPUINFO in chromebook_link.h Simon Glass (20): x86: Correct XIP_ROM_SIZE x86: Drop RAMTOP Kconfig x86: Correct ifdtool microcode calculation x86: video: Add a debug() to display the frame buffer address x86: pci: Don't return a vesa mode when there is not video x86: video: Add debug option to time the BIOS copy x86: ivybridge: Only run the Video BIOS when video is enabled x86: Use cache, don't clear the display in video BIOS x86: Tidy up VESA mode numbers x86: pci: Display vesa modes in hex x86: ivybridge: Drop support for ROM caching x86: Add support for MTRRs x86: ivybridge: Set up an MTRR for the video frame buffer x86: board_f: Adjust x86 boot order for performance x86: ivybridge: Request MTRRs for DRAM regions x86: Commit the current MTRRs before relocation x86: ivybridge: Add a way to turn off the CAR x86: Disable CAR before relocation on platforms that need it x86: ivybridge: Update microcode early in boot x86: Add an 'mtrr' command to list and adjust MTRRs arch/x86/Kconfig | 39 +++++- arch/x86/cpu/Makefile | 1 + arch/x86/cpu/coreboot/Kconfig | 15 +++ arch/x86/cpu/coreboot/coreboot.c | 22 ++-- arch/x86/cpu/coreboot/pci.c | 30 ++++- arch/x86/cpu/coreboot/timestamp.c | 33 ++++-- arch/x86/cpu/ivybridge/car.S | 74 +++++++++++- arch/x86/cpu/ivybridge/cpu.c | 27 +---- arch/x86/cpu/ivybridge/gma.c | 16 ++- arch/x86/cpu/ivybridge/microcode_intel.c | 26 ++-- arch/x86/cpu/ivybridge/sdram.c | 10 ++ arch/x86/cpu/mtrr.c | 81 +++++++++++++ arch/x86/cpu/pci.c | 11 +- arch/x86/cpu/queensbay/fsp_support.c | 95 ++++++++------- arch/x86/cpu/queensbay/tnc_dram.c | 39 +++--- arch/x86/cpu/start.S | 8 ++ arch/x86/dts/Makefile | 4 +- arch/x86/dts/alex.dts | 24 ---- arch/x86/dts/chromebook_link.dts | 217 ++++++++++++++++++++++++++++++++- arch/x86/dts/coreboot.dtsi | 17 --- arch/x86/dts/crownbay.dts | 94 +++++++++++++-- arch/x86/dts/link.dts | 224 ----------------------------------- arch/x86/dts/serial.dtsi | 9 ++ arch/x86/include/asm/arch-ivybridge/microcode.h | 6 + arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h | 68 +++-------- arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h | 5 +- arch/x86/include/asm/global_data.h | 16 ++- arch/x86/include/asm/mtrr.h | 163 ++++++++++++------------- arch/x86/include/asm/pci.h | 2 +- arch/x86/lib/Makefile | 1 + arch/x86/lib/bios.c | 14 ++- arch/x86/lib/cmd_hob.c | 18 +-- arch/x86/lib/cmd_mtrr.c | 138 +++++++++++++++++++++ arch/x86/lib/init_helpers.c | 8 ++ arch/x86/lib/tsc_timer.c | 8 +- board/coreboot/coreboot/Kconfig | 27 ++++- board/coreboot/coreboot/MAINTAINERS | 2 +- board/coreboot/coreboot/coreboot.c | 2 + board/google/chromebook_link/Kconfig | 9 ++ board/intel/crownbay/Kconfig | 1 + common/board_f.c | 8 +- configs/chromebook_link_defconfig | 1 + configs/coreboot-x86_defconfig | 1 - doc/README.x86 | 57 ++++++++- drivers/pci/pci.c | 25 ++-- drivers/pci/pci_rom.c | 9 +- drivers/serial/ns16550.c | 31 +++++ drivers/serial/serial_x86.c | 8 +- drivers/video/Kconfig | 8 ++ drivers/video/x86_fb.c | 1 + include/asm-generic/global_data.h | 6 + include/configs/chromebook_link.h | 8 +- include/configs/coreboot.h | 75 ------------ include/configs/crownbay.h | 2 - include/fdtdec.h | 108 +++++++++++++++-- lib/fdtdec.c | 171 +++++++++++++++++++++++--- tools/ifdtool.c | 4 +- 57 files changed, 1413 insertions(+), 714 deletions(-) create mode 100644 arch/x86/cpu/coreboot/Kconfig create mode 100644 arch/x86/cpu/mtrr.c delete mode 100644 arch/x86/dts/alex.dts mode change 120000 => 100644 arch/x86/dts/chromebook_link.dts delete mode 100644 arch/x86/dts/coreboot.dtsi delete mode 100644 arch/x86/dts/link.dts create mode 100644 arch/x86/dts/serial.dtsi create mode 100644 arch/x86/lib/cmd_mtrr.c delete mode 100644 include/configs/coreboot.h Regards, Simon

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[U-Boot] [PATCH v6 0/5] i2c: UniPhier: add I2C drivers based on driver model
by Masahiro Yamada 13 Jan '15

13 Jan '15

Masahiro Yamada (5): i2c: add CONFIG_DM_I2C to Kconfig i2c: UniPhier: add driver for UniPhier i2c controller i2c: UniPhier: add driver for UniPhier FIFO-builtin i2c controller ARM: UniPhier: enable I2C for UniPhier SoCs ARM: UniPhier: enable CONFIG_I2C_EEPROM configs/ph1_ld4_defconfig | 2 + configs/ph1_pro4_defconfig | 2 + configs/ph1_sld8_defconfig | 2 + drivers/i2c/Kconfig | 22 +++ drivers/i2c/Makefile | 2 + drivers/i2c/i2c-uniphier-f.c | 379 +++++++++++++++++++++++++++++++++++++++++++ drivers/i2c/i2c-uniphier.c | 239 +++++++++++++++++++++++++++ include/configs/uniphier.h | 3 + 8 files changed, 651 insertions(+) create mode 100644 drivers/i2c/i2c-uniphier-f.c create mode 100644 drivers/i2c/i2c-uniphier.c -- 1.9.1

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[U-Boot] [PATCH 1/2] console: Use pre-console buffer to get complete log on all consoles
by Siarhei Siamashka 13 Jan '15

13 Jan '15

Currently the pre-console buffer can accumulate early log messages and flush them to the serial console as soon as it becomes available. This patch just adds one more pre-console buffer flushing point and does all the same for the other consoles too. This is particularly useful for the vga/hdmi/lcd console, where we can see all the older messages now (except for the log messages from SPL). Naturally, we don't want to get an extra copy of the log messages on the serial console again at the second flushing point, so the serial console has to be explicitly filtered out. Signed-off-by: Siarhei Siamashka <siarhei.siamashka(a)gmail.com> --- common/console.c | 46 +++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 41 insertions(+), 5 deletions(-) diff --git a/common/console.c b/common/console.c index 29560c3..fc1963b 100644 --- a/common/console.c +++ b/common/console.c @@ -199,6 +199,20 @@ static void console_putc(int file, const char c) } } +#ifdef CONFIG_PRE_CONSOLE_BUFFER +static void console_putc_noserial(int file, const char c) +{ + int i; + struct stdio_dev *dev; + + for (i = 0; i < cd_count[file]; i++) { + dev = console_devices[file][i]; + if (dev->putc != NULL && strcmp(dev->name, "serial") != 0) + dev->putc(dev, c); + } +} +#endif + static void console_puts(int file, const char *s) { int i; @@ -236,6 +250,14 @@ static inline void console_putc(int file, const char c) stdio_devices[file]->putc(stdio_devices[file], c); } +#ifdef CONFIG_PRE_CONSOLE_BUFFER +static inline void console_putc_noserial(int file, const char c) +{ + if (strcmp(stdio_devices[file]->name, "serial") != 0) + stdio_devices[file]->putc(stdio_devices[file], c); +} +#endif + static inline void console_puts(int file, const char *s) { stdio_devices[file]->puts(stdio_devices[file], s); @@ -382,6 +404,9 @@ int tstc(void) return serial_tstc(); } +#define PRE_CONSOLE_FLUSHPOINT1_SERIAL 0 +#define PRE_CONSOLE_FLUSHPOINT2_EVERYTHING_BUT_SERIAL 1 + #ifdef CONFIG_PRE_CONSOLE_BUFFER #define CIRC_BUF_IDX(idx) ((idx) % (unsigned long)CONFIG_PRE_CON_BUF_SZ) @@ -398,7 +423,7 @@ static void pre_console_puts(const char *s) pre_console_putc(*s++); } -static void print_pre_console_buffer(void) +static void print_pre_console_buffer(int flushpoint) { unsigned long i = 0; char *buffer = (char *)CONFIG_PRE_CON_BUF_ADDR; @@ -407,12 +432,20 @@ static void print_pre_console_buffer(void) i = gd->precon_buf_idx - CONFIG_PRE_CON_BUF_SZ; while (i < gd->precon_buf_idx) - putc(buffer[CIRC_BUF_IDX(i++)]); + switch (flushpoint) { + case PRE_CONSOLE_FLUSHPOINT1_SERIAL: + putc(buffer[CIRC_BUF_IDX(i++)]); + break; + case PRE_CONSOLE_FLUSHPOINT2_EVERYTHING_BUT_SERIAL: + console_putc_noserial(stdout, + buffer[CIRC_BUF_IDX(i++)]); + break; + } } #else static inline void pre_console_putc(const char c) {} static inline void pre_console_puts(const char *s) {} -static inline void print_pre_console_buffer(void) {} +static inline void print_pre_console_buffer(int flushpoint) {} #endif void putc(const char c) @@ -441,6 +474,7 @@ void putc(const char c) fputc(stdout, c); } else { /* Send directly to the handler */ + pre_console_putc(c); serial_putc(c); } } @@ -472,6 +506,7 @@ void puts(const char *s) fputs(stdout, s); } else { /* Send directly to the handler */ + pre_console_puts(s); serial_puts(s); } } @@ -679,7 +714,7 @@ int console_init_f(void) gd->flags |= GD_FLG_SILENT; #endif - print_pre_console_buffer(); + print_pre_console_buffer(PRE_CONSOLE_FLUSHPOINT1_SERIAL); return 0; } @@ -794,6 +829,7 @@ done: if ((stdio_devices[stdin] == NULL) && (stdio_devices[stdout] == NULL)) return 0; #endif + print_pre_console_buffer(PRE_CONSOLE_FLUSHPOINT2_EVERYTHING_BUT_SERIAL); return 0; } @@ -869,7 +905,7 @@ int console_init_r(void) if ((stdio_devices[stdin] == NULL) && (stdio_devices[stdout] == NULL)) return 0; #endif - + print_pre_console_buffer(PRE_CONSOLE_FLUSHPOINT2_EVERYTHING_BUT_SERIAL); return 0; } -- 2.0.5

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[U-Boot] [PATCH] sunxi: axp221: correct ALDO2 description for sun6i
by Chen-Yu Tsai 13 Jan '15

13 Jan '15

ALDO2 is used to power LPDDR2 SDRAM on both the reference design and the Hummingbird A31, when this type of RAM is present. Signed-off-by: Chen-Yu Tsai <wens(a)csie.org> --- Hi Hans, It seems I was on something when I read the board schematics, as I misread them. ALDO2 is only used for LPDDR2, which nobody seems to use, and we don't support anyway. VCC-PM-CPUS is powered from GPIO0-LDO, as is VCC-PB (which no one seems to use either.) Sorry for the mixup. ChenYu --- drivers/power/Kconfig | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index ef0c093..df7a759 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -46,14 +46,13 @@ config AXP221_ALDO1_VOLT config AXP221_ALDO2_VOLT int "axp221 aldo2 voltage" depends on AXP221_POWER - default 1800 if MACH_SUN6I + default 0 if MACH_SUN6I default 2500 if MACH_SUN8I ---help--- Set the voltage (mV) to program the axp221 aldo2 at, set to 0 to - disable aldo2. On sun6i (A31) boards this is typically connected to - VCC-PM, which powers the port M gpios, and should be set to 1.8V. - On sun8i (A23) this is typically connected to VDD-DLL and must be - set to 2.5V. + disable aldo2. On sun6i (A31) boards this is typically used for LPDDR2 + SDRAM, and should be set to 1.8V if present. On sun8i (A23) this is + typically connected to VDD-DLL and must be set to 2.5V. config AXP221_ALDO3_VOLT int "axp221 aldo3 voltage" -- 2.1.4

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[U-Boot] [PATCH 0/3] sunxi: Enable VGA output on Hummingbird A31
by Chen-Yu Tsai 13 Jan '15

13 Jan '15

Hi Hans, Ian, This series enables the VGA output on the Hummingbird A31. The VGA output is driven from LCD0, through an external DAC that's powered up by toggling pin PH25. Patch 1 allows selecting CONFIG_VIDEO_VGA_VIA_LCD on sun6i and sun8i. These 2 platforms do not have builtin TV encoders, and some vendor may use an external DAC to support VGA. Patch 2 adds support for toggling a GPIO pin as part of the video init sequence to power up the DAC Patch 3 updates the Hummingbird A31 defconfig to enable VGA output. I have one question about the VGA_VIA_LCD code in general. The color depth is forced to 18. Is this necessary? Can we make it configurable? I haven't tried displaying pictures so I don't know if it makes a visible difference. Also with the VGA output on my Hummingbird A31, I get greenish flashing pixels where it should be black, like in and between characters. Once booted in to the kernel this disappears, and I get a nice console with simplefb. Kind of weird. Cheers ChenYu Chen-Yu Tsai (3): sunxi: video: Allow external DACs for VGA on platforms without TV encoders sunxi: video: Add support for external DAC enable pin sunxi: Hummingbird_A31_defconfig: Enable VGA output through external DAC board/sunxi/Kconfig | 10 +++++++++- configs/Hummingbird_A31_defconfig | 2 ++ drivers/video/sunxi_display.c | 18 ++++++++++++++++++ 3 files changed, 29 insertions(+), 1 deletion(-) -- 2.1.4

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[U-Boot] [PATCH] ARM: UniPhier: add static to local functions
by Masahiro Yamada 13 Jan '15

13 Jan '15

Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> --- arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c | 6 +++--- arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c | 6 +++--- arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c | 6 +++--- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c index 68b9d5f..b83582f 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c @@ -11,7 +11,7 @@ #undef DPLL_SSC_RATE_1PER -void dpll_init(void) +static void dpll_init(void) { u32 tmp; @@ -42,7 +42,7 @@ void dpll_init(void) writel(tmp, SC_DPLLCTRL2); } -void upll_init(void) +static void upll_init(void) { u32 tmp, clk_mode_upll, clk_mode_axosel; @@ -82,7 +82,7 @@ void upll_init(void) writel(tmp, SC_UPLLCTRL); } -void vpll_init(void) +static void vpll_init(void) { u32 tmp, clk_mode_axosel; diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c index 2dcc089..1db90f8 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c @@ -11,7 +11,7 @@ #undef DPLL_SSC_RATE_1PER -void dpll_init(void) +static void dpll_init(void) { u32 tmp; @@ -46,7 +46,7 @@ void dpll_init(void) writel(tmp, SC_DPLLCTRL2); } -void stop_mpll(void) +static void stop_mpll(void) { u32 tmp; @@ -62,7 +62,7 @@ void stop_mpll(void) ; } -void vpll_init(void) +static void vpll_init(void) { u32 tmp, clk_mode_axosel; diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c index 4d87053..4b82700 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c @@ -9,7 +9,7 @@ #include <asm/arch/sc-regs.h> #include <asm/arch/sg-regs.h> -void dpll_init(void) +static void dpll_init(void) { u32 tmp; /* @@ -54,7 +54,7 @@ void dpll_init(void) writel(tmp, SC_DPLLCTRL2); } -void upll_init(void) +static void upll_init(void) { u32 tmp, clk_mode_upll, clk_mode_axosel; @@ -94,7 +94,7 @@ void upll_init(void) writel(tmp, SC_UPLLCTRL); } -void vpll_init(void) +static void vpll_init(void) { u32 tmp, clk_mode_axosel; -- 1.9.1

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[U-Boot] [PATCH] gpt: Fix the protective MBR partition size
by Maxime Ripard 13 Jan '15

13 Jan '15

According to the UEFI Spec (Table 16, section 5.2.3 of the version 2.4 Errata B), the protective MBR partition record size must be set to the size of the disk minus one, in LBAs. However, the current code was setting the size as the total number of LBAs on the disk, resulting in an off-by-one error. This confused the AM335x ROM code, and will probably confuse other tools as well. Signed-off-by: Maxime Ripard <maxime.ripard(a)free-electrons.com> --- disk/part_efi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/disk/part_efi.c b/disk/part_efi.c index 612f0926b62b..5ca17c138e96 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -240,7 +240,7 @@ static int set_protective_mbr(block_dev_desc_t *dev_desc) p_mbr->signature = MSDOS_MBR_SIGNATURE; p_mbr->partition_record[0].sys_ind = EFI_PMBR_OSTYPE_EFI_GPT; p_mbr->partition_record[0].start_sect = 1; - p_mbr->partition_record[0].nr_sects = (u32) dev_desc->lba; + p_mbr->partition_record[0].nr_sects = (u32) dev_desc->lba - 1; /* Write MBR sector to the MMC device */ if (dev_desc->block_write(dev_desc->dev, 0, 1, p_mbr) != 1) { -- 2.2.1

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[U-Boot] [PATCH] ARM: exynos: clock: remove clock_get_periph_rate()
by Jaehoon Chung 13 Jan '15

13 Jan '15

This api is wrong array bounds. arch/arm/cpu/armv7/exynos/clock.c: In function 'clock_get_periph_rate': arch/arm/cpu/armv7/exynos/clock.c:265:47: warning: array subscript is above array bounds [-Warray-bounds] struct clk_bit_info *bit_info = &clk_bit_info[peripheral]; And it doesn't use anywhere. It only used to get pwm clock. So it changes from clock_get_periph_rate() to get_pwm_clock. Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> --- arch/arm/cpu/armv7/exynos/clock.c | 173 +++++---------------------------- arch/arm/include/asm/arch-exynos/clk.h | 9 -- 2 files changed, 25 insertions(+), 157 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index b31c13b..9458428 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -15,49 +15,6 @@ #define PLL_DIV_65535 65535 #define PLL_DIV_65536 65536 -/* * - * This structure is to store the src bit, div bit and prediv bit - * positions of the peripheral clocks of the src and div registers - */ -struct clk_bit_info { - int8_t src_bit; - int8_t div_bit; - int8_t prediv_bit; -}; - -/* src_bit div_bit prediv_bit */ -static struct clk_bit_info clk_bit_info[] = { - {0, 0, -1}, - {4, 4, -1}, - {8, 8, -1}, - {12, 12, -1}, - {0, 0, 8}, - {4, 16, 24}, - {8, 0, 8}, - {12, 16, 24}, - {-1, -1, -1}, - {16, 0, 8}, - {20, 16, 24}, - {24, 0, 8}, - {0, 0, 4}, - {4, 12, 16}, - {-1, -1, -1}, - {-1, -1, -1}, - {-1, 24, 0}, - {-1, 24, 0}, - {-1, 24, 0}, - {-1, 24, 0}, - {-1, 24, 0}, - {-1, 24, 0}, - {-1, 24, 0}, - {-1, 24, 0}, - {24, 0, -1}, - {24, 0, -1}, - {24, 0, -1}, - {24, 0, -1}, - {24, 0, -1}, -}; - /* Epll Clock division values to achive different frequency output */ static struct set_epll_con_val exynos5_epll_div[] = { { 192000000, 0, 48, 3, 1, 0 }, @@ -260,110 +217,6 @@ static unsigned long exynos5_get_pll_clk(int pllreg) return fout; } -static unsigned long exynos5_get_periph_rate(int peripheral) -{ - struct clk_bit_info *bit_info = &clk_bit_info[peripheral]; - unsigned long sclk, sub_clk; - unsigned int src, div, sub_div; - struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); - - switch (peripheral) { - case PERIPH_ID_UART0: - case PERIPH_ID_UART1: - case PERIPH_ID_UART2: - case PERIPH_ID_UART3: - src = readl(&clk->src_peric0); - div = readl(&clk->div_peric0); - break; - case PERIPH_ID_PWM0: - case PERIPH_ID_PWM1: - case PERIPH_ID_PWM2: - case PERIPH_ID_PWM3: - case PERIPH_ID_PWM4: - src = readl(&clk->src_peric0); - div = readl(&clk->div_peric3); - break; - case PERIPH_ID_I2S0: - src = readl(&clk->src_mau); - div = readl(&clk->div_mau); - case PERIPH_ID_SPI0: - case PERIPH_ID_SPI1: - src = readl(&clk->src_peric1); - div = readl(&clk->div_peric1); - break; - case PERIPH_ID_SPI2: - src = readl(&clk->src_peric1); - div = readl(&clk->div_peric2); - break; - case PERIPH_ID_SPI3: - case PERIPH_ID_SPI4: - src = readl(&clk->sclk_src_isp); - div = readl(&clk->sclk_div_isp); - break; - case PERIPH_ID_SDMMC0: - case PERIPH_ID_SDMMC1: - case PERIPH_ID_SDMMC2: - case PERIPH_ID_SDMMC3: - src = readl(&clk->src_fsys); - div = readl(&clk->div_fsys1); - break; - case PERIPH_ID_I2C0: - case PERIPH_ID_I2C1: - case PERIPH_ID_I2C2: - case PERIPH_ID_I2C3: - case PERIPH_ID_I2C4: - case PERIPH_ID_I2C5: - case PERIPH_ID_I2C6: - case PERIPH_ID_I2C7: - sclk = exynos5_get_pll_clk(MPLL); - sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit) - & 0x7) + 1; - div = ((readl(&clk->div_top0) >> bit_info->prediv_bit) - & 0x7) + 1; - return (sclk / sub_div) / div; - default: - debug("%s: invalid peripheral %d", __func__, peripheral); - return -1; - }; - - src = (src >> bit_info->src_bit) & 0xf; - - switch (src) { - case EXYNOS_SRC_MPLL: - sclk = exynos5_get_pll_clk(MPLL); - break; - case EXYNOS_SRC_EPLL: - sclk = exynos5_get_pll_clk(EPLL); - break; - case EXYNOS_SRC_VPLL: - sclk = exynos5_get_pll_clk(VPLL); - break; - default: - return 0; - } - - /* Ratio clock division for this peripheral */ - sub_div = (div >> bit_info->div_bit) & 0xf; - sub_clk = sclk / (sub_div + 1); - - /* Pre-ratio clock division for SDMMC0 and 2 */ - if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) { - div = (div >> bit_info->prediv_bit) & 0xff; - return sub_clk / (div + 1); - } - - return sub_clk; -} - -unsigned long clock_get_periph_rate(int peripheral) -{ - if (cpu_is_exynos5()) - return exynos5_get_periph_rate(peripheral); - else - return 0; -} - /* exynos5420: return pll clock frequency */ static unsigned long exynos5420_get_pll_clk(int pllreg) { @@ -527,6 +380,30 @@ static unsigned long exynos4x12_get_pwm_clk(void) return pclk; } +/* exynos5: return pwm clock frequency */ +static unsigned long exynos5_get_pwm_clk(void) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + unsigned long sclk; + unsigned int ratio, src; + + /* + * CLK_SRC_PERIC0 + * PWM_SEL[27:24] + */ + src = (readl(&clk->src_peric0) >> 24) & 0xf; + sclk = get_pll_clk(src); + + /* + * CLK_DIV_PERIC3 + * PWM_RATIO[3:0] + */ + ratio = readl(&clk->div_peric3) & 0xf; + + return sclk / (ratio + 1); +} + /* exynos5420: return pwm clock frequency */ static unsigned long exynos5420_get_pwm_clk(void) { @@ -1622,7 +1499,7 @@ unsigned long get_pwm_clk(void) if (cpu_is_exynos5()) { if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_get_pwm_clk(); - return clock_get_periph_rate(PERIPH_ID_PWM0); + return exynos5_get_pwm_clk(); } else { if (proid_is_exynos4412()) return exynos4x12_get_pwm_clk(); diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index db24dc0..a76565b 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -44,13 +44,4 @@ int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq, int set_epll_clk(unsigned long rate); int set_spi_clk(int periph_id, unsigned int rate); -/** - * get the clk frequency of the required peripheral - * - * @param peripheral Peripheral id - * - * @return frequency of the peripheral clk - */ -unsigned long clock_get_periph_rate(int peripheral); - #endif -- 1.9.1

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[U-Boot] Question about compile warnings of exynos clock
by Joonyoung Shim 13 Jan '15

13 Jan '15

Hi, I found below compile warnings, CC arch/arm/cpu/armv7/exynos/clock.o arch/arm/cpu/armv7/exynos/clock.c: In function ‘clock_get_periph_rate’: arch/arm/cpu/armv7/exynos/clock.c:265:47: warning: array subscript is above array bounds [-Warray-bounds] struct clk_bit_info *bit_info = &clk_bit_info[peripheral]; ^ arch/arm/cpu/armv7/exynos/clock.c:265:47: warning: array subscript is above array bounds [-Warray-bounds] ... > static unsigned long exynos5_get_periph_rate(int peripheral) > { > struct clk_bit_info *bit_info = &clk_bit_info[peripheral]; > This can access out of bounds of clk_bit_info[] array from exynos5_get_periph_rate(). The peripheral value comes from enum periph_id but it gets out of count clk_bit_info[] array. So, i don't think exynos5_get_periph_rate is working correctly. Currently, exynos5_get_periph_rate is used by clock_get_periph_rate only from get_pwm_clk. Is it ongoing to work for generic api to get the clk freq? If not, let's remove exynos5_get_periph_rate and clock_get_periph_rate. Thanks.

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[U-Boot] [PATCH v5 0/5] i2c: UniPhier: add I2C drivers based on driver model
by Masahiro Yamada 13 Jan '15

13 Jan '15

Masahiro Yamada (5): i2c: add CONFIG_DM_I2C to Kconfig i2c: UniPhier: add driver for UniPhier i2c controller i2c: UniPhier: add driver for UniPhier FIFO-builtin i2c controller ARM: UniPhier: enable I2C for UniPhier SoCs ARM: UniPhier: enable CONFIG_I2C_EEPROM configs/ph1_ld4_defconfig | 2 + configs/ph1_pro4_defconfig | 2 + configs/ph1_sld8_defconfig | 2 + drivers/i2c/Kconfig | 22 +++ drivers/i2c/Makefile | 2 + drivers/i2c/i2c-uniphier-f.c | 380 +++++++++++++++++++++++++++++++++++++++++++ drivers/i2c/i2c-uniphier.c | 235 ++++++++++++++++++++++++++ include/configs/uniphier.h | 3 + 8 files changed, 648 insertions(+) create mode 100644 drivers/i2c/i2c-uniphier-f.c create mode 100644 drivers/i2c/i2c-uniphier.c -- 1.9.1

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